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n16-timing-closure

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• 785e9461a0 docs: ESP32 host firmware specification (docs/FIRMWARE_SPEC.md) v3-artix7 micheleandClaude Sonnet 5 2026-09-22 08:39:29 +02:00
• e3fe007469 docs: reframe primary docs -- N=16 is now the real fabrication target micheleandClaude Sonnet 5 2026-09-22 08:36:37 +02:00
• 0303aacb9f docs: consolidate N=16 to N=8's own level of rigor (EXP-0098) -- whole family real and closed n16-timing-closure micheleandClaude Sonnet 5 2026-09-22 01:15:15 +02:00
• cc6cfe168e docs: update LaTeX docs for N16 real timing closure + honest ESP32-S3 projection (EXP-0097) micheleandClaude Sonnet 5 2026-09-22 00:59:46 +02:00
• 2ab2ff7769 docs: N=8 re-verified with MAC pipeline fix (improves margin), N=16 margin-hunt result (EXP-0097 cont.) micheleandClaude Sonnet 5 2026-09-22 00:44:54 +02:00
• f9b366d747 feat: N=16 real timing CLOSED via extra MAC pipeline stage (EXP-0097, branch n16-timing-closure) micheleandClaude Sonnet 5 2026-09-22 00:17:18 +02:00
• 4c59b7e7c8 docs: add preliminary datasheet for FPGA-Neural N8 (semiconductor-style) micheleandClaude Sonnet 5 2026-09-21 08:57:15 +02:00
• fc0130e2e2 docs: LaTeX chapters for hardware, chip architecture, and tests/timing micheleandClaude Sonnet 5 2026-09-21 08:54:25 +02:00
• 264950923b feat: N=8 hybrid systolic promoted to the real, definitive deployment target (EXP-0096) micheleandClaude Sonnet 5 2026-09-21 08:29:04 +02:00
• 6d06404428 feat: real N=4/N=8 timing curve -- N=8 REALLY CLOSES (0 failing endpoints, EXP-0095) micheleandClaude Sonnet 5 2026-09-21 07:56:19 +02:00
• 67ccb420d6 docs: real P&R directive tuning closes most of remaining N=16 timing gap (EXP-0094 cont.) micheleandClaude Sonnet 5 2026-09-21 02:39:45 +02:00
• 9e1f16db47 feat: real hierarchical 2-level arbiter, real N=16 timing WNS -0.913ns -> -0.646ns (EXP-0094) micheleandClaude Sonnet 5 2026-09-21 02:25:44 +02:00
• 50c940a41d docs: real, full P&R for N=16 hybrid systolic system -- timing NOT met (EXP-0093) micheleandClaude Sonnet 5 2026-09-21 00:41:17 +02:00
• 996dda3415 feat: real functional xsim verification of N=16 hybrid systolic system (EXP-0092) micheleandClaude Sonnet 5 2026-09-21 00:31:02 +02:00
• 4acc669d43 feat: real N=16 hybrid systolic top-level, synthesis-only pass (EXP-0091) micheleandClaude Sonnet 5 2026-09-21 00:12:12 +02:00
• bd1fb5dc14 feat: real Director extension for group dispatch + systolic_group.v P&R sanity check (EXP-0090) micheleandClaude Sonnet 5 2026-09-21 00:05:16 +02:00
• 932aec2490 feat: real first step of 4x4 hybrid systolic architecture (EXP-0089) micheleandClaude Sonnet 5 2026-09-20 22:54:52 +02:00
• 7f9ece12dc docs: real P&R signoff for the result-writeback engine (EXP-0088) micheleandClaude Sonnet 5 2026-09-20 19:27:00 +02:00
• ccaf3ee059 feat: real result-writeback engine, removes the last hard N-scaling pin blocker (EXP-0088) micheleandClaude Sonnet 5 2026-09-20 19:18:57 +02:00
• 344e798ad5 feat: real DDRManager re-measurement at 32-bit channel + BOM/pinout docs (EXP-0087) micheleandClaude Sonnet 5 2026-09-20 18:37:41 +02:00
• 678caa9bce docs: real timing closure for 32-bit DDR3 channel (EXP-0086) michele 2026-09-20 18:05:30 +02:00
• bdc821222f feat: real active-low data_ready_n sticky IRQ pin (EXP-0085) micheleandClaude Sonnet 5 2026-09-20 16:33:46 +02:00
• 9dead54ebf feat: real 32-bit DDR3 channel widening - functionally complete, timing NOT yet closed (EXP-0084) micheleandClaude Sonnet 5 2026-09-20 16:28:44 +02:00
• 376ccb6ee2 docs: capture two more exploratory scaling directions (BRAM cache, ESP32-side scheduling) micheleandClaude Sonnet 5 2026-09-20 13:22:17 +02:00
• 32d32f4c0e docs: capture exploratory 4x4 hybrid systolic scaling direction (not built) micheleandClaude Sonnet 5 2026-09-20 13:18:46 +02:00
• fa327b75ca feat: DDRManager phase 1 - single-slot look-ahead activation prefetch (EXP-0083) micheleandClaude Sonnet 5 2026-09-20 10:59:45 +02:00
• cbd16dd727 docs: sync physical/architecture docs with EXP-0081/0082 reality, add 32-bit vs dual-channel analysis micheleandClaude Sonnet 5 2026-09-20 10:07:16 +02:00
• e6768623d6 docs: confirm denser activation packing is real-timing-safe, margin improved (EXP-0082) micheleandClaude Sonnet 5 2026-09-20 10:01:58 +02:00
• 8ad04987de feat: denser activation packing, real bandwidth ceiling doubled (EXP-0081) micheleandClaude Sonnet 5 2026-09-20 09:55:16 +02:00
• 27cf5f36da docs: complete architecture analysis - DDR3 bandwidth is the real ceiling, not DSP count (EXP-0080) micheleandClaude Sonnet 5 2026-09-20 09:44:10 +02:00
• 43a12379a5 feat: MILESTONE - real activation-fetch engine, full N=2 system verified on real DDR3 (EXP-0079) micheleandClaude Sonnet 5 2026-09-20 08:13:15 +02:00
• 78577dde59 docs: log real Vivado stale-source bug + final flash-bridge P&R signoff (EXP-0078) micheleandClaude Sonnet 5 2026-09-20 07:24:33 +02:00
• a4c080da83 feat: config-flash passthrough bridge via STARTUPE2, real board-exclusive flash access (EXP-0077) micheleandClaude Sonnet 5 2026-09-19 21:45:17 +02:00
• fd6cc7a2fa docs: log final re-verified real P&R signoff after SPI fix + reg file (EXP-0076) micheleandClaude Sonnet 5 2026-09-19 19:22:32 +02:00
• ca17765fe3 fix: real SPI MISO bit-corruption bug found+fixed; add register file + pin plan (EXP-0075) micheleandClaude Sonnet 5 2026-09-19 18:31:51 +02:00
• 835ae881dc feat: MILESTONE - first real in-context P&R, timing closes at 310MHz DDR3 (EXP-0074) micheleandClaude Sonnet 5 2026-09-19 17:47:40 +02:00
• 6caea54b8e fix: neural_director_packed.v SV literal for synth; exonerate it from a testbench race (EXP-0073) micheleandClaude Sonnet 5 2026-09-19 13:37:25 +02:00
• 562cf91f1e feat: spi_host_bridge_v3.v, SPI opcode re-audit against real V3 RTL (EXP-0072) micheleandClaude Sonnet 5 2026-09-17 08:56:15 +02:00
• 786464ee21 feat: host_mem_bridge.v, word<->burst translator for host DDR3 access (EXP-0071) micheleandClaude Sonnet 5 2026-09-17 08:53:23 +02:00
• 598feb975b feat: first genuine N=2 multi-core system verified against real DDR3 (EXP-0070) micheleandClaude Sonnet 5 2026-09-17 08:51:43 +02:00
• afff0c4f02 test: fix tb_sdram_arbiter_n.v hang, root-caused as testbench bug (EXP-0069) micheleandClaude Sonnet 5 2026-09-17 08:44:46 +02:00
• e25e4a1506 feat: real DDR3 memory path verified against MIG's own ddr3_model.sv (EXP-0068) micheleandClaude Sonnet 5 2026-09-17 08:43:22 +02:00
• 0589620b58 exp: real P&R of the N=2 multi-core system, first genuine system Fmax (EXP-0067) micheleandClaude Sonnet 5 2026-09-17 00:21:01 +02:00
• 09fbf01ea5 feat: first genuine N=2 multi-core system, two real bugs found+fixed (EXP-0066) micheleandClaude Sonnet 5 2026-09-17 00:16:47 +02:00
• 124a0dbca0 feat: packed_slot.v, real per-slot sequencer FSM (EXP-0065) micheleandClaude Sonnet 5 2026-09-17 00:02:35 +02:00
• 71600096f9 feat: neural_director_packed.v, job-pairing scheduler for packed cores (EXP-0064) micheleandClaude Sonnet 5 2026-09-16 23:52:19 +02:00
• 5afa6a7477 exp: real P&R of verified weight-reuse memory path + packed core (EXP-0063) micheleandClaude Sonnet 5 2026-09-16 23:44:24 +02:00
• 9ca180a787 test: first real end-to-end weight-reuse -> packed-core integration, bug found+fixed (EXP-0062) micheleandClaude Sonnet 5 2026-09-16 23:41:35 +02:00
• 5c127fb069 feat: weight_tile_gather.v, real synthesizable byte-to-tile adapter (EXP-0061) micheleandClaude Sonnet 5 2026-09-16 23:34:09 +02:00
• 94b63705be exp: N=8 packed-core array real P&R, isolates placement density from interconnect (EXP-0060) micheleandClaude Sonnet 5 2026-09-16 23:29:54 +02:00
• 34b15cc0a7 exp: first real Vivado synthesis+P&R on XC7A100T for V3 DSP-packed core (EXP-0059) micheleandClaude Sonnet 5 2026-09-16 23:18:18 +02:00
• 9851930613 docs: extract V2 datasheet into submodule michele 2026-09-16 23:03:43 +02:00
• 1cbe7b85d5 v3: real Artix-7 compute core -- DSP48 packing verified, 2 real bugs found and fixed micheleandClaude Sonnet 5 2026-09-16 19:48:46 +02:00
• ff5908f25f docs: log DEC-0009 -- project v22 paused, hard DSP resource ceiling on ECP5 v22-final v22 micheleandClaude Sonnet 5 2026-09-16 15:38:39 +02:00
• 3416b8d3cf exp: fix pulse-race hang in tb_layer_reuse_vs_zero_reuse.v (EXP-0058 follow-up); real remaining bug still open, 7.16x NOT yet re-verified micheleandClaude Sonnet 5 2026-09-16 15:38:12 +02:00
• 80c89fa10d exp: real end-to-end weight-reuse integration with neural_processor.v (EXP-0058) micheleandClaude Sonnet 5 2026-09-16 14:26:09 +02:00
• ca94083366 prod: promote EXP-0056 fixes into production RTL (dependency_manager.v, nms_activation_fill_ctrl_v3.v) micheleandClaude Sonnet 5 2026-09-16 12:29:52 +02:00
• 49b25f6eb6 exp: layer_prefetch_ctrl.v, real synthesizable RTL for layer-weight-reuse prefetch, fixes a real address-truncation bug (EXP-0057b) micheleandClaude Sonnet 5 2026-09-16 12:25:32 +02:00
• 1ce78dff6e exp: N=16 timing closure fixed (EXP-0056), weight-reuse gives real 7.16x memory speedup without DDR3 (EXP-0057) micheleandClaude Sonnet 5 2026-09-16 12:01:11 +02:00
• fce8ff2d66 exp: fork real board top (fpga_neural_v2_top_openrow.v) with open-row SDRAM backend, verified functionally identical micheleandClaude Sonnet 5 2026-09-16 08:02:14 +02:00
• ee5a68f6e6 exp: SDRAM CDC bridge + open-row policy (EXP-0053/54/55) -- open-row is a real ~5% D-Stress win, CDC bridge measured net-negative once integrated micheleandClaude Sonnet 5 2026-09-16 07:07:57 +02:00
• 03b5cbc25b exp: bank-interleaved SDRAM pipelining works in isolation, ~0.3% gain integrated (EXP-0052) micheleandClaude Sonnet 5 2026-09-16 02:56:51 +02:00
• cc5db09f61 exp: dual-bank SDRAM sim shows W/AR split gives only ~9% cycle gain, not thrashing removal (EXP-0051) micheleandClaude Sonnet 5 2026-09-16 02:18:57 +02:00
• e809b71806 docs+synth: post-fix Fmax measurement (EXP-0051) - honest result, N=8 regressed v21 micheleandClaude Sonnet 5 2026-09-15 23:24:25 +00:00
• 6a46dc857f fix: propagate runtime-indexed-crossbar fix to slot_mem_arbiter(_wide) + dataflow_core mux micheleandClaude Sonnet 5 2026-09-15 22:39:00 +00:00
• 19ef54aea8 docs+synth: Phase 0 complete - N=8 baseline + toolchain discrepancy closed micheleandClaude Sonnet 5 2026-09-15 21:44:10 +00:00
• 685a4d6cfe docs+synth: Phase 0 baseline (N_SLOTS=4, real board top), fix stale LPF freq micheleandClaude Sonnet 5 2026-09-15 20:28:16 +00:00
• 8b8ca239ca docs: consolidate all V2 datasheets into one current, complete document main micheleandClaude Sonnet 5 2026-09-09 00:41:06 +02:00
• 1efd63912f docs: polish V2 datasheet to professional third-person English micheleandClaude Sonnet 5 2026-09-07 20:17:09 +02:00
• d4792beed7 docs: embed real KiCad schematic export in V2 datasheet, verify BOM from source micheleandClaude Sonnet 5 2026-09-07 20:03:57 +02:00
• 7eb02ba4bd docs: resolve FPGA grade to commercial (8BG381C), correct temp range data micheleandClaude Sonnet 5 2026-09-07 19:46:14 +02:00
• 22e226a087 docs: resolve the +1V1 label mystery and close remaining schematic open items micheleandClaude Sonnet 5 2026-09-07 19:42:46 +02:00
• 1e36853072 docs: clear CAS#/WE# false alarm, resolve TLV73325 EN wiring micheleandClaude Sonnet 5 2026-09-07 19:38:48 +02:00
• e2956d0377 docs: add real BOM, flag FPGA grade discrepancy (8BG381I vs 8BG381C) micheleandClaude Sonnet 5 2026-09-07 19:36:51 +02:00
• 4cbbe5a29d docs: real KiCad schematic review + reserved PCB module section micheleandClaude Sonnet 5 2026-09-07 19:35:03 +02:00
• 44be4a7d81 docs: reflect flash #1 removal and the N=4 8/8 timing recovery micheleandClaude Sonnet 5 2026-09-07 19:20:57 +02:00
• 481b5d223f perf: fix N=4@64MHz 7/8->8/8 by removing any_pending fan-out (user's idea) micheleandClaude Sonnet 5 2026-09-07 19:16:01 +02:00
• ee708775c7 Revert "feat: integrate flash #1 (neural-network data) RTL into V2 top-level" michele 2026-09-07 19:02:44 +02:00
• 59901a4905 feat: integrate flash #1 (neural-network data) RTL into V2 top-level micheleandClaude Sonnet 5 2026-09-07 18:31:50 +02:00
• b4f33388a9 fix: add missing sdram_clk output port -- real chip never had a clock pin micheleandClaude Sonnet 5 2026-09-07 17:55:23 +02:00
• abaaf21f56 docs: datasheet addendum for two-flash programming architecture + FPGA_DATA_READY micheleandClaude Sonnet 5 2026-09-07 13:11:12 +02:00
• 7d6311bce3 feat: two-flash programming architecture, FPGA_DATA_READY, real JTAG/config pinout micheleandClaude Sonnet 5 2026-09-07 12:46:00 +02:00
• 81a9619214 chore: remove root-level V1 duplicates, superseded by hardware/v1/ freeze micheleandClaude Sonnet 5 2026-09-07 05:30:17 +02:00
• e1cefd13db docs: remove hardware/v2/docs/DatasheetLatex, superseded by datasheet/ micheleandClaude Sonnet 5 2026-09-07 05:10:58 +02:00
• ff49d3c75d docs: bring datasheet/ into the main repo under hardware/v2/docs micheleandClaude Sonnet 5 2026-09-07 05:09:14 +02:00
• f14224d0cd fix: ERR-0029 sdram_unified_backend weight-cache hit-index critical path micheleandClaude Sonnet 5 2026-09-07 03:10:50 +02:00
• a20f1ecd73 docs: memory upgrade writeup (MEMORY_UPGRADE_64MB_N8.md) + supersede stale SDRAM docs micheleandClaude Sonnet 5 2026-09-07 00:21:05 +02:00
• 8d83d97bde feat: SDRAM 8MB->64MB upgrade (AS4C32M16SB-7BIN) + N_SLOTS=8 support micheleandClaude Sonnet 5 2026-09-07 00:20:53 +02:00
• 9b5d1055b8 feat: neural_sim Python golden functional reference simulator micheleandClaude Sonnet 5 2026-09-06 19:51:33 +02:00
• c4763aab10 test: directed SDRAM boundary verification + SPI frequency sweep micheleandClaude Sonnet 5 2026-09-06 19:42:37 +02:00
• eb0b0f9170 docs: PRE-PCB VERIFICATION FREEZE report + config flash freeze micheleandClaude Sonnet 5 2026-09-06 18:32:40 +02:00
• 8890b0abc2 fix: ERR-0026 SDRAM tMRD datasheet-unit mismatch at 64MHz micheleandClaude Sonnet 5 2026-09-06 18:27:36 +02:00
• d6376e8f2a V2 final synthesis/P&R sign-off + LaTeX datasheet port (NOT SILICON READY) micheleandClaude Sonnet 5 2026-09-06 17:50:53 +02:00
• 68f3c5e403 fix(v2): resolve ERR-0025 Part B - SRAM read timing bug in weight/activation memory micheleandClaude Sonnet 5 2026-09-06 17:33:45 +02:00
• 18bf038ed5 v1 datasheet latex source michele 2026-09-06 15:02:25 +02:00
• 43abf28b5b V2.1.0-dev: SPI host bridge + clock/reset architecture (NOT release-ready) micheleandClaude Sonnet 5 2026-09-06 14:35:14 +02:00
• 8e014d8d49 V2.0.0 hardware freeze - single SDRAM micheleandClaude Sonnet 5 2026-09-06 13:39:55 +02:00
• 5c9ec618d3 docs: publish refreshed V1 datasheet (EN/IT, Rev A1) micheleandClaude Sonnet 5 2026-09-05 21:59:02 +02:00
• 63cac6a7e5 perf(v2): shared activation cache - further 1.66-2.00x real speedup (DEC-0016) micheleandClaude Sonnet 5 2026-09-05 20:59:14 +02:00
• e4a5540b6e perf(v2): word-level burst reads - 2.24-2.37x real wall-clock speedup (DEC-0015) micheleandClaude Sonnet 5 2026-09-05 20:35:19 +02:00