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V2 final synthesis/P&R sign-off + LaTeX datasheet port (NOT SILICON READY)

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Real synthesis and place-and-route of the actual final board-level
top (fpga_neural_v2_top.v -- SPI bridge, real EHXPLLL, reset_sync,
compute+memory core), against a real, fully ball-assigned LPF. Also
ports the V2 datasheet to LaTeX using V1's own preamble/macros/
typography, and records a real (non-ESP32, honestly labeled) software
reference comparison.

Synthesis (Yosys, real run): 0 CHECK-pass problems, 38 unique warnings
(43 total), all matching this project's own previously-reviewed benign
set (neural_processor.v's known genvar multi-driver artifact, small-
array-to-register unrolling, the real SDRAM DQ tristate bus) -- no new
warnings from the SPI bridge, PLL, or reset synchronizer.
TRELLIS_FF=6322, TRELLIS_COMB=7084, MULT18X18D=32, EHXPLLL=1 (real PLL
confirmed present), DP16KD=0 (all small SRAMs -> distributed RAM).

Place-and-route (nextpnr-ecp5, real runs, 8 seeds, new
v2_board_top.lpf with all 44 top-level signals ball-assigned from the
official Lattice pinout CSV -- no placeholders): 8/8 PASS at 64MHz.
Worst 68.51MHz (seed 4), best 74.17MHz (seed 7), mean 71.16MHz. Zero
unrouted nets, zero placement/routing errors, TRELLIS_IO=44/245 (17%).
Critical path alternates between dependency_manager's own priority
encoder and sdram_unified_backend's own weight-cache hit-index logic,
matching this project's own prior documented timing investigations --
not a new defect.

New: hardware/v2/constraints/v2_board_top.lpf (final LPF, supersedes
v2_unified.lpf for the board-level top), hardware/v2/reports/
step_final_{synthesis,pnr_worst_seed4,timing}.* (raw evidence),
hardware/v2/docs/DatasheetLatex/ (V2 datasheet, real LaTeX build,
16 pages, visually inspected, ported from hardware/v1/docs/
DatasheetLatex/'s own preamble and macros).

Real, honestly-labeled software baseline: the D-Stress arithmetic
(256 neurons x 128 INT8 MACs) compiled and run on THIS development
machine (Apple M4, arm64, NOT an embedded target, NOT ESP32) --
1.28us/inference, included in the datasheet with an explicit
disclosure that no physical ESP32 hardware was available for a real
embedded-target comparison.

Remaining, disclosed, NOT-yet-closed items (this commit does NOT
claim silicon readiness): real KiCad schematic + ERC, PCB layout,
sourced BOM, real power current-budget estimate, SDRAM-datasheet-
parameter cross-check, configuration-flash selection, and (necessarily)
physical fabrication/bring-up. See hardware/v2/docs/DatasheetLatex/
chapters/08-status-roadmap.tex for the complete, itemized checklist.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
This commit is contained in:
michele
2026-09-06 17:50:53 +02:00
co-authored by Claude Sonnet 5
parent 68f3c5e403
commit d6376e8f2a
28 changed files with 21800 additions and 0 deletions
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hardware/v2/constraints/v2_board_top.lpf
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// FPGA-Neural V2 -- FINAL board-level top constraints (STEP-final).
// Target: fpga_neural_v2_top (N_SLOTS=2 default in this file's own
// simulation-facing top; the frozen hardware reference is N_SLOTS=4,
// synthesized separately at that parameter value -- see the synthesis
// log for the actual instantiation used for these P&R runs).
// FPGA: LFE5U-45F-8BG381, package CABGA381, speed grade -8
//
// This supersedes hardware/v2/constraints/v2_unified.lpf (which
// constrained the OLDER nms_neural_multiprocessor_sdram_unified.v
// simulation-facing top, with its raw 110-pin reg_* bus and an
// assumed-already-80MHz `clk` input). The board-level top has NO
// reg_* ports at all -- job registration is via 4 real SPI pins,
// and the input clock is a real 16MHz oscillator feeding a real
// EHXPLLL (ecp5_pll_sys_clk.v), not a pre-generated 80MHz.
//
// Every ball below is real, sourced from the official Lattice
// pinout CSV (FPGA-SC-02034-3-0-ECP5U-45-Pinout.csv rev 3.0,
// ~/Downloads/, cross-referenced against docs/pinouts.md) -- none
// invented. osc_clk/ext_rst_n reuse the SAME real balls (H5/B4) as
// V1's own validated spi_neuron_top.lpf and the previous v2_unified
// .lpf (same physical clock/reset pins on this package regardless of
// which V2 top-level is programmed). The 4 SPI pins and pll_locked
// are NEW real balls from banks 6/7 (plain GPIO, dual function "-"
// in the CSV, not previously used by the 37-signal SDRAM bus).
BLOCK ASYNCPATHS;
BLOCK RESETPATHS;
// Real 16MHz board oscillator (external to the FPGA; EHXPLLL inside
// the design generates the internal 64MHz system clock -- see
// ecp5_pll_sys_clk.v's own FREQUENCY_PIN_CLKI/CLKOP attributes,
// which nextpnr-ecp5 reads automatically for the generated-clock
// domain; no separate LPF entry is needed for the internal 64MHz net).
FREQUENCY PORT "osc_clk" 16 MHZ;
LOCATE COMP "osc_clk" SITE "H5";
IOBUF PORT "osc_clk" IO_TYPE=LVCMOS33;
LOCATE COMP "ext_rst_n" SITE "B4";
IOBUF PORT "ext_rst_n" IO_TYPE=LVCMOS33;
// ---- real SPI host interface (4 pins, banks 6/7) ----
LOCATE COMP "spi_sclk" SITE "L3"; IOBUF PORT "spi_sclk" IO_TYPE=LVCMOS33;
LOCATE COMP "spi_mosi" SITE "M3"; IOBUF PORT "spi_mosi" IO_TYPE=LVCMOS33;
LOCATE COMP "spi_miso" SITE "L2"; IOBUF PORT "spi_miso" IO_TYPE=LVCMOS33;
LOCATE COMP "spi_cs_n" SITE "N2"; IOBUF PORT "spi_cs_n" IO_TYPE=LVCMOS33;
// ---- PLL lock status (debug/bring-up signal, real ball) ----
LOCATE COMP "pll_locked" SITE "L1"; IOBUF PORT "pll_locked" IO_TYPE=LVCMOS33;
// ---- SDRAM interface (37 signals), unchanged from v2_unified.lpf,
// real balls, banks 6/7 ----
LOCATE COMP "sdram_cke" SITE "B5"; IOBUF PORT "sdram_cke" IO_TYPE=LVCMOS33;
LOCATE COMP "sdram_cs_n" SITE "C5"; IOBUF PORT "sdram_cs_n" IO_TYPE=LVCMOS33;
LOCATE COMP "sdram_ras_n" SITE "C4"; IOBUF PORT "sdram_ras_n" IO_TYPE=LVCMOS33;
LOCATE COMP "sdram_cas_n" SITE "A3"; IOBUF PORT "sdram_cas_n" IO_TYPE=LVCMOS33;
LOCATE COMP "sdram_we_n" SITE "B3"; IOBUF PORT "sdram_we_n" IO_TYPE=LVCMOS33;
LOCATE COMP "sdram_ba[0]" SITE "E4"; IOBUF PORT "sdram_ba[0]" IO_TYPE=LVCMOS33;
LOCATE COMP "sdram_ba[1]" SITE "C3"; IOBUF PORT "sdram_ba[1]" IO_TYPE=LVCMOS33;
LOCATE COMP "sdram_a[0]" SITE "D5"; IOBUF PORT "sdram_a[0]" IO_TYPE=LVCMOS33;
LOCATE COMP "sdram_a[1]" SITE "D3"; IOBUF PORT "sdram_a[1]" IO_TYPE=LVCMOS33;
LOCATE COMP "sdram_a[2]" SITE "F4"; IOBUF PORT "sdram_a[2]" IO_TYPE=LVCMOS33;
LOCATE COMP "sdram_a[3]" SITE "E5"; IOBUF PORT "sdram_a[3]" IO_TYPE=LVCMOS33;
LOCATE COMP "sdram_a[4]" SITE "E3"; IOBUF PORT "sdram_a[4]" IO_TYPE=LVCMOS33;
LOCATE COMP "sdram_a[5]" SITE "F5"; IOBUF PORT "sdram_a[5]" IO_TYPE=LVCMOS33;
LOCATE COMP "sdram_a[6]" SITE "A2"; IOBUF PORT "sdram_a[6]" IO_TYPE=LVCMOS33;
LOCATE COMP "sdram_a[7]" SITE "B1"; IOBUF PORT "sdram_a[7]" IO_TYPE=LVCMOS33;
LOCATE COMP "sdram_a[8]" SITE "C2"; IOBUF PORT "sdram_a[8]" IO_TYPE=LVCMOS33;
LOCATE COMP "sdram_a[9]" SITE "C1"; IOBUF PORT "sdram_a[9]" IO_TYPE=LVCMOS33;
LOCATE COMP "sdram_a[10]" SITE "D2"; IOBUF PORT "sdram_a[10]" IO_TYPE=LVCMOS33;
LOCATE COMP "sdram_a[11]" SITE "D1"; IOBUF PORT "sdram_a[11]" IO_TYPE=LVCMOS33;
LOCATE COMP "sdram_dq[0]" SITE "E1"; IOBUF PORT "sdram_dq[0]" IO_TYPE=LVCMOS33;
LOCATE COMP "sdram_dq[1]" SITE "G5"; IOBUF PORT "sdram_dq[1]" IO_TYPE=LVCMOS33;
LOCATE COMP "sdram_dq[2]" SITE "H3"; IOBUF PORT "sdram_dq[2]" IO_TYPE=LVCMOS33;
LOCATE COMP "sdram_dq[3]" SITE "J5"; IOBUF PORT "sdram_dq[3]" IO_TYPE=LVCMOS33;
LOCATE COMP "sdram_dq[4]" SITE "K3"; IOBUF PORT "sdram_dq[4]" IO_TYPE=LVCMOS33;
LOCATE COMP "sdram_dq[5]" SITE "K2"; IOBUF PORT "sdram_dq[5]" IO_TYPE=LVCMOS33;
LOCATE COMP "sdram_dq[6]" SITE "H1"; IOBUF PORT "sdram_dq[6]" IO_TYPE=LVCMOS33;
LOCATE COMP "sdram_dq[7]" SITE "J1"; IOBUF PORT "sdram_dq[7]" IO_TYPE=LVCMOS33;
LOCATE COMP "sdram_dq[8]" SITE "K1"; IOBUF PORT "sdram_dq[8]" IO_TYPE=LVCMOS33;
LOCATE COMP "sdram_dq[9]" SITE "K4"; IOBUF PORT "sdram_dq[9]" IO_TYPE=LVCMOS33;
LOCATE COMP "sdram_dq[10]" SITE "L4"; IOBUF PORT "sdram_dq[10]" IO_TYPE=LVCMOS33;
LOCATE COMP "sdram_dq[11]" SITE "L5"; IOBUF PORT "sdram_dq[11]" IO_TYPE=LVCMOS33;
LOCATE COMP "sdram_dq[12]" SITE "M5"; IOBUF PORT "sdram_dq[12]" IO_TYPE=LVCMOS33;
LOCATE COMP "sdram_dq[13]" SITE "M4"; IOBUF PORT "sdram_dq[13]" IO_TYPE=LVCMOS33;
LOCATE COMP "sdram_dq[14]" SITE "N4"; IOBUF PORT "sdram_dq[14]" IO_TYPE=LVCMOS33;
LOCATE COMP "sdram_dq[15]" SITE "N5"; IOBUF PORT "sdram_dq[15]" IO_TYPE=LVCMOS33;
LOCATE COMP "sdram_dqm[0]" SITE "P5"; IOBUF PORT "sdram_dqm[0]" IO_TYPE=LVCMOS33;
LOCATE COMP "sdram_dqm[1]" SITE "N3"; IOBUF PORT "sdram_dqm[1]" IO_TYPE=LVCMOS33;
// All 16 top-level ports of fpga_neural_v2_top are now real-ball
// assigned: osc_clk, ext_rst_n, spi_sclk, spi_mosi, spi_miso,
// spi_cs_n, sdram_cke, sdram_cs_n, sdram_ras_n, sdram_cas_n,
// sdram_we_n, sdram_ba[1:0], sdram_a[11:0], sdram_dq[15:0],
// sdram_dqm[1:0], pll_locked -- no placeholders remain in THIS LPF.
hardware/v2/docs/DatasheetLatex/FPGA-Neural-V2-Datasheet-EN.aux
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\relax
\providecommand \babel@aux [2]{\global \let \babel@toc \@gobbletwo }
\@nameuse{bbl@beforestart}
\providecommand\hyper@newdestlabel[2]{}
\providecommand\HyField@AuxAddToFields[1]{}
\providecommand\HyField@AuxAddToCoFields[2]{}
\babel@aux{english}{}
\pgfsyspdfmark {pgfid1}{5216401}{50184874}
\gdef \LT@i {\LT@entry
{1}{108.73918pt}\LT@entry
{1}{120.12054pt}\LT@entry
{1}{243.45622pt}}
\@input{chapters/01-overview.aux}
\@input{chapters/02-architecture.aux}
\@input{chapters/03-clock-reset.aux}
\@input{chapters/04-host-interface.aux}
\@input{chapters/05-pinout-timing.aux}
\@input{chapters/06-power-configuration.aux}
\@input{chapters/07-benchmarks.aux}
\@input{chapters/08-status-roadmap.aux}
\gdef \@abspage@last{16}
hardware/v2/docs/DatasheetLatex/FPGA-Neural-V2-Datasheet-EN.log
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hardware/v2/docs/DatasheetLatex/FPGA-Neural-V2-Datasheet-EN.out
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\BOOKMARK [0][-]{chapter.1}{\376\377\000O\000v\000e\000r\000v\000i\000e\000w}{}% 1
\BOOKMARK [1][-]{section.1.1}{\376\377\000D\000o\000c\000u\000m\000e\000n\000t\000\040\000s\000c\000o\000p\000e\000\040\000a\000n\000d\000\040\000s\000t\000a\000t\000u\000s\000\040\000l\000a\000b\000e\000l\000s}{chapter.1}% 2
\BOOKMARK [1][-]{section.1.2}{\376\377\000F\000r\000o\000z\000e\000n\000\040\000r\000e\000f\000e\000r\000e\000n\000c\000e\000\040\000c\000o\000n\000f\000i\000g\000u\000r\000a\000t\000i\000o\000n}{chapter.1}% 3
\BOOKMARK [0][-]{chapter.2}{\376\377\000A\000r\000c\000h\000i\000t\000e\000c\000t\000u\000r\000e}{}% 4
\BOOKMARK [1][-]{section.2.1}{\376\377\000C\000o\000m\000p\000u\000t\000e\000:\000\040\000N\000e\000u\000r\000a\000l\000\040\000M\000u\000l\000t\000i\000p\000r\000o\000c\000e\000s\000s\000o\000r}{chapter.2}% 5
\BOOKMARK [1][-]{section.2.2}{\376\377\000U\000n\000i\000f\000i\000e\000d\000\040\000s\000i\000n\000g\000l\000e\000-\000S\000D\000R\000A\000M\000\040\000m\000e\000m\000o\000r\000y}{chapter.2}% 6
\BOOKMARK [1][-]{section.2.3}{\376\377\000R\000e\000a\000d\000-\000t\000i\000m\000i\000n\000g\000\040\000d\000i\000s\000c\000i\000p\000l\000i\000n\000e\000\040\000\050\000E\000R\000R\000-\0000\0000\0002\0005\000\051}{chapter.2}% 7
\BOOKMARK [0][-]{chapter.3}{\376\377\000C\000l\000o\000c\000k\000\040\000a\000n\000d\000\040\000r\000e\000s\000e\000t\000\040\000a\000r\000c\000h\000i\000t\000e\000c\000t\000u\000r\000e}{}% 8
\BOOKMARK [1][-]{section.3.1}{\376\377\000C\000l\000o\000c\000k\000\040\000g\000e\000n\000e\000r\000a\000t\000i\000o\000n}{chapter.3}% 9
\BOOKMARK [1][-]{section.3.2}{\376\377\000R\000e\000s\000e\000t\000\040\000a\000r\000c\000h\000i\000t\000e\000c\000t\000u\000r\000e}{chapter.3}% 10
\BOOKMARK [0][-]{chapter.4}{\376\377\000H\000o\000s\000t\000\040\000i\000n\000t\000e\000r\000f\000a\000c\000e\000\040\000\050\000S\000P\000I\000\051}{}% 11
\BOOKMARK [1][-]{section.4.1}{\376\377\000O\000p\000c\000o\000d\000e\000s}{chapter.4}% 12
\BOOKMARK [1][-]{section.4.2}{\376\377\000V\000e\000r\000i\000f\000i\000c\000a\000t\000i\000o\000n}{chapter.4}% 13
\BOOKMARK [0][-]{chapter.5}{\376\377\000P\000i\000n\000o\000u\000t\000,\000\040\000p\000l\000a\000c\000e\000-\000a\000n\000d\000-\000r\000o\000u\000t\000e\000,\000\040\000a\000n\000d\000\040\000t\000i\000m\000i\000n\000g}{}% 14
\BOOKMARK [1][-]{section.5.1}{\376\377\000F\000i\000n\000a\000l\000\040\000p\000i\000n\000o\000u\000t}{chapter.5}% 15
\BOOKMARK [1][-]{section.5.2}{\376\377\000S\000y\000n\000t\000h\000e\000s\000i\000s\000\040\000\050\000r\000e\000a\000l\000,\000\040\000t\000h\000i\000s\000\040\000r\000e\000v\000i\000s\000i\000o\000n\000\051}{chapter.5}% 16
\BOOKMARK [1][-]{section.5.3}{\376\377\000P\000l\000a\000c\000e\000\040\000a\000n\000d\000\040\000r\000o\000u\000t\000e\000:\000\040\0008\000-\000s\000e\000e\000d\000\040\000t\000i\000m\000i\000n\000g\000\040\000t\000a\000b\000l\000e}{chapter.5}% 17
\BOOKMARK [0][-]{chapter.6}{\376\377\000P\000o\000w\000e\000r\000,\000\040\000S\000D\000R\000A\000M\000\040\000e\000l\000e\000c\000t\000r\000i\000c\000a\000l\000,\000\040\000a\000n\000d\000\040\000c\000o\000n\000f\000i\000g\000u\000r\000a\000t\000i\000o\000n}{}% 18
\BOOKMARK [1][-]{section.6.1}{\376\377\000P\000o\000w\000e\000r\000\040\000a\000r\000c\000h\000i\000t\000e\000c\000t\000u\000r\000e\000\040\040\023\000\040\000s\000t\000a\000t\000u\000s\000:\000\040\000O\000P\000E\000N}{chapter.6}% 19
\BOOKMARK [1][-]{section.6.2}{\376\377\000S\000D\000R\000A\000M\000\040\000e\000l\000e\000c\000t\000r\000i\000c\000a\000l\000\040\000/\000\040\000t\000i\000m\000i\000n\000g\000\040\000s\000i\000g\000n\000-\000o\000f\000f\000\040\040\023\000\040\000s\000t\000a\000t\000u\000s\000:\000\040\000P\000A\000R\000T\000I\000A\000L}{chapter.6}% 20
\BOOKMARK [1][-]{section.6.3}{\376\377\000C\000o\000n\000f\000i\000g\000u\000r\000a\000t\000i\000o\000n\000\040\040\023\000\040\000s\000t\000a\000t\000u\000s\000:\000\040\000O\000P\000E\000N}{chapter.6}% 21
\BOOKMARK [0][-]{chapter.7}{\376\377\000B\000e\000n\000c\000h\000m\000a\000r\000k\000s}{}% 22
\BOOKMARK [1][-]{section.7.1}{\376\377\000I\000n\000t\000e\000r\000n\000a\000l\000\040\000b\000e\000n\000c\000h\000m\000a\000r\000k\000:\000\040\000D\000-\000S\000t\000r\000e\000s\000s\000\040\000w\000o\000r\000k\000l\000o\000a\000d}{chapter.7}% 23
\BOOKMARK [1][-]{section.7.2}{\376\377\000H\000o\000s\000t\000-\000i\000n\000t\000e\000r\000f\000a\000c\000e\000\040\000p\000a\000c\000i\000n\000g\000\040\000b\000e\000n\000c\000h\000m\000a\000r\000k}{chapter.7}% 24
\BOOKMARK [1][-]{section.7.3}{\376\377\000S\000o\000f\000t\000w\000a\000r\000e\000\040\000r\000e\000f\000e\000r\000e\000n\000c\000e\000\040\000c\000o\000m\000p\000a\000r\000i\000s\000o\000n}{chapter.7}% 25
\BOOKMARK [0][-]{chapter.8}{\376\377\000C\000h\000i\000p\000\040\000r\000e\000a\000d\000i\000n\000e\000s\000s\000\040\000a\000n\000d\000\040\000r\000o\000a\000d\000m\000a\000p}{}% 26
\BOOKMARK [1][-]{section.8.1}{\376\377\000P\000r\000e\000c\000i\000s\000e\000\040\000r\000e\000a\000d\000i\000n\000e\000s\000s\000\040\000c\000h\000e\000c\000k\000l\000i\000s\000t}{chapter.8}% 27
\BOOKMARK [1][-]{section.8.2}{\376\377\000F\000i\000n\000a\000l\000\040\000a\000n\000s\000w\000e\000r}{chapter.8}% 28
\BOOKMARK [1][-]{section.8.3}{\376\377\000R\000o\000a\000d\000m\000a\000p}{chapter.8}% 29
hardware/v2/docs/DatasheetLatex/FPGA-Neural-V2-Datasheet-EN.pdf
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% ======================================================================
% FPGA-Neural V2 -- INT8 Neural Network Engine, single-SDRAM architecture
% Datasheet / Technical reference manual
% Repository: github.com/manvalan/FPGA-Neural
% Ported from the V1 LaTeX datasheet (hardware/v1/docs/DatasheetLatex/):
% same preamble, macros, typography, and title-page/features-page
% structure -- content rewritten for the V2 architecture throughout.
% ======================================================================
\documentclass[11pt,a4paper,openany]{report}
\newcommand{\datasheetrev}{B0}
\newcommand{\datasheetdate}{September 2026}
\input{preamble}
\begin{document}
\sloppy
% ======================================================================
% TITLE PAGE
% ======================================================================
\begin{titlepage}
\thispagestyle{empty}
\begin{tikzpicture}[remember picture,overlay]
\fill[fnDark] (current page.north west) rectangle
([yshift=-4.3cm]current page.north east);
\fill[fnTeal] ([yshift=-4.3cm]current page.north west) rectangle
([yshift=-4.55cm]current page.north east);
\node[anchor=north west,text=white,font=\Huge\bfseries]
at ([xshift=2.2cm,yshift=-1.15cm]current page.north west)
{FPGA\,--\,Neural V2};
\node[anchor=north west,text=fnLight,font=\large]
at ([xshift=2.25cm,yshift=-2.15cm]current page.north west)
{INT8 Neural Multiprocessor, unified single-SDRAM architecture};
\node[anchor=north west,text=fnLight2,font=\normalsize]
at ([xshift=2.25cm,yshift=-2.85cm]current page.north west)
{Parametric N-processor hardware accelerator -- Datasheet and reference manual};
\node[anchor=north east,text=white,font=\ttfamily\small]
at ([xshift=-2.2cm,yshift=-3.55cm]current page.north east)
{Rev.~\datasheetrev~~\textbullet~~\datasheetdate};
\end{tikzpicture}
\vspace*{5.0cm}
% --- compact block diagram on the title page ---
\begin{center}
\begin{tikzpicture}[node distance=7mm and 12mm]
\node[fnblockD,minimum width=30mm] (host) {HOST\\{\scriptsize MCU / PC (SPI master)}};
\node[fnblockT,right=18mm of host,minimum width=34mm] (fpga)
{FPGA\\{\scriptsize Neural Multiprocessor, N=4}};
\node[fnblock,right=18mm of fpga,minimum width=26mm] (ram)
{SDRAM\\{\scriptsize 8\,MB, unified}};
\draw[fnbus] (host) -- node[fnlbl,above]{SPI Mode 0} (fpga);
\draw[fnbus] (fpga) -- node[fnlbl,above]{16-bit, single chip} (ram);
\node[below=1mm of fpga,font=\scriptsize\itshape,text=fnGrey]
{weights + activations + results, ONE physical memory};
\end{tikzpicture}
\end{center}
\vfill
\begin{center}
\begin{tikzpicture}
\node[draw=fnRule,rounded corners=3pt,inner sep=10pt,fill=fnLight,text width=15.5cm]{
\footnotesize
\textbf{\color{fnDark}Reference target device:} Lattice ECP5 \code{LFE5U-45F-8BG381}
(speed grade $-8$, CABGA381, 72$\times$MULT18X18D, $\approx$44k LUT).\\[2pt]
\textbf{\color{fnDark}Baseline configuration:} INT8/INT32, \code{N\_PROCESSORS}=4,
\code{P\_IN}=8, single external SDRAM Alliance Memory \code{AS4C4M16SA-6TIN}
(weights + activations + results, unified). No PSRAM anywhere in the V2
physical path.\\[2pt]
\textbf{\color{fnDark}Clock:} 16\,MHz board oscillator $\rightarrow$ real
ECP5 \code{EHXPLLL} $\rightarrow$ 64\,MHz system clock, timing-closed
across 8 real place-and-route seeds (worst 68.51\,MHz, best 74.17\,MHz).\\[2pt]
\textbf{\color{fnDark}Host:} real SPI protocol engine
(\code{spi\_host\_bridge.v}) -- WRITE\_JOB / WRITE\_MEM / READ\_MEM /
STATUS / RESET.\\[2pt]
\textbf{\color{fnDark}Status:} RTL verified in simulation (Verilator,
bit-exact), real synthesis (Yosys) and real place-and-route
(nextpnr-ecp5). No fabricated hardware exists -- see \S\ref{ch:status}
for the precise, itemized readiness state. Document describing the
project as of \datasheetdate.
};
\end{tikzpicture}
\end{center}
\vspace{0.6cm}
{\footnotesize\color{fnGrey}\raggedright
Project author: Michele Bigi \textbullet{} MIKILAB / manvalan.\\
This datasheet documents the RTL code, documentation and benchmarks
present in the repository \texttt{github.com/manvalan/FPGA-Neural},
ported from the V1 datasheet's own LaTeX structure (same preamble and
macros, content rewritten for V2).\par}
\end{titlepage}
% ======================================================================
% "FEATURES" PAGE (datasheet style)
% ======================================================================
\input{chapters/00-features}
% ======================================================================
% TABLE OF CONTENTS
% ======================================================================
\newpage
\pagenumbering{roman}
{\color{fnDark}\tableofcontents}
\newpage
\pagenumbering{arabic}
% ======================================================================
% CHAPTERS
% ======================================================================
\include{chapters/01-overview}
\include{chapters/02-architecture}
\include{chapters/03-clock-reset}
\include{chapters/04-host-interface}
\include{chapters/05-pinout-timing}
\include{chapters/06-power-configuration}
\include{chapters/07-benchmarks}
\include{chapters/08-status-roadmap}
\end{document}
hardware/v2/docs/DatasheetLatex/FPGA-Neural-V2-Datasheet-EN.toc
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\babel@toc {english}{}\relax
\contentsline {chapter}{\numberline {1}Overview}{1}{chapter.1}%
\contentsline {section}{\numberline {1.1}Document scope and status labels}{1}{section.1.1}%
\contentsline {section}{\numberline {1.2}Frozen reference configuration}{1}{section.1.2}%
\contentsline {chapter}{\numberline {2}Architecture}{2}{chapter.2}%
\contentsline {section}{\numberline {2.1}Compute: Neural Multiprocessor}{2}{section.2.1}%
\contentsline {section}{\numberline {2.2}Unified single-SDRAM memory}{2}{section.2.2}%
\contentsline {section}{\numberline {2.3}Read-timing discipline (ERR-0025)}{3}{section.2.3}%
\contentsline {chapter}{\numberline {3}Clock and reset architecture}{4}{chapter.3}%
\contentsline {section}{\numberline {3.1}Clock generation}{4}{section.3.1}%
\contentsline {section}{\numberline {3.2}Reset architecture}{4}{section.3.2}%
\contentsline {chapter}{\numberline {4}Host interface (SPI)}{5}{chapter.4}%
\contentsline {section}{\numberline {4.1}Opcodes}{5}{section.4.1}%
\contentsline {section}{\numberline {4.2}Verification}{5}{section.4.2}%
\contentsline {chapter}{\numberline {5}Pinout, place-and-route, and timing}{6}{chapter.5}%
\contentsline {section}{\numberline {5.1}Final pinout}{6}{section.5.1}%
\contentsline {section}{\numberline {5.2}Synthesis (real, this revision)}{6}{section.5.2}%
\contentsline {section}{\numberline {5.3}Place and route: 8-seed timing table}{6}{section.5.3}%
\contentsline {chapter}{\numberline {6}Power, SDRAM electrical, and configuration}{8}{chapter.6}%
\contentsline {section}{\numberline {6.1}Power architecture -- status: OPEN}{8}{section.6.1}%
\contentsline {section}{\numberline {6.2}SDRAM electrical / timing sign-off -- status: PARTIAL}{8}{section.6.2}%
\contentsline {section}{\numberline {6.3}Configuration -- status: OPEN}{8}{section.6.3}%
\contentsline {chapter}{\numberline {7}Benchmarks}{9}{chapter.7}%
\contentsline {section}{\numberline {7.1}Internal benchmark: D-Stress workload}{9}{section.7.1}%
\contentsline {section}{\numberline {7.2}Host-interface pacing benchmark}{9}{section.7.2}%
\contentsline {section}{\numberline {7.3}Software reference comparison}{9}{section.7.3}%
\contentsline {chapter}{\numberline {8}Chip readiness and roadmap}{11}{chapter.8}%
\contentsline {section}{\numberline {8.1}Precise readiness checklist}{11}{section.8.1}%
\contentsline {section}{\numberline {8.2}Final answer}{11}{section.8.2}%
\contentsline {section}{\numberline {8.3}Roadmap}{11}{section.8.3}%
hardware/v2/docs/DatasheetLatex/chapters/00-features.tex
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\thispagestyle{plain}
\noindent
\begin{tikzpicture}
\node[fill=fnDark,text=white,rounded corners=2pt,inner sep=6pt,
minimum width=\textwidth,anchor=west]
{\large\bfseries FPGA-Neural V2 --- General description and features};
\end{tikzpicture}
\vspace{6pt}
\noindent
{\small FPGA-Neural V2 is a \textbf{parametric hardware neural
multiprocessor} built around \code{N\_PROCESSORS} independent INT8 MAC
engines dispatched by a real dependency-graph scheduler
(Dependency Manager $\to$ Neural Director $\to$ per-slot Memory
Manager), streaming weight/activation tiles from, and writing results
to, a \textbf{single external SDRAM chip} -- no PSRAM, no second
memory device anywhere in the V2 physical path. Job registration is
via a real SPI host protocol engine; the host never participates in
the compute datapath.}
\vspace{8pt}
\begin{multicols}{2}
{\color{fnDark}\large\bfseries Features}\\[2pt]
{\footnotesize
\begin{itemize}[leftmargin=1.1em]
\item \textbf{INT8 $\times$ INT8 $\to$ INT32} datapath per processor,
\code{P\_IN}=8-wide parallel MAC, balanced adder tree.
\item \textbf{N\_PROCESSORS} independent Neural Processors (frozen
reference: N=4; N=2 also fully validated; N=8 is a future
evolution).
\item \textbf{Unified single-SDRAM memory}: weights, activations, AND
results all share ONE physical Alliance Memory
\code{AS4C4M16SA-6TIN} (8\,MB, 16-bit), through one
\code{sdram\_unified\_backend} arbitrating a read-only,
cached weight (W) port and a read/write, byte-maskable
activation+result (AR) port.
\item Real dependency-graph scheduling: the Dependency Manager tracks
per-node WAITING/READY/DISPATCHED state and producer/consumer
wake-up; the Neural Director allocates the first free processor
slot.
\item \textbf{Real SPI host protocol engine}
(\code{spi\_host\_bridge.v}): \code{WRITE\_JOB} (job
registration), \code{WRITE\_MEM}/\code{READ\_MEM} (raw SDRAM
access), \code{STATUS}, \code{RESET}.
\item \textbf{Real ECP5 clock generation}: 16\,MHz oscillator
$\to$ \code{EHXPLLL} (real Project Trellis \code{ecppll}
parameters) $\to$ 64\,MHz system clock.
\item Real reset architecture (\code{reset\_sync.v}): asynchronous
assertion, synchronous deassertion, gated by external POR and
PLL lock.
\item Verified in \textbf{simulation} (Verilator, bit-exact) and real
synthesis + place-and-route (Yosys + nextpnr-ecp5).
\end{itemize}}
\columnbreak
{\color{fnDark}\large\bfseries Applications}\\[2pt]
{\footnotesize
\begin{itemize}[leftmargin=1.1em]
\item Deterministic low-latency inference as an SPI peripheral of a
microcontroller or SoC host.
\item Reusable dependency-graph compute fabric, not a single fixed
network topology.
\item Edge AI on compact, INT8-quantized dense/DAG-structured
networks.
\item Off-loading neural workload from a constrained host CPU to
dedicated hardware with predictable, measured throughput.
\end{itemize}}
\vspace{4pt}
{\color{fnDark}\large\bfseries Target \& toolchain}\\[2pt]
{\footnotesize
\begin{itemize}[leftmargin=1.1em]
\item FPGA: Lattice ECP5 \code{LFE5U-45F-8BG381} ($-8$, CABGA381).
\item Synthesis: Yosys; place\&route: nextpnr-ecp5.
\item Simulation: Verilator (trusted per this project's own DEC-0004
protocol) and Icarus Verilog (cross-checked).
\item SDRAM: Alliance Memory \code{AS4C4M16SA-6TIN} (4M$\times$16, 8\,MB).
\end{itemize}}
\end{multicols}
\vspace{2pt}
% --- key parameter table ---
\noindent
{\small\color{fnDark}\bfseries Key parameters (frozen V2 reference configuration)}
\vspace{2pt}
\noindent
\begin{tabularx}{\textwidth}{L{3.4cm}L{3.8cm}Y}
\toprule
\rowh \thd{Quantity} & \thd{Value} & \thd{Notes} \\
\midrule
Data precision & INT8 (signed) & \code{DATA\_WIDTH}=8 \\
\rowa Accumulator & INT32 (signed) & \code{ACC\_WIDTH}=32 \\
Processors & 4 (N=2 also validated) & \code{N\_PROCESSORS} \\
\rowa MAC width per processor & 8 & \code{P\_IN}=8 \\
Activation & ReLU + INT8 saturate & fixed, matches golden model \\
\rowa External memory & 1 $\times$ SDRAM, 8\,MB & \code{AS4C4M16SA-6TIN}, unified \\
System clock & 64\,MHz (real P\&R, 8/8 seeds PASS) & 16\,MHz osc.\ $\to$ EHXPLLL \\
\rowa Bit-exact regression & 256/256, N=2 and N=4 & Verilator, D-Stress workload \\
Host interface & real SPI (4 pins) & \code{spi\_host\_bridge.v} \\
\bottomrule
\end{tabularx}
\vspace{8pt}
\noindent
{\small\color{fnDark}\bfseries System block diagram}
\begin{center}
\begin{tikzpicture}[node distance=6mm and 10mm,font=\footnotesize]
\node[fnblockD,minimum width=26mm,minimum height=13mm] (host){HOST\\{\scriptsize SPI master}};
\node[fnblockT,right=16mm of host,minimum width=56mm,minimum height=24mm] (eng){};
\node[anchor=north,font=\footnotesize\bfseries,text=fnDark] at (eng.north){FPGA -- Neural Multiprocessor (N=4)};
\node[fnreg,fill=white] (spi) at ([yshift=-3mm]eng.center){\code{spi\_host\_bridge} + Dependency Manager};
\node[fnreg,fill=white,below=2.5mm of spi] (mm){Neural Director $\to$ 4$\times$ Memory Manager $\to$ Neural Processor};
\node[fnreg,fill=white,above=2.5mm of spi] (be){\code{sdram\_unified\_backend} (W + AR arbitration)};
\node[fnblock,right=16mm of eng,minimum width=24mm,minimum height=13mm] (ram){SDRAM 8\,MB\\{\scriptsize unified: W+A+R}};
\draw[fnbus] (host) -- node[fnlbl,above]{SPI} (eng.west|-host);
\draw[fnbus] (eng.east|-ram) -- node[fnlbl,above]{16-bit} (ram);
\end{tikzpicture}
\end{center}
\begin{center}\footnotesize\itshape\color{fnGrey}
Weights, activations and results all share the single physical SDRAM;
the host only registers jobs and reads back results over SPI.\end{center}
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@@ -0,0 +1,53 @@
\relax
\providecommand\hyper@newdestlabel[2]{}
\gdef \LT@ii {\LT@entry
{1}{125.81102pt}\LT@entry
{1}{346.50493pt}}
\@writefile{toc}{\contentsline {chapter}{\numberline {1}Overview}{1}{chapter.1}\protected@file@percent }
\@writefile{lof}{\addvspace {10\p@ }}
\@writefile{lot}{\addvspace {10\p@ }}
\@writefile{toc}{\contentsline {section}{\numberline {1.1}Document scope and status labels}{1}{section.1.1}\protected@file@percent }
\newlabel{sec:status-labels}{{1.1}{1}{Document scope and status labels}{section.1.1}{}}
\@writefile{toc}{\contentsline {section}{\numberline {1.2}Frozen reference configuration}{1}{section.1.2}\protected@file@percent }
\@setckpt{chapters/01-overview}{
\setcounter{page}{2}
\setcounter{equation}{0}
\setcounter{enumi}{3}
\setcounter{enumii}{0}
\setcounter{enumiii}{0}
\setcounter{enumiv}{0}
\setcounter{footnote}{0}
\setcounter{mpfootnote}{0}
\setcounter{part}{0}
\setcounter{chapter}{1}
\setcounter{section}{2}
\setcounter{subsection}{0}
\setcounter{subsubsection}{0}
\setcounter{paragraph}{0}
\setcounter{subparagraph}{0}
\setcounter{figure}{0}
\setcounter{table}{1}
\setcounter{LT@tables}{2}
\setcounter{LT@chunks}{1}
\setcounter{parentequation}{0}
\setcounter{tcbbreakpart}{0}
\setcounter{tcblayer}{0}
\setcounter{tcolorbox@number}{0}
\setcounter{tcbrastercolumn}{1}
\setcounter{tcbrasterrow}{1}
\setcounter{tcbrasternum}{1}
\setcounter{tcbraster}{0}
\setcounter{lstnumber}{1}
\setcounter{tcblisting}{0}
\setcounter{caption@flags}{0}
\setcounter{continuedfloat}{0}
\setcounter{tikztiming@nrows}{0}
\setcounter{tikztimingrows}{0}
\setcounter{tikztimingtrans}{0}
\setcounter{tikztimingtranspos}{0}
\setcounter{section@level}{0}
\setcounter{Item}{3}
\setcounter{Hfootnote}{0}
\setcounter{bookmark@seq@number}{3}
\setcounter{lstlisting}{0}
}
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\chapter{Overview}
FPGA-Neural V2 succeeds V1 with three architectural changes, all
frozen and verified in this revision:
\begin{enumerate}
\item \textbf{Neural multiprocessor}: N\_PROCESSORS (4, frozen
reference) independent Neural Processors instead of V1's single
engine, scheduled by a real dependency-graph Dependency Manager and
Neural Director.
\item \textbf{Unified single-SDRAM memory}: one physical Alliance
Memory \code{AS4C4M16SA-6TIN} SDRAM serves weights, activations,
\emph{and} results. V1's PSRAM (\code{IS66WVE4M16EBLL-70BLI}) and
its controller are not part of V2's physical path at all.
\item \textbf{Real physical host interface}: a from-scratch SPI
protocol engine (\code{spi\_host\_bridge.v}) replaces the internal
110-pin \code{reg\_*} testbench bus as the board-level top's own
physical interface.
\end{enumerate}
V1 itself (\code{hardware/v1/**}) is untouched and remains the golden,
independently certified reference design; V2 shares no RTL file with
it.
\section{Document scope and status labels}
\label{sec:status-labels}
This datasheet distinguishes explicitly between:
\begin{itemize}
\item \textbf{RTL verified} -- verified through RTL simulation only.
\item \textbf{Simulation verified} -- verified in simulation for the
specific configuration named.
\item \textbf{Synthesis verified} -- synthesizes cleanly for the
target FPGA (Yosys, real run, zero unintended latches or
multi-driver issues beyond a small, previously-reviewed benign set).
\item \textbf{P\&R verified} -- successfully placed, routed, and
timing-analyzed by nextpnr-ecp5 for a real, ball-assigned LPF.
\item \textbf{Hardware designed} -- schematic/PCB electrically
designed but not fabricated.
\item \textbf{Hardware validated} -- physically tested on fabricated
hardware.
\item \textbf{Silicon validated} -- the actual physical FPGA has been
programmed and tested.
\end{itemize}
As of \datasheetdate, V2 is \textbf{RTL verified}, \textbf{simulation
verified} (bit-exact), \textbf{synthesis verified}, and \textbf{P\&R
verified}. No item in this datasheet is presented as hardware- or
silicon-validated -- no fabricated V2 board exists. See
Chapter~\ref{ch:status} for the complete, itemized status.
\section{Frozen reference configuration}
\begin{tabularx}{\textwidth}{L{4cm}Y}
\toprule
\rowh \thd{Parameter} & \thd{Value} \\
\midrule
FPGA & Lattice \code{LFE5U-45F-8BG381}, speed grade $-8$, CABGA381 \\
\rowa N\_PROCESSORS & 4 (frozen reference; N=2 also fully validated) \\
P\_IN & 8 (MAC width per processor) \\
\rowa ACC\_WIDTH & 32 \\
External memory & 1 $\times$ SDRAM, Alliance Memory \code{AS4C4M16SA-6TIN}, 8\,MB \\
\rowa Oscillator & 16\,MHz (board-level, external) \\
System clock & 64\,MHz, generated by a real ECP5 \code{EHXPLLL} \\
\rowa Host interface & real SPI (4 pins), \code{spi\_host\_bridge.v} \\
\bottomrule
\end{tabularx}
hardware/v2/docs/DatasheetLatex/chapters/02-architecture.aux
+54
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@@ -0,0 +1,54 @@
\relax
\providecommand\hyper@newdestlabel[2]{}
\gdef \LT@iii {\LT@entry
{1}{103.04872pt}\LT@entry
{1}{103.04872pt}\LT@entry
{1}{266.2185pt}}
\@writefile{toc}{\contentsline {chapter}{\numberline {2}Architecture}{2}{chapter.2}\protected@file@percent }
\@writefile{lof}{\addvspace {10\p@ }}
\@writefile{lot}{\addvspace {10\p@ }}
\@writefile{toc}{\contentsline {section}{\numberline {2.1}Compute: Neural Multiprocessor}{2}{section.2.1}\protected@file@percent }
\@writefile{toc}{\contentsline {section}{\numberline {2.2}Unified single-SDRAM memory}{2}{section.2.2}\protected@file@percent }
\@writefile{toc}{\contentsline {section}{\numberline {2.3}Read-timing discipline (ERR-0025)}{3}{section.2.3}\protected@file@percent }
\@setckpt{chapters/02-architecture}{
\setcounter{page}{4}
\setcounter{equation}{0}
\setcounter{enumi}{3}
\setcounter{enumii}{0}
\setcounter{enumiii}{0}
\setcounter{enumiv}{0}
\setcounter{footnote}{0}
\setcounter{mpfootnote}{0}
\setcounter{part}{0}
\setcounter{chapter}{2}
\setcounter{section}{3}
\setcounter{subsection}{0}
\setcounter{subsubsection}{0}
\setcounter{paragraph}{0}
\setcounter{subparagraph}{0}
\setcounter{figure}{0}
\setcounter{table}{1}
\setcounter{LT@tables}{3}
\setcounter{LT@chunks}{1}
\setcounter{parentequation}{0}
\setcounter{tcbbreakpart}{0}
\setcounter{tcblayer}{0}
\setcounter{tcolorbox@number}{0}
\setcounter{tcbrastercolumn}{1}
\setcounter{tcbrasterrow}{1}
\setcounter{tcbrasternum}{1}
\setcounter{tcbraster}{0}
\setcounter{lstnumber}{1}
\setcounter{tcblisting}{0}
\setcounter{caption@flags}{0}
\setcounter{continuedfloat}{0}
\setcounter{tikztiming@nrows}{0}
\setcounter{tikztimingrows}{0}
\setcounter{tikztimingtrans}{0}
\setcounter{tikztimingtranspos}{0}
\setcounter{section@level}{0}
\setcounter{Item}{3}
\setcounter{Hfootnote}{0}
\setcounter{bookmark@seq@number}{7}
\setcounter{lstlisting}{0}
}
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\chapter{Architecture}
\section{Compute: Neural Multiprocessor}
Each of the \code{N\_PROCESSORS} Neural Processors is an independent
INT8 datapath: \code{P\_IN}=8 parallel multipliers feeding a balanced
binary adder tree into a 32-bit accumulator, followed by ReLU and INT8
saturation -- byte-for-byte identical to \code{neural\_processor.v},
unmodified since before the V2 single-SDRAM freeze. Job dispatch is a
real dependency-graph pipeline:
\begin{center}
\begin{tikzpicture}[node distance=5mm and 6mm,font=\scriptsize]
\node[fnreg] (host) {SPI host\\bridge};
\node[fnreg,right=of host] (dm) {Dependency\\Manager};
\node[fnreg,right=of dm] (dir) {Neural\\Director};
\node[fnreg,below=of dir] (mm) {Memory Manager\\(per slot)};
\node[fnreg,left=of mm] (np) {Neural\\Processor};
\draw[fnarrow] (host) -- (dm);
\draw[fnarrow] (dm) -- (dir);
\draw[fnarrow] (dir) -- (mm);
\draw[fnarrow] (mm) -- (np);
\end{tikzpicture}
\end{center}
The Dependency Manager holds a per-node table (state, required/
resolved producer count, job descriptor fields) and hands READY nodes
to the Director one at a time (valid/ready, backpressure-safe). The
Director allocates the first free processor slot (first-free, not
load-balanced) and frees it the instant that slot's job completes.
\section{Unified single-SDRAM memory}
\begin{center}
\begin{tikzpicture}[node distance=6mm and 10mm,font=\footnotesize]
\node[fnblockT,minimum width=50mm,minimum height=20mm] (fpga){};
\node[anchor=north,font=\bfseries,text=fnDark] at (fpga.north){FPGA};
\node[fnreg,fill=white] (np) at ([yshift=2mm]fpga.center){4$\times$ Neural Processor};
\node[fnreg,fill=white,below=2mm of np] (be){Unified SDRAM Backend / Arbiter};
\node[fnblock,right=16mm of fpga,minimum height=20mm] (ram){\code{AS4C4M16SA-6TIN}\\Weights\\Activations\\Results};
\draw[fnbus] (fpga.east|-be) -- node[fnlbl,above]{16-bit SDRAM bus} (ram);
\end{tikzpicture}
\end{center}
\code{sdram\_unified\_backend.v} owns exactly one \code{sdram\_
controller.v} instance and presents two logical ports:
\begin{itemize}
\item \textbf{W} (weight fetch): 64-bit, read-only, a 4-entry
fully-associative ``other half'' cache (round-robin eviction --
safe under any sizing, since an evicted-too-early entry only costs
an extra real fetch, never wrong data).
\item \textbf{AR} (activation fill + result write-back): 16-bit,
read/write, byte-maskable via real SDR SDRAM DQM semantics
(\code{lb\_n}/\code{ub\_n}).
\end{itemize}
Both ports are, in turn, each arbitrated across the N\_PROCESSORS
slots by a generic, reused \code{slot\_mem\_arbiter} (a proven,
pending-latch-based, single-owner-until-ready design used identically
throughout this project).
\subsection*{Official V2 memory map}
\begin{tabularx}{\textwidth}{L{3.2cm}L{3.2cm}Y}
\toprule
\rowh \thd{Region} & \thd{Base address} & \thd{Notes} \\
\midrule
Weights & \code{0x010000} & 1\,MB-aligned \\
\rowa Activations & \code{0x200000} & 1\,MB-aligned \\
Results & \code{0x300000} & 1\,MB-aligned \\
\bottomrule
\end{tabularx}
All three regions are non-overlapping within the single 8\,MB
(\code{0x000000}--\code{0x7FFFFF}) SDRAM address space. Base addresses
are host-programmable per job (via \code{WRITE\_JOB}'s own
\code{x\_base}/\code{w\_base}/\code{result\_addr} fields), not hard-coded
in the datapath.
\section{Read-timing discipline (ERR-0025)}
The shared weight and activation SRAMs (\code{nms\_weight\_packed.v},
\code{nms\_activation\_replicated.v}) use \textbf{combinational} read
ports, matching the exact 1-cycle latency assumption of the per-slot
Memory Manager's own pipelined read-ahead consumer. An earlier,
registered-read implementation added one uncounted cycle of latency
that a busy, multi-tile job's own prefetch lead time always absorbed
invisibly, but that an uncontested single-tile job exposed on its
first (only) tile -- found and fixed via this revision's own
board-level SPI integration testing, with zero regression to the
existing bit-exact regression suite (identical cycle counts before and
after the fix).
hardware/v2/docs/DatasheetLatex/chapters/03-clock-reset.aux
+49
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@@ -0,0 +1,49 @@
\relax
\providecommand\hyper@newdestlabel[2]{}
\@writefile{toc}{\contentsline {chapter}{\numberline {3}Clock and reset architecture}{4}{chapter.3}\protected@file@percent }
\@writefile{lof}{\addvspace {10\p@ }}
\@writefile{lot}{\addvspace {10\p@ }}
\@writefile{toc}{\contentsline {section}{\numberline {3.1}Clock generation}{4}{section.3.1}\protected@file@percent }
\@writefile{toc}{\contentsline {section}{\numberline {3.2}Reset architecture}{4}{section.3.2}\protected@file@percent }
\@setckpt{chapters/03-clock-reset}{
\setcounter{page}{5}
\setcounter{equation}{0}
\setcounter{enumi}{3}
\setcounter{enumii}{0}
\setcounter{enumiii}{0}
\setcounter{enumiv}{0}
\setcounter{footnote}{0}
\setcounter{mpfootnote}{0}
\setcounter{part}{0}
\setcounter{chapter}{3}
\setcounter{section}{2}
\setcounter{subsection}{0}
\setcounter{subsubsection}{0}
\setcounter{paragraph}{0}
\setcounter{subparagraph}{0}
\setcounter{figure}{0}
\setcounter{table}{0}
\setcounter{LT@tables}{3}
\setcounter{LT@chunks}{1}
\setcounter{parentequation}{0}
\setcounter{tcbbreakpart}{0}
\setcounter{tcblayer}{0}
\setcounter{tcolorbox@number}{0}
\setcounter{tcbrastercolumn}{1}
\setcounter{tcbrasterrow}{1}
\setcounter{tcbrasternum}{1}
\setcounter{tcbraster}{0}
\setcounter{lstnumber}{1}
\setcounter{tcblisting}{0}
\setcounter{caption@flags}{0}
\setcounter{continuedfloat}{0}
\setcounter{tikztiming@nrows}{0}
\setcounter{tikztimingrows}{0}
\setcounter{tikztimingtrans}{0}
\setcounter{tikztimingtranspos}{0}
\setcounter{section@level}{0}
\setcounter{Item}{3}
\setcounter{Hfootnote}{0}
\setcounter{bookmark@seq@number}{10}
\setcounter{lstlisting}{0}
}
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\chapter{Clock and reset architecture}
\section{Clock generation}
\begin{center}
\begin{tikzpicture}[node distance=8mm and 14mm,font=\footnotesize]
\node[fnblockD] (osc){16\,MHz\\oscillator};
\node[fnblockT,right=of osc] (pll){ECP5 \code{EHXPLLL}};
\node[fnblock,right=of pll] (sys){system clock\\64\,MHz};
\draw[fnbus] (osc) -- (pll);
\draw[fnbus] (pll) -- (sys);
\end{tikzpicture}
\end{center}
\code{ecp5\_pll\_sys\_clk.v} instantiates a real \code{EHXPLLL}, with
parameters generated by Project Trellis's own \code{ecppll} utility
(not hand-derived): \code{CLKI\_DIV}=1, \code{CLKFB\_DIV}=4,
\code{CLKOP\_DIV}=9, \code{FEEDBK\_PATH}=\code{CLKOP}, giving a real
VCO frequency of 576\,MHz (within the ECP5's documented 400--800\,MHz
range) and an exact, zero-error 64\,MHz output ($16 \times 4 / 1$,
divided by 9 at the VCO). 64\,MHz was chosen over 80\,MHz specifically
because it is the highest frequency at which \emph{all} measured P\&R
seeds close timing with real margin -- see Chapter~\ref{ch:pinout} for
the full 8-seed table.
Simulation note: \code{EHXPLLL} has no open, licensable behavioral
model (Lattice ships it only inside encrypted simulation libraries).
\code{ecp5\_pll\_sys\_clk.v} therefore provides a declared,
simulation-only bypass under a \code{`SIM} define (\code{clk\_sys}
tied directly to \code{clk\_16mhz}, \code{locked} tied high) -- this is
not, and does not claim to be, a simulation of real PLL lock timing.
\section{Reset architecture}
\begin{center}
\begin{tikzpicture}[node distance=8mm and 14mm,font=\footnotesize]
\node[fnblockD] (por){External POR\\/ supervisor};
\node[fnblockT,right=of por] (rs){\code{reset\_sync.v}};
\node[fnblock,right=of rs] (rst){\code{rst}\\(sync-deassert)};
\node[fnblock,below=6mm of rs] (lock){PLL \code{locked}};
\draw[fnbus] (por) -- (rs);
\draw[fnbus] (rs) -- (rst);
\draw[fnbus] (lock) -- (rs);
\end{tikzpicture}
\end{center}
\code{reset\_sync.v} is a standard async-assert/sync-deassert bridge:
\code{rst} is asserted \emph{immediately} (combinationally) whenever
either the external POR (\code{ext\_rst\_n}, active-low) is asserted
\emph{or} the PLL has not yet reported lock, and is released only
after two flip-flops of the system clock following both conditions
clearing -- so no downstream synchronous logic (SDRAM controller,
compute datapath, SPI bridge) ever sees an asynchronous release edge.
This is a real, RTL-implemented mechanism, not a placeholder: it is
included, unmodified, in every synthesis and P\&R run reported in this
datasheet.
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+54
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@@ -0,0 +1,54 @@
\relax
\providecommand\hyper@newdestlabel[2]{}
\gdef \LT@iv {\LT@entry
{1}{68.9055pt}\LT@entry
{1}{103.04872pt}\LT@entry
{1}{300.36172pt}}
\@writefile{toc}{\contentsline {chapter}{\numberline {4}Host interface (SPI)}{5}{chapter.4}\protected@file@percent }
\@writefile{lof}{\addvspace {10\p@ }}
\@writefile{lot}{\addvspace {10\p@ }}
\@writefile{toc}{\contentsline {section}{\numberline {4.1}Opcodes}{5}{section.4.1}\protected@file@percent }
\@writefile{toc}{\contentsline {section}{\numberline {4.2}Verification}{5}{section.4.2}\protected@file@percent }
\newlabel{sec:host}{{4.2}{5}{Verification}{section.4.2}{}}
\@setckpt{chapters/04-host-interface}{
\setcounter{page}{6}
\setcounter{equation}{0}
\setcounter{enumi}{3}
\setcounter{enumii}{0}
\setcounter{enumiii}{0}
\setcounter{enumiv}{0}
\setcounter{footnote}{0}
\setcounter{mpfootnote}{0}
\setcounter{part}{0}
\setcounter{chapter}{4}
\setcounter{section}{2}
\setcounter{subsection}{0}
\setcounter{subsubsection}{0}
\setcounter{paragraph}{0}
\setcounter{subparagraph}{0}
\setcounter{figure}{0}
\setcounter{table}{1}
\setcounter{LT@tables}{4}
\setcounter{LT@chunks}{1}
\setcounter{parentequation}{0}
\setcounter{tcbbreakpart}{0}
\setcounter{tcblayer}{0}
\setcounter{tcolorbox@number}{0}
\setcounter{tcbrastercolumn}{1}
\setcounter{tcbrasterrow}{1}
\setcounter{tcbrasternum}{1}
\setcounter{tcbraster}{0}
\setcounter{lstnumber}{1}
\setcounter{tcblisting}{0}
\setcounter{caption@flags}{0}
\setcounter{continuedfloat}{0}
\setcounter{tikztiming@nrows}{0}
\setcounter{tikztimingrows}{0}
\setcounter{tikztimingtrans}{0}
\setcounter{tikztimingtranspos}{0}
\setcounter{section@level}{0}
\setcounter{Item}{3}
\setcounter{Hfootnote}{0}
\setcounter{bookmark@seq@number}{13}
\setcounter{lstlisting}{0}
}
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\chapter{Host interface (SPI)}
\code{spi\_host\_bridge.v} is the real, physical host interface for
V2's board-level top (\code{fpga\_neural\_v2\_top.v}). It replaces the
internal 110-pin \code{reg\_*} bus (a simulation/testbench convenience
that must never be represented as a physical board interface) with 4
real pins: \sig{spi\_sclk}, \sig{spi\_mosi}, \sig{spi\_miso},
\sig{spi\_cs\_n}. Mode 0 (CPOL=0/CPHA=0), MSB-first, one opcode per
CS-low period.
\section{Opcodes}
\begin{tabularx}{\textwidth}{L{2cm}L{3.2cm}Y}
\toprule
\rowh \thd{Opcode} & \thd{Name} & \thd{Function} \\
\midrule
\op{0x10} & \op{WRITE\_JOB} & 15-byte payload: node id, required
dependency count, producer ids, \sig{x\_base}, \sig{w\_base},
\sig{n\_tiles}, \sig{result\_addr}. Registers one Dependency Manager
job; \sig{reg\_valid} is held until the same-cycle
\sig{reg\_valid}\,\&\&\,\sig{reg\_ready} acceptance fires. \\
\rowa \op{0x01} & \op{WRITE\_MEM} & word-addressed raw SDRAM write,
via a second, arbitrated AR port. \\
\op{0x02} & \op{READ\_MEM} & word-addressed raw SDRAM read. \\
\rowa \op{0x20} & \op{STATUS} & 1-byte status: job-busy, mem-busy,
sticky last-job-accepted. \\
\op{0x0F} & \op{RESET} & pulses a soft-reset into the compute+memory
core (not the SPI bridge's own state, avoiding a self-reset hazard). \\
\bottomrule
\end{tabularx}
\section{Verification}
\label{sec:host}
The protocol engine is verified in two independent ways:
\begin{itemize}
\item \textbf{Isolated}: \code{tb\_spi\_host\_bridge.v}, 18/18 PASS --
every opcode, including a real DQM-style byte-masked
\op{WRITE\_MEM}.
\item \textbf{End-to-end}: \code{tb\_fpga\_neural\_v2\_top\_smoke.v},
11/11 PASS -- a single job, two jobs back-to-back, two jobs across a
realistic $\sim$85\,\textmu s SPI-paced gap, and a parametric sweep
of inter-job gaps (100\,ns / 5\,000\,ns / 50\,000\,ns), all checked
bit-exact against a software golden model via a real SDRAM backdoor
readback.
\end{itemize}
Both regressions pass with \textbf{zero regression} to the existing
N=2/N=4 D-Stress bit-exact baseline (identical cycle counts before and
after every fix applied during this interface's own development).
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\relax
\providecommand\hyper@newdestlabel[2]{}
\gdef \LT@v {\LT@entry
{1}{85.97733pt}\LT@entry
{1}{57.52458pt}\LT@entry
{1}{40.45274pt}\LT@entry
{1}{288.3613pt}}
\gdef \LT@vi {\LT@entry
{1}{108.73918pt}\LT@entry
{1}{363.57677pt}}
\@writefile{toc}{\contentsline {chapter}{\numberline {5}Pinout, place-and-route, and timing}{6}{chapter.5}\protected@file@percent }
\@writefile{lof}{\addvspace {10\p@ }}
\@writefile{lot}{\addvspace {10\p@ }}
\newlabel{ch:pinout}{{5}{6}{Pinout, place-and-route, and timing}{chapter.5}{}}
\@writefile{toc}{\contentsline {section}{\numberline {5.1}Final pinout}{6}{section.5.1}\protected@file@percent }
\@writefile{toc}{\contentsline {section}{\numberline {5.2}Synthesis (real, this revision)}{6}{section.5.2}\protected@file@percent }
\@writefile{toc}{\contentsline {section}{\numberline {5.3}Place and route: 8-seed timing table}{6}{section.5.3}\protected@file@percent }
\gdef \LT@vii {\LT@entry
{1}{57.52458pt}\LT@entry
{1}{80.28644pt}\LT@entry
{1}{68.9055pt}\LT@entry
{1}{265.59943pt}}
\@setckpt{chapters/05-pinout-timing}{
\setcounter{page}{8}
\setcounter{equation}{0}
\setcounter{enumi}{3}
\setcounter{enumii}{0}
\setcounter{enumiii}{0}
\setcounter{enumiv}{0}
\setcounter{footnote}{0}
\setcounter{mpfootnote}{0}
\setcounter{part}{0}
\setcounter{chapter}{5}
\setcounter{section}{3}
\setcounter{subsection}{0}
\setcounter{subsubsection}{0}
\setcounter{paragraph}{0}
\setcounter{subparagraph}{0}
\setcounter{figure}{0}
\setcounter{table}{3}
\setcounter{LT@tables}{7}
\setcounter{LT@chunks}{1}
\setcounter{parentequation}{0}
\setcounter{tcbbreakpart}{0}
\setcounter{tcblayer}{0}
\setcounter{tcolorbox@number}{0}
\setcounter{tcbrastercolumn}{1}
\setcounter{tcbrasterrow}{1}
\setcounter{tcbrasternum}{1}
\setcounter{tcbraster}{0}
\setcounter{lstnumber}{1}
\setcounter{tcblisting}{0}
\setcounter{caption@flags}{0}
\setcounter{continuedfloat}{0}
\setcounter{tikztiming@nrows}{0}
\setcounter{tikztimingrows}{0}
\setcounter{tikztimingtrans}{0}
\setcounter{tikztimingtranspos}{0}
\setcounter{section@level}{0}
\setcounter{Item}{3}
\setcounter{Hfootnote}{0}
\setcounter{bookmark@seq@number}{17}
\setcounter{lstlisting}{0}
}
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\chapter{Pinout, place-and-route, and timing}
\label{ch:pinout}
\section{Final pinout}
All 44 top-level signals of \code{fpga\_neural\_v2\_top.v} carry a
real ball assignment (\code{v2\_board\_top.lpf}), sourced from the
official Lattice pinout CSV (rev.\ 3.0) and confirmed by a real,
successful nextpnr-ecp5 P\&R run -- \textbf{no placeholders}.
\begin{tabularx}{\textwidth}{L{2.6cm}L{1.6cm}L{1cm}Y}
\toprule
\rowh \thd{Signal} & \thd{Ball} & \thd{Bank} & \thd{Notes} \\
\midrule
\sig{osc\_clk} & H5 & -- & reused from V1's own validated LPF \\
\rowa \sig{ext\_rst\_n} & B4 & -- & reused from V1's own validated LPF \\
\sig{spi\_sclk} & L3 & 6/7 & real, plain GPIO \\
\rowa \sig{spi\_mosi} & M3 & 6/7 & real, plain GPIO \\
\sig{spi\_miso} & L2 & 6/7 & real, plain GPIO \\
\rowa \sig{spi\_cs\_n} & N2 & 6/7 & real, plain GPIO \\
\sig{pll\_locked} & L1 & 6/7 & real, plain GPIO (bring-up/debug) \\
\rowa \sig{sdram\_*} (37 signals) & see LPF & 6/7 & control/address/data/mask bus \\
\bottomrule
\end{tabularx}
All signals are assumed LVCMOS33, matching banks 6/7's own real VCCIO
range and the SDRAM device's own 3.3\,V requirement (not yet
independently cross-verified at the schematic/PCB level -- a
disclosed WARNING, not a blocker).
\section{Synthesis (real, this revision)}
Yosys \code{synth\_ecp5}, target \code{fpga\_neural\_v2\_top}, real
run, zero CHECK-pass problems:
\begin{tabularx}{\textwidth}{L{3.4cm}Y}
\toprule
\rowh \thd{Resource} & \thd{Count} \\
\midrule
\code{TRELLIS\_FF} & 6\,322 \\
\rowa \code{TRELLIS\_COMB} (LUT4 equiv.) & 7\,084 \\
\code{MULT18X18D} & 32 (=\,4 processors $\times$ 8-wide MAC) \\
\rowa \code{EHXPLLL} & 1 (real PLL, confirmed present) \\
\code{DP16KD} & 0 (all small SRAMs synthesize to distributed RAM) \\
\bottomrule
\end{tabularx}
38 unique warnings (43 total), all matching this project's own
previously-reviewed, benign baseline set (a known \code{genvar}
multi-driver artifact in \code{neural\_processor.v}, small-array-to-
register unrolling, and the real SDRAM \code{DQ} tristate bus) -- no
new warnings introduced by the SPI bridge, PLL, or reset synchronizer.
\section{Place and route: 8-seed timing table}
Real nextpnr-ecp5 P\&R, same final top and LPF, 8 distinct seeds,
target 64\,MHz:
\begin{tabularx}{\textwidth}{L{1.6cm}L{2.4cm}L{2cm}Y}
\toprule
\rowh \thd{Seed} & \thd{Fmax (MHz)} & \thd{Result} & \thd{Slack @ 64\,MHz} \\
\midrule
1 & 73.17 & \PASS & +1.958\,ns \\
\rowa 2 & 68.90 & \PASS & +1.111\,ns \\
3 & 72.10 & \PASS & +1.755\,ns \\
\rowa 4 & 68.51 & \PASS & +1.029\,ns (worst) \\
5 & 69.29 & \PASS & +1.193\,ns \\
\rowa 6 & 73.03 & \PASS & +1.931\,ns \\
7 & 74.17 & \PASS & +2.143\,ns (best) \\
\rowa 8 & 70.10 & \PASS & +1.360\,ns \\
\bottomrule
\end{tabularx}
\textbf{8/8 seeds PASS at 64\,MHz} -- worst 68.51\,MHz, best
74.17\,MHz, mean 71.16\,MHz. Every seed also fits with real routing
margin: \code{TRELLIS\_IO}=44/245 (17\%), zero unrouted nets, zero
placement/routing errors, across all 8 runs.
The critical path is routing-dominated (typ.\ 15--20\% logic / 80--85\%
routing) and alternates, seed to seed, between two comparably-tight
structures already documented in this project's own prior timing
investigations: \code{dependency\_manager.v}'s own wide priority-encoder
scan, and \code{sdram\_unified\_backend.v}'s own weight-cache
hit-index logic -- neither is a new defect introduced by this
revision.
Hold timing was not separately reported by this toolchain's standard
summary output and was not independently analyzed this round (an
honest, disclosed OPEN item, not a fabricated PASS).
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+54
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@@ -0,0 +1,54 @@
\relax
\providecommand\hyper@newdestlabel[2]{}
\gdef \LT@viii {\LT@entry
{1}{85.97733pt}\LT@entry
{1}{74.59596pt}\LT@entry
{1}{311.74266pt}}
\@writefile{toc}{\contentsline {chapter}{\numberline {6}Power, SDRAM electrical, and configuration}{8}{chapter.6}\protected@file@percent }
\@writefile{lof}{\addvspace {10\p@ }}
\@writefile{lot}{\addvspace {10\p@ }}
\@writefile{toc}{\contentsline {section}{\numberline {6.1}Power architecture -- status: OPEN}{8}{section.6.1}\protected@file@percent }
\@writefile{toc}{\contentsline {section}{\numberline {6.2}SDRAM electrical / timing sign-off -- status: PARTIAL}{8}{section.6.2}\protected@file@percent }
\@writefile{toc}{\contentsline {section}{\numberline {6.3}Configuration -- status: OPEN}{8}{section.6.3}\protected@file@percent }
\@setckpt{chapters/06-power-configuration}{
\setcounter{page}{9}
\setcounter{equation}{0}
\setcounter{enumi}{3}
\setcounter{enumii}{0}
\setcounter{enumiii}{0}
\setcounter{enumiv}{0}
\setcounter{footnote}{0}
\setcounter{mpfootnote}{0}
\setcounter{part}{0}
\setcounter{chapter}{6}
\setcounter{section}{3}
\setcounter{subsection}{0}
\setcounter{subsubsection}{0}
\setcounter{paragraph}{0}
\setcounter{subparagraph}{0}
\setcounter{figure}{0}
\setcounter{table}{1}
\setcounter{LT@tables}{8}
\setcounter{LT@chunks}{1}
\setcounter{parentequation}{0}
\setcounter{tcbbreakpart}{0}
\setcounter{tcblayer}{0}
\setcounter{tcolorbox@number}{0}
\setcounter{tcbrastercolumn}{1}
\setcounter{tcbrasterrow}{1}
\setcounter{tcbrasternum}{1}
\setcounter{tcbraster}{0}
\setcounter{lstnumber}{1}
\setcounter{tcblisting}{0}
\setcounter{caption@flags}{0}
\setcounter{continuedfloat}{0}
\setcounter{tikztiming@nrows}{0}
\setcounter{tikztimingrows}{0}
\setcounter{tikztimingtrans}{0}
\setcounter{tikztimingtranspos}{0}
\setcounter{section@level}{0}
\setcounter{Item}{3}
\setcounter{Hfootnote}{0}
\setcounter{bookmark@seq@number}{21}
\setcounter{lstlisting}{0}
}
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\chapter{Power, SDRAM electrical, and configuration}
\section{Power architecture -- status: OPEN}
Rail \emph{voltages} are real, DATASHEET VALUEs from the actual ECP5
and \code{AS4C4M16SA-6TIN} datasheets; regulator selection, current
budget, and decoupling are \textbf{not} finalized in this revision.
\begin{tabularx}{\textwidth}{L{2.6cm}L{2.2cm}Y}
\toprule
\rowh \thd{Rail} & \thd{Nominal} & \thd{Status} \\
\midrule
VCC (core) & 1.1\,V & DATASHEET VALUE; regulator TBD \\
\rowa VCCAUX & 2.5\,V & DATASHEET VALUE; regulator TBD \\
VCCIO 6/7 (SDRAM) & 3.3\,V (assumed) & matches SDRAM's own LVCMOS33 need; not independently re-verified \\
\rowa SDRAM VDD/VDDQ & 3.3\,V & DATASHEET VALUE (\code{AS4C4M16SA-6TIN}) \\
\bottomrule
\end{tabularx}
No real power-estimation tool was run against the actual synthesized
netlist this revision; a real, computed current budget therefore
remains an OPEN item, not an invented number.
\section{SDRAM electrical / timing sign-off -- status: PARTIAL}
\code{AS4C4M16SA-6TIN} is a standard JEDEC SDR SDRAM; the controller
(\code{sdram\_controller.v}) implements a real power-up wait, mode
register set, and periodic AUTO REFRESH, verified functionally in
simulation (init/refresh/read/write/burst/masked-write, 40 real
refresh events per D-Stress run, zero corruption). A byte-for-byte
cross-check of the controller's own timing constants against the
device's real datasheet parameters (CAS latency, \sig{tRCD},
\sig{tRP}, refresh interval, setup/hold) was \textbf{not} independently
re-performed this revision -- simulation-level correctness is
established; a dedicated datasheet-parameter audit remains an OPEN
item before board layout.
\section{Configuration -- status: OPEN}
Standard ECP5 JTAG (\sig{TDI}/\sig{TDO}/\sig{TCK}/\sig{TMS}) and
configuration (\sig{PROGRAMN}/\sig{INITN}/\sig{DONE}/\sig{CCLK}) pins
are identified and standard (real balls listed in
\code{docs/pinouts.md}); JTAG remains available regardless of boot
mode. No configuration-flash part number has been selected, and no
SPI-flash-boot-vs-JTAG-only decision has been made this revision.
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+58
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@@ -0,0 +1,58 @@
\relax
\providecommand\hyper@newdestlabel[2]{}
\gdef \LT@ix {\LT@entry
{1}{68.9055pt}\LT@entry
{1}{80.28644pt}\LT@entry
{1}{80.28644pt}\LT@entry
{1}{242.83757pt}}
\gdef \LT@x {\LT@entry
{1}{137.19194pt}\LT@entry
{1}{335.12401pt}}
\@writefile{toc}{\contentsline {chapter}{\numberline {7}Benchmarks}{9}{chapter.7}\protected@file@percent }
\@writefile{lof}{\addvspace {10\p@ }}
\@writefile{lot}{\addvspace {10\p@ }}
\@writefile{toc}{\contentsline {section}{\numberline {7.1}Internal benchmark: D-Stress workload}{9}{section.7.1}\protected@file@percent }
\@writefile{toc}{\contentsline {section}{\numberline {7.2}Host-interface pacing benchmark}{9}{section.7.2}\protected@file@percent }
\@writefile{toc}{\contentsline {section}{\numberline {7.3}Software reference comparison}{9}{section.7.3}\protected@file@percent }
\@setckpt{chapters/07-benchmarks}{
\setcounter{page}{11}
\setcounter{equation}{0}
\setcounter{enumi}{3}
\setcounter{enumii}{0}
\setcounter{enumiii}{0}
\setcounter{enumiv}{0}
\setcounter{footnote}{0}
\setcounter{mpfootnote}{0}
\setcounter{part}{0}
\setcounter{chapter}{7}
\setcounter{section}{3}
\setcounter{subsection}{0}
\setcounter{subsubsection}{0}
\setcounter{paragraph}{0}
\setcounter{subparagraph}{0}
\setcounter{figure}{0}
\setcounter{table}{2}
\setcounter{LT@tables}{10}
\setcounter{LT@chunks}{1}
\setcounter{parentequation}{0}
\setcounter{tcbbreakpart}{0}
\setcounter{tcblayer}{0}
\setcounter{tcolorbox@number}{0}
\setcounter{tcbrastercolumn}{1}
\setcounter{tcbrasterrow}{1}
\setcounter{tcbrasternum}{1}
\setcounter{tcbraster}{0}
\setcounter{lstnumber}{1}
\setcounter{tcblisting}{0}
\setcounter{caption@flags}{0}
\setcounter{continuedfloat}{0}
\setcounter{tikztiming@nrows}{0}
\setcounter{tikztimingrows}{0}
\setcounter{tikztimingtrans}{0}
\setcounter{tikztimingtranspos}{0}
\setcounter{section@level}{0}
\setcounter{Item}{3}
\setcounter{Hfootnote}{0}
\setcounter{bookmark@seq@number}{25}
\setcounter{lstlisting}{0}
}
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\chapter{Benchmarks}
\section{Internal benchmark: D-Stress workload}
256 independent neurons, 128 inputs each (16 tiles of \code{P\_IN}=8),
one shared activation vector -- the project's own existing, reused
benchmark, run against the final, frozen RTL via Verilator.
\begin{tabularx}{\textwidth}{L{2cm}L{2.4cm}L{2.4cm}Y}
\toprule
\rowh \thd{Config} & \thd{Cycles} & \thd{Correctness} & \thd{Latency @ 64\,MHz} \\
\midrule
N=2 & 49\,788 & 256/256 \PASS & 777.9\,\textmu s \\
\rowa N=4 & 49\,771 & 256/256 \PASS & 777.7\,\textmu s \\
\bottomrule
\end{tabularx}
Cycle counts are \textbf{simulation-verified} (Verilator, bit-exact)
and unchanged before/after the ERR-0025 read-timing fix. Latency at
64\,MHz is a \textbf{derived} figure (cycles~/~clock), not an
independently re-simulated wall-clock measurement, and is not a
measured-hardware number (no fabricated board exists).
N=4 barely improves over N=2 on this specific workload
($49\,771$ vs.\ $49\,788$ cycles) because the workload is dominated by
shared-SDRAM and shared-activation-fill traffic, not by raw MAC
throughput -- consistent with this project's own prior STEP17/18
memory-bound-vs-compute-bound findings, not a new anomaly.
\section{Host-interface pacing benchmark}
The board-level SPI smoke test (\S\ref{sec:host}) exercises single-job,
back-to-back, and gap-swept (100\,ns/5\,000\,ns/50\,000\,ns/$\sim$85\,\textmu s)
dispatch patterns -- all 11/11 bit-exact -- establishing that realistic
host pacing does not, itself, change correctness (only the STEP19-era
registered-read bug did, and that is fixed).
\section{Software reference comparison}
\textbf{No physical ESP32 (or other embedded MCU) hardware is
available in this environment.} A real ESP32 benchmark was
\emph{not} performed, and no ESP32 number is estimated or invented
here -- this is a disclosed OPEN item, not a claimed result.
As an honest, clearly-labeled illustrative data point only, the
identical D-Stress arithmetic (256 neurons $\times$ 128 INT8 MACs,
ReLU + INT8 saturate) was compiled (\code{cc~-O2}) and run on the
\emph{development machine itself} (Apple M4, arm64 -- \textbf{not}
an embedded target):
\begin{tabularx}{\textwidth}{L{4.4cm}Y}
\toprule
\rowh \thd{Metric} & \thd{Value} \\
\midrule
Platform & Apple M4 (arm64), \code{cc -O2}, single-threaded scalar C \\
\rowa Latency, full 256-neuron batch & 1.28\,\textmu s \\
Throughput & $2.56\times10^{10}$ MAC/s \\
\bottomrule
\end{tabularx}
On this specific, tiny workload, a modern, auto-vectorizing,
multi-GHz superscalar CPU outperforms the current FPGA design's
\emph{simulated} cycle count in raw latency. This is reported
honestly rather than omitted: FPGA-Neural V2's real value proposition
is a deterministic, low-power, standalone SDRAM-attached accelerator
for hosts that do \emph{not} have this class of CPU (e.g.\ an
ESP32-class microcontroller) -- not a claim of outperforming a
desktop-class processor on this workload size. A real, meaningful
software baseline for THAT comparison requires the actual embedded
target hardware, which remains unavailable this revision.
hardware/v2/docs/DatasheetLatex/chapters/08-status-roadmap.aux
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\relax
\providecommand\hyper@newdestlabel[2]{}
\gdef \LT@xi {\LT@entry
{1}{194.09746pt}\LT@entry
{1}{278.21849pt}}
\@writefile{toc}{\contentsline {chapter}{\numberline {8}Chip readiness and roadmap}{11}{chapter.8}\protected@file@percent }
\@writefile{lof}{\addvspace {10\p@ }}
\@writefile{lot}{\addvspace {10\p@ }}
\newlabel{ch:status}{{8}{11}{Chip readiness and roadmap}{chapter.8}{}}
\@writefile{toc}{\contentsline {section}{\numberline {8.1}Precise readiness checklist}{11}{section.8.1}\protected@file@percent }
\@writefile{toc}{\contentsline {section}{\numberline {8.2}Final answer}{11}{section.8.2}\protected@file@percent }
\@writefile{toc}{\contentsline {section}{\numberline {8.3}Roadmap}{11}{section.8.3}\protected@file@percent }
\@setckpt{chapters/08-status-roadmap}{
\setcounter{page}{13}
\setcounter{equation}{0}
\setcounter{enumi}{3}
\setcounter{enumii}{0}
\setcounter{enumiii}{0}
\setcounter{enumiv}{0}
\setcounter{footnote}{0}
\setcounter{mpfootnote}{0}
\setcounter{part}{0}
\setcounter{chapter}{8}
\setcounter{section}{3}
\setcounter{subsection}{0}
\setcounter{subsubsection}{0}
\setcounter{paragraph}{0}
\setcounter{subparagraph}{0}
\setcounter{figure}{0}
\setcounter{table}{1}
\setcounter{LT@tables}{11}
\setcounter{LT@chunks}{1}
\setcounter{parentequation}{0}
\setcounter{tcbbreakpart}{0}
\setcounter{tcblayer}{0}
\setcounter{tcolorbox@number}{0}
\setcounter{tcbrastercolumn}{1}
\setcounter{tcbrasterrow}{1}
\setcounter{tcbrasternum}{1}
\setcounter{tcbraster}{0}
\setcounter{lstnumber}{1}
\setcounter{tcblisting}{0}
\setcounter{caption@flags}{0}
\setcounter{continuedfloat}{0}
\setcounter{tikztiming@nrows}{0}
\setcounter{tikztimingrows}{0}
\setcounter{tikztimingtrans}{0}
\setcounter{tikztimingtranspos}{0}
\setcounter{section@level}{0}
\setcounter{Item}{3}
\setcounter{Hfootnote}{0}
\setcounter{bookmark@seq@number}{29}
\setcounter{lstlisting}{0}
}
hardware/v2/docs/DatasheetLatex/chapters/08-status-roadmap.tex
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\chapter{Chip readiness and roadmap}
\label{ch:status}
\section{Precise readiness checklist}
Per this project's own standing rule: no item below is checked unless
genuinely verified; no OPEN item is masked as a future enhancement.
\begin{tabularx}{\textwidth}{L{6.4cm}Y}
\toprule
\rowh \thd{Item} & \thd{Status} \\
\midrule
RTL frozen, zero V1 dependency & \OK \\
\rowa Bit-exact regression (N=2, N=4) & \OK\ (256/256, Verilator) \\
Real SPI host interface, end-to-end & \OK\ (11/11, zero regression) \\
\rowa SDRAM validation (init/refresh/masked-write) & \OK \\
Synthesis (final top, real Yosys run) & \OK\ (0 CHECK-pass problems) \\
\rowa Place\&route (8 real seeds) & \OK\ (8/8 fit, routed, zero errors) \\
Timing closure @ 64\,MHz & \OK\ (8/8 seeds PASS, worst 68.51\,MHz) \\
\rowa Final pinout (44/44 top-level signals) & \OK\ (real balls, P\&R-confirmed) \\
Hold-time analysis & OPEN (not reported by this toolchain's summary) \\
\rowa Power: rail voltages & OK (real datasheet values) \\
Power: regulator selection / current budget & OPEN \\
\rowa SDRAM datasheet-parameter cross-check & OPEN (sim-level only) \\
Configuration flash selection & OPEN \\
\rowa Real KiCad schematic + ERC & NOT STARTED \\
PCB layout & NOT STARTED \\
\rowa BOM (sourced, purchasable parts) & NOT STARTED \\
Physical board bring-up & NOT APPLICABLE (no board fabricated) \\
\rowa Real embedded-target (ESP32) software baseline & NOT AVAILABLE (no hardware) \\
\bottomrule
\end{tabularx}
\section{Final answer}
\begin{center}
\Large\bfseries\color{fnRed}NOT SILICON READY
\end{center}
The RTL, simulation, synthesis, place-and-route, timing, and pinout
gates are all genuinely closed for the final board-level top. The
remaining, real, disclosed blockers are entirely in the physical
domain -- schematic capture, PCB layout, sourced BOM, and (necessarily)
physical fabrication and bring-up -- none of which were claimed
complete in this revision.
\section{Roadmap}
\begin{itemize}
\item Real KiCad schematic capture + ERC.
\item PCB layout (BGA escape, SDRAM routing, power integrity).
\item Sourced, purchasable BOM (regulators, configuration flash,
connectors).
\item Real power current-budget estimate against the actual
synthesized netlist.
\item Real SDRAM-datasheet-parameter cross-check of controller timing
constants.
\item First physical board fabrication and the 15-step bring-up
procedure already documented in \code{FIRST\_POWER\_ON.md}.
\item A real embedded-target (ESP32-class) software baseline, once
hardware is available, to replace this revision's honestly-labeled
desktop-CPU illustrative comparison.
\end{itemize}
hardware/v2/docs/DatasheetLatex/preamble.tex
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% ======================================================================
% FPGA-Neural Datasheet -- preamble / stile
% ======================================================================
\usepackage[T1]{fontenc}
\usepackage[utf8]{inputenc}
\usepackage[english]{babel}
\usepackage{helvet}
\renewcommand{\familydefault}{\sfdefault}
\usepackage{courier}
\usepackage{microtype}
\usepackage[a4paper,top=2.4cm,bottom=2.3cm,left=2.2cm,right=2.2cm,headheight=15pt]{geometry}
\usepackage[table]{xcolor}
\usepackage{graphicx}
\usepackage{booktabs}
\usepackage{tabularx}
\usepackage{longtable}
\usepackage{array}
\usepackage{ltablex}
\keepXColumns
\usepackage{multirow}
\usepackage{multicol}
\usepackage{enumitem}
\usepackage{amsmath}
\usepackage{amssymb}
\usepackage{ragged2e}
% ---------- Palette ----------------------------------------------------
\definecolor{fnDark}{HTML}{0B2E4F} % blu profondo (primario)
\definecolor{fnBlue}{HTML}{15629B} % blu medio
\definecolor{fnTeal}{HTML}{0E8F8A} % accento teal
\definecolor{fnAmber}{HTML}{C9761B} % accento ambra
\definecolor{fnRed}{HTML}{B22C34} % fail / warning
\definecolor{fnGreen}{HTML}{2E7D32} % pass / ok
\definecolor{fnGrey}{HTML}{5B6B78}
\definecolor{fnLight}{HTML}{EEF3F7} % sfondo chiaro
\definecolor{fnLight2}{HTML}{E2ECF3}
\definecolor{fnRule}{HTML}{9FB4C4}
\definecolor{codebg}{HTML}{F5F7F9}
\definecolor{codekw}{HTML}{15629B}
\definecolor{codecom}{HTML}{5B6B78}
\definecolor{codestr}{HTML}{0E8F8A}
% ---------- Titoli -----------------------------------------------------
\usepackage{titlesec}
\titleformat{\chapter}[display]
{\normalfont\bfseries\color{fnDark}}
{\filright\Large\color{fnTeal}CHAPTER \thechapter}
{6pt}
{\Huge\filright}
[\vspace{2pt}{\color{fnRule}\titlerule[1.3pt]}]
\titlespacing*{\chapter}{0pt}{6pt}{18pt}
\titleformat{\section}
{\normalfont\large\bfseries\color{fnDark}}{\thesection}{0.6em}{}
\titleformat{\subsection}
{\normalfont\bfseries\color{fnBlue}}{\thesubsection}{0.6em}{}
\titleformat{\subsubsection}
{\normalfont\bfseries\color{fnGrey}}{\thesubsubsection}{0.6em}{}
\titlespacing*{\section}{0pt}{12pt}{4pt}
% ---------- Header / footer -------------------------------------------
\usepackage{fancyhdr}
\pagestyle{fancy}
\fancyhf{}
\renewcommand{\headrulewidth}{0.6pt}
\renewcommand{\footrulewidth}{0.4pt}
\renewcommand{\headrule}{\hbox to\headwidth{\color{fnRule}\leaders\hrule height \headrulewidth\hfill}}
\renewcommand{\footrule}{\hbox to\headwidth{\color{fnRule}\leaders\hrule height \footrulewidth\hfill}}
\renewcommand{\chaptermark}[1]{\markboth{#1}{}}
\fancyhead[L]{\small\color{fnDark}\textbf{FPGA-Neural}}
\fancyhead[R]{\footnotesize\color{fnGrey}\nouppercase{\leftmark}}
\fancyfoot[L]{\small\color{fnGrey}Datasheet~\textbf{Rev.\,\datasheetrev}}
\fancyfoot[C]{\small\color{fnGrey}manvalan/FPGA-Neural}
\fancyfoot[R]{\small\color{fnGrey}\thepage}
\fancypagestyle{plain}{\fancyhf{}%
\fancyfoot[L]{\small\color{fnGrey}Datasheet~\textbf{Rev.\,\datasheetrev}}%
\fancyfoot[C]{\small\color{fnGrey}manvalan/FPGA-Neural}%
\fancyfoot[R]{\small\color{fnGrey}\thepage}%
\renewcommand{\headrulewidth}{0pt}}
% ---------- tcolorbox --------------------------------------------------
\usepackage[most]{tcolorbox}
\tcbuselibrary{skins,breakable}
% Box "nota"
\newtcolorbox{fnnote}[1][Note]{
enhanced, breakable, colback=fnLight, colframe=fnTeal,
boxrule=0.4pt, left=8pt, right=8pt, top=5pt, bottom=5pt,
fonttitle=\bfseries\color{white}, coltitle=white,
attach boxed title to top left={xshift=6pt,yshift=-3pt},
boxed title style={colback=fnTeal,boxrule=0pt,arc=1pt}, title={#1}}
% Box "attenzione"
\newtcolorbox{fnwarn}[1][Warning]{
enhanced, breakable, colback=fnLight, colframe=fnAmber,
boxrule=0.4pt, left=8pt, right=8pt, top=5pt, bottom=5pt,
fonttitle=\bfseries\color{white}, coltitle=white,
attach boxed title to top left={xshift=6pt,yshift=-3pt},
boxed title style={colback=fnAmber,boxrule=0pt,arc=1pt}, title={#1}}
% Box "registro/parametro"
\newtcolorbox{fnspec}[1][Specification]{
enhanced, breakable, colback=white, colframe=fnBlue,
boxrule=0.7pt, left=8pt, right=8pt, top=5pt, bottom=5pt, arc=1.5pt,
fonttitle=\bfseries\color{white}, coltitle=white,
attach boxed title to top left={xshift=6pt,yshift=-3pt},
boxed title style={colback=fnBlue,boxrule=0pt,arc=1pt}, title={#1}}
% ---------- listings (Verilog) ----------------------------------------
\usepackage{listings}
\lstdefinestyle{verilog}{
language=Verilog,
backgroundcolor=\color{codebg},
basicstyle=\ttfamily\scriptsize,
keywordstyle=\color{codekw}\bfseries,
commentstyle=\color{codecom}\itshape,
stringstyle=\color{codestr},
numbers=left, numberstyle=\tiny\color{fnGrey}, numbersep=7pt,
showstringspaces=false, breaklines=true, frame=leftline,
framerule=1.2pt, rulecolor=\color{fnTeal},
xleftmargin=12pt, framexleftmargin=10pt, tabsize=2,
morekeywords={logic,always_ff,always_comb,localparam,signed,genvar,generate,endgenerate}
}
\lstset{style=verilog}
% ---------- Tabelle ----------------------------------------------------
\newcolumntype{L}[1]{>{\raggedright\arraybackslash}p{#1}}
\newcolumntype{C}[1]{>{\centering\arraybackslash}p{#1}}
\newcolumntype{R}[1]{>{\raggedleft\arraybackslash}p{#1}}
\newcolumntype{Y}{>{\raggedright\arraybackslash}X}
\renewcommand{\arraystretch}{1.25}
\arrayrulecolor{fnRule}
% intestazione tabella colorata
\newcommand{\thd}[1]{\textbf{\color{white}#1}}
\newcommand{\rowh}{\rowcolor{fnDark}}
\newcommand{\rowa}{\rowcolor{fnLight}}
% ---------- Caption ----------------------------------------------------
\usepackage{caption}
\captionsetup{font=small,labelfont={bf,color=fnTeal},labelsep=period}
% ---------- TikZ / pgfplots -------------------------------------------
\usepackage{tikz}
\usetikzlibrary{arrows.meta,positioning,calc,shapes.geometric,shapes.misc,
fit,backgrounds,chains,decorations.pathreplacing,decorations.markings,
matrix,shadows.blur}
\usepackage{pgfplots}
\pgfplotsset{compat=1.17}
\usepackage{tikz-timing}
% stili di blocco riusabili
\tikzset{
fnblock/.style={draw=fnBlue,fill=fnLight,rounded corners=2pt,
minimum height=9mm,minimum width=24mm,align=center,font=\small,
inner sep=4pt,line width=0.7pt},
fnblockT/.style={fnblock,draw=fnTeal,fill=fnLight2},
fnblockD/.style={fnblock,draw=fnDark,fill=fnDark,text=white},
fnblockA/.style={fnblock,draw=fnAmber,fill=white},
fnreg/.style={draw=fnGrey,fill=white,minimum height=8mm,align=center,
font=\footnotesize,inner sep=3pt},
fnstate/.style={draw=fnBlue,fill=fnLight,circle,minimum size=13mm,
align=center,font=\scriptsize,line width=0.7pt},
fnarrow/.style={-{Stealth[length=2.6mm]},line width=0.8pt,draw=fnDark},
fnarrowT/.style={-{Stealth[length=2.6mm]},line width=0.8pt,draw=fnTeal},
fnbus/.style={-{Stealth[length=3mm]},line width=1.6pt,draw=fnBlue},
fnlbl/.style={font=\scriptsize\itshape,fill=white,inner sep=1pt,text=fnGrey}
}
% ---------- varie ------------------------------------------------------
\newcommand{\reg}[1]{\texttt{\textbf{#1}}}
\newcommand{\sig}[1]{\texttt{#1}}
\newcommand{\op}[1]{\texttt{\color{fnBlue}#1}}
\newcommand{\PASS}{\textcolor{fnGreen}{\textbf{PASS}}}
\newcommand{\FAIL}{\textcolor{fnRed}{\textbf{FAIL}}}
\newcommand{\OK}{\textcolor{fnGreen}{\textbf{OK}}}
\newcommand{\code}[1]{\texttt{#1}}
\usepackage{enumitem}
\setlist{noitemsep,topsep=2pt,leftmargin=1.4em}
\usepackage[hidelinks,colorlinks=true,linkcolor=fnBlue,urlcolor=fnTeal,
citecolor=fnBlue]{hyperref}
hardware/v2/reports/step_final_pnr_worst_seed4.log
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Info: constraining clock net 'osc_clk' to 16.00 MHz
Info: Logic utilisation before packing:
Info: Total LUT4s: 6634/43848 15%
Info: logic LUTs: 4074/43848 9%
Info: carry LUTs: 1426/43848 3%
Info: RAM LUTs: 756/ 5481 13%
Info: RAMW LUTs: 378/10962 3%
Info: Total DFFs: 6322/43848 14%
Info: Packing IOs..
Info: $sdram_dq[15]$iobuf_i: sdram_dq_$_TBUF__Y.Y
Info: pin 'sdram_dq[15]$tr_io' constrained to Bel 'X0/Y59/PIOB'.
Info: $sdram_dq[14]$iobuf_i: sdram_dq_$_TBUF__Y_15.Y
Info: pin 'sdram_dq[14]$tr_io' constrained to Bel 'X0/Y59/PIOC'.
Info: $sdram_dq[13]$iobuf_i: sdram_dq_$_TBUF__Y_14.Y
Info: pin 'sdram_dq[13]$tr_io' constrained to Bel 'X0/Y59/PIOA'.
Info: $sdram_dq[12]$iobuf_i: sdram_dq_$_TBUF__Y_13.Y
Info: pin 'sdram_dq[12]$tr_io' constrained to Bel 'X0/Y53/PIOA'.
Info: $sdram_dq[11]$iobuf_i: sdram_dq_$_TBUF__Y_12.Y
Info: pin 'sdram_dq[11]$tr_io' constrained to Bel 'X0/Y44/PIOD'.
Info: $sdram_dq[10]$iobuf_i: sdram_dq_$_TBUF__Y_11.Y
Info: pin 'sdram_dq[10]$tr_io' constrained to Bel 'X0/Y44/PIOC'.
Info: $sdram_dq[9]$iobuf_i: sdram_dq_$_TBUF__Y_10.Y
Info: pin 'sdram_dq[9]$tr_io' constrained to Bel 'X0/Y44/PIOA'.
Info: $sdram_dq[8]$iobuf_i: sdram_dq_$_TBUF__Y_9.Y
Info: pin 'sdram_dq[8]$tr_io' constrained to Bel 'X0/Y41/PIOD'.
Info: $sdram_dq[7]$iobuf_i: sdram_dq_$_TBUF__Y_8.Y
Info: pin 'sdram_dq[7]$tr_io' constrained to Bel 'X0/Y41/PIOB'.
Info: $sdram_dq[6]$iobuf_i: sdram_dq_$_TBUF__Y_7.Y
Info: pin 'sdram_dq[6]$tr_io' constrained to Bel 'X0/Y41/PIOC'.
Info: $sdram_dq[5]$iobuf_i: sdram_dq_$_TBUF__Y_6.Y
Info: pin 'sdram_dq[5]$tr_io' constrained to Bel 'X0/Y41/PIOA'.
Info: $sdram_dq[4]$iobuf_i: sdram_dq_$_TBUF__Y_5.Y
Info: pin 'sdram_dq[4]$tr_io' constrained to Bel 'X0/Y38/PIOD'.
Info: $sdram_dq[3]$iobuf_i: sdram_dq_$_TBUF__Y_4.Y
Info: pin 'sdram_dq[3]$tr_io' constrained to Bel 'X0/Y38/PIOB'.
Info: $sdram_dq[2]$iobuf_i: sdram_dq_$_TBUF__Y_3.Y
Info: pin 'sdram_dq[2]$tr_io' constrained to Bel 'X0/Y29/PIOD'.
Info: $sdram_dq[1]$iobuf_i: sdram_dq_$_TBUF__Y_2.Y
Info: pin 'sdram_dq[1]$tr_io' constrained to Bel 'X0/Y29/PIOB'.
Info: $sdram_dq[0]$iobuf_i: sdram_dq_$_TBUF__Y_1.Y
Info: pin 'sdram_dq[0]$tr_io' constrained to Bel 'X0/Y26/PIOD'.
Info: pin 'spi_sclk$tr_io' constrained to Bel 'X0/Y62/PIOC'.
Info: pin 'spi_mosi$tr_io' constrained to Bel 'X0/Y62/PIOB'.
Info: pin 'spi_miso$tr_io' constrained to Bel 'X0/Y62/PIOD'.
Info: pin 'spi_cs_n$tr_io' constrained to Bel 'X0/Y65/PIOA'.
Info: pin 'sdram_we_n$tr_io' constrained to Bel 'X0/Y14/PIOD'.
Info: pin 'sdram_ras_n$tr_io' constrained to Bel 'X0/Y14/PIOA'.
Info: pin 'sdram_dqm[1]$tr_io' constrained to Bel 'X0/Y62/PIOA'.
Info: pin 'sdram_dqm[0]$tr_io' constrained to Bel 'X0/Y59/PIOD'.
Info: pin 'sdram_cs_n$tr_io' constrained to Bel 'X0/Y11/PIOD'.
Info: pin 'sdram_cke$tr_io' constrained to Bel 'X0/Y11/PIOC'.
Info: pin 'sdram_cas_n$tr_io' constrained to Bel 'X0/Y14/PIOC'.
Info: pin 'sdram_ba[1]$tr_io' constrained to Bel 'X0/Y17/PIOC'.
Info: pin 'sdram_ba[0]$tr_io' constrained to Bel 'X0/Y17/PIOA'.
Info: pin 'sdram_a[11]$tr_io' constrained to Bel 'X0/Y26/PIOB'.
Info: pin 'sdram_a[10]$tr_io' constrained to Bel 'X0/Y26/PIOC'.
Info: pin 'sdram_a[9]$tr_io' constrained to Bel 'X0/Y26/PIOA'.
Info: pin 'sdram_a[8]$tr_io' constrained to Bel 'X0/Y23/PIOD'.
Info: pin 'sdram_a[7]$tr_io' constrained to Bel 'X0/Y23/PIOB'.
Info: pin 'sdram_a[6]$tr_io' constrained to Bel 'X0/Y23/PIOA'.
Info: pin 'sdram_a[5]$tr_io' constrained to Bel 'X0/Y20/PIOD'.
Info: pin 'sdram_a[4]$tr_io' constrained to Bel 'X0/Y20/PIOB'.
Info: pin 'sdram_a[3]$tr_io' constrained to Bel 'X0/Y20/PIOC'.
Info: pin 'sdram_a[2]$tr_io' constrained to Bel 'X0/Y20/PIOA'.
Info: pin 'sdram_a[1]$tr_io' constrained to Bel 'X0/Y17/PIOD'.
Info: pin 'sdram_a[0]$tr_io' constrained to Bel 'X0/Y17/PIOB'.
Info: pin 'pll_locked$tr_io' constrained to Bel 'X0/Y65/PIOC'.
Info: pin 'osc_clk$tr_io' constrained to Bel 'X0/Y29/PIOC'.
Info: pin 'ext_rst_n$tr_io' constrained to Bel 'X0/Y14/PIOB'.
Info: placed PLL 'u_pll.pll_i' at bel 'X1/Y4/EHXPLL_UL'
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 2575 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Input frequency of PLL 'u_pll.pll_i' is constrained to 16.0 MHz
Info: Derived frequency constraint of 64.0 MHz for net clk
Info: Promoting globals...
Info: promoting clock net clk to global network
Info: Checksum: 0xb24b3184
Info: Device utilisation:
Info: TRELLIS_IO: 44/ 245 17%
Info: DCCA: 1/ 56 1%
Info: DP16KD: 0/ 108 0%
Info: MULT18X18D: 32/ 72 44%
Info: ALU54B: 0/ 36 0%
Info: EHXPLLL: 1/ 4 25%
Info: EXTREFB: 0/ 2 0%
Info: DCUA: 0/ 2 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 0/ 160 0%
Info: SIOLOGIC: 0/ 85 0%
Info: GSR: 0/ 1 0%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 0/ 1 0%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 6322/ 43848 14%
Info: TRELLIS_COMB: 7084/ 43848 16%
Info: TRELLIS_RAMW: 189/ 5481 3%
Info: Placed 45 cells based on constraints.
Info: Creating initial analytic placement for 7811 cells, random placement wirelen = 635413.
Info: at initial placer iter 0, wirelen = 3641
Info: at initial placer iter 1, wirelen = 3058
Info: at initial placer iter 2, wirelen = 2978
Info: at initial placer iter 3, wirelen = 3006
Info: Running main analytical placer, max placement attempts per cell = 23368866.
Info: at iteration #1, type ALL: wirelen solved = 2851, spread = 105823, legal = 123819; time = 0.20s
Info: at iteration #2, type ALL: wirelen solved = 12848, spread = 74308, legal = 90806; time = 0.19s
Info: at iteration #3, type ALL: wirelen solved = 18878, spread = 70946, legal = 86425; time = 0.16s
Info: at iteration #4, type ALL: wirelen solved = 23629, spread = 67877, legal = 80958; time = 0.16s
Info: at iteration #5, type ALL: wirelen solved = 25972, spread = 66034, legal = 82304; time = 0.14s
Info: at iteration #6, type ALL: wirelen solved = 27044, spread = 64778, legal = 81280; time = 0.16s
Info: at iteration #7, type ALL: wirelen solved = 27677, spread = 65077, legal = 78916; time = 0.13s
Info: at iteration #8, type ALL: wirelen solved = 28674, spread = 64171, legal = 80070; time = 0.16s
Info: at iteration #9, type ALL: wirelen solved = 29347, spread = 64047, legal = 77328; time = 0.15s
Info: at iteration #10, type ALL: wirelen solved = 29869, spread = 64168, legal = 79757; time = 0.15s
Info: at iteration #11, type ALL: wirelen solved = 30347, spread = 63680, legal = 78577; time = 0.14s
Info: at iteration #12, type ALL: wirelen solved = 30887, spread = 67391, legal = 77285; time = 0.14s
Info: at iteration #13, type ALL: wirelen solved = 34628, spread = 66938, legal = 79231; time = 0.14s
Info: at iteration #14, type ALL: wirelen solved = 35255, spread = 66705, legal = 76218; time = 0.11s
Info: at iteration #15, type ALL: wirelen solved = 35781, spread = 66489, legal = 76421; time = 0.12s
Info: at iteration #16, type ALL: wirelen solved = 35889, spread = 66722, legal = 79650; time = 0.13s
Info: at iteration #17, type ALL: wirelen solved = 35933, spread = 66113, legal = 76579; time = 0.14s
Info: at iteration #18, type ALL: wirelen solved = 36378, spread = 66541, legal = 79035; time = 0.14s
Info: at iteration #19, type ALL: wirelen solved = 36628, spread = 66908, legal = 79994; time = 0.13s
Info: HeAP Placer Time: 3.65s
Info: of which solving equations: 1.79s
Info: of which spreading cells: 0.31s
Info: of which strict legalisation: 1.01s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 811, wirelen = 76218
Info: at iteration #5: temp = 0.000000, timing cost = 1839, wirelen = 70366
Info: at iteration #10: temp = 0.000000, timing cost = 1064, wirelen = 68627
Info: at iteration #15: temp = 0.000000, timing cost = 998, wirelen = 68181
Info: at iteration #20: temp = 0.000000, timing cost = 989, wirelen = 68031
Info: at iteration #25: temp = 0.000000, timing cost = 981, wirelen = 67961
Info: at iteration #26: temp = 0.000000, timing cost = 976, wirelen = 67948
Info: SA placement time 5.68s
Info: Max frequency for clock '$glbnet$clk': 55.01 MHz (FAIL at 64.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk: 5.11 ns
Info: Max delay posedge $glbnet$clk -> <async> : 11.47 ns
Info: Slack histogram:
Info: legend: * represents 35 endpoint(s)
Info: + represents [1,35) endpoint(s)
Info: [ -2553, -1682) |+
Info: [ -1682, -811) |+
Info: [ -811, 60) |***+
Info: [ 60, 931) |***+
Info: [ 931, 1802) |****+
Info: [ 1802, 2673) |******+
Info: [ 2673, 3544) |********+
Info: [ 3544, 4415) |************+
Info: [ 4415, 5286) |****************+
Info: [ 5286, 6157) |*********************************+
Info: [ 6157, 7028) |***************************************+
Info: [ 7028, 7899) |******************************************+
Info: [ 7899, 8770) |******************************+
Info: [ 8770, 9641) |********************************+
Info: [ 9641, 10512) |******************************+
Info: [ 10512, 11383) |********************************+
Info: [ 11383, 12254) |*****************************************************+
Info: [ 12254, 13125) |************************************************************
Info: [ 13125, 13996) |*******************************************************+
Info: [ 13996, 14867) |*********************************************+
Info: Checksum: 0x5d5c6e8a
Info: Routing globals...
Info: routing clock net $glbnet$clk using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 37675 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 419 580 | 419 580 | 37353| 0.43 0.43|
Info: 2000 | 583 1416 | 164 836 | 36558| 0.23 0.66|
Info: 3000 | 770 2229 | 187 813 | 35851| 0.20 0.86|
Info: 4000 | 911 3088 | 141 859 | 35050| 0.16 1.02|
Info: 5000 | 1030 3969 | 119 881 | 34240| 0.14 1.16|
Info: 6000 | 1126 4873 | 96 904 | 33433| 0.15 1.31|
Info: 7000 | 1228 5771 | 102 898 | 32626| 0.13 1.44|
Info: 8000 | 1315 6684 | 87 913 | 31773| 0.15 1.60|
Info: 9000 | 1415 7584 | 100 900 | 30983| 0.14 1.73|
Info: 10000 | 1551 8448 | 136 864 | 30319| 0.16 1.90|
Info: 11000 | 1652 9347 | 101 899 | 29468| 0.14 2.04|
Info: 12000 | 1762 10237 | 110 890 | 28715| 0.12 2.15|
Info: 13000 | 1904 11095 | 142 858 | 27921| 0.14 2.29|
Info: 14000 | 2069 11930 | 165 835 | 27228| 0.13 2.42|
Info: 15000 | 2184 12815 | 115 885 | 26471| 0.13 2.55|
Info: 16000 | 2327 13672 | 143 857 | 25781| 0.17 2.71|
Info: 17000 | 2504 14495 | 177 823 | 25060| 0.12 2.84|
Info: 18000 | 2737 15262 | 233 767 | 24524| 0.15 2.98|
Info: 19000 | 2876 16123 | 139 861 | 23853| 0.19 3.17|
Info: 20000 | 3048 16948 | 172 825 | 23152| 0.13 3.30|
Info: 21000 | 3336 17659 | 288 711 | 22496| 0.12 3.42|
Info: 22000 | 3544 18440 | 208 781 | 21769| 0.11 3.54|
Info: 23000 | 3769 19204 | 225 764 | 21250| 0.18 3.71|
Info: 24000 | 4012 19949 | 243 745 | 20632| 0.15 3.86|
Info: 25000 | 4252 20697 | 240 748 | 19952| 0.14 4.00|
Info: 26000 | 4517 21413 | 265 716 | 19279| 0.12 4.12|
Info: 27000 | 4726 22171 | 209 758 | 18550| 0.13 4.25|
Info: 28000 | 4914 22961 | 188 790 | 17871| 0.13 4.39|
Info: 29000 | 5077 23715 | 163 754 | 17083| 0.12 4.51|
Info: 30000 | 5244 24483 | 167 768 | 16309| 0.11 4.62|
Info: 31000 | 5441 25242 | 197 759 | 15588| 0.12 4.74|
Info: 32000 | 5647 26002 | 206 760 | 15031| 0.15 4.89|
Info: 33000 | 5815 26811 | 168 809 | 14346| 0.11 5.00|
Info: 34000 | 5963 27591 | 148 780 | 13591| 0.12 5.12|
Info: 35000 | 6114 28372 | 151 781 | 12881| 0.15 5.28|
Info: 36000 | 6255 29197 | 141 825 | 12144| 0.12 5.40|
Info: 37000 | 6417 30013 | 162 816 | 11508| 0.16 5.56|
Info: 38000 | 6512 30859 | 95 846 | 10796| 0.12 5.68|
Info: 39000 | 6634 31704 | 122 845 | 9991| 0.15 5.83|
Info: 40000 | 6755 32507 | 121 803 | 9206| 0.11 5.94|
Info: 41000 | 6919 33305 | 164 798 | 8538| 0.21 6.15|
Info: 42000 | 7054 34113 | 135 808 | 7753| 0.15 6.30|
Info: 43000 | 7173 34919 | 119 806 | 6932| 0.12 6.42|
Info: 44000 | 7402 35656 | 229 737 | 6354| 0.24 6.66|
Info: 45000 | 7499 36517 | 97 861 | 5552| 0.09 6.76|
Info: 46000 | 7761 37251 | 262 734 | 5018| 0.24 7.00|
Info: 47000 | 8050 37956 | 289 705 | 4602| 0.23 7.23|
Info: 48000 | 8179 38827 | 129 871 | 3829| 0.10 7.33|
Info: 49000 | 8436 39570 | 257 743 | 3221| 0.29 7.61|
Info: 50000 | 8700 40306 | 264 736 | 2865| 0.31 7.92|
Info: 51000 | 8962 41044 | 262 738 | 2239| 0.16 8.08|
Info: 52000 | 9165 41792 | 203 748 | 1504| 0.15 8.23|
Info: 53000 | 9312 42547 | 147 755 | 895| 0.22 8.45|
Info: 54000 | 9443 43303 | 131 756 | 142| 0.19 8.64|
Info: 54162 | 9461 43421 | 18 118 | 0| 0.05 8.69|
Info: Routing complete.
Info: Router1 time 8.69s
Info: Checksum: 0x662d74ce
Info: Critical path report for clock '$glbnet$clk' (posedge -> posedge):
Info: type curr total name
Info: clk-to-q 0.52 0.52 Source u_arbiter_wide.m_addr_TRELLIS_FF_Q_15.Q
Info: routing 0.92 1.45 Net wide_arb_m_addr[16] (19,3) -> (18,3)
Info: Sink u_sdram_backend.w_hit_idx_c_LUT4_Z_D_LUT4_Z_1_D_LUT4_Z_D_LUT4_Z_3_D_LUT4_Z.C
Info: Defined in:
Info: hardware/v2/nms/rtl/fpga_neural_v2_top.v:217.28-217.43
Info: logic 0.24 1.68 Source u_sdram_backend.w_hit_idx_c_LUT4_Z_D_LUT4_Z_1_D_LUT4_Z_D_LUT4_Z_3_D_LUT4_Z.F
Info: routing 0.62 2.31 Net u_sdram_backend.w_hit_idx_c_LUT4_Z_D_LUT4_Z_1_D_LUT4_Z_D_LUT4_Z_3_D[2] (18,3) -> (18,3)
Info: Sink u_sdram_backend.w_hit_idx_c_LUT4_Z_D_LUT4_Z_1_D_LUT4_Z_D_LUT4_Z_3.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.24 2.54 Source u_sdram_backend.w_hit_idx_c_LUT4_Z_D_LUT4_Z_1_D_LUT4_Z_D_LUT4_Z_3.F
Info: routing 1.13 3.67 Net u_sdram_backend.w_hit_idx_c_LUT4_Z_D_LUT4_Z_1_D_LUT4_Z_D[2] (18,3) -> (17,4)
Info: Sink u_sdram_backend.w_hit_idx_c_LUT4_Z_D_LUT4_Z_1_D_LUT4_Z.C
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.24 3.90 Source u_sdram_backend.w_hit_idx_c_LUT4_Z_D_LUT4_Z_1_D_LUT4_Z.F
Info: routing 0.88 4.78 Net u_sdram_backend.w_hit_idx_c_LUT4_Z_D_LUT4_Z_1_D[3] (17,4) -> (16,4)
Info: Sink u_sdram_backend.w_hit_idx_c_LUT4_Z_D_LUT4_Z_1.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.24 5.02 Source u_sdram_backend.w_hit_idx_c_LUT4_Z_D_LUT4_Z_1.F
Info: routing 1.78 6.80 Net u_sdram_backend.w_hit_idx_c_LUT4_Z_C[0] (16,4) -> (13,21)
Info: Sink u_sdram_backend.w_hit_idx_c_LUT4_Z_1.C
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.24 7.03 Source u_sdram_backend.w_hit_idx_c_LUT4_Z_1.F
Info: routing 1.39 8.43 Net u_sdram_backend.w_hit_idx_c[1] (13,21) -> (14,11)
Info: Sink u_sdram_backend.w_hit_idx_c_LUT4_Z_C_LUT4_C.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.24 8.66 Source u_sdram_backend.w_hit_idx_c_LUT4_Z_C_LUT4_C.F
Info: routing 0.43 9.09 Net u_sdram_backend.w_hit_idx_c_LUT4_Z_C_LUT4_C_Z[1] (14,11) -> (14,11)
Info: Sink u_sdram_backend.w_hit_idx_c_LUT4_Z_C_LUT4_C_Z_LUT4_D.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.24 9.32 Source u_sdram_backend.w_hit_idx_c_LUT4_Z_C_LUT4_C_Z_LUT4_D.F
Info: routing 2.36 11.69 Net u_sdram_backend.w_hit_idx_c_LUT4_Z_C_LUT4_C_Z_LUT4_D_Z[1] (14,11) -> (12,40)
Info: Sink u_sdram_backend.w_hit_idx_c_LUT4_Z_C_LUT4_C_Z_LUT4_D_Z_LUT4_D.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.24 11.92 Source u_sdram_backend.w_hit_idx_c_LUT4_Z_C_LUT4_C_Z_LUT4_D_Z_LUT4_D.F
Info: routing 2.67 14.60 Net u_sdram_backend.w_hit_idx_c_LUT4_Z_C_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z (12,40) -> (14,7)
Info: Sink u_sdram_backend.w_rdata_TRELLIS_FF_Q_51.CE
Info: setup 0.00 14.60 Source u_sdram_backend.w_rdata_TRELLIS_FF_Q_51.CE
Info: 2.41 ns logic, 12.18 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk':
Info: type curr total name
Info: source 0.00 0.00 Source sdram_dq[3]$tr_io.O
Info: routing 3.24 3.24 Net sdram_dq[3]$TRELLIS_IO_IN (0,38) -> (14,18)
Info: Sink u_sdram_backend.u_sdram_ctrl.rdata_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_S1_S0_LUT4_D_2_Z_LUT4_D_Z_LUT4_Z_14_D_LUT4_Z.B
Info: Defined in:
Info: hardware/v2/nms/rtl/sdram_controller.v:80.25-80.33
Info: logic 0.24 3.47 Source u_sdram_backend.u_sdram_ctrl.rdata_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_S1_S0_LUT4_D_2_Z_LUT4_D_Z_LUT4_Z_14_D_LUT4_Z.F
Info: routing 0.70 4.17 Net u_sdram_backend.u_sdram_ctrl.rdata_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_S1_S0_LUT4_D_2_Z_LUT4_D_Z_LUT4_Z_14_D[2] (14,18) -> (14,19)
Info: Sink u_sdram_backend.u_sdram_ctrl.rdata_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_S1_S0_LUT4_D_2_Z_LUT4_D_Z_LUT4_Z_14.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.24 4.41 Source u_sdram_backend.u_sdram_ctrl.rdata_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_S1_S0_LUT4_D_2_Z_LUT4_D_Z_LUT4_Z_14.F
Info: routing 0.13 4.53 Net u_sdram_backend.u_sdram_ctrl.rdata_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_S1_S0_LUT4_D_2_Z_LUT4_D_Z[51] (14,19) -> (14,19)
Info: Sink u_sdram_backend.u_sdram_ctrl.rdata_TRELLIS_FF_Q_51.DI
Info: setup 0.00 4.53 Source u_sdram_backend.u_sdram_ctrl.rdata_TRELLIS_FF_Q_51.DI
Info: 0.47 ns logic, 4.06 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$clk' -> '<async>':
Info: type curr total name
Info: clk-to-q 0.52 0.52 Source u_spi_bridge.byte_idx_TRELLIS_FF_Q.Q
Info: routing 2.25 2.78 Net u_spi_bridge.byte_idx[0] (24,52) -> (25,29)
Info: Sink u_spi_bridge.rx_valid_LUT4_C_Z_LUT4_Z_C_LUT4_Z.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.24 3.01 Source u_spi_bridge.rx_valid_LUT4_C_Z_LUT4_Z_C_LUT4_Z.F
Info: routing 0.43 3.44 Net u_spi_bridge.rx_valid_LUT4_C_Z_LUT4_Z_C[0] (25,29) -> (25,29)
Info: Sink u_spi_bridge.rx_valid_LUT4_C_Z_LUT4_Z.C
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.24 3.68 Source u_spi_bridge.rx_valid_LUT4_C_Z_LUT4_Z.F
Info: routing 2.89 6.57 Net u_spi_bridge.byte_idx_TRELLIS_FF_Q_DI_LUT4_Z_D[1] (25,29) -> (21,56)
Info: Sink spi_miso_LUT4_Z_D_LUT4_Z.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.24 6.80 Source spi_miso_LUT4_Z_D_LUT4_Z.F
Info: routing 0.22 7.02 Net spi_miso_LUT4_Z_B[3] (21,56) -> (21,56)
Info: Sink spi_miso_LUT4_Z.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.24 7.26 Source spi_miso_LUT4_Z.F
Info: routing 2.13 9.39 Net spi_miso$TRELLIS_IO_OUT (21,56) -> (0,62)
Info: Sink spi_miso$tr_io.I
Info: Defined in:
Info: hardware/v2/rtl/spi_host_bridge.v:83.17-83.21
Info: 1.47 ns logic, 7.92 ns routing
Info: Max frequency for clock '$glbnet$clk': 68.51 MHz (PASS at 64.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk: 4.53 ns
Info: Max delay posedge $glbnet$clk -> <async> : 9.39 ns
Info: Slack histogram:
Info: legend: * represents 35 endpoint(s)
Info: + represents [1,35) endpoint(s)
Info: [ 1029, 1712) |+
Info: [ 1712, 2395) |+
Info: [ 2395, 3078) |**+
Info: [ 3078, 3761) |****+
Info: [ 3761, 4444) |******+
Info: [ 4444, 5127) |******+
Info: [ 5127, 5810) |*******+
Info: [ 5810, 6493) |**********+
Info: [ 6493, 7176) |***************+
Info: [ 7176, 7859) |*******************+
Info: [ 7859, 8542) |***********************************+
Info: [ 8542, 9225) |*************************************************+
Info: [ 9225, 9908) |**********************************+
Info: [ 9908, 10591) |******************************+
Info: [ 10591, 11274) |*************************************+
Info: [ 11274, 11957) |***************************+
Info: [ 11957, 12640) |**********************************************+
Info: [ 12640, 13323) |***********************************************************+
Info: [ 13323, 14006) |************************************************************
Info: [ 14006, 14689) |********************************************************+
Info: Program finished normally.
hardware/v2/reports/step_final_synthesis.log
+18198
View File
File diff suppressed because one or more lines are too long
hardware/v2/reports/step_final_timing.csv
+9
View File
@@ -0,0 +1,9 @@
seed,fmax_mhz,pass_at_64mhz,slack_ns_at_64mhz
1,73.17,PASS,1.958
2,68.90,PASS,1.111
3,72.10,PASS,1.755
4,68.51,PASS,1.029
5,69.29,PASS,1.193
6,73.03,PASS,1.931
7,74.17,PASS,2.143
8,70.10,PASS,1.360
1 seed fmax_mhz pass_at_64mhz slack_ns_at_64mhz
2 1 73.17 PASS 1.958
3 2 68.90 PASS 1.111
4 3 72.10 PASS 1.755
5 4 68.51 PASS 1.029
6 5 69.29 PASS 1.193
7 6 73.03 PASS 1.931
8 7 74.17 PASS 2.143
9 8 70.10 PASS 1.360