micheleandClaude Sonnet 5
0303aacb9f
N=2 re-verified with the same shared pipelined neural_processor_packed.v (EXP-0097's fix): real functional xsim 8/8 PASS (identical completion time to the pre-fix baseline), real full P&R WNS=+0.389ns (up from +0.099962ns), 0 failing endpoints, 16 DSP48E1 -- no regression. Real, consolidated family state, all sharing the same pipelined core: N=2: WNS=+0.389ns, 16 DSP48E1, 8/8 functional PASS N=8: WNS=+0.108ns, 64 DSP48E1, 16/16 functional PASS N=16: WNS=+0.269ns, 128 DSP48E1, 32/32 functional PASS Updated the project's own primary real docs (docs/PHYSICAL_REALIZATION.md S3, docs/ARCHITECTURE_ANALYSIS.md S5.6) to the same depth EXP-0096 gave N=8 alone -- not just the docs/latex/ deliverables. Clear two-track framing throughout: the physically fabricated board still uses N=8's original, unmodified core (WNS=0.000ns exact); this consolidated, improved family lives on the isolated n16-timing-closure branch, pending a real hardware decision on whether/when to adopt it. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC