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docs: reframe primary docs -- N=16 is now the real fabrication target

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Physical board fabrication moved to N=16 (with the EXP-0097 MAC-
pipeline fix); v3-artix7 fast-forward merged with n16-timing-closure.
No physical board change needed -- DDR3/SPI/flash/config pins are
identical across all N_GROUPS values. N=2/N=8 kept documented as real,
valid fallback signoffs.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
This commit is contained in:
michele
2026-09-22 08:36:37 +02:00
co-authored by Claude Sonnet 5
parent 0303aacb9f
commit e3fe007469
2 changed files with 45 additions and 29 deletions
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docs/ARCHITECTURE_ANALYSIS.md
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# FPGA-Neural V3 — Architecture Analysis: Timing, Bottlenecks, and Recommended Interventions
Scope: the current, real, P&R-verified V3 design (`hardware/v3/`, branch
`v3-artix7` for the physically-fabricated board; branch
`n16-timing-closure` for the real, consolidated follow-up below),
updated through EXP-0097/0098 (a real MAC-pipeline fix that closes
timing for the WHOLE real family — N=2/N=8/N=16 — not just N=8). The
board **currently in physical fabrication** uses N=8's own original,
unmodified EXP-0095/0096 signoff (`n8_system_ddr3_top.v`, 32-bit DDR3,
155.039MHz, WNS=0.000ns exact, 8 real parallel PEs). Separately, on an
isolated real branch, EXP-0097/0098 found that one shared-core fix
closes N=16 too (WNS=+0.269ns) and improves N=2 (+0.389ns) and N=8
(+0.108ns) as well — see §5.6 for the full real story. Every
`v3-artix7`, now fast-forward merged with the former
`n16-timing-closure` branch). **UPDATE (2026-09-22): the real physical
fabrication target moved to N=16** (`n16_system_ddr3_top.v`, with the
real EXP-0097 MAC-pipeline fix, WNS=+0.269ns, 16 real parallel PEs) —
no physical board change needed, DDR3/SPI/flash/config pins are
identical regardless of `N_GROUPS`. The same MAC-pipeline fix also
improves N=2 (+0.389ns) and N=8 (+0.108ns), both kept as real, valid
fallback signoffs — see §5.6 for the full real story. Every
number in this document is either
directly measured (real simulation trace, real P&R report) or a calculation
built from directly-measured building blocks — the two are labeled
docs/PHYSICAL_REALIZATION.md
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@@ -165,26 +165,44 @@ these from an ESP32 doing real JTAG bit-banging (TAP state machine, IR/DR
shifting) rather than a bench programmer — that firmware is separate,
software-side work, not covered here.
## 3. Real timing signoff — N=8 in physical fabrication; N=2/N=8/N=16 all real, closed on branch `n16-timing-closure` (EXP-0095…0098)
## 3. Real timing signoff — N=16 IS NOW THE REAL FABRICATION TARGET (EXP-0095…0098)
**Real, current, two-track status (2026-09-22)**: the **physical board
currently being fabricated** uses **N=8** (`hardware/v3/rtl/
n8_system_ddr3_top.v`, unmodified, EXP-0095/0096 signoff below) — this
was the real, definitive decision made on 2026-09-21 after a real,
measured N=4/8/16 timing curve found N=8 the largest configuration
that closed cleanly at the time. Separately, on an isolated real
development branch (`n16-timing-closure`, does NOT affect the board
already in fabrication), a real fix (EXP-0097 — an extra real pipeline
stage in `neural_processor_packed.v`'s own MAC datapath, see
`docs/ARCHITECTURE_ANALYSIS.md` §5.6) has since **closed real timing
for N=16 too, and improved N=2's and N=8's own margins** — the whole
real product family (N=2/N=8/N=16) now closes with positive margin
under that fix. Whether/when to adopt this fix for a future board
revision (potentially N=16) is a real, open hardware decision, not an
RTL blocker — see `docs/ARCHITECTURE_ANALYSIS.md` §5.6 for the full
story.
**UPDATE (2026-09-22): the user moved physical board fabrication to
N=16.** `hardware/v3/rtl/n16_system_ddr3_top.v` (with the real EXP-0097
MAC-pipeline fix) is now the real, current target — `v3-artix7` (the
branch representing what is actually being built) has been fast-
forward merged with the former `n16-timing-closure` branch, so both
now point at the same real, consolidated state. **No physical board
change is needed for this** — DDR3/SPI/flash/config pins are all
package-level and identical regardless of `N_GROUPS` (confirmed real,
not assumed, since N=2/N=8/N=16 all route through the exact same real
XDC). Only the bitstream target changes.
### 3.0 N=8, in physical fabrication (`n8_system_ddr3_top.v`, EXP-0095/0096, unmodified core)
N=8's own real signoff (§3.0 below) remains accurate and valid as a
real, simpler fallback if ever needed, but is no longer what is
physically being fabricated. N=2 (EXP-0088) remains the simplest real
fallback below that. See `docs/ARCHITECTURE_ANALYSIS.md` §5.6 for the
full real story of how N=16 was closed (EXP-0097/0098).
### 3.0 N=16, the current real fabrication target (`n16_system_ddr3_top.v`, EXP-0097/0098, with the MAC-pipeline fix)
| Metric | Value |
|---|---|
| DDR3 PHY clock (sys_clk_p/n) | **310.078 MHz** (3.225ns period) |
| Compute domain clock (ui_clk/clk_pll_i) | **155.039 MHz** |
| WNS (setup slack) | **+0.269 ns** — real, closed, 0 failing setup endpoints |
| WHS (hold slack) | +0.026 ns |
| Failing endpoints | 0 of 106087 (setup), 0 of 106084 (hold) |
| LUTs used | 19903 / 63400 (31.39%) |
| Registers used | 35409 / 126800 (27.93%) |
| DSP48E1 used | 128 / 240 (53.33%) — 8 per PE × 16 real parallel PEs |
| Real parallelism | **16 real parallel processing elements** |
| Real functional verification | 32/32 PASS, real DDR3 model (`tb_n16_system_ddr3.v`) |
See `docs/ARCHITECTURE_ANALYSIS.md` §5.6.1 for the full real root-cause
and fix story (the MAC-datapath pipeline split that closed this).
### 3.0-fallback N=8, real, valid fallback signoff (`n8_system_ddr3_top.v`, EXP-0095/0096, unmodified core)
Top-level RTL: `hardware/v3/rtl/n8_system_ddr3_top.v` — 2 groups × 4
PEs, shared-weight-broadcast systolic architecture
@@ -217,7 +235,7 @@ reach this result, EXP-0094/0095) after ANY further RTL change before
trusting timing again — do not assume it still holds. This zero-margin
result is exactly why EXP-0097's own pipeline fix (below) was pursued.
### 3.0.1 The real, consolidated family — EXP-0097/0098, branch `n16-timing-closure` (not yet on the fabricated board)
### 3.0.1 The real, consolidated family — EXP-0097/0098 (N=16 is the fabrication target; N=2/N=8 kept real and valid as fallbacks)
A single real fix (`neural_processor_packed.v`, an extra real pipeline
stage in the packed-MAC datapath — full real root-cause story in