exp: N=8 packed-core array real P&R, isolates placement density from interconnect (EXP-0060)
New hardware/v3/rtl/np_packed_array.v: flat array of 8 unmodified neural_processor_packed.v instances, fully independent I/O, zero shared arbiter/Director logic -- isolates exactly one variable (DSP/placement density) from EXP-0059's single-core baseline. Real Vivado post-route: 64/240 DSP48E1 (26.67%), WNS -2.592ns @ 200MHz -> Fmax ~131.7MHz, only -2.4% vs the single-core 134.9MHz. Placement density alone is NOT the main driver of the ECP5-era gap between isolated-core and full-system Fmax -- narrows the question for the still-unbuilt real Director/arbiter/memory integration. Full writeup in hardware/v2/logs/experiments.log EXP-0060. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
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Claude Sonnet 5
@@ -3713,3 +3713,51 @@ actually targeted (part number confirmed xc7a100tcsg324-1, package/
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board pinout not yet chosen) is still needed before any real bring-up,
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matching this project's own "no board target skipped" discipline from
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V2/STEP19.
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EXP-0060 -- N=8 neural_processor_packed.v placement/routing density
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check, real Vivado P&R, isolating the congestion variable from any
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Director/arbiter/memory RTL (2026-09-17)
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CONTEXT: EXP-0059's own next_action flagged that the isolated single-
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core Fmax (134.9MHz real post-route) is not the same question as real
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N-core system Fmax -- on V2/ECP5 the full board-level system Fmax
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(64-97MHz) was measurably lower than the isolated dataflow-core Fmax
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(92.63MHz). Before building the (larger, riskier, unverified) real
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Director+arbiter+memory integration, this experiment isolates ONE
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variable first, per this project's own "one variable at a time" rule:
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what does pure DSP/placement DENSITY alone do to Fmax, with zero
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shared interconnect logic between cores?
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METHOD: new `hardware/v3/rtl/np_packed_array.v`, N_CORES=8 flat array
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of unmodified neural_processor_packed.v instances, each core's I/O fully
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independent (flattened N*WIDTH buses, sliced per-instance, generate
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block) -- deliberately NO arbiter/Director/shared bus, so any Fmax
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change vs EXP-0059's single-core number is attributable ONLY to
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placement/routing congestion from DSP/LUT/FF density, not to any new
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(unverified) integration logic. Real Vivado 2026.1 out-of-context
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synth + opt_design + place_design + route_design, same 200MHz
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(-period 5.000) constraint and part (xc7a100tcsg324-1) as EXP-0059,
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via `hardware/v3/synth/synth_np_packed_array_n8.tcl`.
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RESULT (real, post-route, not estimated): 64/240 DSP48E1 (26.67%,
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exactly 8 cores x 8 DSP, matches EXP-0059's per-core count). WNS
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-2.592ns @ 200MHz -> real critical path 7.592ns -> Fmax ~131.7MHz.
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Vs EXP-0059's single-core 134.9MHz: a real but SMALL degradation,
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-2.4%, from placement/routing density alone at 8 independent cores /
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~27% DSP utilization.
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DECISION: the earlier V2/ECP5 gap between isolated-core and full-
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system Fmax is NOT mostly explained by raw compute-array placement
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density (this experiment's -2.4% is far smaller than ECP5's ~30%+
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isolated-vs-system gap) -- the real driver is most likely the shared
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Director/arbiter/memory-path interconnect logic itself, not yet built
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or tested here. This narrows, not answers, the open question from
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EXP-0059 -- still no real system-level number exists.
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next_action: build the real Director + memory-feed path for the
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packed 2-job-per-core model (neural_director.v needs real changes to
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dispatch PAIRS of jobs per core, not a 1:1 port) as a properly
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correctness-verified (isolated testbench, bit-exact vs golden model)
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integration BEFORE the next real P&R congestion check -- do not
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synthesize unverified integration RTL just to get another Fmax number,
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per this project's own correctness-first standard.
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@@ -0,0 +1,80 @@
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`timescale 1ns/1ps
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// ============================================================
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// EXP-0059 follow-up -- N independent neural_processor_packed.v
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// cores, flat array, NO Director/arbiter/memory path yet.
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//
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// PURPOSE: isolate exactly one variable -- what real P&R placement/
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// routing congestion does to Fmax once N copies of the DSP48-packed
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// core sit side by side on XC7A100T -- before adding any new
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// (unverified) integration RTL (Director, arbiter, memory path).
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// Each core keeps its own independent, unshared I/O (flattened to
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// N*WIDTH buses, sliced per-instance below); there is deliberately NO
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// interconnect logic here to conflate with the placement-density
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// question this experiment is asking. Matches this project's own
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// "one variable at a time" convention (see decisions.log).
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// ============================================================
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module np_packed_array #(
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parameter DATA_WIDTH = 8,
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parameter P_IN = 8,
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parameter ACC_WIDTH = 32,
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parameter N_CORES = 8
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)(
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input wire clk,
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input wire rst,
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input wire [N_CORES-1:0] job_valid,
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output wire [N_CORES-1:0] job_ready,
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input wire [N_CORES*16-1:0] job_node_id_a,
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input wire [N_CORES*16-1:0] job_node_id_b,
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input wire [N_CORES*DATA_WIDTH-1:0] job_bias,
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input wire [N_CORES*2-1:0] job_activation,
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input wire [N_CORES-1:0] operand_valid,
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output wire [N_CORES-1:0] operand_ready,
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input wire [N_CORES*DATA_WIDTH*P_IN-1:0] input_data_a,
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input wire [N_CORES*DATA_WIDTH*P_IN-1:0] input_data_b,
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input wire [N_CORES*DATA_WIDTH*P_IN-1:0] weight_data,
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input wire [N_CORES-1:0] tile_last,
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output wire [N_CORES-1:0] result_valid,
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input wire [N_CORES-1:0] result_ready,
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output wire [N_CORES*DATA_WIDTH-1:0] result_data_a,
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output wire [N_CORES*DATA_WIDTH-1:0] result_data_b,
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output wire [N_CORES*16-1:0] result_node_id_a,
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output wire [N_CORES*16-1:0] result_node_id_b,
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output wire [N_CORES*4-1:0] np_state,
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output wire [N_CORES-1:0] np_error
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);
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genvar gc;
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generate
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for (gc = 0; gc < N_CORES; gc = gc + 1) begin : GEN_CORE
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neural_processor_packed #(
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.DATA_WIDTH(DATA_WIDTH), .P_IN(P_IN), .ACC_WIDTH(ACC_WIDTH)
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) u_core (
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.clk(clk), .rst(rst),
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.job_valid(job_valid[gc]),
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.job_ready(job_ready[gc]),
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.job_node_id_a(job_node_id_a[gc*16 +: 16]),
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.job_node_id_b(job_node_id_b[gc*16 +: 16]),
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.job_bias(job_bias[gc*DATA_WIDTH +: DATA_WIDTH]),
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.job_activation(job_activation[gc*2 +: 2]),
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.operand_valid(operand_valid[gc]),
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.operand_ready(operand_ready[gc]),
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.input_data_a(input_data_a[gc*DATA_WIDTH*P_IN +: DATA_WIDTH*P_IN]),
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.input_data_b(input_data_b[gc*DATA_WIDTH*P_IN +: DATA_WIDTH*P_IN]),
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.weight_data(weight_data[gc*DATA_WIDTH*P_IN +: DATA_WIDTH*P_IN]),
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.tile_last(tile_last[gc]),
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.result_valid(result_valid[gc]),
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.result_ready(result_ready[gc]),
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.result_data_a(result_data_a[gc*DATA_WIDTH +: DATA_WIDTH]),
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.result_data_b(result_data_b[gc*DATA_WIDTH +: DATA_WIDTH]),
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.result_node_id_a(result_node_id_a[gc*16 +: 16]),
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.result_node_id_b(result_node_id_b[gc*16 +: 16]),
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.np_state(np_state[gc*4 +: 4]),
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.np_error(np_error[gc])
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);
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end
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endgenerate
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endmodule
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@@ -0,0 +1,11 @@
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read_verilog -sv /home/michele/Develop/FPGA-Neural/hardware/v3/rtl/neural_processor_packed.v
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read_verilog -sv /home/michele/Develop/FPGA-Neural/hardware/v3/rtl/np_packed_array.v
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synth_design -top np_packed_array -part xc7a100tcsg324-1 -mode out_of_context -generic N_CORES=8
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create_clock -name clk -period 5.000 [get_ports clk]
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opt_design
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report_utilization -file /tmp/util_np_array_n8_postsynth.rpt
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place_design
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route_design
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report_utilization -file /tmp/util_np_array_n8_postroute.rpt
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report_timing_summary -file /tmp/timing_np_array_n8_postroute.rpt
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write_checkpoint -force /tmp/np_array_n8_postroute.dcp
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