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docs+synth: Phase 0 complete - N=8 baseline + toolchain discrepancy closed

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N=8 baseline (EXP-0050, real fpga_neural_v2_top + v2_board_top.lpf, fresh
8-seed sweep): 8/8 PASS at 64MHz, worst 80.97MHz, mean 84.62MHz. DSP
64/72 (88.9%) confirms real N_SLOTS=8. This directly contradicts the
brief's own premise (N8 expected to collapse to ~31MHz) and the project's
historical numbers (3-5/8 pass, worst ~55-67MHz) despite bit-identical
RTL.

Investigated and closed the same discrepancy already flagged for N=4:
logs/experiments.log:2563 explicitly tags historical Fmax numbers as
measured on "Yosys 0.68+"; this session's toolchain is Yosys 0.69+59, a
nightly dated the same day as the session -- a confirmed ~59-commit
version gap. Critical-path inspection on both N=4 and N=8 confirms the
underlying RTL congestion the project diagnosed is real and still
present (same bottleneck locations as previously documented) -- the
newer toolchain just places it well enough to still clear 64MHz.

Decision: this session's numbers are adopted as the operative baseline
for Phase 1+ (see timing.log for the full writeup). Also found, not yet
applied: slot_mem_arbiter.v/slot_mem_arbiter_wide.v both still have the
runtime-indexed-crossbar anti-pattern already fixed in neural_director.v,
sitting right on the arbiter<->backend boundary the brief names -- a
concrete Phase 1 candidate.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
This commit is contained in:
michele
2026-09-15 21:44:10 +00:00
co-authored by Claude Sonnet 5
parent 685a4d6cfe
commit 19ef54aea8
12 changed files with 1051471 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
hardware/v2/logs/timing.log
+79
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@@ -189,3 +189,82 @@ request, 2026-09-15) after an N=8 P&R run against the WRONG target
(the obsolete wrapper, since discarded) stalled for 2h42m without
converging on a single seed -- to be re-attempted against the correct
fpga_neural_v2_top target, with a time budget decided before re-running.
[2026-09-15] EXP-0050 -- fpga_neural_v2_top (real board-level top,
N_SLOTS=8), real nextpnr-ecp5 --45k --package CABGA381 --speed 8
--lpf hardware/v2/constraints/v2_board_top.lpf, fresh 8-seed sweep
(re-attempt after ERR-0031's wrong-target run stalled 2h42m/seed0
without converging -- this run, on the CORRECT target, completed all
8 seeds in under 30 minutes total, ~2-3 min/seed)
Fmax: seed0 84.22, seed1 81.77, seed2 88.64, seed3 84.81, seed4 86.78,
seed5 81.04, seed6 88.70, seed7 80.97 MHz. n=8, worst=80.97 MHz,
mean=84.62 MHz, **8/8 PASS at 64MHz**.
Resources: MULT18X18D 64/72 (88.9%, exactly 8/slot x 8 slots, confirms
N_SLOTS=8 genuinely applied, not a silent N=4 default). DP16KD 0/108.
Critical path (worst seed7, real report, sanity-checked -- NOT a
degenerate/false-path result): u_dataflow_core.GEN_SLOT[4].u_mm.
act_resident_tag (a TRELLIS_FF) -> routing/logic chain through
GEN_SLOT[0] and GEN_SLOT[7]'s own buf_valid LUT chains -- 2.96ns
logic + 9.39ns routing. This IS the activation-fill resident_tag/
resident_count broadcast path the brief's own diagnosis named, real
and present, but NOT enough by itself to fail 64MHz on this
toolchain/seed set.
SURPRISING RESULT, disclosed not hidden: this directly contradicts
the brief's own stated premise ("N8 integrato ~31 MHz crolla") and
this project's own prior historical measurements (errors.log/
decisions.log record N_SLOTS=8 @ 64MHz around 3-5/8 PASS, worst-case
~55-67MHz, across several fix passes). RTL is bit-identical to that
historical state (no RTL changes this session). Consistent with
EXP-0049's own N_SLOTS=4 finding (this session's numbers also came out
higher than DEC-0042's historical N=4 numbers) -- same direction, same
open, unresolved hypothesis (nextpnr-ecp5 build/version difference
between this session's OSS CAD Suite toolchain and whatever produced
the historical numbers).
STATUS: Phase 0 baseline for N_SLOTS=8 established: 8/8 PASS @ 64MHz,
worst 80.97MHz, mean 84.62MHz -- under THIS session's toolchain, the
N=8 "gate" the brief is built around does not reproduce. Reported to
user for direction before proceeding with Phase 1's RTL interventions.
[2026-09-15] Discrepancy investigation (EXP-0049/EXP-0050 vs DEC-0042/
ERR-0029 historical numbers) -- CLOSED, root cause confirmed (partially)
CONFIRMED: `logs/experiments.log` line 2563 (a prior session's own
entry) explicitly classifies its own historical Fmax numbers as
"POST-SYNTH (Yosys 0.68+, synth_ecp5) + POST-P&R". This session's
toolchain (OSS CAD Suite) reports `yosys -V` = "Yosys 0.69+59 (git
sha1 d85872386-dirty)" and its own `VERSION` file = "20260915" (a
nightly build dated the SAME DAY as this session, downloaded fresh
this session per tools_cache/oss-cad-suite-linux-x64.tgz's own
timestamp) -- a real, confirmed Yosys version gap of 59+ commits
between the historical baseline (Sep 5-9) and now (Sep 15).
nextpnr-ecp5's own historical version was never recorded in any prior
log entry (a real logging gap -- see recommendation below), so the
nextpnr side of this hypothesis remains unconfirmed, but nextpnr-ecp5
and Yosys/Trellis are released together in OSS CAD Suite nightlies, so
a comparable placer-side version gap is likely.
CROSS-CHECK, not just version numbers: both this session's N=4 (seed3)
and N=8 (seed7) critical paths were inspected directly and are REAL,
sane, and land on the SAME bottleneck locations this project's own
prior sessions already diagnosed -- N=4: job_out_slot (neural_director)
-> node_producer_ids (dependency_manager), matching DEC-0042's own
root-cause trace verbatim; N=8: act_resident_tag broadcast fan-out
across GEN_SLOT instances, matching the brief's own activation-fill
congestion hypothesis. The underlying RTL congestion this project
diagnosed is REAL and still present -- this session's newer toolchain
places it well enough to still clear 64MHz, it did not make the
bottleneck disappear from the netlist.
CONCLUSION: the higher Fmax this session measures for both N_SLOTS=4
and N_SLOTS=8 is attributed to a real Yosys/nextpnr-ecp5 toolchain
version difference (confirmed for Yosys, likely for nextpnr-ecp5),
not a methodology error, missing constraint, or wrong target (both of
which WERE real errors this session, already found and fixed
separately -- ERR-0030/ERR-0031 -- before this investigation). Given
this session's numbers come from real synthesis+P&R with real physical
constraints and real, sane, precedented critical paths, they are
adopted as the authoritative current baseline for all Phase 1+ work in
this brief, superseding DEC-0042/ERR-0029's numbers (which remain
historically valid for their own, older toolchain).
PROCESS RECOMMENDATION (to prevent this ambiguity recurring): every
synthesis.log/timing.log entry should record `yosys -V` and
`nextpnr-ecp5 --version` output going forward -- neither was ever
captured historically, which is what made this investigation take real
effort instead of a one-line diff.
hardware/v2/nms/synthesis/nms_multiproc_n8/nextpnr_seed0.log
+497
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@@ -0,0 +1,497 @@
Info: constraining clock net 'osc_clk' to 16.00 MHz
Info: Logic utilisation before packing:
Info: Total LUT4s: 10214/43848 23%
Info: logic LUTs: 5504/43848 12%
Info: carry LUTs: 2772/43848 6%
Info: RAM LUTs: 1292/ 5481 23%
Info: RAMW LUTs: 646/10962 5%
Info: Total DFFs: 11126/43848 25%
Info: Packing IOs..
Info: $sdram_dq[15]$iobuf_i: sdram_dq_$_TBUF__Y.Y
Info: pin 'sdram_dq[15]$tr_io' constrained to Bel 'X0/Y59/PIOB'.
Info: $sdram_dq[14]$iobuf_i: sdram_dq_$_TBUF__Y_15.Y
Info: pin 'sdram_dq[14]$tr_io' constrained to Bel 'X0/Y59/PIOC'.
Info: $sdram_dq[13]$iobuf_i: sdram_dq_$_TBUF__Y_14.Y
Info: pin 'sdram_dq[13]$tr_io' constrained to Bel 'X0/Y59/PIOA'.
Info: $sdram_dq[12]$iobuf_i: sdram_dq_$_TBUF__Y_13.Y
Info: pin 'sdram_dq[12]$tr_io' constrained to Bel 'X0/Y53/PIOA'.
Info: $sdram_dq[11]$iobuf_i: sdram_dq_$_TBUF__Y_12.Y
Info: pin 'sdram_dq[11]$tr_io' constrained to Bel 'X0/Y44/PIOD'.
Info: $sdram_dq[10]$iobuf_i: sdram_dq_$_TBUF__Y_11.Y
Info: pin 'sdram_dq[10]$tr_io' constrained to Bel 'X0/Y44/PIOC'.
Info: $sdram_dq[9]$iobuf_i: sdram_dq_$_TBUF__Y_10.Y
Info: pin 'sdram_dq[9]$tr_io' constrained to Bel 'X0/Y44/PIOA'.
Info: $sdram_dq[8]$iobuf_i: sdram_dq_$_TBUF__Y_9.Y
Info: pin 'sdram_dq[8]$tr_io' constrained to Bel 'X0/Y41/PIOD'.
Info: $sdram_dq[7]$iobuf_i: sdram_dq_$_TBUF__Y_8.Y
Info: pin 'sdram_dq[7]$tr_io' constrained to Bel 'X0/Y41/PIOB'.
Info: $sdram_dq[6]$iobuf_i: sdram_dq_$_TBUF__Y_7.Y
Info: pin 'sdram_dq[6]$tr_io' constrained to Bel 'X0/Y41/PIOC'.
Info: $sdram_dq[5]$iobuf_i: sdram_dq_$_TBUF__Y_6.Y
Info: pin 'sdram_dq[5]$tr_io' constrained to Bel 'X0/Y41/PIOA'.
Info: $sdram_dq[4]$iobuf_i: sdram_dq_$_TBUF__Y_5.Y
Info: pin 'sdram_dq[4]$tr_io' constrained to Bel 'X0/Y38/PIOD'.
Info: $sdram_dq[3]$iobuf_i: sdram_dq_$_TBUF__Y_4.Y
Info: pin 'sdram_dq[3]$tr_io' constrained to Bel 'X0/Y38/PIOB'.
Info: $sdram_dq[2]$iobuf_i: sdram_dq_$_TBUF__Y_3.Y
Info: pin 'sdram_dq[2]$tr_io' constrained to Bel 'X0/Y29/PIOD'.
Info: $sdram_dq[1]$iobuf_i: sdram_dq_$_TBUF__Y_2.Y
Info: pin 'sdram_dq[1]$tr_io' constrained to Bel 'X0/Y29/PIOB'.
Info: $sdram_dq[0]$iobuf_i: sdram_dq_$_TBUF__Y_1.Y
Info: pin 'sdram_dq[0]$tr_io' constrained to Bel 'X0/Y26/PIOD'.
Info: pin 'spi_sclk$tr_io' constrained to Bel 'X0/Y62/PIOC'.
Info: pin 'spi_mosi$tr_io' constrained to Bel 'X0/Y62/PIOB'.
Info: pin 'spi_miso$tr_io' constrained to Bel 'X0/Y62/PIOD'.
Info: pin 'spi_cs_n$tr_io' constrained to Bel 'X0/Y65/PIOA'.
Info: pin 'sdram_we_n$tr_io' constrained to Bel 'X0/Y14/PIOD'.
Info: pin 'sdram_ras_n$tr_io' constrained to Bel 'X0/Y14/PIOA'.
Info: pin 'sdram_dqm[1]$tr_io' constrained to Bel 'X0/Y62/PIOA'.
Info: pin 'sdram_dqm[0]$tr_io' constrained to Bel 'X0/Y59/PIOD'.
Info: pin 'sdram_cs_n$tr_io' constrained to Bel 'X0/Y11/PIOD'.
Info: pin 'sdram_clk$tr_io' constrained to Bel 'X0/Y38/PIOA'.
Info: pin 'sdram_cke$tr_io' constrained to Bel 'X0/Y11/PIOC'.
Info: pin 'sdram_cas_n$tr_io' constrained to Bel 'X0/Y14/PIOC'.
Info: pin 'sdram_ba[1]$tr_io' constrained to Bel 'X0/Y17/PIOC'.
Info: pin 'sdram_ba[0]$tr_io' constrained to Bel 'X0/Y17/PIOA'.
Info: pin 'sdram_a[12]$tr_io' constrained to Bel 'X0/Y35/PIOB'.
Info: pin 'sdram_a[11]$tr_io' constrained to Bel 'X0/Y26/PIOB'.
Info: pin 'sdram_a[10]$tr_io' constrained to Bel 'X0/Y26/PIOC'.
Info: pin 'sdram_a[9]$tr_io' constrained to Bel 'X0/Y26/PIOA'.
Info: pin 'sdram_a[8]$tr_io' constrained to Bel 'X0/Y23/PIOD'.
Info: pin 'sdram_a[7]$tr_io' constrained to Bel 'X0/Y23/PIOB'.
Info: pin 'sdram_a[6]$tr_io' constrained to Bel 'X0/Y23/PIOA'.
Info: pin 'sdram_a[5]$tr_io' constrained to Bel 'X0/Y20/PIOD'.
Info: pin 'sdram_a[4]$tr_io' constrained to Bel 'X0/Y20/PIOB'.
Info: pin 'sdram_a[3]$tr_io' constrained to Bel 'X0/Y20/PIOC'.
Info: pin 'sdram_a[2]$tr_io' constrained to Bel 'X0/Y20/PIOA'.
Info: pin 'sdram_a[1]$tr_io' constrained to Bel 'X0/Y17/PIOD'.
Info: pin 'sdram_a[0]$tr_io' constrained to Bel 'X0/Y17/PIOB'.
Info: pin 'pll_locked$tr_io' constrained to Bel 'X0/Y65/PIOC'.
Info: pin 'osc_clk$tr_io' constrained to Bel 'X0/Y29/PIOC'.
Info: pin 'ext_rst_n$tr_io' constrained to Bel 'X0/Y14/PIOB'.
Info: pin 'data_ready$tr_io' constrained to Bel 'X0/Y32/PIOA'.
Info: placed PLL 'u_pll.pll_i' at bel 'X1/Y4/EHXPLL_UL'
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 3832 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Input frequency of PLL 'u_pll.pll_i' is constrained to 16.0 MHz
Info: Derived frequency constraint of 64.0 MHz for net sdram_clk$TRELLIS_IO_OUT
Info: Promoting globals...
Info: promoting clock net sdram_clk$TRELLIS_IO_OUT to global network
Info: Checksum: 0x94c17baa
Info: Device utilisation:
Info: TRELLIS_IO: 47/ 245 19%
Info: DCCA: 1/ 56 1%
Info: DP16KD: 0/ 108 0%
Info: MULT18X18D: 64/ 72 88%
Info: ALU54B: 0/ 36 0%
Info: EHXPLLL: 1/ 4 25%
Info: EXTREFB: 0/ 2 0%
Info: DCUA: 0/ 2 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 0/ 160 0%
Info: SIOLOGIC: 0/ 85 0%
Info: GSR: 0/ 1 0%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 0/ 1 0%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 11126/ 43848 25%
Info: TRELLIS_COMB: 11032/ 43848 25%
Info: TRELLIS_RAMW: 323/ 5481 5%
Info: Placed 48 cells based on constraints.
Info: Creating initial analytic placement for 12988 cells, random placement wirelen = 1056415.
Info: at initial placer iter 0, wirelen = 5199
Info: at initial placer iter 1, wirelen = 4619
Info: at initial placer iter 2, wirelen = 4278
Info: at initial placer iter 3, wirelen = 4242
Info: Running main analytical placer, max placement attempts per cell = 63811104.
Info: at iteration #1, type ALL: wirelen solved = 4197, spread = 246691, legal = 270367; time = 2.49s
Info: at iteration #2, type ALL: wirelen solved = 24576, spread = 174929, legal = 198491; time = 2.33s
Info: at iteration #3, type ALL: wirelen solved = 35850, spread = 157783, legal = 189081; time = 2.21s
Info: at iteration #4, type ALL: wirelen solved = 42434, spread = 152331, legal = 177726; time = 2.24s
Info: at iteration #5, type ALL: wirelen solved = 44664, spread = 148397, legal = 181320; time = 2.28s
Info: at iteration #6, type ALL: wirelen solved = 45304, spread = 147056, legal = 179038; time = 2.28s
Info: at iteration #7, type ALL: wirelen solved = 47190, spread = 147358, legal = 173708; time = 2.15s
Info: at iteration #8, type ALL: wirelen solved = 49616, spread = 145208, legal = 179614; time = 2.24s
Info: at iteration #9, type ALL: wirelen solved = 49879, spread = 150739, legal = 172947; time = 2.15s
Info: at iteration #10, type ALL: wirelen solved = 53106, spread = 149368, legal = 172316; time = 2.09s
Info: at iteration #11, type ALL: wirelen solved = 54504, spread = 149665, legal = 168807; time = 2.23s
Info: at iteration #12, type ALL: wirelen solved = 55105, spread = 149822, legal = 170978; time = 2.21s
Info: at iteration #13, type ALL: wirelen solved = 56128, spread = 150392, legal = 174421; time = 2.18s
Info: at iteration #14, type ALL: wirelen solved = 57876, spread = 150893, legal = 169068; time = 2.11s
Info: at iteration #15, type ALL: wirelen solved = 58396, spread = 150771, legal = 169733; time = 2.07s
Info: at iteration #16, type ALL: wirelen solved = 59831, spread = 150938, legal = 171101; time = 2.14s
Info: HeAP Placer Time: 40.33s
Info: of which solving equations: 8.12s
Info: of which spreading cells: 1.35s
Info: of which strict legalisation: 27.48s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 2488, wirelen = 168807
Info: at iteration #5: temp = 0.000000, timing cost = 2167, wirelen = 157433
Info: at iteration #10: temp = 0.000000, timing cost = 1699, wirelen = 154826
Info: at iteration #15: temp = 0.000000, timing cost = 2020, wirelen = 153737
Info: at iteration #20: temp = 0.000000, timing cost = 1997, wirelen = 153269
Info: at iteration #25: temp = 0.000000, timing cost = 1995, wirelen = 153093
Info: at iteration #30: temp = 0.000000, timing cost = 1988, wirelen = 152986
Info: at iteration #35: temp = 0.000000, timing cost = 1983, wirelen = 152958
Info: at iteration #36: temp = 0.000000, timing cost = 1976, wirelen = 152940
Info: SA placement time 60.53s
Info: Max frequency for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT': 65.99 MHz (PASS at 64.00 MHz)
Info: Max delay <async> -> posedge $glbnet$sdram_clk$TRELLIS_IO_OUT: 7.10 ns
Info: Max delay posedge $glbnet$sdram_clk$TRELLIS_IO_OUT -> <async> : 7.94 ns
Info: Slack histogram:
Info: legend: * represents 63 endpoint(s)
Info: + represents [1,63) endpoint(s)
Info: [ 472, 1201) |+
Info: [ 1201, 1930) |+
Info: [ 1930, 2659) |**+
Info: [ 2659, 3388) |***+
Info: [ 3388, 4117) |***+
Info: [ 4117, 4846) |*****+
Info: [ 4846, 5575) |*****+
Info: [ 5575, 6304) |******+
Info: [ 6304, 7033) |***********+
Info: [ 7033, 7762) |*************+
Info: [ 7762, 8491) |****************************+
Info: [ 8491, 9220) |***********************************************+
Info: [ 9220, 9949) |***********************************************+
Info: [ 9949, 10678) |*****************************************+
Info: [ 10678, 11407) |***********************************+
Info: [ 11407, 12136) |****************************************+
Info: [ 12136, 12865) |***************************************************+
Info: [ 12865, 13594) |************************************************************
Info: [ 13594, 14323) |**********************************************+
Info: [ 14323, 15052) |**************************************************+
Info: Checksum: 0x818ce9f4
Info: Routing globals...
Info: routing clock net $glbnet$sdram_clk$TRELLIS_IO_OUT using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 60852 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 736 263 | 736 263 | 60721| 1.77 1.77|
Info: 2000 | 1466 533 | 730 270 | 60615| 1.31 3.08|
Info: 3000 | 2050 949 | 584 416 | 60529| 1.10 4.18|
Info: 4000 | 2639 1360 | 589 411 | 60388| 1.48 5.67|
Info: 5000 | 3206 1793 | 567 433 | 60298| 1.46 7.12|
Info: 6000 | 3790 2209 | 584 416 | 60151| 1.70 8.82|
Info: 7000 | 4304 2695 | 514 486 | 60035| 1.46 10.28|
Info: 8000 | 4874 3125 | 570 430 | 59836| 1.53 11.81|
Info: 9000 | 5491 3508 | 617 383 | 59724| 1.26 13.07|
Info: 10000 | 5936 4063 | 445 555 | 59584| 1.21 14.27|
Info: 11000 | 6351 4648 | 415 585 | 59440| 1.41 15.68|
Info: 12000 | 6789 5210 | 438 562 | 59288| 1.67 17.35|
Info: 13000 | 7164 5835 | 375 625 | 59133| 1.71 19.06|
Info: 14000 | 7563 6436 | 399 601 | 58930| 2.21 21.27|
Info: 15000 | 7821 7178 | 258 742 | 58502| 1.56 22.83|
Info: 16000 | 8040 7959 | 219 781 | 58013| 1.40 24.23|
Info: 17000 | 8311 8688 | 271 729 | 57539| 1.99 26.22|
Info: 18000 | 8578 9421 | 267 733 | 56946| 1.94 28.15|
Info: 19000 | 8801 10198 | 223 777 | 56480| 2.27 30.42|
Info: 20000 | 8912 11087 | 111 889 | 55754| 1.17 31.59|
Info: 21000 | 9046 11953 | 134 866 | 54954| 0.86 32.45|
Info: 22000 | 9230 12769 | 184 816 | 54703| 1.38 33.83|
Info: 23000 | 9394 13605 | 164 836 | 54010| 0.86 34.69|
Info: 24000 | 9545 14454 | 151 849 | 53277| 1.05 35.74|
Info: 25000 | 9676 15323 | 131 869 | 52472| 0.96 36.71|
Info: 26000 | 9776 16223 | 100 900 | 51725| 0.63 37.34|
Info: 27000 | 9875 17124 | 99 901 | 50912| 0.91 38.24|
Info: 28000 | 9980 18019 | 105 895 | 50075| 0.71 38.96|
Info: 29000 | 10066 18933 | 86 914 | 49232| 0.70 39.66|
Info: 30000 | 10109 19890 | 43 957 | 48338| 0.50 40.17|
Info: 31000 | 10237 20762 | 128 872 | 47703| 0.54 40.70|
Info: 32000 | 10293 21706 | 56 944 | 46820| 0.47 41.17|
Info: 33000 | 10397 22602 | 104 896 | 46096| 0.60 41.77|
Info: 34000 | 10455 23544 | 58 942 | 45230| 0.41 42.18|
Info: 35000 | 10581 24418 | 126 874 | 44375| 0.46 42.64|
Info: 36000 | 10667 25332 | 86 914 | 43602| 0.52 43.16|
Info: 37000 | 10746 26253 | 79 921 | 42889| 0.44 43.60|
Info: 38000 | 10862 27137 | 116 884 | 42212| 0.55 44.15|
Info: 39000 | 11061 27938 | 199 801 | 41487| 0.82 44.96|
Info: 40000 | 11229 28770 | 168 832 | 40881| 0.56 45.52|
Info: 41000 | 11404 29595 | 175 825 | 40161| 0.65 46.17|
Info: 42000 | 11542 30457 | 138 862 | 39478| 0.60 46.77|
Info: 43000 | 11720 31279 | 178 822 | 38850| 0.59 47.36|
Info: 44000 | 11823 32176 | 103 897 | 38124| 0.49 47.85|
Info: 45000 | 11919 33080 | 96 904 | 37464| 0.52 48.37|
Info: 46000 | 12094 33904 | 175 824 | 36736| 0.70 49.07|
Info: 47000 | 12321 34676 | 227 772 | 36086| 0.49 49.56|
Info: 48000 | 12573 35423 | 252 747 | 35378| 0.53 50.09|
Info: 49000 | 12832 36164 | 259 741 | 34875| 0.67 50.75|
Info: 50000 | 13052 36944 | 220 780 | 34307| 0.62 51.37|
Info: 51000 | 13264 37731 | 212 787 | 33790| 0.71 52.09|
Info: 52000 | 13474 38518 | 210 787 | 33119| 0.75 52.84|
Info: 53000 | 13758 39228 | 284 710 | 32543| 0.66 53.50|
Info: 54000 | 13951 40020 | 193 792 | 32104| 0.81 54.31|
Info: 55000 | 14105 40863 | 154 843 | 31581| 0.61 54.92|
Info: 56000 | 14313 41644 | 208 781 | 31020| 0.68 55.60|
Info: 57000 | 14566 42377 | 253 733 | 30689| 0.59 56.18|
Info: 58000 | 14739 43202 | 173 825 | 30260| 0.60 56.79|
Info: 59000 | 14970 43962 | 231 760 | 29876| 0.76 57.55|
Info: 60000 | 15204 44703 | 234 741 | 29496| 0.82 58.37|
Info: 61000 | 15414 45453 | 210 750 | 29313| 0.82 59.20|
Info: 62000 | 15628 46227 | 214 774 | 29023| 1.13 60.32|
Info: 63000 | 15846 46956 | 218 729 | 28355| 0.73 61.06|
Info: 64000 | 16052 47731 | 206 775 | 27819| 0.71 61.76|
Info: 65000 | 16301 48448 | 249 717 | 27297| 0.90 62.66|
Info: 66000 | 16532 49172 | 231 724 | 26799| 0.76 63.42|
Info: 67000 | 16773 49901 | 241 729 | 26439| 1.00 64.42|
Info: 68000 | 16985 50634 | 212 733 | 25917| 0.67 65.09|
Info: 69000 | 17190 51392 | 205 758 | 25336| 0.90 65.99|
Info: 70000 | 17396 52129 | 206 737 | 24700| 0.70 66.69|
Info: 71000 | 17626 52858 | 230 729 | 24071| 0.86 67.55|
Info: 72000 | 17806 53635 | 180 777 | 23390| 0.60 68.15|
Info: 73000 | 18046 54393 | 240 758 | 23314| 1.30 69.44|
Info: 74000 | 18228 55168 | 182 775 | 22859| 0.80 70.24|
Info: 75000 | 18418 55953 | 190 785 | 22497| 0.73 70.98|
Info: 76000 | 18620 56692 | 202 739 | 21990| 0.76 71.74|
Info: 77000 | 18908 57361 | 288 669 | 21568| 1.40 73.14|
Info: 78000 | 19159 58076 | 251 715 | 21267| 0.85 73.99|
Info: 79000 | 19358 58836 | 199 760 | 20712| 0.89 74.87|
Info: 80000 | 19582 59582 | 224 746 | 20145| 1.23 76.11|
Info: 81000 | 19852 60295 | 270 713 | 19657| 0.96 77.07|
Info: 82000 | 20139 61001 | 287 706 | 19379| 1.04 78.10|
Info: 83000 | 20444 61680 | 305 679 | 19235| 1.09 79.19|
Info: 84000 | 20701 62411 | 257 731 | 19131| 1.23 80.42|
Info: 85000 | 20925 63186 | 224 775 | 18816| 1.11 81.54|
Info: 86000 | 21208 63892 | 283 706 | 18598| 1.06 82.60|
Info: 87000 | 21463 64630 | 255 738 | 19079| 1.57 84.16|
Info: 88000 | 21622 65471 | 159 841 | 18520| 1.17 85.33|
Info: 89000 | 21825 66266 | 203 795 | 18252| 1.26 86.60|
Info: 90000 | 22015 67037 | 190 771 | 17625| 0.63 87.22|
Info: 91000 | 22235 67805 | 220 768 | 17317| 1.01 88.23|
Info: 92000 | 22438 68601 | 203 796 | 17107| 1.13 89.36|
Info: 93000 | 22667 69322 | 229 721 | 16546| 1.00 90.36|
Info: 94000 | 22884 70083 | 217 761 | 15966| 0.99 91.35|
Info: 95000 | 23187 70780 | 303 697 | 15775| 1.55 92.90|
Info: 96000 | 23448 71519 | 261 739 | 15694| 1.79 94.69|
Info: 97000 | 23681 72255 | 233 736 | 15179| 1.06 95.75|
Info: 98000 | 23912 72976 | 231 721 | 14706| 1.07 96.82|
Info: 99000 | 24136 73720 | 224 744 | 14167| 0.98 97.79|
Info: 100000 | 24333 74483 | 197 763 | 13837| 1.11 98.90|
Info: 101000 | 24597 75193 | 264 710 | 13427| 1.16 100.06|
Info: 102000 | 24865 75905 | 268 712 | 13083| 1.11 101.17|
Info: 103000 | 25150 76620 | 285 715 | 13025| 1.35 102.52|
Info: 104000 | 25432 77338 | 282 718 | 12956| 1.26 103.78|
Info: 105000 | 25800 77970 | 368 632 | 12951| 1.62 105.40|
Info: 106000 | 26043 78727 | 243 757 | 12743| 1.44 106.84|
Info: 107000 | 26210 79468 | 167 741 | 12036| 0.76 107.60|
Info: 108000 | 26444 80205 | 234 737 | 11552| 1.19 108.79|
Info: 109000 | 26676 80929 | 232 724 | 11363| 1.10 109.89|
Info: 110000 | 26808 81752 | 132 823 | 10882| 0.67 110.56|
Info: 111000 | 27044 82484 | 236 732 | 10566| 1.09 111.65|
Info: 112000 | 27192 83256 | 148 772 | 10212| 1.31 112.96|
Info: 113000 | 27393 84055 | 201 799 | 10002| 1.29 114.25|
Info: 114000 | 27769 84679 | 376 624 | 10031| 1.40 115.65|
Info: 115000 | 28093 85355 | 324 676 | 9999| 1.47 117.12|
Info: 116000 | 28379 86061 | 286 706 | 9759| 1.44 118.56|
Info: 117000 | 28677 86763 | 298 702 | 9651| 1.52 120.09|
Info: 118000 | 29041 87399 | 364 636 | 9607| 1.79 121.87|
Info: 119000 | 29396 88044 | 355 645 | 9458| 1.65 123.52|
Info: 120000 | 29802 88638 | 406 594 | 9387| 1.67 125.20|
Info: 121000 | 29961 89401 | 159 763 | 8608| 0.71 125.90|
Info: 122000 | 30053 90303 | 92 902 | 7725| 0.44 126.35|
Info: 123000 | 30411 90942 | 358 639 | 7332| 1.24 127.59|
Info: 124000 | 30782 91571 | 371 629 | 7384| 1.52 129.11|
Info: 125000 | 31145 92208 | 363 637 | 7153| 1.40 130.51|
Info: 126000 | 31430 92923 | 285 715 | 7187| 1.49 132.00|
Info: 127000 | 31814 93539 | 384 616 | 6987| 1.77 133.78|
Info: 128000 | 32293 94060 | 479 521 | 6954| 1.68 135.46|
Info: 129000 | 32641 94712 | 348 652 | 6754| 1.73 137.19|
Info: 130000 | 33032 95321 | 391 609 | 6624| 1.65 138.84|
Info: 131000 | 33367 95976 | 335 655 | 6231| 1.72 140.55|
Info: 132000 | 33554 96789 | 187 813 | 5497| 0.73 141.28|
Info: 133000 | 33857 97486 | 303 697 | 5115| 1.15 142.43|
Info: 134000 | 34285 98058 | 428 572 | 5018| 2.15 144.58|
Info: 135000 | 34655 98688 | 370 630 | 5084| 1.67 146.25|
Info: 136000 | 35109 99234 | 454 546 | 5053| 1.61 147.86|
Info: 137000 | 35445 99898 | 336 664 | 5059| 1.96 149.82|
Info: 138000 | 35738 100605 | 293 707 | 5070| 1.46 151.28|
Info: 139000 | 36118 101225 | 380 620 | 4923| 1.87 153.15|
Info: 140000 | 36508 101835 | 390 610 | 4871| 1.90 155.05|
Info: 141000 | 36903 102440 | 395 605 | 4781| 2.13 157.18|
Info: 142000 | 37293 103050 | 390 610 | 4678| 2.02 159.20|
Info: 143000 | 37685 103658 | 392 608 | 4618| 1.58 160.78|
Info: 144000 | 38074 104269 | 389 611 | 4892| 1.71 162.49|
Info: 145000 | 38333 105010 | 259 741 | 4699| 1.92 164.41|
Info: 146000 | 38656 105687 | 323 677 | 4607| 1.79 166.21|
Info: 147000 | 39023 106320 | 367 633 | 4545| 1.92 168.13|
Info: 148000 | 39386 106957 | 363 637 | 4529| 2.02 170.14|
Info: 149000 | 39820 107523 | 434 566 | 4453| 2.28 172.42|
Info: 150000 | 40292 108051 | 472 528 | 4430| 2.41 174.83|
Info: 151000 | 40739 108604 | 447 553 | 4313| 1.97 176.79|
Info: 152000 | 41157 109186 | 418 582 | 4295| 2.08 178.87|
Info: 153000 | 41449 109894 | 292 708 | 3761| 1.10 179.97|
Info: 154000 | 41780 110563 | 331 669 | 3335| 1.28 181.25|
Info: 155000 | 42115 111217 | 335 654 | 2963| 1.47 182.71|
Info: 156000 | 42391 111902 | 276 685 | 2768| 1.56 184.28|
Info: 157000 | 42751 112535 | 360 633 | 2686| 1.78 186.05|
Info: 158000 | 42971 113223 | 220 688 | 2169| 1.62 187.68|
Info: 159000 | 43250 113914 | 279 691 | 2076| 1.79 189.46|
Info: 160000 | 43504 114602 | 254 688 | 1647| 1.84 191.30|
Info: 161000 | 43737 115254 | 233 652 | 1108| 1.30 192.60|
Info: 162000 | 44003 115917 | 266 663 | 695| 1.58 194.18|
Info: 163000 | 44270 116604 | 267 687 | 410| 1.72 195.91|
Info: 164000 | 44562 117289 | 292 685 | 315| 1.81 197.72|
Info: 164897 | 44804 117893 | 242 604 | 0| 1.61 199.33|
Info: Routing complete.
Info: Router1 time 199.33s
Info: Checksum: 0x025a3ac8
Info: Critical path report for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT' (posedge -> posedge):
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source u_arbiter_wide.m_addr_TRELLIS_FF_Q_24.Q
Info: routing 0.88 1.28 Net u_arbiter_wide.m_addr[24] (38,9) -> (38,6)
Info: Sink u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_Z_1.A
Info: Defined in:
Info: hardware/v2/rtl/slot_mem_arbiter_wide.v:75.35-75.41
Info: logic 0.18 1.46 Source u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_Z_1.F
Info: routing 0.77 2.23 Net u_sdram_backend.w_cache_valid[2]_LUT4_C_Z[1] (38,6) -> (35,5)
Info: Sink u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D.C
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 2.41 Source u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D.F
Info: routing 0.32 2.73 Net u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z[3] (35,5) -> (35,5)
Info: Sink u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 2.91 Source u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D.F
Info: routing 0.72 3.63 Net u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z[3] (35,5) -> (36,6)
Info: Sink u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 3.82 Source u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D.F
Info: routing 0.65 4.47 Net u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z[3] (36,6) -> (36,8)
Info: Sink u_sdram_backend.w_cache_valid[3]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.65 Source u_sdram_backend.w_cache_valid[3]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.F
Info: routing 0.98 5.62 Net u_sdram_backend.w_cache_valid[3]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z[2] (36,8) -> (21,8)
Info: Sink u_sdram_backend.w_cache_valid[0]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 5.80 Source u_sdram_backend.w_cache_valid[0]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.F
Info: routing 1.03 6.83 Net u_sdram_backend.w_cache_hit_LUT4_B_Z[3] (21,8) -> (33,5)
Info: Sink u_sdram_backend.w_cache_hit_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 7.01 Source u_sdram_backend.w_cache_hit_LUT4_Z.F
Info: routing 0.81 7.82 Net u_sdram_backend.w_alloc_ptr_TRELLIS_FF_Q_CE[0] (33,5) -> (23,5)
Info: Sink u_sdram_backend.w_cache_hit_LUT4_C.C
Info: Defined in:
Info: hardware/v2/nms/rtl/sdram_unified_backend.v:184.10-184.21
Info: logic 0.18 8.00 Source u_sdram_backend.w_cache_hit_LUT4_C.F
Info: routing 0.78 8.78 Net u_sdram_backend.w_cache_hit_LUT4_C_Z[0] (23,5) -> (22,11)
Info: Sink u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z.C
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 8.96 Source u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z.F
Info: routing 0.80 9.76 Net u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D[3] (22,11) -> (22,17)
Info: Sink u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_D.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 9.94 Source u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_D.F
Info: routing 1.93 11.87 Net u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_D_Z[3] (22,17) -> (22,52)
Info: Sink u_sdram_backend.ctrl_wdata_TRELLIS_FF_Q_14.CE
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: setup 0.00 11.87 Source u_sdram_backend.ctrl_wdata_TRELLIS_FF_Q_14.CE
Info: 2.19 ns logic, 9.68 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$sdram_clk$TRELLIS_IO_OUT':
Info: type curr total name
Info: source 0.00 0.00 Source ext_rst_n$tr_io.O
Info: routing 1.20 1.20 Net ext_rst_n$TRELLIS_IO_IN (0,14) -> (2,21)
Info: Sink ext_rst_n_LUT4_D.D
Info: Defined in:
Info: hardware/v2/rtl/reset_sync.v:18.17-18.26
Info: logic 0.18 1.38 Source ext_rst_n_LUT4_D.F
Info: routing 3.05 4.43 Net ext_rst_n_LUT4_D_Z (2,21) -> (31,61)
Info: Sink ext_rst_n_LUT4_D_Z_TRELLIS_FF_LSR_DI_TRELLIS_FF_Q.LSR
Info: setup 0.29 4.72 Source ext_rst_n_LUT4_D_Z_TRELLIS_FF_LSR_DI_TRELLIS_FF_Q.LSR
Info: 0.47 ns logic, 4.25 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$sdram_clk$TRELLIS_IO_OUT' -> '<async>':
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source u_spi_bridge.byte_idx_TRELLIS_FF_Q_2.Q
Info: routing 0.78 1.17 Net u_spi_bridge.byte_idx[2] (30,51) -> (33,49)
Info: Sink u_dataflow_core.u_dep_mgr.reg_required_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 1.35 Source u_dataflow_core.u_dep_mgr.reg_required_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_Z.F
Info: routing 0.35 1.70 Net u_dataflow_core.u_dep_mgr.reg_required_TRELLIS_FF_Q_CE_LUT4_Z_C[3] (33,49) -> (33,49)
Info: Sink u_spi_bridge.soft_rst_pulse_TRELLIS_FF_Q_DI_PFUMX_Z_C0_PFUMX_C0_Z_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 1.88 Source u_spi_bridge.soft_rst_pulse_TRELLIS_FF_Q_DI_PFUMX_Z_C0_PFUMX_C0_Z_LUT4_Z.F
Info: routing 1.46 3.35 Net host_mem_ready_LUT4_B_1_Z_LUT4_C_Z[1] (33,49) -> (25,51)
Info: Sink spi_miso_LUT4_Z_D_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 3.53 Source spi_miso_LUT4_Z_D_LUT4_Z.F
Info: routing 1.33 4.86 Net spi_miso_LUT4_Z_B[3] (25,51) -> (25,56)
Info: Sink spi_miso_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 5.04 Source spi_miso_LUT4_Z.F
Info: routing 1.71 6.74 Net spi_miso$TRELLIS_IO_OUT (25,56) -> (0,62)
Info: Sink spi_miso$tr_io.I
Info: Defined in:
Info: hardware/v2/nms/rtl/fpga_neural_v2_top.v:55.17-55.25
Info: 1.12 ns logic, 5.63 ns routing
Info: Max frequency for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT': 84.22 MHz (PASS at 64.00 MHz)
Info: Max delay <async> -> posedge $glbnet$sdram_clk$TRELLIS_IO_OUT: 4.72 ns
Info: Max delay posedge $glbnet$sdram_clk$TRELLIS_IO_OUT -> <async> : 6.74 ns
Info: Slack histogram:
Info: legend: * represents 56 endpoint(s)
Info: + represents [1,56) endpoint(s)
Info: [ 3751, 4310) |+
Info: [ 4310, 4869) |+
Info: [ 4869, 5428) |**+
Info: [ 5428, 5987) |*****+
Info: [ 5987, 6546) |*****+
Info: [ 6546, 7105) |*****+
Info: [ 7105, 7664) |******+
Info: [ 7664, 8223) |*******+
Info: [ 8223, 8782) |***********+
Info: [ 8782, 9341) |********************+
Info: [ 9341, 9900) |*******************************+
Info: [ 9900, 10459) |****************************************+
Info: [ 10459, 11018) |************************************************+
Info: [ 11018, 11577) |*********************************************+
Info: [ 11577, 12136) |*********************************************+
Info: [ 12136, 12695) |************************************************************
Info: [ 12695, 13254) |********************************************************+
Info: [ 13254, 13813) |***********************************************************+
Info: [ 13813, 14372) |***********************************************************+
Info: [ 14372, 14931) |****************************************************+
Info: Program finished normally.
hardware/v2/nms/synthesis/nms_multiproc_n8/nextpnr_seed1.log
+455
View File
@@ -0,0 +1,455 @@
Info: constraining clock net 'osc_clk' to 16.00 MHz
Info: Logic utilisation before packing:
Info: Total LUT4s: 10214/43848 23%
Info: logic LUTs: 5504/43848 12%
Info: carry LUTs: 2772/43848 6%
Info: RAM LUTs: 1292/ 5481 23%
Info: RAMW LUTs: 646/10962 5%
Info: Total DFFs: 11126/43848 25%
Info: Packing IOs..
Info: $sdram_dq[15]$iobuf_i: sdram_dq_$_TBUF__Y.Y
Info: pin 'sdram_dq[15]$tr_io' constrained to Bel 'X0/Y59/PIOB'.
Info: $sdram_dq[14]$iobuf_i: sdram_dq_$_TBUF__Y_15.Y
Info: pin 'sdram_dq[14]$tr_io' constrained to Bel 'X0/Y59/PIOC'.
Info: $sdram_dq[13]$iobuf_i: sdram_dq_$_TBUF__Y_14.Y
Info: pin 'sdram_dq[13]$tr_io' constrained to Bel 'X0/Y59/PIOA'.
Info: $sdram_dq[12]$iobuf_i: sdram_dq_$_TBUF__Y_13.Y
Info: pin 'sdram_dq[12]$tr_io' constrained to Bel 'X0/Y53/PIOA'.
Info: $sdram_dq[11]$iobuf_i: sdram_dq_$_TBUF__Y_12.Y
Info: pin 'sdram_dq[11]$tr_io' constrained to Bel 'X0/Y44/PIOD'.
Info: $sdram_dq[10]$iobuf_i: sdram_dq_$_TBUF__Y_11.Y
Info: pin 'sdram_dq[10]$tr_io' constrained to Bel 'X0/Y44/PIOC'.
Info: $sdram_dq[9]$iobuf_i: sdram_dq_$_TBUF__Y_10.Y
Info: pin 'sdram_dq[9]$tr_io' constrained to Bel 'X0/Y44/PIOA'.
Info: $sdram_dq[8]$iobuf_i: sdram_dq_$_TBUF__Y_9.Y
Info: pin 'sdram_dq[8]$tr_io' constrained to Bel 'X0/Y41/PIOD'.
Info: $sdram_dq[7]$iobuf_i: sdram_dq_$_TBUF__Y_8.Y
Info: pin 'sdram_dq[7]$tr_io' constrained to Bel 'X0/Y41/PIOB'.
Info: $sdram_dq[6]$iobuf_i: sdram_dq_$_TBUF__Y_7.Y
Info: pin 'sdram_dq[6]$tr_io' constrained to Bel 'X0/Y41/PIOC'.
Info: $sdram_dq[5]$iobuf_i: sdram_dq_$_TBUF__Y_6.Y
Info: pin 'sdram_dq[5]$tr_io' constrained to Bel 'X0/Y41/PIOA'.
Info: $sdram_dq[4]$iobuf_i: sdram_dq_$_TBUF__Y_5.Y
Info: pin 'sdram_dq[4]$tr_io' constrained to Bel 'X0/Y38/PIOD'.
Info: $sdram_dq[3]$iobuf_i: sdram_dq_$_TBUF__Y_4.Y
Info: pin 'sdram_dq[3]$tr_io' constrained to Bel 'X0/Y38/PIOB'.
Info: $sdram_dq[2]$iobuf_i: sdram_dq_$_TBUF__Y_3.Y
Info: pin 'sdram_dq[2]$tr_io' constrained to Bel 'X0/Y29/PIOD'.
Info: $sdram_dq[1]$iobuf_i: sdram_dq_$_TBUF__Y_2.Y
Info: pin 'sdram_dq[1]$tr_io' constrained to Bel 'X0/Y29/PIOB'.
Info: $sdram_dq[0]$iobuf_i: sdram_dq_$_TBUF__Y_1.Y
Info: pin 'sdram_dq[0]$tr_io' constrained to Bel 'X0/Y26/PIOD'.
Info: pin 'spi_sclk$tr_io' constrained to Bel 'X0/Y62/PIOC'.
Info: pin 'spi_mosi$tr_io' constrained to Bel 'X0/Y62/PIOB'.
Info: pin 'spi_miso$tr_io' constrained to Bel 'X0/Y62/PIOD'.
Info: pin 'spi_cs_n$tr_io' constrained to Bel 'X0/Y65/PIOA'.
Info: pin 'sdram_we_n$tr_io' constrained to Bel 'X0/Y14/PIOD'.
Info: pin 'sdram_ras_n$tr_io' constrained to Bel 'X0/Y14/PIOA'.
Info: pin 'sdram_dqm[1]$tr_io' constrained to Bel 'X0/Y62/PIOA'.
Info: pin 'sdram_dqm[0]$tr_io' constrained to Bel 'X0/Y59/PIOD'.
Info: pin 'sdram_cs_n$tr_io' constrained to Bel 'X0/Y11/PIOD'.
Info: pin 'sdram_clk$tr_io' constrained to Bel 'X0/Y38/PIOA'.
Info: pin 'sdram_cke$tr_io' constrained to Bel 'X0/Y11/PIOC'.
Info: pin 'sdram_cas_n$tr_io' constrained to Bel 'X0/Y14/PIOC'.
Info: pin 'sdram_ba[1]$tr_io' constrained to Bel 'X0/Y17/PIOC'.
Info: pin 'sdram_ba[0]$tr_io' constrained to Bel 'X0/Y17/PIOA'.
Info: pin 'sdram_a[12]$tr_io' constrained to Bel 'X0/Y35/PIOB'.
Info: pin 'sdram_a[11]$tr_io' constrained to Bel 'X0/Y26/PIOB'.
Info: pin 'sdram_a[10]$tr_io' constrained to Bel 'X0/Y26/PIOC'.
Info: pin 'sdram_a[9]$tr_io' constrained to Bel 'X0/Y26/PIOA'.
Info: pin 'sdram_a[8]$tr_io' constrained to Bel 'X0/Y23/PIOD'.
Info: pin 'sdram_a[7]$tr_io' constrained to Bel 'X0/Y23/PIOB'.
Info: pin 'sdram_a[6]$tr_io' constrained to Bel 'X0/Y23/PIOA'.
Info: pin 'sdram_a[5]$tr_io' constrained to Bel 'X0/Y20/PIOD'.
Info: pin 'sdram_a[4]$tr_io' constrained to Bel 'X0/Y20/PIOB'.
Info: pin 'sdram_a[3]$tr_io' constrained to Bel 'X0/Y20/PIOC'.
Info: pin 'sdram_a[2]$tr_io' constrained to Bel 'X0/Y20/PIOA'.
Info: pin 'sdram_a[1]$tr_io' constrained to Bel 'X0/Y17/PIOD'.
Info: pin 'sdram_a[0]$tr_io' constrained to Bel 'X0/Y17/PIOB'.
Info: pin 'pll_locked$tr_io' constrained to Bel 'X0/Y65/PIOC'.
Info: pin 'osc_clk$tr_io' constrained to Bel 'X0/Y29/PIOC'.
Info: pin 'ext_rst_n$tr_io' constrained to Bel 'X0/Y14/PIOB'.
Info: pin 'data_ready$tr_io' constrained to Bel 'X0/Y32/PIOA'.
Info: placed PLL 'u_pll.pll_i' at bel 'X1/Y4/EHXPLL_UL'
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 3832 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Input frequency of PLL 'u_pll.pll_i' is constrained to 16.0 MHz
Info: Derived frequency constraint of 64.0 MHz for net sdram_clk$TRELLIS_IO_OUT
Info: Promoting globals...
Info: promoting clock net sdram_clk$TRELLIS_IO_OUT to global network
Info: Checksum: 0x94c17baa
Info: Device utilisation:
Info: TRELLIS_IO: 47/ 245 19%
Info: DCCA: 1/ 56 1%
Info: DP16KD: 0/ 108 0%
Info: MULT18X18D: 64/ 72 88%
Info: ALU54B: 0/ 36 0%
Info: EHXPLLL: 1/ 4 25%
Info: EXTREFB: 0/ 2 0%
Info: DCUA: 0/ 2 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 0/ 160 0%
Info: SIOLOGIC: 0/ 85 0%
Info: GSR: 0/ 1 0%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 0/ 1 0%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 11126/ 43848 25%
Info: TRELLIS_COMB: 11032/ 43848 25%
Info: TRELLIS_RAMW: 323/ 5481 5%
Info: Placed 48 cells based on constraints.
Info: Creating initial analytic placement for 12988 cells, random placement wirelen = 1046225.
Info: at initial placer iter 0, wirelen = 5377
Info: at initial placer iter 1, wirelen = 4705
Info: at initial placer iter 2, wirelen = 4312
Info: at initial placer iter 3, wirelen = 4224
Info: Running main analytical placer, max placement attempts per cell = 63811104.
Info: at iteration #1, type ALL: wirelen solved = 4435, spread = 244376, legal = 272909; time = 2.66s
Info: at iteration #2, type ALL: wirelen solved = 24120, spread = 174513, legal = 199334; time = 2.42s
Info: at iteration #3, type ALL: wirelen solved = 35074, spread = 157386, legal = 188353; time = 2.37s
Info: at iteration #4, type ALL: wirelen solved = 40530, spread = 150184, legal = 177148; time = 2.27s
Info: at iteration #5, type ALL: wirelen solved = 42036, spread = 145225, legal = 176204; time = 2.36s
Info: at iteration #6, type ALL: wirelen solved = 44419, spread = 143104, legal = 170591; time = 2.35s
Info: at iteration #7, type ALL: wirelen solved = 45685, spread = 143198, legal = 172841; time = 2.26s
Info: at iteration #8, type ALL: wirelen solved = 48163, spread = 138178, legal = 167479; time = 2.11s
Info: at iteration #9, type ALL: wirelen solved = 47699, spread = 145511, legal = 166652; time = 2.19s
Info: at iteration #10, type ALL: wirelen solved = 50691, spread = 146225, legal = 163195; time = 2.11s
Info: at iteration #11, type ALL: wirelen solved = 52034, spread = 146565, legal = 167154; time = 2.17s
Info: at iteration #12, type ALL: wirelen solved = 53789, spread = 146835, legal = 163070; time = 2.16s
Info: at iteration #13, type ALL: wirelen solved = 54260, spread = 146886, legal = 163893; time = 2.10s
Info: at iteration #14, type ALL: wirelen solved = 55213, spread = 147415, legal = 163224; time = 2.15s
Info: at iteration #15, type ALL: wirelen solved = 56142, spread = 147217, legal = 167508; time = 2.21s
Info: at iteration #16, type ALL: wirelen solved = 57748, spread = 147986, legal = 161568; time = 2.15s
Info: at iteration #17, type ALL: wirelen solved = 58796, spread = 150113, legal = 162812; time = 2.07s
Info: at iteration #18, type ALL: wirelen solved = 59687, spread = 151460, legal = 163714; time = 2.14s
Info: at iteration #19, type ALL: wirelen solved = 61027, spread = 151579, legal = 168790; time = 2.10s
Info: at iteration #20, type ALL: wirelen solved = 62620, spread = 152629, legal = 167452; time = 2.09s
Info: at iteration #21, type ALL: wirelen solved = 63063, spread = 155541, legal = 162822; time = 2.16s
Info: HeAP Placer Time: 52.45s
Info: of which solving equations: 10.47s
Info: of which spreading cells: 1.90s
Info: of which strict legalisation: 35.53s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 1750, wirelen = 161568
Info: at iteration #5: temp = 0.000000, timing cost = 1445, wirelen = 150908
Info: at iteration #10: temp = 0.000000, timing cost = 1346, wirelen = 148293
Info: at iteration #15: temp = 0.000000, timing cost = 1300, wirelen = 147298
Info: at iteration #20: temp = 0.000000, timing cost = 1287, wirelen = 146941
Info: at iteration #25: temp = 0.000000, timing cost = 1282, wirelen = 146825
Info: at iteration #30: temp = 0.000000, timing cost = 1280, wirelen = 146778
Info: at iteration #31: temp = 0.000000, timing cost = 1283, wirelen = 146775
Info: SA placement time 51.12s
Info: Max frequency for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT': 64.82 MHz (PASS at 64.00 MHz)
Info: Max delay <async> -> posedge $glbnet$sdram_clk$TRELLIS_IO_OUT: 6.98 ns
Info: Max delay posedge $glbnet$sdram_clk$TRELLIS_IO_OUT -> <async> : 8.81 ns
Info: Slack histogram:
Info: legend: * represents 62 endpoint(s)
Info: + represents [1,62) endpoint(s)
Info: [ 198, 941) |+
Info: [ 941, 1684) |+
Info: [ 1684, 2427) |+
Info: [ 2427, 3170) |*+
Info: [ 3170, 3913) |**+
Info: [ 3913, 4656) |*****+
Info: [ 4656, 5399) |*******+
Info: [ 5399, 6142) |******+
Info: [ 6142, 6885) |***********+
Info: [ 6885, 7628) |************+
Info: [ 7628, 8371) |*******************+
Info: [ 8371, 9114) |******************************************+
Info: [ 9114, 9857) |**************************************************+
Info: [ 9857, 10600) |*******************************************+
Info: [ 10600, 11343) |************************************+
Info: [ 11343, 12086) |***************************************************+
Info: [ 12086, 12829) |************************************************************
Info: [ 12829, 13572) |********************************************************+
Info: [ 13572, 14315) |***********************************************+
Info: [ 14315, 15058) |****************************************************+
Info: Checksum: 0x8379aea6
Info: Routing globals...
Info: routing clock net $glbnet$sdram_clk$TRELLIS_IO_OUT using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 60904 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 628 371 | 628 371 | 60764| 1.86 1.86|
Info: 2000 | 1088 911 | 460 540 | 60685| 1.84 3.70|
Info: 3000 | 1758 1241 | 670 330 | 60539| 1.06 4.76|
Info: 4000 | 2311 1688 | 553 447 | 60476| 1.33 6.09|
Info: 5000 | 2940 2059 | 629 371 | 60384| 2.28 8.37|
Info: 6000 | 3398 2601 | 458 542 | 60277| 2.95 11.32|
Info: 7000 | 3926 3073 | 528 472 | 60074| 4.18 15.50|
Info: 8000 | 4419 3580 | 493 507 | 59855| 4.47 19.97|
Info: 9000 | 4891 4108 | 472 528 | 59650| 3.21 23.18|
Info: 10000 | 5318 4681 | 427 573 | 59433| 1.55 24.73|
Info: 11000 | 5739 5260 | 421 579 | 59152| 1.44 26.17|
Info: 12000 | 6129 5870 | 390 610 | 58820| 2.42 28.59|
Info: 13000 | 6462 6537 | 333 667 | 58344| 2.40 30.99|
Info: 14000 | 6805 7194 | 343 657 | 58040| 5.65 36.64|
Info: 15000 | 6999 8000 | 194 806 | 57638| 2.55 39.19|
Info: 16000 | 7220 8779 | 221 779 | 56990| 2.21 41.40|
Info: 17000 | 7369 9630 | 149 851 | 56230| 1.69 43.09|
Info: 18000 | 7477 10522 | 108 892 | 55397| 1.13 44.23|
Info: 19000 | 7610 11389 | 133 867 | 54607| 1.07 45.30|
Info: 20000 | 7726 12273 | 116 884 | 53809| 0.91 46.21|
Info: 21000 | 7817 13182 | 91 909 | 52965| 1.73 47.94|
Info: 22000 | 7933 14066 | 116 884 | 52217| 1.07 49.01|
Info: 23000 | 8037 14962 | 104 896 | 51468| 0.97 49.98|
Info: 24000 | 8091 15908 | 54 946 | 50564| 0.60 50.58|
Info: 25000 | 8145 16854 | 54 946 | 49670| 0.66 51.24|
Info: 26000 | 8198 17801 | 53 947 | 48797| 1.13 52.37|
Info: 27000 | 8320 18679 | 122 878 | 48033| 1.43 53.80|
Info: 28000 | 8374 19625 | 54 946 | 47173| 0.68 54.48|
Info: 29000 | 8446 20553 | 72 928 | 46422| 0.51 54.99|
Info: 30000 | 8502 21497 | 56 944 | 45541| 0.53 55.52|
Info: 31000 | 8650 22349 | 148 852 | 44766| 0.95 56.48|
Info: 32000 | 8771 23228 | 121 879 | 44112| 0.67 57.14|
Info: 33000 | 8890 24109 | 119 881 | 43453| 0.76 57.90|
Info: 34000 | 8994 25005 | 104 896 | 42611| 0.61 58.51|
Info: 35000 | 9088 25911 | 94 906 | 41858| 0.56 59.07|
Info: 36000 | 9179 26820 | 91 909 | 41068| 0.53 59.61|
Info: 37000 | 9284 27715 | 105 895 | 40337| 0.51 60.12|
Info: 38000 | 9421 28578 | 137 863 | 39567| 0.57 60.69|
Info: 39000 | 9566 29433 | 145 855 | 38918| 0.54 61.23|
Info: 40000 | 9661 30338 | 95 905 | 38373| 0.55 61.79|
Info: 41000 | 9762 31237 | 101 899 | 37627| 0.57 62.36|
Info: 42000 | 9899 32100 | 137 863 | 36978| 0.80 63.16|
Info: 43000 | 10079 32919 | 180 819 | 36342| 1.05 64.21|
Info: 44000 | 10276 33720 | 197 801 | 35831| 1.06 65.27|
Info: 45000 | 10428 34568 | 152 848 | 35108| 0.64 65.91|
Info: 46000 | 10636 35360 | 208 792 | 34617| 0.76 66.67|
Info: 47000 | 10841 36155 | 205 795 | 34038| 0.70 67.37|
Info: 48000 | 11028 36959 | 187 804 | 33408| 0.64 68.00|
Info: 49000 | 11188 37788 | 160 829 | 32789| 0.76 68.77|
Info: 50000 | 11387 38574 | 199 786 | 32071| 0.55 69.31|
Info: 51000 | 11590 39356 | 203 782 | 31497| 0.57 69.89|
Info: 52000 | 11866 40072 | 276 716 | 30898| 1.25 71.14|
Info: 53000 | 12056 40858 | 190 786 | 30185| 0.79 71.92|
Info: 54000 | 12220 41647 | 164 789 | 29419| 0.53 72.45|
Info: 55000 | 12442 42363 | 222 716 | 28749| 0.59 73.04|
Info: 56000 | 12678 43086 | 236 723 | 28233| 0.75 73.79|
Info: 57000 | 12865 43855 | 187 769 | 27645| 0.73 74.52|
Info: 58000 | 13081 44624 | 216 769 | 27229| 1.07 75.59|
Info: 59000 | 13241 45401 | 160 777 | 26576| 0.57 76.16|
Info: 60000 | 13445 46121 | 204 720 | 25863| 0.79 76.95|
Info: 61000 | 13635 46890 | 190 769 | 25222| 0.57 77.52|
Info: 62000 | 13796 47707 | 161 817 | 24620| 0.81 78.33|
Info: 63000 | 13943 48470 | 147 763 | 23890| 0.69 79.02|
Info: 64000 | 14106 49253 | 163 783 | 23176| 0.62 79.64|
Info: 65000 | 14275 50056 | 169 803 | 22518| 0.88 80.52|
Info: 66000 | 14446 50830 | 171 774 | 21904| 0.83 81.35|
Info: 67000 | 14634 51607 | 188 777 | 21324| 1.04 82.40|
Info: 68000 | 14796 52403 | 162 796 | 20629| 0.89 83.29|
Info: 69000 | 14993 53187 | 197 784 | 20035| 0.89 84.18|
Info: 70000 | 15176 53968 | 183 781 | 19311| 0.69 84.87|
Info: 71000 | 15421 54716 | 245 748 | 18836| 1.32 86.19|
Info: 72000 | 15611 55499 | 190 783 | 18293| 0.83 87.02|
Info: 73000 | 15845 56219 | 234 720 | 17771| 0.76 87.78|
Info: 74000 | 16050 56984 | 205 765 | 17113| 1.52 89.30|
Info: 75000 | 16228 57777 | 178 793 | 16748| 0.91 90.20|
Info: 76000 | 16466 58497 | 238 720 | 16370| 1.54 91.74|
Info: 77000 | 16764 59194 | 298 697 | 15941| 1.52 93.26|
Info: 78000 | 16892 59999 | 128 805 | 15122| 0.47 93.74|
Info: 79000 | 17065 60791 | 173 792 | 14573| 0.67 94.41|
Info: 80000 | 17267 61554 | 202 763 | 14064| 0.65 95.06|
Info: 81000 | 17495 62297 | 228 743 | 13779| 1.39 96.45|
Info: 82000 | 17676 63108 | 181 811 | 13496| 2.03 98.48|
Info: 83000 | 17854 63917 | 178 809 | 13117| 0.94 99.42|
Info: 84000 | 18141 64630 | 287 713 | 12871| 1.99 101.41|
Info: 85000 | 18469 65293 | 328 663 | 12495| 1.79 103.20|
Info: 86000 | 18705 66021 | 236 728 | 12130| 1.14 104.34|
Info: 87000 | 18828 66798 | 123 777 | 11330| 0.45 104.79|
Info: 88000 | 18959 67574 | 131 776 | 10547| 0.45 105.24|
Info: 89000 | 19229 68229 | 270 655 | 10012| 1.02 106.26|
Info: 90000 | 19480 68968 | 251 739 | 9603| 1.30 107.56|
Info: 91000 | 19769 69645 | 289 677 | 9144| 1.08 108.64|
Info: 92000 | 19883 70480 | 114 835 | 8342| 0.51 109.15|
Info: 93000 | 20122 71237 | 239 757 | 7817| 1.00 110.15|
Info: 94000 | 20389 71968 | 267 731 | 7350| 1.11 111.27|
Info: 95000 | 20746 72611 | 357 643 | 7147| 1.52 112.79|
Info: 96000 | 21127 73230 | 381 619 | 6946| 1.65 114.44|
Info: 97000 | 21420 73937 | 293 707 | 6550| 1.40 115.84|
Info: 98000 | 21650 74693 | 230 756 | 5975| 1.05 116.88|
Info: 99000 | 21874 75469 | 224 776 | 5623| 0.99 117.88|
Info: 100000 | 22147 76196 | 273 727 | 5277| 1.09 118.96|
Info: 101000 | 22589 76754 | 442 558 | 5131| 1.55 120.51|
Info: 102000 | 22994 77349 | 405 595 | 4905| 1.67 122.18|
Info: 103000 | 23349 77994 | 355 645 | 4743| 1.58 123.76|
Info: 104000 | 23791 78552 | 442 558 | 4626| 1.65 125.41|
Info: 105000 | 24227 79116 | 436 564 | 4484| 1.47 126.88|
Info: 106000 | 24644 79699 | 417 583 | 4344| 1.89 128.77|
Info: 107000 | 25019 80324 | 375 625 | 4216| 1.33 130.10|
Info: 108000 | 25276 81067 | 257 743 | 3978| 1.12 131.22|
Info: 109000 | 25596 81747 | 320 680 | 3471| 0.83 132.05|
Info: 110000 | 25916 82427 | 320 680 | 3152| 1.38 133.44|
Info: 111000 | 26254 83079 | 338 652 | 3025| 1.13 134.57|
Info: 112000 | 26543 83746 | 289 667 | 2718| 1.38 135.94|
Info: 113000 | 26822 84425 | 279 679 | 2492| 1.49 137.43|
Info: 114000 | 27019 85145 | 197 720 | 2037| 1.38 138.81|
Info: 115000 | 27216 85829 | 197 684 | 1422| 1.11 139.92|
Info: 116000 | 27475 86492 | 259 663 | 914| 1.39 141.31|
Info: 117000 | 27748 87134 | 273 642 | 510| 1.23 142.54|
Info: 118000 | 28073 87764 | 325 630 | 264| 1.53 144.08|
Info: 118880 | 28373 88307 | 300 543 | 0| 1.83 145.90|
Info: Routing complete.
Info: Router1 time 145.90s
Info: Checksum: 0xc292ce30
Info: Critical path report for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT' (posedge -> posedge):
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source u_arbiter_wide.m_addr_TRELLIS_FF_Q_1.Q
Info: routing 1.04 1.43 Net u_arbiter_wide.m_addr[1] (40,2) -> (27,2)
Info: Sink u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_PFUMX_Z_C0_LUT4_Z.B
Info: Defined in:
Info: hardware/v2/rtl/slot_mem_arbiter_wide.v:75.35-75.41
Info: logic 0.18 1.61 Source u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_PFUMX_Z_C0_LUT4_Z.F
Info: routing 0.71 2.33 Net u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_PFUMX_Z_C0[4] (27,2) -> (27,5)
Info: Sink u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_PFUMX_Z_BLUT_LUT4_Z.M
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.19 2.52 Source u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: routing 0.63 3.15 Net u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z[2] (27,5) -> (27,6)
Info: Sink u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D.C
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 3.33 Source u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D.F
Info: routing 0.39 3.72 Net u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z[3] (27,6) -> (28,5)
Info: Sink u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 3.90 Source u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D.F
Info: routing 0.45 4.36 Net u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z[3] (28,5) -> (28,5)
Info: Sink u_sdram_backend.w_cache_valid[3]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.53 Source u_sdram_backend.w_cache_valid[3]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.F
Info: routing 1.77 6.30 Net u_sdram_backend.w_cache_valid[3]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z[2] (28,5) -> (21,21)
Info: Sink u_sdram_backend.w_cache_valid[0]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 6.48 Source u_sdram_backend.w_cache_valid[0]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.F
Info: routing 1.31 7.80 Net u_sdram_backend.w_cache_hit_LUT4_B_Z[3] (21,21) -> (24,8)
Info: Sink u_sdram_backend.w_cache_hit_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 7.98 Source u_sdram_backend.w_cache_hit_LUT4_Z.F
Info: routing 0.03 8.01 Net u_sdram_backend.w_alloc_ptr_TRELLIS_FF_Q_CE[0] (24,8) -> (24,8)
Info: Sink u_sdram_backend.w_cache_hit_LUT4_C.C
Info: Defined in:
Info: hardware/v2/nms/rtl/sdram_unified_backend.v:184.10-184.21
Info: logic 0.18 8.19 Source u_sdram_backend.w_cache_hit_LUT4_C.F
Info: routing 0.56 8.76 Net u_sdram_backend.w_cache_hit_LUT4_C_Z[0] (24,8) -> (24,11)
Info: Sink u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z.C
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 8.94 Source u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z.F
Info: routing 1.00 9.94 Net u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D[3] (24,11) -> (23,19)
Info: Sink u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_D.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 10.12 Source u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_D.F
Info: routing 2.11 12.23 Net u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_D_Z[3] (23,19) -> (23,55)
Info: Sink u_sdram_backend.ctrl_wdata_TRELLIS_FF_Q_14.CE
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: setup 0.00 12.23 Source u_sdram_backend.ctrl_wdata_TRELLIS_FF_Q_14.CE
Info: 2.21 ns logic, 10.02 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$sdram_clk$TRELLIS_IO_OUT':
Info: type curr total name
Info: source 0.00 0.00 Source ext_rst_n$tr_io.O
Info: routing 0.80 0.80 Net ext_rst_n$TRELLIS_IO_IN (0,14) -> (2,16)
Info: Sink ext_rst_n_LUT4_D.D
Info: Defined in:
Info: hardware/v2/rtl/reset_sync.v:18.17-18.26
Info: logic 0.18 0.98 Source ext_rst_n_LUT4_D.F
Info: routing 3.95 4.93 Net ext_rst_n_LUT4_D_Z (2,16) -> (34,59)
Info: Sink ext_rst_n_LUT4_D_Z_TRELLIS_FF_LSR_DI_TRELLIS_FF_Q.LSR
Info: setup 0.29 5.21 Source ext_rst_n_LUT4_D_Z_TRELLIS_FF_LSR_DI_TRELLIS_FF_Q.LSR
Info: 0.47 ns logic, 4.74 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$sdram_clk$TRELLIS_IO_OUT' -> '<async>':
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source u_spi_bridge.byte_idx_TRELLIS_FF_Q_2.Q
Info: routing 1.45 1.84 Net u_spi_bridge.byte_idx[2] (33,52) -> (35,41)
Info: Sink u_dataflow_core.u_dep_mgr.reg_required_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 2.02 Source u_dataflow_core.u_dep_mgr.reg_required_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_Z.F
Info: routing 0.35 2.37 Net u_dataflow_core.u_dep_mgr.reg_required_TRELLIS_FF_Q_CE_LUT4_Z_C[3] (35,41) -> (35,41)
Info: Sink u_spi_bridge.soft_rst_pulse_TRELLIS_FF_Q_DI_PFUMX_Z_C0_PFUMX_C0_Z_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 2.55 Source u_spi_bridge.soft_rst_pulse_TRELLIS_FF_Q_DI_PFUMX_Z_C0_PFUMX_C0_Z_LUT4_Z.F
Info: routing 1.43 3.98 Net host_mem_ready_LUT4_B_1_Z_LUT4_C_Z[1] (35,41) -> (27,56)
Info: Sink spi_miso_LUT4_Z_D_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.16 Source spi_miso_LUT4_Z_D_LUT4_Z.F
Info: routing 0.84 5.01 Net spi_miso_LUT4_Z_B[3] (27,56) -> (28,57)
Info: Sink spi_miso_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 5.19 Source spi_miso_LUT4_Z.F
Info: routing 1.69 6.88 Net spi_miso$TRELLIS_IO_OUT (28,57) -> (0,62)
Info: Sink spi_miso$tr_io.I
Info: Defined in:
Info: hardware/v2/nms/rtl/fpga_neural_v2_top.v:55.17-55.25
Info: 1.12 ns logic, 5.76 ns routing
Info: Max frequency for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT': 81.77 MHz (PASS at 64.00 MHz)
Info: Max delay <async> -> posedge $glbnet$sdram_clk$TRELLIS_IO_OUT: 5.21 ns
Info: Max delay posedge $glbnet$sdram_clk$TRELLIS_IO_OUT -> <async> : 6.88 ns
Info: Slack histogram:
Info: legend: * represents 69 endpoint(s)
Info: + represents [1,69) endpoint(s)
Info: [ 3396, 3973) |+
Info: [ 3973, 4550) |+
Info: [ 4550, 5127) |+
Info: [ 5127, 5704) |****+
Info: [ 5704, 6281) |****+
Info: [ 6281, 6858) |***+
Info: [ 6858, 7435) |***+
Info: [ 7435, 8012) |***+
Info: [ 8012, 8589) |*********+
Info: [ 8589, 9166) |*************+
Info: [ 9166, 9743) |*****************+
Info: [ 9743, 10320) |**************************+
Info: [ 10320, 10897) |************************************+
Info: [ 10897, 11474) |**************************************+
Info: [ 11474, 12051) |****************************************+
Info: [ 12051, 12628) |********************************************+
Info: [ 12628, 13205) |************************************************************
Info: [ 13205, 13782) |*****************************************************+
Info: [ 13782, 14359) |****************************************************+
Info: [ 14359, 14936) |********************************************+
Info: Program finished normally.
hardware/v2/nms/synthesis/nms_multiproc_n8/nextpnr_seed2.log
+484
View File
@@ -0,0 +1,484 @@
Info: constraining clock net 'osc_clk' to 16.00 MHz
Info: Logic utilisation before packing:
Info: Total LUT4s: 10214/43848 23%
Info: logic LUTs: 5504/43848 12%
Info: carry LUTs: 2772/43848 6%
Info: RAM LUTs: 1292/ 5481 23%
Info: RAMW LUTs: 646/10962 5%
Info: Total DFFs: 11126/43848 25%
Info: Packing IOs..
Info: $sdram_dq[15]$iobuf_i: sdram_dq_$_TBUF__Y.Y
Info: pin 'sdram_dq[15]$tr_io' constrained to Bel 'X0/Y59/PIOB'.
Info: $sdram_dq[14]$iobuf_i: sdram_dq_$_TBUF__Y_15.Y
Info: pin 'sdram_dq[14]$tr_io' constrained to Bel 'X0/Y59/PIOC'.
Info: $sdram_dq[13]$iobuf_i: sdram_dq_$_TBUF__Y_14.Y
Info: pin 'sdram_dq[13]$tr_io' constrained to Bel 'X0/Y59/PIOA'.
Info: $sdram_dq[12]$iobuf_i: sdram_dq_$_TBUF__Y_13.Y
Info: pin 'sdram_dq[12]$tr_io' constrained to Bel 'X0/Y53/PIOA'.
Info: $sdram_dq[11]$iobuf_i: sdram_dq_$_TBUF__Y_12.Y
Info: pin 'sdram_dq[11]$tr_io' constrained to Bel 'X0/Y44/PIOD'.
Info: $sdram_dq[10]$iobuf_i: sdram_dq_$_TBUF__Y_11.Y
Info: pin 'sdram_dq[10]$tr_io' constrained to Bel 'X0/Y44/PIOC'.
Info: $sdram_dq[9]$iobuf_i: sdram_dq_$_TBUF__Y_10.Y
Info: pin 'sdram_dq[9]$tr_io' constrained to Bel 'X0/Y44/PIOA'.
Info: $sdram_dq[8]$iobuf_i: sdram_dq_$_TBUF__Y_9.Y
Info: pin 'sdram_dq[8]$tr_io' constrained to Bel 'X0/Y41/PIOD'.
Info: $sdram_dq[7]$iobuf_i: sdram_dq_$_TBUF__Y_8.Y
Info: pin 'sdram_dq[7]$tr_io' constrained to Bel 'X0/Y41/PIOB'.
Info: $sdram_dq[6]$iobuf_i: sdram_dq_$_TBUF__Y_7.Y
Info: pin 'sdram_dq[6]$tr_io' constrained to Bel 'X0/Y41/PIOC'.
Info: $sdram_dq[5]$iobuf_i: sdram_dq_$_TBUF__Y_6.Y
Info: pin 'sdram_dq[5]$tr_io' constrained to Bel 'X0/Y41/PIOA'.
Info: $sdram_dq[4]$iobuf_i: sdram_dq_$_TBUF__Y_5.Y
Info: pin 'sdram_dq[4]$tr_io' constrained to Bel 'X0/Y38/PIOD'.
Info: $sdram_dq[3]$iobuf_i: sdram_dq_$_TBUF__Y_4.Y
Info: pin 'sdram_dq[3]$tr_io' constrained to Bel 'X0/Y38/PIOB'.
Info: $sdram_dq[2]$iobuf_i: sdram_dq_$_TBUF__Y_3.Y
Info: pin 'sdram_dq[2]$tr_io' constrained to Bel 'X0/Y29/PIOD'.
Info: $sdram_dq[1]$iobuf_i: sdram_dq_$_TBUF__Y_2.Y
Info: pin 'sdram_dq[1]$tr_io' constrained to Bel 'X0/Y29/PIOB'.
Info: $sdram_dq[0]$iobuf_i: sdram_dq_$_TBUF__Y_1.Y
Info: pin 'sdram_dq[0]$tr_io' constrained to Bel 'X0/Y26/PIOD'.
Info: pin 'spi_sclk$tr_io' constrained to Bel 'X0/Y62/PIOC'.
Info: pin 'spi_mosi$tr_io' constrained to Bel 'X0/Y62/PIOB'.
Info: pin 'spi_miso$tr_io' constrained to Bel 'X0/Y62/PIOD'.
Info: pin 'spi_cs_n$tr_io' constrained to Bel 'X0/Y65/PIOA'.
Info: pin 'sdram_we_n$tr_io' constrained to Bel 'X0/Y14/PIOD'.
Info: pin 'sdram_ras_n$tr_io' constrained to Bel 'X0/Y14/PIOA'.
Info: pin 'sdram_dqm[1]$tr_io' constrained to Bel 'X0/Y62/PIOA'.
Info: pin 'sdram_dqm[0]$tr_io' constrained to Bel 'X0/Y59/PIOD'.
Info: pin 'sdram_cs_n$tr_io' constrained to Bel 'X0/Y11/PIOD'.
Info: pin 'sdram_clk$tr_io' constrained to Bel 'X0/Y38/PIOA'.
Info: pin 'sdram_cke$tr_io' constrained to Bel 'X0/Y11/PIOC'.
Info: pin 'sdram_cas_n$tr_io' constrained to Bel 'X0/Y14/PIOC'.
Info: pin 'sdram_ba[1]$tr_io' constrained to Bel 'X0/Y17/PIOC'.
Info: pin 'sdram_ba[0]$tr_io' constrained to Bel 'X0/Y17/PIOA'.
Info: pin 'sdram_a[12]$tr_io' constrained to Bel 'X0/Y35/PIOB'.
Info: pin 'sdram_a[11]$tr_io' constrained to Bel 'X0/Y26/PIOB'.
Info: pin 'sdram_a[10]$tr_io' constrained to Bel 'X0/Y26/PIOC'.
Info: pin 'sdram_a[9]$tr_io' constrained to Bel 'X0/Y26/PIOA'.
Info: pin 'sdram_a[8]$tr_io' constrained to Bel 'X0/Y23/PIOD'.
Info: pin 'sdram_a[7]$tr_io' constrained to Bel 'X0/Y23/PIOB'.
Info: pin 'sdram_a[6]$tr_io' constrained to Bel 'X0/Y23/PIOA'.
Info: pin 'sdram_a[5]$tr_io' constrained to Bel 'X0/Y20/PIOD'.
Info: pin 'sdram_a[4]$tr_io' constrained to Bel 'X0/Y20/PIOB'.
Info: pin 'sdram_a[3]$tr_io' constrained to Bel 'X0/Y20/PIOC'.
Info: pin 'sdram_a[2]$tr_io' constrained to Bel 'X0/Y20/PIOA'.
Info: pin 'sdram_a[1]$tr_io' constrained to Bel 'X0/Y17/PIOD'.
Info: pin 'sdram_a[0]$tr_io' constrained to Bel 'X0/Y17/PIOB'.
Info: pin 'pll_locked$tr_io' constrained to Bel 'X0/Y65/PIOC'.
Info: pin 'osc_clk$tr_io' constrained to Bel 'X0/Y29/PIOC'.
Info: pin 'ext_rst_n$tr_io' constrained to Bel 'X0/Y14/PIOB'.
Info: pin 'data_ready$tr_io' constrained to Bel 'X0/Y32/PIOA'.
Info: placed PLL 'u_pll.pll_i' at bel 'X1/Y4/EHXPLL_UL'
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 3832 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Input frequency of PLL 'u_pll.pll_i' is constrained to 16.0 MHz
Info: Derived frequency constraint of 64.0 MHz for net sdram_clk$TRELLIS_IO_OUT
Info: Promoting globals...
Info: promoting clock net sdram_clk$TRELLIS_IO_OUT to global network
Info: Checksum: 0x94c17baa
Info: Device utilisation:
Info: TRELLIS_IO: 47/ 245 19%
Info: DCCA: 1/ 56 1%
Info: DP16KD: 0/ 108 0%
Info: MULT18X18D: 64/ 72 88%
Info: ALU54B: 0/ 36 0%
Info: EHXPLLL: 1/ 4 25%
Info: EXTREFB: 0/ 2 0%
Info: DCUA: 0/ 2 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 0/ 160 0%
Info: SIOLOGIC: 0/ 85 0%
Info: GSR: 0/ 1 0%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 0/ 1 0%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 11126/ 43848 25%
Info: TRELLIS_COMB: 11032/ 43848 25%
Info: TRELLIS_RAMW: 323/ 5481 5%
Info: Placed 48 cells based on constraints.
Info: Creating initial analytic placement for 12988 cells, random placement wirelen = 1047745.
Info: at initial placer iter 0, wirelen = 5414
Info: at initial placer iter 1, wirelen = 4738
Info: at initial placer iter 2, wirelen = 4314
Info: at initial placer iter 3, wirelen = 4255
Info: Running main analytical placer, max placement attempts per cell = 63811104.
Info: at iteration #1, type ALL: wirelen solved = 4201, spread = 244331, legal = 270496; time = 2.56s
Info: at iteration #2, type ALL: wirelen solved = 24008, spread = 173398, legal = 197736; time = 2.28s
Info: at iteration #3, type ALL: wirelen solved = 36246, spread = 156253, legal = 187097; time = 2.35s
Info: at iteration #4, type ALL: wirelen solved = 41576, spread = 158201, legal = 188458; time = 2.34s
Info: at iteration #5, type ALL: wirelen solved = 45175, spread = 154781, legal = 186816; time = 2.24s
Info: at iteration #6, type ALL: wirelen solved = 46737, spread = 153328, legal = 184903; time = 2.32s
Info: at iteration #7, type ALL: wirelen solved = 48307, spread = 151947, legal = 187195; time = 2.26s
Info: at iteration #8, type ALL: wirelen solved = 48854, spread = 151070, legal = 183462; time = 2.32s
Info: at iteration #9, type ALL: wirelen solved = 49866, spread = 149139, legal = 183454; time = 2.40s
Info: at iteration #10, type ALL: wirelen solved = 51600, spread = 149127, legal = 177935; time = 2.28s
Info: at iteration #11, type ALL: wirelen solved = 52644, spread = 148641, legal = 174670; time = 2.17s
Info: at iteration #12, type ALL: wirelen solved = 53339, spread = 148306, legal = 180699; time = 2.30s
Info: at iteration #13, type ALL: wirelen solved = 55131, spread = 149533, legal = 179232; time = 2.29s
Info: at iteration #14, type ALL: wirelen solved = 56357, spread = 149465, legal = 179151; time = 2.23s
Info: at iteration #15, type ALL: wirelen solved = 57732, spread = 150933, legal = 175918; time = 2.21s
Info: at iteration #16, type ALL: wirelen solved = 58529, spread = 150634, legal = 176265; time = 2.24s
Info: HeAP Placer Time: 41.76s
Info: of which solving equations: 8.44s
Info: of which spreading cells: 1.40s
Info: of which strict legalisation: 28.47s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 3263, wirelen = 174670
Info: at iteration #5: temp = 0.000000, timing cost = 2477, wirelen = 163716
Info: at iteration #10: temp = 0.000000, timing cost = 2462, wirelen = 161169
Info: at iteration #15: temp = 0.000000, timing cost = 2462, wirelen = 160134
Info: at iteration #20: temp = 0.000000, timing cost = 2429, wirelen = 159661
Info: at iteration #25: temp = 0.000000, timing cost = 2415, wirelen = 159465
Info: at iteration #30: temp = 0.000000, timing cost = 2405, wirelen = 159355
Info: at iteration #35: temp = 0.000000, timing cost = 2406, wirelen = 159256
Info: at iteration #40: temp = 0.000000, timing cost = 2410, wirelen = 159174
Info: at iteration #43: temp = 0.000000, timing cost = 2398, wirelen = 159150
Info: SA placement time 74.75s
Info: Max frequency for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT': 64.05 MHz (PASS at 64.00 MHz)
Info: Max delay <async> -> posedge $glbnet$sdram_clk$TRELLIS_IO_OUT: 4.95 ns
Info: Max delay posedge $glbnet$sdram_clk$TRELLIS_IO_OUT -> <async> : 7.32 ns
Info: Slack histogram:
Info: legend: * represents 64 endpoint(s)
Info: + represents [1,64) endpoint(s)
Info: [ 12, 764) |+
Info: [ 764, 1516) |+
Info: [ 1516, 2268) |**+
Info: [ 2268, 3020) |***+
Info: [ 3020, 3772) |****+
Info: [ 3772, 4524) |*****+
Info: [ 4524, 5276) |*******+
Info: [ 5276, 6028) |************+
Info: [ 6028, 6780) |***********************+
Info: [ 6780, 7532) |***************************************+
Info: [ 7532, 8284) |******************************************+
Info: [ 8284, 9036) |************************************+
Info: [ 9036, 9788) |*********************************+
Info: [ 9788, 10540) |*********************+
Info: [ 10540, 11292) |***************+
Info: [ 11292, 12044) |********************************+
Info: [ 12044, 12796) |**************************************************+
Info: [ 12796, 13548) |************************************************************
Info: [ 13548, 14300) |*****************************************************+
Info: [ 14300, 15052) |*************************************************+
Info: Checksum: 0xe5042654
Info: Routing globals...
Info: routing clock net $glbnet$sdram_clk$TRELLIS_IO_OUT using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 60567 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 656 343 | 656 343 | 60404| 2.84 2.84|
Info: 2000 | 1421 578 | 765 235 | 60319| 0.82 3.65|
Info: 3000 | 2104 895 | 683 317 | 60220| 1.12 4.77|
Info: 4000 | 2647 1352 | 543 457 | 60072| 1.50 6.27|
Info: 5000 | 3196 1803 | 549 451 | 59937| 1.51 7.78|
Info: 6000 | 3782 2217 | 586 414 | 59797| 1.28 9.06|
Info: 7000 | 4299 2700 | 517 483 | 59631| 1.53 10.60|
Info: 8000 | 4824 3175 | 525 475 | 59488| 1.60 12.20|
Info: 9000 | 5317 3682 | 493 507 | 59315| 1.51 13.71|
Info: 10000 | 5702 4297 | 385 615 | 59111| 1.46 15.17|
Info: 11000 | 6280 4719 | 578 422 | 58967| 1.27 16.44|
Info: 12000 | 6749 5250 | 469 531 | 58823| 1.69 18.13|
Info: 13000 | 7057 5942 | 308 692 | 58445| 1.27 19.40|
Info: 14000 | 7463 6536 | 406 594 | 58094| 1.60 21.00|
Info: 15000 | 7679 7320 | 216 784 | 57499| 1.33 22.33|
Info: 16000 | 8038 7961 | 359 641 | 57160| 1.35 23.68|
Info: 17000 | 8346 8653 | 308 692 | 56619| 1.56 25.24|
Info: 18000 | 8539 9460 | 193 807 | 56247| 1.23 26.47|
Info: 19000 | 8674 10325 | 135 865 | 55592| 1.47 27.94|
Info: 20000 | 8803 11196 | 129 871 | 54809| 0.93 28.87|
Info: 21000 | 8874 12125 | 71 929 | 53905| 0.68 29.55|
Info: 22000 | 9002 12997 | 128 872 | 53140| 0.64 30.19|
Info: 23000 | 9077 13922 | 75 925 | 52444| 0.46 30.66|
Info: 24000 | 9204 14795 | 127 873 | 51699| 0.81 31.46|
Info: 25000 | 9283 15716 | 79 921 | 50960| 0.61 32.07|
Info: 26000 | 9363 16636 | 80 920 | 50229| 0.66 32.73|
Info: 27000 | 9477 17522 | 114 886 | 49513| 0.51 33.24|
Info: 28000 | 9574 18425 | 97 903 | 48731| 0.50 33.74|
Info: 29000 | 9665 19334 | 91 909 | 48052| 0.64 34.39|
Info: 30000 | 9743 20256 | 78 922 | 47269| 0.66 35.05|
Info: 31000 | 9805 21194 | 62 938 | 46420| 0.57 35.61|
Info: 32000 | 9882 22117 | 77 923 | 45573| 0.52 36.13|
Info: 33000 | 9961 23038 | 79 921 | 44824| 0.51 36.64|
Info: 34000 | 10060 23939 | 99 901 | 44126| 0.49 37.14|
Info: 35000 | 10199 24800 | 139 861 | 43527| 0.56 37.70|
Info: 36000 | 10292 25707 | 93 907 | 42733| 0.55 38.25|
Info: 37000 | 10424 26575 | 132 868 | 42079| 0.54 38.79|
Info: 38000 | 10520 27479 | 96 904 | 41356| 0.49 39.28|
Info: 39000 | 10688 28311 | 168 832 | 40755| 1.10 40.38|
Info: 40000 | 10828 29171 | 140 860 | 40124| 0.59 40.97|
Info: 41000 | 10988 30011 | 160 840 | 39447| 0.62 41.60|
Info: 42000 | 11132 30867 | 144 856 | 38763| 0.70 42.30|
Info: 43000 | 11330 31669 | 198 802 | 38089| 0.62 42.92|
Info: 44000 | 11524 32475 | 194 806 | 37642| 0.69 43.61|
Info: 45000 | 11722 33277 | 198 802 | 36987| 0.78 44.39|
Info: 46000 | 11980 34019 | 258 742 | 36457| 0.74 45.13|
Info: 47000 | 12148 34851 | 168 832 | 35993| 0.61 45.73|
Info: 48000 | 12321 35678 | 173 827 | 35275| 0.62 46.35|
Info: 49000 | 12539 36460 | 218 782 | 34649| 0.72 47.08|
Info: 50000 | 12728 37270 | 189 810 | 34060| 0.83 47.91|
Info: 51000 | 12966 38027 | 238 757 | 33619| 0.78 48.68|
Info: 52000 | 13223 38761 | 257 734 | 33024| 0.74 49.42|
Info: 53000 | 13498 39469 | 275 708 | 32448| 0.80 50.23|
Info: 54000 | 13697 40255 | 199 786 | 31801| 0.58 50.80|
Info: 55000 | 13992 40948 | 295 693 | 31329| 0.84 51.64|
Info: 56000 | 14252 41683 | 260 735 | 31100| 1.07 52.71|
Info: 57000 | 14469 42456 | 217 773 | 30421| 0.72 53.43|
Info: 58000 | 14779 43128 | 310 672 | 29937| 0.77 54.20|
Info: 59000 | 15020 43829 | 241 701 | 29335| 0.92 55.12|
Info: 60000 | 15249 44592 | 229 763 | 28955| 0.92 56.04|
Info: 61000 | 15482 45299 | 233 707 | 28441| 0.72 56.76|
Info: 62000 | 15727 46023 | 245 724 | 28073| 1.07 57.83|
Info: 63000 | 15983 46722 | 256 699 | 27481| 0.76 58.59|
Info: 64000 | 16235 47417 | 252 695 | 27058| 0.86 59.45|
Info: 65000 | 16516 48121 | 281 704 | 26850| 1.07 60.52|
Info: 66000 | 16782 48832 | 266 711 | 26420| 1.19 61.71|
Info: 67000 | 17004 49575 | 222 743 | 26040| 0.92 62.63|
Info: 68000 | 17269 50294 | 265 719 | 25685| 1.16 63.79|
Info: 69000 | 17592 50946 | 323 652 | 25393| 1.28 65.07|
Info: 70000 | 17844 51672 | 252 726 | 24997| 1.31 66.38|
Info: 71000 | 18112 52381 | 268 709 | 24523| 1.05 67.43|
Info: 72000 | 18372 53098 | 260 717 | 24062| 1.00 68.44|
Info: 73000 | 18605 53836 | 233 738 | 23451| 1.11 69.55|
Info: 74000 | 18897 54500 | 292 664 | 23003| 0.98 70.52|
Info: 75000 | 19137 55223 | 240 723 | 22482| 1.34 71.86|
Info: 76000 | 19489 55871 | 352 648 | 22639| 2.39 74.25|
Info: 77000 | 19760 56600 | 271 729 | 22385| 1.24 75.49|
Info: 78000 | 20027 57307 | 267 707 | 21919| 0.91 76.40|
Info: 79000 | 20225 58050 | 198 743 | 21326| 0.78 77.18|
Info: 80000 | 20534 58736 | 309 686 | 21020| 1.62 78.81|
Info: 81000 | 20707 59485 | 173 749 | 20551| 0.97 79.77|
Info: 82000 | 21036 60135 | 329 650 | 20287| 1.41 81.18|
Info: 83000 | 21270 60878 | 234 743 | 19772| 0.92 82.10|
Info: 84000 | 21680 61468 | 410 590 | 19729| 2.45 84.55|
Info: 85000 | 21978 62157 | 298 689 | 19496| 1.21 85.76|
Info: 86000 | 22293 62821 | 315 664 | 19144| 1.31 87.07|
Info: 87000 | 22532 63571 | 239 750 | 18649| 0.97 88.04|
Info: 88000 | 22834 64269 | 302 698 | 18477| 1.58 89.62|
Info: 89000 | 23035 65056 | 201 787 | 17910| 0.98 90.60|
Info: 90000 | 23266 65800 | 231 744 | 17345| 1.10 91.70|
Info: 91000 | 23621 66445 | 355 645 | 17302| 1.49 93.19|
Info: 92000 | 23795 67214 | 174 769 | 16586| 0.74 93.93|
Info: 93000 | 24015 67978 | 220 764 | 16140| 1.18 95.12|
Info: 94000 | 24305 68688 | 290 710 | 16051| 1.44 96.56|
Info: 95000 | 24703 69290 | 398 602 | 16012| 1.82 98.38|
Info: 96000 | 25110 69883 | 407 593 | 15999| 1.56 99.94|
Info: 97000 | 25459 70534 | 349 651 | 16012| 1.82 101.77|
Info: 98000 | 25814 71179 | 355 645 | 15892| 2.03 103.80|
Info: 99000 | 25986 71960 | 172 781 | 15322| 0.97 104.77|
Info: 100000 | 26160 72729 | 174 769 | 14752| 0.90 105.67|
Info: 101000 | 26498 73385 | 338 656 | 14718| 1.60 107.27|
Info: 102000 | 26731 74110 | 233 725 | 14190| 0.99 108.26|
Info: 103000 | 27075 74764 | 344 654 | 14041| 1.46 109.71|
Info: 104000 | 27375 75435 | 300 671 | 13865| 1.45 111.17|
Info: 105000 | 27660 76142 | 285 707 | 13684| 1.31 112.48|
Info: 106000 | 27993 76809 | 333 667 | 13511| 1.36 113.84|
Info: 107000 | 28435 77367 | 442 558 | 13593| 1.74 115.58|
Info: 108000 | 28670 78132 | 235 765 | 13494| 1.32 116.90|
Info: 109000 | 29040 78762 | 370 630 | 13470| 1.84 118.74|
Info: 110000 | 29350 79452 | 310 690 | 13222| 1.40 120.14|
Info: 111000 | 29705 80088 | 355 636 | 12883| 1.69 121.84|
Info: 112000 | 30087 80706 | 382 618 | 12784| 1.78 123.61|
Info: 113000 | 30462 81331 | 375 625 | 12664| 1.93 125.54|
Info: 114000 | 30831 81962 | 369 631 | 12683| 1.80 127.34|
Info: 115000 | 31156 82637 | 325 675 | 12664| 1.73 129.07|
Info: 116000 | 31415 83336 | 259 699 | 12242| 1.12 130.20|
Info: 117000 | 31650 84037 | 235 701 | 11796| 1.01 131.21|
Info: 118000 | 31928 84723 | 278 686 | 11285| 1.46 132.67|
Info: 119000 | 32116 85400 | 188 677 | 10678| 1.15 133.81|
Info: 120000 | 32324 86105 | 208 705 | 10014| 0.79 134.61|
Info: 121000 | 32696 86728 | 372 623 | 9739| 2.00 136.61|
Info: 122000 | 33087 87330 | 391 602 | 9616| 1.52 138.13|
Info: 123000 | 33534 87883 | 447 553 | 9474| 1.62 139.75|
Info: 124000 | 33920 88497 | 386 614 | 9433| 1.86 141.61|
Info: 125000 | 34269 89148 | 349 651 | 9296| 1.61 143.22|
Info: 126000 | 34733 89684 | 464 536 | 9296| 2.04 145.26|
Info: 127000 | 35106 90311 | 373 627 | 9241| 1.97 147.23|
Info: 128000 | 35344 91033 | 238 722 | 8668| 0.94 148.18|
Info: 129000 | 35554 91803 | 210 770 | 8127| 0.96 149.13|
Info: 130000 | 35932 92425 | 378 622 | 8023| 1.74 150.87|
Info: 131000 | 36085 93264 | 153 839 | 7231| 0.52 151.39|
Info: 132000 | 36522 93827 | 437 563 | 7201| 1.94 153.33|
Info: 133000 | 37004 94345 | 482 518 | 6928| 2.25 155.58|
Info: 134000 | 37440 94909 | 436 564 | 6801| 1.86 157.44|
Info: 135000 | 37838 95511 | 398 602 | 6740| 1.64 159.08|
Info: 136000 | 38205 96144 | 367 633 | 6659| 1.53 160.61|
Info: 137000 | 38608 96741 | 403 597 | 6542| 2.28 162.90|
Info: 138000 | 39010 97339 | 402 598 | 6445| 1.72 164.62|
Info: 139000 | 39357 97992 | 347 653 | 6608| 1.70 166.32|
Info: 140000 | 39721 98628 | 364 636 | 6645| 1.69 168.01|
Info: 141000 | 40079 99270 | 358 642 | 6468| 2.47 170.48|
Info: 142000 | 40388 99955 | 309 685 | 6012| 1.50 171.98|
Info: 143000 | 40722 100621 | 334 666 | 6009| 1.69 173.67|
Info: 144000 | 41097 101246 | 375 625 | 5780| 1.72 175.39|
Info: 145000 | 41462 101881 | 365 635 | 5795| 2.15 177.54|
Info: 146000 | 41837 102506 | 375 625 | 5626| 1.60 179.14|
Info: 147000 | 42130 103213 | 293 707 | 5060| 1.08 180.23|
Info: 148000 | 42552 103791 | 422 578 | 5018| 2.43 182.66|
Info: 149000 | 43014 104329 | 462 538 | 4910| 2.73 185.39|
Info: 150000 | 43485 104858 | 471 529 | 4909| 2.30 187.69|
Info: 151000 | 43906 105437 | 421 579 | 4838| 2.05 189.74|
Info: 152000 | 44310 106033 | 404 596 | 4869| 5.00 194.74|
Info: 153000 | 44789 106554 | 479 521 | 4921| 2.34 197.08|
Info: 154000 | 45276 107067 | 487 513 | 4699| 2.38 199.47|
Info: 155000 | 45758 107585 | 482 518 | 4585| 1.98 201.44|
Info: 156000 | 46166 108177 | 408 592 | 4731| 2.67 204.12|
Info: 157000 | 46435 108908 | 269 731 | 4718| 1.51 205.62|
Info: 158000 | 46759 109584 | 324 676 | 4772| 1.83 207.45|
Info: 159000 | 47166 110177 | 407 593 | 4522| 2.99 210.45|
Info: 160000 | 47598 110745 | 432 568 | 4446| 3.45 213.90|
Info: 161000 | 48131 111212 | 533 467 | 4408| 4.51 218.40|
Info: 162000 | 48553 111790 | 422 578 | 4455| 1.68 220.08|
Info: 163000 | 49028 112315 | 475 525 | 4366| 2.06 222.14|
Info: 164000 | 49444 112899 | 416 584 | 4422| 1.71 223.85|
Info: 165000 | 49804 113539 | 360 640 | 4317| 2.75 226.59|
Info: 166000 | 50242 114101 | 438 562 | 4124| 2.28 228.88|
Info: 167000 | 50598 114745 | 356 644 | 3880| 1.61 230.48|
Info: 168000 | 51004 115339 | 406 594 | 3553| 1.63 232.11|
Info: 169000 | 51401 115942 | 397 603 | 3541| 2.01 234.13|
Info: 170000 | 51837 116506 | 436 564 | 3384| 2.31 236.43|
Info: 171000 | 52324 117019 | 487 513 | 3377| 2.13 238.56|
Info: 172000 | 52719 117624 | 395 605 | 3224| 3.80 242.36|
Info: 173000 | 53031 118285 | 312 661 | 2817| 1.65 244.01|
Info: 174000 | 53397 118899 | 366 614 | 2746| 1.94 245.95|
Info: 175000 | 53712 119522 | 315 623 | 2383| 2.31 248.26|
Info: 176000 | 54009 120162 | 297 640 | 2056| 1.72 249.98|
Info: 177000 | 54381 120737 | 372 575 | 1934| 1.81 251.79|
Info: 178000 | 54838 121280 | 457 543 | 1919| 2.16 253.95|
Info: 179000 | 55134 121984 | 296 704 | 2185| 2.90 256.85|
Info: 180000 | 55513 122605 | 379 621 | 1903| 3.25 260.10|
Info: 181000 | 55875 123187 | 362 582 | 1505| 2.01 262.11|
Info: 182000 | 56199 123784 | 324 597 | 1108| 2.18 264.30|
Info: 183000 | 56536 124404 | 337 620 | 892| 2.26 266.56|
Info: 184000 | 56828 125031 | 292 627 | 432| 1.85 268.40|
Info: 185000 | 57266 125586 | 438 555 | 410| 2.53 270.93|
Info: 186000 | 57573 126279 | 307 693 | 424| 1.92 272.85|
Info: 187000 | 57983 126869 | 410 590 | 421| 2.11 274.97|
Info: 188000 | 58387 127465 | 404 596 | 436| 2.19 277.16|
Info: 189000 | 58739 128080 | 352 615 | 155| 1.58 278.73|
Info: 190000 | 59143 128667 | 404 587 | 100| 1.75 280.49|
Info: 190635 | 59430 129005 | 287 338 | 0| 1.39 281.88|
Info: Routing complete.
Info: Router1 time 281.88s
Info: Checksum: 0xe618c5dd
Info: Critical path report for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT' (posedge -> posedge):
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source u_dataflow_core.GEN_SLOT[3].u_np.x0[4]_TRELLIS_FF_Q_3.Q
Info: routing 4.01 4.41 Net u_dataflow_core.GEN_SLOT[3].u_np.x0[4][3] (9,37) -> (78,22)
Info: Sink u_dataflow_core.GEN_SLOT[3].u_np.product_comb[4]_MULT18X18D_P9.A3
Info: Defined in:
Info: hardware/v2/rtl/neural_processor.v:99.44-99.46
Info: logic 3.07 7.47 Source u_dataflow_core.GEN_SLOT[3].u_np.product_comb[4]_MULT18X18D_P9.P4
Info: routing 3.81 11.28 Net u_dataflow_core.GEN_SLOT[3].u_np.product_comb[4][4] (78,22) -> (13,36)
Info: Sink u_dataflow_core.GEN_SLOT[3].u_np.prod1[4]_TRELLIS_FF_Q_4.M
Info: Defined in:
Info: hardware/v2/rtl/neural_processor.v:135.34-135.46
Info: setup 0.00 11.28 Source u_dataflow_core.GEN_SLOT[3].u_np.prod1[4]_TRELLIS_FF_Q_4.M
Info: 3.46 ns logic, 7.82 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$sdram_clk$TRELLIS_IO_OUT':
Info: type curr total name
Info: source 0.00 0.00 Source sdram_dq[15]$tr_io.O
Info: routing 2.97 2.97 Net sdram_dq[15]$TRELLIS_IO_IN (0,59) -> (17,32)
Info: Sink u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_127_DI_LUT4_Z_D_LUT4_Z.C
Info: Defined in:
Info: hardware/v2/nms/rtl/sdram_unified_backend.v:104.24-104.32
Info: logic 0.18 3.15 Source u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_127_DI_LUT4_Z_D_LUT4_Z.F
Info: routing 0.94 4.09 Net u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_127_DI_LUT4_Z_D[2] (17,32) -> (19,32)
Info: Sink u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_127_DI_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.27 Source u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_127_DI_LUT4_Z.F
Info: routing 0.12 4.39 Net u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_127_DI (19,32) -> (19,32)
Info: Sink u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_127.DI
Info: setup 0.00 4.39 Source u_sdram_backend.ctrl_rdata_TRELLIS_FF_Q_127.DI
Info: 0.36 ns logic, 4.03 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$sdram_clk$TRELLIS_IO_OUT' -> '<async>':
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source u_spi_bridge.byte_idx_TRELLIS_FF_Q_3.Q
Info: routing 1.09 1.48 Net u_spi_bridge.byte_idx[3] (28,53) -> (28,49)
Info: Sink u_dataflow_core.u_dep_mgr.reg_required_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_Z.C
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 1.66 Source u_dataflow_core.u_dep_mgr.reg_required_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_Z.F
Info: routing 0.64 2.31 Net u_dataflow_core.u_dep_mgr.reg_required_TRELLIS_FF_Q_CE_LUT4_Z_C[3] (28,49) -> (28,50)
Info: Sink u_spi_bridge.soft_rst_pulse_TRELLIS_FF_Q_DI_PFUMX_Z_C0_PFUMX_C0_Z_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 2.49 Source u_spi_bridge.soft_rst_pulse_TRELLIS_FF_Q_DI_PFUMX_Z_C0_PFUMX_C0_Z_LUT4_Z.F
Info: routing 0.56 3.05 Net host_mem_ready_LUT4_B_1_Z_LUT4_C_Z[1] (28,50) -> (23,50)
Info: Sink spi_miso_LUT4_Z_D_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 3.23 Source spi_miso_LUT4_Z_D_LUT4_Z.F
Info: routing 0.86 4.09 Net spi_miso_LUT4_Z_B[3] (23,50) -> (23,56)
Info: Sink spi_miso_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.27 Source spi_miso_LUT4_Z.F
Info: routing 1.86 6.12 Net spi_miso$TRELLIS_IO_OUT (23,56) -> (0,62)
Info: Sink spi_miso$tr_io.I
Info: Defined in:
Info: hardware/v2/nms/rtl/fpga_neural_v2_top.v:55.17-55.25
Info: 1.12 ns logic, 5.01 ns routing
Info: Max frequency for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT': 88.64 MHz (PASS at 64.00 MHz)
Info: Max delay <async> -> posedge $glbnet$sdram_clk$TRELLIS_IO_OUT: 4.39 ns
Info: Max delay posedge $glbnet$sdram_clk$TRELLIS_IO_OUT -> <async> : 6.12 ns
Info: Slack histogram:
Info: legend: * represents 56 endpoint(s)
Info: + represents [1,56) endpoint(s)
Info: [ 4343, 4872) |+
Info: [ 4872, 5401) |****+
Info: [ 5401, 5930) |****+
Info: [ 5930, 6459) |****+
Info: [ 6459, 6988) |*****+
Info: [ 6988, 7517) |*********+
Info: [ 7517, 8046) |**********+
Info: [ 8046, 8575) |************+
Info: [ 8575, 9104) |*************************+
Info: [ 9104, 9633) |***********************************************+
Info: [ 9633, 10162) |*************************************************+
Info: [ 10162, 10691) |************************************************+
Info: [ 10691, 11220) |****************************************+
Info: [ 11220, 11749) |***********************+
Info: [ 11749, 12278) |*****************+
Info: [ 12278, 12807) |*************************************+
Info: [ 12807, 13336) |************************************************************
Info: [ 13336, 13865) |*********************************************************+
Info: [ 13865, 14394) |******************************************************+
Info: [ 14394, 14923) |*************************************************+
Info: Program finished normally.
hardware/v2/nms/synthesis/nms_multiproc_n8/nextpnr_seed3.log
+466
View File
@@ -0,0 +1,466 @@
Info: constraining clock net 'osc_clk' to 16.00 MHz
Info: Logic utilisation before packing:
Info: Total LUT4s: 10214/43848 23%
Info: logic LUTs: 5504/43848 12%
Info: carry LUTs: 2772/43848 6%
Info: RAM LUTs: 1292/ 5481 23%
Info: RAMW LUTs: 646/10962 5%
Info: Total DFFs: 11126/43848 25%
Info: Packing IOs..
Info: $sdram_dq[15]$iobuf_i: sdram_dq_$_TBUF__Y.Y
Info: pin 'sdram_dq[15]$tr_io' constrained to Bel 'X0/Y59/PIOB'.
Info: $sdram_dq[14]$iobuf_i: sdram_dq_$_TBUF__Y_15.Y
Info: pin 'sdram_dq[14]$tr_io' constrained to Bel 'X0/Y59/PIOC'.
Info: $sdram_dq[13]$iobuf_i: sdram_dq_$_TBUF__Y_14.Y
Info: pin 'sdram_dq[13]$tr_io' constrained to Bel 'X0/Y59/PIOA'.
Info: $sdram_dq[12]$iobuf_i: sdram_dq_$_TBUF__Y_13.Y
Info: pin 'sdram_dq[12]$tr_io' constrained to Bel 'X0/Y53/PIOA'.
Info: $sdram_dq[11]$iobuf_i: sdram_dq_$_TBUF__Y_12.Y
Info: pin 'sdram_dq[11]$tr_io' constrained to Bel 'X0/Y44/PIOD'.
Info: $sdram_dq[10]$iobuf_i: sdram_dq_$_TBUF__Y_11.Y
Info: pin 'sdram_dq[10]$tr_io' constrained to Bel 'X0/Y44/PIOC'.
Info: $sdram_dq[9]$iobuf_i: sdram_dq_$_TBUF__Y_10.Y
Info: pin 'sdram_dq[9]$tr_io' constrained to Bel 'X0/Y44/PIOA'.
Info: $sdram_dq[8]$iobuf_i: sdram_dq_$_TBUF__Y_9.Y
Info: pin 'sdram_dq[8]$tr_io' constrained to Bel 'X0/Y41/PIOD'.
Info: $sdram_dq[7]$iobuf_i: sdram_dq_$_TBUF__Y_8.Y
Info: pin 'sdram_dq[7]$tr_io' constrained to Bel 'X0/Y41/PIOB'.
Info: $sdram_dq[6]$iobuf_i: sdram_dq_$_TBUF__Y_7.Y
Info: pin 'sdram_dq[6]$tr_io' constrained to Bel 'X0/Y41/PIOC'.
Info: $sdram_dq[5]$iobuf_i: sdram_dq_$_TBUF__Y_6.Y
Info: pin 'sdram_dq[5]$tr_io' constrained to Bel 'X0/Y41/PIOA'.
Info: $sdram_dq[4]$iobuf_i: sdram_dq_$_TBUF__Y_5.Y
Info: pin 'sdram_dq[4]$tr_io' constrained to Bel 'X0/Y38/PIOD'.
Info: $sdram_dq[3]$iobuf_i: sdram_dq_$_TBUF__Y_4.Y
Info: pin 'sdram_dq[3]$tr_io' constrained to Bel 'X0/Y38/PIOB'.
Info: $sdram_dq[2]$iobuf_i: sdram_dq_$_TBUF__Y_3.Y
Info: pin 'sdram_dq[2]$tr_io' constrained to Bel 'X0/Y29/PIOD'.
Info: $sdram_dq[1]$iobuf_i: sdram_dq_$_TBUF__Y_2.Y
Info: pin 'sdram_dq[1]$tr_io' constrained to Bel 'X0/Y29/PIOB'.
Info: $sdram_dq[0]$iobuf_i: sdram_dq_$_TBUF__Y_1.Y
Info: pin 'sdram_dq[0]$tr_io' constrained to Bel 'X0/Y26/PIOD'.
Info: pin 'spi_sclk$tr_io' constrained to Bel 'X0/Y62/PIOC'.
Info: pin 'spi_mosi$tr_io' constrained to Bel 'X0/Y62/PIOB'.
Info: pin 'spi_miso$tr_io' constrained to Bel 'X0/Y62/PIOD'.
Info: pin 'spi_cs_n$tr_io' constrained to Bel 'X0/Y65/PIOA'.
Info: pin 'sdram_we_n$tr_io' constrained to Bel 'X0/Y14/PIOD'.
Info: pin 'sdram_ras_n$tr_io' constrained to Bel 'X0/Y14/PIOA'.
Info: pin 'sdram_dqm[1]$tr_io' constrained to Bel 'X0/Y62/PIOA'.
Info: pin 'sdram_dqm[0]$tr_io' constrained to Bel 'X0/Y59/PIOD'.
Info: pin 'sdram_cs_n$tr_io' constrained to Bel 'X0/Y11/PIOD'.
Info: pin 'sdram_clk$tr_io' constrained to Bel 'X0/Y38/PIOA'.
Info: pin 'sdram_cke$tr_io' constrained to Bel 'X0/Y11/PIOC'.
Info: pin 'sdram_cas_n$tr_io' constrained to Bel 'X0/Y14/PIOC'.
Info: pin 'sdram_ba[1]$tr_io' constrained to Bel 'X0/Y17/PIOC'.
Info: pin 'sdram_ba[0]$tr_io' constrained to Bel 'X0/Y17/PIOA'.
Info: pin 'sdram_a[12]$tr_io' constrained to Bel 'X0/Y35/PIOB'.
Info: pin 'sdram_a[11]$tr_io' constrained to Bel 'X0/Y26/PIOB'.
Info: pin 'sdram_a[10]$tr_io' constrained to Bel 'X0/Y26/PIOC'.
Info: pin 'sdram_a[9]$tr_io' constrained to Bel 'X0/Y26/PIOA'.
Info: pin 'sdram_a[8]$tr_io' constrained to Bel 'X0/Y23/PIOD'.
Info: pin 'sdram_a[7]$tr_io' constrained to Bel 'X0/Y23/PIOB'.
Info: pin 'sdram_a[6]$tr_io' constrained to Bel 'X0/Y23/PIOA'.
Info: pin 'sdram_a[5]$tr_io' constrained to Bel 'X0/Y20/PIOD'.
Info: pin 'sdram_a[4]$tr_io' constrained to Bel 'X0/Y20/PIOB'.
Info: pin 'sdram_a[3]$tr_io' constrained to Bel 'X0/Y20/PIOC'.
Info: pin 'sdram_a[2]$tr_io' constrained to Bel 'X0/Y20/PIOA'.
Info: pin 'sdram_a[1]$tr_io' constrained to Bel 'X0/Y17/PIOD'.
Info: pin 'sdram_a[0]$tr_io' constrained to Bel 'X0/Y17/PIOB'.
Info: pin 'pll_locked$tr_io' constrained to Bel 'X0/Y65/PIOC'.
Info: pin 'osc_clk$tr_io' constrained to Bel 'X0/Y29/PIOC'.
Info: pin 'ext_rst_n$tr_io' constrained to Bel 'X0/Y14/PIOB'.
Info: pin 'data_ready$tr_io' constrained to Bel 'X0/Y32/PIOA'.
Info: placed PLL 'u_pll.pll_i' at bel 'X1/Y4/EHXPLL_UL'
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 3832 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Input frequency of PLL 'u_pll.pll_i' is constrained to 16.0 MHz
Info: Derived frequency constraint of 64.0 MHz for net sdram_clk$TRELLIS_IO_OUT
Info: Promoting globals...
Info: promoting clock net sdram_clk$TRELLIS_IO_OUT to global network
Info: Checksum: 0x94c17baa
Info: Device utilisation:
Info: TRELLIS_IO: 47/ 245 19%
Info: DCCA: 1/ 56 1%
Info: DP16KD: 0/ 108 0%
Info: MULT18X18D: 64/ 72 88%
Info: ALU54B: 0/ 36 0%
Info: EHXPLLL: 1/ 4 25%
Info: EXTREFB: 0/ 2 0%
Info: DCUA: 0/ 2 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 0/ 160 0%
Info: SIOLOGIC: 0/ 85 0%
Info: GSR: 0/ 1 0%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 0/ 1 0%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 11126/ 43848 25%
Info: TRELLIS_COMB: 11032/ 43848 25%
Info: TRELLIS_RAMW: 323/ 5481 5%
Info: Placed 48 cells based on constraints.
Info: Creating initial analytic placement for 12988 cells, random placement wirelen = 1059899.
Info: at initial placer iter 0, wirelen = 5771
Info: at initial placer iter 1, wirelen = 4462
Info: at initial placer iter 2, wirelen = 4650
Info: at initial placer iter 3, wirelen = 4479
Info: Running main analytical placer, max placement attempts per cell = 63811104.
Info: at iteration #1, type ALL: wirelen solved = 4197, spread = 244168, legal = 270892; time = 2.59s
Info: at iteration #2, type ALL: wirelen solved = 24295, spread = 175678, legal = 199996; time = 2.35s
Info: at iteration #3, type ALL: wirelen solved = 35302, spread = 161759, legal = 190932; time = 2.40s
Info: at iteration #4, type ALL: wirelen solved = 41197, spread = 155149, legal = 181423; time = 2.20s
Info: at iteration #5, type ALL: wirelen solved = 43625, spread = 149250, legal = 176763; time = 2.22s
Info: at iteration #6, type ALL: wirelen solved = 45023, spread = 152971, legal = 177372; time = 2.16s
Info: at iteration #7, type ALL: wirelen solved = 48063, spread = 148925, legal = 177840; time = 2.14s
Info: at iteration #8, type ALL: wirelen solved = 48719, spread = 149539, legal = 173373; time = 2.14s
Info: at iteration #9, type ALL: wirelen solved = 50505, spread = 147008, legal = 172815; time = 2.28s
Info: at iteration #10, type ALL: wirelen solved = 51422, spread = 148310, legal = 169471; time = 2.17s
Info: at iteration #11, type ALL: wirelen solved = 53240, spread = 146807, legal = 168999; time = 2.22s
Info: at iteration #12, type ALL: wirelen solved = 53504, spread = 147237, legal = 175333; time = 2.22s
Info: at iteration #13, type ALL: wirelen solved = 54672, spread = 147814, legal = 170109; time = 2.10s
Info: at iteration #14, type ALL: wirelen solved = 55571, spread = 147946, legal = 174287; time = 2.12s
Info: at iteration #15, type ALL: wirelen solved = 57220, spread = 148122, legal = 173304; time = 2.12s
Info: at iteration #16, type ALL: wirelen solved = 57544, spread = 148548, legal = 173348; time = 2.24s
Info: HeAP Placer Time: 40.97s
Info: of which solving equations: 8.44s
Info: of which spreading cells: 1.34s
Info: of which strict legalisation: 27.66s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 1980, wirelen = 168999
Info: at iteration #5: temp = 0.000000, timing cost = 2177, wirelen = 157942
Info: at iteration #10: temp = 0.000000, timing cost = 1930, wirelen = 155491
Info: at iteration #15: temp = 0.000000, timing cost = 1869, wirelen = 154525
Info: at iteration #20: temp = 0.000000, timing cost = 1906, wirelen = 154129
Info: at iteration #25: temp = 0.000000, timing cost = 1895, wirelen = 153959
Info: at iteration #30: temp = 0.000000, timing cost = 1888, wirelen = 153874
Info: at iteration #35: temp = 0.000000, timing cost = 1877, wirelen = 153826
Info: at iteration #38: temp = 0.000000, timing cost = 1875, wirelen = 153800
Info: SA placement time 60.93s
Info: Max frequency for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT': 63.54 MHz (FAIL at 64.00 MHz)
Info: Max delay <async> -> posedge $glbnet$sdram_clk$TRELLIS_IO_OUT: 7.04 ns
Info: Max delay posedge $glbnet$sdram_clk$TRELLIS_IO_OUT -> <async> : 8.43 ns
Info: Slack histogram:
Info: legend: * represents 65 endpoint(s)
Info: + represents [1,65) endpoint(s)
Info: [ -112, 647) |+
Info: [ 647, 1406) |+
Info: [ 1406, 2165) |+
Info: [ 2165, 2924) |***+
Info: [ 2924, 3683) |*+
Info: [ 3683, 4442) |***+
Info: [ 4442, 5201) |*****+
Info: [ 5201, 5960) |*******+
Info: [ 5960, 6719) |**********+
Info: [ 6719, 7478) |**********+
Info: [ 7478, 8237) |************************+
Info: [ 8237, 8996) |******************************************+
Info: [ 8996, 9755) |***********************************************+
Info: [ 9755, 10514) |************************************+
Info: [ 10514, 11273) |********************************+
Info: [ 11273, 12032) |****************************************+
Info: [ 12032, 12791) |************************************************************
Info: [ 12791, 13550) |***********************************************************+
Info: [ 13550, 14309) |*************************************************+
Info: [ 14309, 15068) |**************************************************+
Info: Checksum: 0x7f7c414c
Info: Routing globals...
Info: routing clock net $glbnet$sdram_clk$TRELLIS_IO_OUT using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 60733 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 618 381 | 618 381 | 60595| 1.85 1.85|
Info: 2000 | 1232 767 | 614 386 | 60514| 1.38 3.23|
Info: 3000 | 1825 1174 | 593 407 | 60343| 1.52 4.75|
Info: 4000 | 2443 1556 | 618 382 | 60207| 1.42 6.17|
Info: 5000 | 3055 1944 | 612 388 | 60085| 1.39 7.56|
Info: 6000 | 3752 2247 | 697 303 | 60006| 1.45 9.01|
Info: 7000 | 4269 2730 | 517 483 | 59918| 2.54 11.55|
Info: 8000 | 4717 3282 | 448 552 | 59709| 1.96 13.50|
Info: 9000 | 5181 3818 | 464 536 | 59462| 1.40 14.91|
Info: 10000 | 5575 4424 | 394 606 | 59229| 1.95 16.85|
Info: 11000 | 5932 5067 | 357 643 | 58958| 1.64 18.49|
Info: 12000 | 6248 5751 | 316 684 | 58527| 1.34 19.83|
Info: 13000 | 6480 6519 | 232 768 | 57882| 1.40 21.23|
Info: 14000 | 6744 7255 | 264 736 | 57406| 1.62 22.85|
Info: 15000 | 7045 7954 | 301 699 | 56922| 1.70 24.55|
Info: 16000 | 7316 8683 | 271 729 | 56444| 2.46 27.01|
Info: 17000 | 7500 9499 | 184 816 | 55880| 1.93 28.94|
Info: 18000 | 7777 10222 | 277 723 | 55508| 1.46 30.39|
Info: 19000 | 7959 11040 | 182 818 | 54890| 1.22 31.61|
Info: 20000 | 8128 11871 | 169 831 | 54161| 1.42 33.03|
Info: 21000 | 8235 12764 | 107 893 | 53308| 0.57 33.60|
Info: 22000 | 8300 13699 | 65 935 | 52467| 0.48 34.08|
Info: 23000 | 8369 14630 | 69 931 | 51617| 0.57 34.65|
Info: 24000 | 8503 15496 | 134 866 | 50957| 1.10 35.75|
Info: 25000 | 8591 16408 | 88 912 | 50143| 0.85 36.60|
Info: 26000 | 8675 17324 | 84 916 | 49322| 0.56 37.16|
Info: 27000 | 8737 18262 | 62 938 | 48473| 0.47 37.62|
Info: 28000 | 8849 19150 | 112 888 | 48001| 0.65 38.27|
Info: 29000 | 8945 20054 | 96 904 | 47186| 0.66 38.93|
Info: 30000 | 9020 20979 | 75 925 | 46366| 0.56 39.49|
Info: 31000 | 9169 21830 | 149 851 | 46113| 0.71 40.20|
Info: 32000 | 9247 22752 | 78 922 | 45337| 0.48 40.68|
Info: 33000 | 9364 23635 | 117 883 | 44567| 0.74 41.42|
Info: 34000 | 9450 24549 | 86 914 | 43775| 0.61 42.03|
Info: 35000 | 9536 25463 | 86 914 | 43024| 0.66 42.69|
Info: 36000 | 9666 26333 | 130 870 | 42565| 0.58 43.27|
Info: 37000 | 9763 27236 | 97 903 | 41816| 0.63 43.90|
Info: 38000 | 9897 28102 | 134 866 | 41094| 0.79 44.70|
Info: 39000 | 10071 28928 | 174 826 | 40590| 0.93 45.63|
Info: 40000 | 10204 29795 | 133 867 | 39937| 0.54 46.17|
Info: 41000 | 10377 30622 | 173 827 | 39268| 0.64 46.81|
Info: 42000 | 10532 31467 | 155 845 | 38506| 0.87 47.68|
Info: 43000 | 10713 32286 | 181 819 | 37862| 0.72 48.40|
Info: 44000 | 10864 33135 | 151 849 | 37279| 0.60 49.00|
Info: 45000 | 11076 33923 | 212 788 | 36833| 0.76 49.76|
Info: 46000 | 11244 34755 | 168 832 | 36245| 0.75 50.51|
Info: 47000 | 11467 35532 | 223 777 | 35845| 0.95 51.46|
Info: 48000 | 11665 36334 | 198 802 | 35510| 0.91 52.38|
Info: 49000 | 11839 37160 | 174 826 | 34859| 0.76 53.13|
Info: 50000 | 12051 37948 | 212 788 | 34606| 0.79 53.93|
Info: 51000 | 12268 38730 | 217 782 | 34041| 0.82 54.74|
Info: 52000 | 12506 39490 | 238 760 | 33602| 1.25 55.99|
Info: 53000 | 12775 40215 | 269 725 | 33077| 0.80 56.80|
Info: 54000 | 12996 40985 | 221 770 | 32773| 1.37 58.17|
Info: 55000 | 13186 41788 | 190 803 | 32447| 0.78 58.95|
Info: 56000 | 13468 42500 | 282 712 | 31970| 0.76 59.71|
Info: 57000 | 13690 43263 | 222 763 | 31413| 1.01 60.73|
Info: 58000 | 13934 44000 | 244 737 | 30854| 0.66 61.39|
Info: 59000 | 14172 44745 | 238 745 | 30339| 0.77 62.16|
Info: 60000 | 14380 45522 | 208 777 | 29907| 0.75 62.90|
Info: 61000 | 14635 46258 | 255 736 | 29570| 0.66 63.57|
Info: 62000 | 14860 47012 | 225 754 | 29246| 1.15 64.72|
Info: 63000 | 15126 47737 | 266 725 | 28801| 1.21 65.92|
Info: 64000 | 15349 48472 | 223 735 | 28239| 1.04 66.96|
Info: 65000 | 15551 49250 | 202 778 | 27902| 1.17 68.14|
Info: 66000 | 15773 49984 | 222 734 | 27391| 0.63 68.76|
Info: 67000 | 16111 50638 | 338 654 | 27245| 0.91 69.68|
Info: 68000 | 16398 51319 | 287 681 | 26712| 1.03 70.71|
Info: 69000 | 16627 52059 | 229 740 | 26306| 1.03 71.74|
Info: 70000 | 16967 52677 | 340 618 | 25978| 1.00 72.74|
Info: 71000 | 17210 53418 | 243 741 | 25543| 0.95 73.69|
Info: 72000 | 17372 54211 | 162 793 | 25037| 0.59 74.28|
Info: 73000 | 17624 54894 | 252 683 | 24620| 1.13 75.40|
Info: 74000 | 17879 55600 | 255 706 | 24167| 0.94 76.35|
Info: 75000 | 18151 56311 | 272 711 | 23612| 0.76 77.11|
Info: 76000 | 18407 57038 | 256 727 | 23165| 1.22 78.33|
Info: 77000 | 18645 57737 | 238 699 | 22815| 0.93 79.26|
Info: 78000 | 18811 58488 | 166 751 | 22167| 0.54 79.81|
Info: 79000 | 19091 59188 | 280 700 | 21737| 1.04 80.85|
Info: 80000 | 19350 59896 | 259 708 | 21380| 1.21 82.05|
Info: 81000 | 19599 60631 | 249 735 | 20967| 0.98 83.03|
Info: 82000 | 19878 61346 | 279 715 | 20784| 1.43 84.46|
Info: 83000 | 20105 62104 | 227 758 | 20401| 1.37 85.84|
Info: 84000 | 20348 62826 | 243 722 | 19953| 0.98 86.82|
Info: 85000 | 20596 63558 | 248 732 | 19628| 1.00 87.82|
Info: 86000 | 20801 64344 | 205 786 | 19541| 1.12 88.94|
Info: 87000 | 21071 65067 | 270 723 | 19410| 1.12 90.07|
Info: 88000 | 21318 65810 | 247 743 | 19159| 1.01 91.08|
Info: 89000 | 21557 66544 | 239 734 | 18759| 1.16 92.23|
Info: 90000 | 21905 67195 | 348 651 | 18495| 2.02 94.26|
Info: 91000 | 22083 67980 | 178 785 | 17884| 0.76 95.02|
Info: 92000 | 22344 68695 | 261 715 | 17569| 0.94 95.95|
Info: 93000 | 22640 69387 | 296 692 | 17393| 1.56 97.52|
Info: 94000 | 22932 70084 | 292 697 | 17113| 1.30 98.82|
Info: 95000 | 23190 70800 | 258 716 | 16817| 1.17 99.99|
Info: 96000 | 23500 71463 | 310 663 | 16455| 1.41 101.40|
Info: 97000 | 23800 72160 | 300 697 | 16272| 1.62 103.02|
Info: 98000 | 24127 72833 | 327 673 | 16126| 1.63 104.66|
Info: 99000 | 24369 73554 | 242 721 | 15589| 0.89 105.55|
Info: 100000 | 24590 74292 | 221 738 | 15155| 1.03 106.58|
Info: 101000 | 24835 75014 | 245 722 | 14836| 1.09 107.67|
Info: 102000 | 25168 75681 | 333 667 | 14777| 2.58 110.24|
Info: 103000 | 25462 76356 | 294 675 | 14517| 1.17 111.41|
Info: 104000 | 25622 77169 | 160 813 | 13722| 0.50 111.91|
Info: 105000 | 26006 77779 | 384 610 | 13592| 2.12 114.03|
Info: 106000 | 26367 78418 | 361 639 | 13549| 1.83 115.86|
Info: 107000 | 26606 79160 | 239 742 | 13181| 1.26 117.12|
Info: 108000 | 26931 79835 | 325 675 | 13256| 1.32 118.44|
Info: 109000 | 27236 80530 | 305 695 | 13222| 1.77 120.21|
Info: 110000 | 27668 81098 | 432 568 | 13189| 1.65 121.87|
Info: 111000 | 28066 81700 | 398 602 | 13134| 1.87 123.74|
Info: 112000 | 28441 82325 | 375 625 | 13055| 1.73 125.47|
Info: 113000 | 28849 82917 | 408 592 | 12912| 2.31 127.78|
Info: 114000 | 29226 83540 | 377 623 | 13024| 2.27 130.04|
Info: 115000 | 29549 84217 | 323 677 | 12841| 3.56 133.60|
Info: 116000 | 29773 84939 | 224 722 | 12324| 1.20 134.80|
Info: 117000 | 29899 85716 | 126 777 | 11545| 0.42 135.22|
Info: 118000 | 30145 86449 | 246 733 | 11317| 0.97 136.19|
Info: 119000 | 30319 87188 | 174 739 | 10567| 0.74 136.93|
Info: 120000 | 30500 87954 | 181 766 | 10086| 0.72 137.65|
Info: 121000 | 30831 88610 | 331 656 | 9724| 1.09 138.74|
Info: 122000 | 31267 89174 | 436 564 | 9555| 2.00 140.74|
Info: 123000 | 31615 89826 | 348 652 | 9787| 1.78 142.52|
Info: 124000 | 31908 90533 | 293 707 | 9702| 2.19 144.71|
Info: 125000 | 32232 91209 | 324 676 | 9478| 1.69 146.40|
Info: 126000 | 32608 91833 | 376 624 | 9464| 1.64 148.04|
Info: 127000 | 32926 92515 | 318 682 | 9346| 1.64 149.68|
Info: 128000 | 33355 93086 | 429 571 | 9392| 1.95 151.63|
Info: 129000 | 33839 93602 | 484 516 | 9288| 2.85 154.47|
Info: 130000 | 34202 94239 | 363 637 | 9298| 1.91 156.38|
Info: 131000 | 34501 94885 | 299 646 | 8808| 1.05 157.43|
Info: 132000 | 34844 95542 | 343 657 | 8709| 1.63 159.06|
Info: 133000 | 35155 96207 | 311 665 | 8258| 1.15 160.21|
Info: 134000 | 35420 96940 | 265 733 | 7821| 1.10 161.31|
Info: 135000 | 35698 97647 | 278 707 | 7304| 1.09 162.40|
Info: 136000 | 36122 98223 | 424 576 | 7171| 1.74 164.14|
Info: 137000 | 36567 98778 | 445 555 | 7071| 1.72 165.87|
Info: 138000 | 36942 99403 | 375 625 | 7073| 1.79 167.65|
Info: 139000 | 37311 100034 | 369 631 | 6905| 1.84 169.49|
Info: 140000 | 37784 100561 | 473 527 | 6782| 2.11 171.60|
Info: 141000 | 38224 101121 | 440 560 | 6671| 1.95 173.55|
Info: 142000 | 38635 101710 | 411 589 | 6610| 1.90 175.45|
Info: 143000 | 39015 102330 | 380 620 | 6373| 1.69 177.14|
Info: 144000 | 39247 103096 | 232 766 | 5748| 1.08 178.22|
Info: 145000 | 39462 103881 | 215 785 | 5174| 0.92 179.14|
Info: 146000 | 39842 104501 | 380 620 | 5126| 1.63 180.77|
Info: 147000 | 40314 105029 | 472 528 | 4977| 1.89 182.66|
Info: 148000 | 40755 105588 | 441 559 | 4880| 1.94 184.60|
Info: 149000 | 41159 106184 | 404 596 | 4985| 1.86 186.46|
Info: 150000 | 41535 106808 | 376 624 | 4799| 1.85 188.31|
Info: 151000 | 42006 107337 | 471 529 | 4662| 2.36 190.67|
Info: 152000 | 42450 107893 | 444 556 | 4627| 2.00 192.68|
Info: 153000 | 42880 108463 | 430 570 | 4590| 2.70 195.37|
Info: 154000 | 43337 109006 | 457 543 | 4553| 4.17 199.54|
Info: 155000 | 43783 109560 | 446 554 | 4484| 2.44 201.99|
Info: 156000 | 44230 110113 | 447 553 | 4464| 2.55 204.54|
Info: 157000 | 44625 110718 | 395 605 | 4349| 3.05 207.59|
Info: 158000 | 45150 111193 | 525 475 | 4318| 3.30 210.89|
Info: 159000 | 45570 111773 | 420 580 | 4260| 1.88 212.76|
Info: 160000 | 45951 112392 | 381 619 | 4122| 1.75 214.52|
Info: 161000 | 46278 113065 | 327 673 | 3902| 1.27 215.79|
Info: 162000 | 46683 113660 | 405 595 | 3719| 1.65 217.44|
Info: 163000 | 47051 114292 | 368 632 | 3405| 1.64 219.09|
Info: 164000 | 47425 114918 | 374 626 | 3081| 1.08 220.17|
Info: 165000 | 47812 115508 | 387 590 | 2914| 1.87 222.04|
Info: 166000 | 48083 116172 | 271 664 | 2554| 2.73 224.77|
Info: 167000 | 48533 116682 | 450 510 | 2344| 2.17 226.94|
Info: 168000 | 48775 117400 | 242 718 | 2184| 1.79 228.73|
Info: 169000 | 49117 118011 | 342 611 | 1834| 1.66 230.39|
Info: 170000 | 49489 118579 | 372 568 | 1588| 1.61 232.00|
Info: 171000 | 49831 119209 | 342 630 | 1504| 2.75 234.75|
Info: 172000 | 50215 119813 | 384 604 | 1363| 2.33 237.08|
Info: 173000 | 50553 120449 | 338 636 | 1241| 1.60 238.68|
Info: 174000 | 50846 121099 | 293 650 | 883| 2.22 240.90|
Info: 175000 | 51121 121771 | 275 672 | 541| 1.78 242.68|
Info: 176000 | 51407 122448 | 286 677 | 347| 1.68 244.36|
Info: 177000 | 51784 123070 | 377 622 | 395| 2.35 246.71|
Info: 178000 | 52198 123636 | 414 566 | 257| 1.97 248.67|
Info: 178813 | 52449 124164 | 251 528 | 0| 1.30 249.97|
Info: Routing complete.
Info: Router1 time 249.97s
Info: Checksum: 0x1adcdc1c
Info: Critical path report for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT' (posedge -> posedge):
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source u_dataflow_core.GEN_SLOT[4].u_np.w0[6]_TRELLIS_FF_Q_6.Q
Info: routing 4.20 4.59 Net u_dataflow_core.GEN_SLOT[4].u_np.w0[6][6] (19,4) -> (82,22)
Info: Sink u_dataflow_core.GEN_SLOT[4].u_np.product_comb[6]_MULT18X18D_P9.B6
Info: Defined in:
Info: hardware/v2/rtl/neural_processor.v:100.44-100.46
Info: logic 3.07 7.66 Source u_dataflow_core.GEN_SLOT[4].u_np.product_comb[6]_MULT18X18D_P9.P12
Info: routing 4.13 11.79 Net u_dataflow_core.GEN_SLOT[4].u_np.product_comb[6][12] (82,22) -> (14,9)
Info: Sink u_dataflow_core.GEN_SLOT[4].u_np.level0[6]_TRELLIS_FF_Q_12.M
Info: Defined in:
Info: hardware/v2/rtl/neural_processor.v:135.34-135.46
Info: setup 0.00 11.79 Source u_dataflow_core.GEN_SLOT[4].u_np.level0[6]_TRELLIS_FF_Q_12.M
Info: 3.46 ns logic, 8.33 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$sdram_clk$TRELLIS_IO_OUT':
Info: type curr total name
Info: source 0.00 0.00 Source ext_rst_n$tr_io.O
Info: routing 0.91 0.91 Net ext_rst_n$TRELLIS_IO_IN (0,14) -> (2,15)
Info: Sink ext_rst_n_LUT4_D.D
Info: Defined in:
Info: hardware/v2/rtl/reset_sync.v:18.17-18.26
Info: logic 0.18 1.09 Source ext_rst_n_LUT4_D.F
Info: routing 3.72 4.81 Net ext_rst_n_LUT4_D_Z (2,15) -> (36,59)
Info: Sink ext_rst_n_LUT4_D_Z_TRELLIS_FF_LSR_DI_TRELLIS_FF_Q.LSR
Info: setup 0.29 5.10 Source ext_rst_n_LUT4_D_Z_TRELLIS_FF_LSR_DI_TRELLIS_FF_Q.LSR
Info: 0.47 ns logic, 4.63 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$sdram_clk$TRELLIS_IO_OUT' -> '<async>':
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source u_spi_bridge.byte_idx_TRELLIS_FF_Q_2.Q
Info: routing 1.17 1.56 Net u_spi_bridge.byte_idx[2] (32,51) -> (31,45)
Info: Sink u_dataflow_core.u_dep_mgr.reg_required_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 1.74 Source u_dataflow_core.u_dep_mgr.reg_required_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_Z.F
Info: routing 0.90 2.65 Net u_dataflow_core.u_dep_mgr.reg_required_TRELLIS_FF_Q_CE_LUT4_Z_C[3] (31,45) -> (30,48)
Info: Sink u_spi_bridge.soft_rst_pulse_TRELLIS_FF_Q_DI_PFUMX_Z_C0_PFUMX_C0_Z_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 2.83 Source u_spi_bridge.soft_rst_pulse_TRELLIS_FF_Q_DI_PFUMX_Z_C0_PFUMX_C0_Z_LUT4_Z.F
Info: routing 1.25 4.08 Net host_mem_ready_LUT4_B_1_Z_LUT4_C_Z[1] (30,48) -> (25,56)
Info: Sink spi_miso_LUT4_Z_D_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.26 Source spi_miso_LUT4_Z_D_LUT4_Z.F
Info: routing 0.50 4.76 Net spi_miso_LUT4_Z_B[3] (25,56) -> (26,56)
Info: Sink spi_miso_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.93 Source spi_miso_LUT4_Z.F
Info: routing 1.80 6.73 Net spi_miso$TRELLIS_IO_OUT (26,56) -> (0,62)
Info: Sink spi_miso$tr_io.I
Info: Defined in:
Info: hardware/v2/nms/rtl/fpga_neural_v2_top.v:55.17-55.25
Info: 1.12 ns logic, 5.62 ns routing
Info: Max frequency for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT': 84.81 MHz (PASS at 64.00 MHz)
Info: Max delay <async> -> posedge $glbnet$sdram_clk$TRELLIS_IO_OUT: 5.10 ns
Info: Max delay posedge $glbnet$sdram_clk$TRELLIS_IO_OUT -> <async> : 6.73 ns
Info: Slack histogram:
Info: legend: * represents 69 endpoint(s)
Info: + represents [1,69) endpoint(s)
Info: [ 3834, 4389) |+
Info: [ 4389, 4944) |+
Info: [ 4944, 5499) |**+
Info: [ 5499, 6054) |****+
Info: [ 6054, 6609) |***+
Info: [ 6609, 7164) |*****+
Info: [ 7164, 7719) |******+
Info: [ 7719, 8274) |******+
Info: [ 8274, 8829) |***************+
Info: [ 8829, 9384) |*****************+
Info: [ 9384, 9939) |***********************+
Info: [ 9939, 10494) |*********************************+
Info: [ 10494, 11049) |*************************************+
Info: [ 11049, 11604) |*********************************+
Info: [ 11604, 12159) |****************************+
Info: [ 12159, 12714) |********************************************+
Info: [ 12714, 13269) |************************************************************
Info: [ 13269, 13824) |************************************************+
Info: [ 13824, 14379) |**********************************************+
Info: [ 14379, 14934) |*******************************************+
Info: Program finished normally.
hardware/v2/nms/synthesis/nms_multiproc_n8/nextpnr_seed4.log
+488
View File
@@ -0,0 +1,488 @@
Info: constraining clock net 'osc_clk' to 16.00 MHz
Info: Logic utilisation before packing:
Info: Total LUT4s: 10214/43848 23%
Info: logic LUTs: 5504/43848 12%
Info: carry LUTs: 2772/43848 6%
Info: RAM LUTs: 1292/ 5481 23%
Info: RAMW LUTs: 646/10962 5%
Info: Total DFFs: 11126/43848 25%
Info: Packing IOs..
Info: $sdram_dq[15]$iobuf_i: sdram_dq_$_TBUF__Y.Y
Info: pin 'sdram_dq[15]$tr_io' constrained to Bel 'X0/Y59/PIOB'.
Info: $sdram_dq[14]$iobuf_i: sdram_dq_$_TBUF__Y_15.Y
Info: pin 'sdram_dq[14]$tr_io' constrained to Bel 'X0/Y59/PIOC'.
Info: $sdram_dq[13]$iobuf_i: sdram_dq_$_TBUF__Y_14.Y
Info: pin 'sdram_dq[13]$tr_io' constrained to Bel 'X0/Y59/PIOA'.
Info: $sdram_dq[12]$iobuf_i: sdram_dq_$_TBUF__Y_13.Y
Info: pin 'sdram_dq[12]$tr_io' constrained to Bel 'X0/Y53/PIOA'.
Info: $sdram_dq[11]$iobuf_i: sdram_dq_$_TBUF__Y_12.Y
Info: pin 'sdram_dq[11]$tr_io' constrained to Bel 'X0/Y44/PIOD'.
Info: $sdram_dq[10]$iobuf_i: sdram_dq_$_TBUF__Y_11.Y
Info: pin 'sdram_dq[10]$tr_io' constrained to Bel 'X0/Y44/PIOC'.
Info: $sdram_dq[9]$iobuf_i: sdram_dq_$_TBUF__Y_10.Y
Info: pin 'sdram_dq[9]$tr_io' constrained to Bel 'X0/Y44/PIOA'.
Info: $sdram_dq[8]$iobuf_i: sdram_dq_$_TBUF__Y_9.Y
Info: pin 'sdram_dq[8]$tr_io' constrained to Bel 'X0/Y41/PIOD'.
Info: $sdram_dq[7]$iobuf_i: sdram_dq_$_TBUF__Y_8.Y
Info: pin 'sdram_dq[7]$tr_io' constrained to Bel 'X0/Y41/PIOB'.
Info: $sdram_dq[6]$iobuf_i: sdram_dq_$_TBUF__Y_7.Y
Info: pin 'sdram_dq[6]$tr_io' constrained to Bel 'X0/Y41/PIOC'.
Info: $sdram_dq[5]$iobuf_i: sdram_dq_$_TBUF__Y_6.Y
Info: pin 'sdram_dq[5]$tr_io' constrained to Bel 'X0/Y41/PIOA'.
Info: $sdram_dq[4]$iobuf_i: sdram_dq_$_TBUF__Y_5.Y
Info: pin 'sdram_dq[4]$tr_io' constrained to Bel 'X0/Y38/PIOD'.
Info: $sdram_dq[3]$iobuf_i: sdram_dq_$_TBUF__Y_4.Y
Info: pin 'sdram_dq[3]$tr_io' constrained to Bel 'X0/Y38/PIOB'.
Info: $sdram_dq[2]$iobuf_i: sdram_dq_$_TBUF__Y_3.Y
Info: pin 'sdram_dq[2]$tr_io' constrained to Bel 'X0/Y29/PIOD'.
Info: $sdram_dq[1]$iobuf_i: sdram_dq_$_TBUF__Y_2.Y
Info: pin 'sdram_dq[1]$tr_io' constrained to Bel 'X0/Y29/PIOB'.
Info: $sdram_dq[0]$iobuf_i: sdram_dq_$_TBUF__Y_1.Y
Info: pin 'sdram_dq[0]$tr_io' constrained to Bel 'X0/Y26/PIOD'.
Info: pin 'spi_sclk$tr_io' constrained to Bel 'X0/Y62/PIOC'.
Info: pin 'spi_mosi$tr_io' constrained to Bel 'X0/Y62/PIOB'.
Info: pin 'spi_miso$tr_io' constrained to Bel 'X0/Y62/PIOD'.
Info: pin 'spi_cs_n$tr_io' constrained to Bel 'X0/Y65/PIOA'.
Info: pin 'sdram_we_n$tr_io' constrained to Bel 'X0/Y14/PIOD'.
Info: pin 'sdram_ras_n$tr_io' constrained to Bel 'X0/Y14/PIOA'.
Info: pin 'sdram_dqm[1]$tr_io' constrained to Bel 'X0/Y62/PIOA'.
Info: pin 'sdram_dqm[0]$tr_io' constrained to Bel 'X0/Y59/PIOD'.
Info: pin 'sdram_cs_n$tr_io' constrained to Bel 'X0/Y11/PIOD'.
Info: pin 'sdram_clk$tr_io' constrained to Bel 'X0/Y38/PIOA'.
Info: pin 'sdram_cke$tr_io' constrained to Bel 'X0/Y11/PIOC'.
Info: pin 'sdram_cas_n$tr_io' constrained to Bel 'X0/Y14/PIOC'.
Info: pin 'sdram_ba[1]$tr_io' constrained to Bel 'X0/Y17/PIOC'.
Info: pin 'sdram_ba[0]$tr_io' constrained to Bel 'X0/Y17/PIOA'.
Info: pin 'sdram_a[12]$tr_io' constrained to Bel 'X0/Y35/PIOB'.
Info: pin 'sdram_a[11]$tr_io' constrained to Bel 'X0/Y26/PIOB'.
Info: pin 'sdram_a[10]$tr_io' constrained to Bel 'X0/Y26/PIOC'.
Info: pin 'sdram_a[9]$tr_io' constrained to Bel 'X0/Y26/PIOA'.
Info: pin 'sdram_a[8]$tr_io' constrained to Bel 'X0/Y23/PIOD'.
Info: pin 'sdram_a[7]$tr_io' constrained to Bel 'X0/Y23/PIOB'.
Info: pin 'sdram_a[6]$tr_io' constrained to Bel 'X0/Y23/PIOA'.
Info: pin 'sdram_a[5]$tr_io' constrained to Bel 'X0/Y20/PIOD'.
Info: pin 'sdram_a[4]$tr_io' constrained to Bel 'X0/Y20/PIOB'.
Info: pin 'sdram_a[3]$tr_io' constrained to Bel 'X0/Y20/PIOC'.
Info: pin 'sdram_a[2]$tr_io' constrained to Bel 'X0/Y20/PIOA'.
Info: pin 'sdram_a[1]$tr_io' constrained to Bel 'X0/Y17/PIOD'.
Info: pin 'sdram_a[0]$tr_io' constrained to Bel 'X0/Y17/PIOB'.
Info: pin 'pll_locked$tr_io' constrained to Bel 'X0/Y65/PIOC'.
Info: pin 'osc_clk$tr_io' constrained to Bel 'X0/Y29/PIOC'.
Info: pin 'ext_rst_n$tr_io' constrained to Bel 'X0/Y14/PIOB'.
Info: pin 'data_ready$tr_io' constrained to Bel 'X0/Y32/PIOA'.
Info: placed PLL 'u_pll.pll_i' at bel 'X1/Y4/EHXPLL_UL'
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 3832 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Input frequency of PLL 'u_pll.pll_i' is constrained to 16.0 MHz
Info: Derived frequency constraint of 64.0 MHz for net sdram_clk$TRELLIS_IO_OUT
Info: Promoting globals...
Info: promoting clock net sdram_clk$TRELLIS_IO_OUT to global network
Info: Checksum: 0x94c17baa
Info: Device utilisation:
Info: TRELLIS_IO: 47/ 245 19%
Info: DCCA: 1/ 56 1%
Info: DP16KD: 0/ 108 0%
Info: MULT18X18D: 64/ 72 88%
Info: ALU54B: 0/ 36 0%
Info: EHXPLLL: 1/ 4 25%
Info: EXTREFB: 0/ 2 0%
Info: DCUA: 0/ 2 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 0/ 160 0%
Info: SIOLOGIC: 0/ 85 0%
Info: GSR: 0/ 1 0%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 0/ 1 0%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 11126/ 43848 25%
Info: TRELLIS_COMB: 11032/ 43848 25%
Info: TRELLIS_RAMW: 323/ 5481 5%
Info: Placed 48 cells based on constraints.
Info: Creating initial analytic placement for 12988 cells, random placement wirelen = 1047922.
Info: at initial placer iter 0, wirelen = 5095
Info: at initial placer iter 1, wirelen = 4551
Info: at initial placer iter 2, wirelen = 4309
Info: at initial placer iter 3, wirelen = 4373
Info: Running main analytical placer, max placement attempts per cell = 63811104.
Info: at iteration #1, type ALL: wirelen solved = 4183, spread = 245867, legal = 271943; time = 2.46s
Info: at iteration #2, type ALL: wirelen solved = 24125, spread = 175570, legal = 199785; time = 2.34s
Info: at iteration #3, type ALL: wirelen solved = 35363, spread = 163946, legal = 191281; time = 2.25s
Info: at iteration #4, type ALL: wirelen solved = 42584, spread = 159230, legal = 187167; time = 2.29s
Info: at iteration #5, type ALL: wirelen solved = 44728, spread = 156885, legal = 183091; time = 2.22s
Info: at iteration #6, type ALL: wirelen solved = 47013, spread = 151954, legal = 180474; time = 2.18s
Info: at iteration #7, type ALL: wirelen solved = 47908, spread = 149524, legal = 178546; time = 2.21s
Info: at iteration #8, type ALL: wirelen solved = 49110, spread = 150215, legal = 175858; time = 2.13s
Info: at iteration #9, type ALL: wirelen solved = 51250, spread = 147266, legal = 174567; time = 2.14s
Info: at iteration #10, type ALL: wirelen solved = 51878, spread = 147085, legal = 173704; time = 2.22s
Info: at iteration #11, type ALL: wirelen solved = 52415, spread = 148233, legal = 174672; time = 2.21s
Info: at iteration #12, type ALL: wirelen solved = 54281, spread = 147796, legal = 173545; time = 2.20s
Info: at iteration #13, type ALL: wirelen solved = 54964, spread = 148201, legal = 172528; time = 2.17s
Info: at iteration #14, type ALL: wirelen solved = 56402, spread = 147445, legal = 175354; time = 2.19s
Info: at iteration #15, type ALL: wirelen solved = 57302, spread = 148890, legal = 174628; time = 2.29s
Info: at iteration #16, type ALL: wirelen solved = 58677, spread = 149396, legal = 174396; time = 2.18s
Info: at iteration #17, type ALL: wirelen solved = 59322, spread = 149938, legal = 171197; time = 2.24s
Info: at iteration #18, type ALL: wirelen solved = 59919, spread = 149761, legal = 172587; time = 2.17s
Info: at iteration #19, type ALL: wirelen solved = 61069, spread = 152429, legal = 170474; time = 2.16s
Info: at iteration #20, type ALL: wirelen solved = 62694, spread = 153352, legal = 171104; time = 2.19s
Info: at iteration #21, type ALL: wirelen solved = 63519, spread = 153947, legal = 169291; time = 2.16s
Info: at iteration #22, type ALL: wirelen solved = 64556, spread = 155580, legal = 173108; time = 2.17s
Info: at iteration #23, type ALL: wirelen solved = 65507, spread = 158865, legal = 169892; time = 2.06s
Info: at iteration #24, type ALL: wirelen solved = 66740, spread = 158634, legal = 170056; time = 2.18s
Info: at iteration #25, type ALL: wirelen solved = 67027, spread = 159789, legal = 169038; time = 2.11s
Info: at iteration #26, type ALL: wirelen solved = 68178, spread = 159938, legal = 171678; time = 2.02s
Info: at iteration #27, type ALL: wirelen solved = 69138, spread = 160605, legal = 170223; time = 2.09s
Info: at iteration #28, type ALL: wirelen solved = 69795, spread = 161201, legal = 171591; time = 1.99s
Info: at iteration #29, type ALL: wirelen solved = 70823, spread = 162504, legal = 170574; time = 2.00s
Info: at iteration #30, type ALL: wirelen solved = 71594, spread = 162207, legal = 172825; time = 2.02s
Info: HeAP Placer Time: 72.52s
Info: of which solving equations: 13.50s
Info: of which spreading cells: 2.63s
Info: of which strict legalisation: 50.09s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 2480, wirelen = 169038
Info: at iteration #5: temp = 0.000000, timing cost = 2849, wirelen = 158068
Info: at iteration #10: temp = 0.000000, timing cost = 2706, wirelen = 155506
Info: at iteration #15: temp = 0.000000, timing cost = 2733, wirelen = 154695
Info: at iteration #20: temp = 0.000000, timing cost = 2699, wirelen = 154405
Info: at iteration #25: temp = 0.000000, timing cost = 2774, wirelen = 154280
Info: at iteration #30: temp = 0.000000, timing cost = 2763, wirelen = 154233
Info: at iteration #35: temp = 0.000000, timing cost = 2761, wirelen = 154173
Info: at iteration #35: temp = 0.000000, timing cost = 2759, wirelen = 154175
Info: SA placement time 57.86s
Info: Max frequency for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT': 67.82 MHz (PASS at 64.00 MHz)
Info: Max delay <async> -> posedge $glbnet$sdram_clk$TRELLIS_IO_OUT: 7.29 ns
Info: Max delay posedge $glbnet$sdram_clk$TRELLIS_IO_OUT -> <async> : 7.62 ns
Info: Slack histogram:
Info: legend: * represents 59 endpoint(s)
Info: + represents [1,59) endpoint(s)
Info: [ 880, 1589) |+
Info: [ 1589, 2298) |**+
Info: [ 2298, 3007) |**+
Info: [ 3007, 3716) |**+
Info: [ 3716, 4425) |*****+
Info: [ 4425, 5134) |***+
Info: [ 5134, 5843) |*******+
Info: [ 5843, 6552) |******+
Info: [ 6552, 7261) |************+
Info: [ 7261, 7970) |**********************+
Info: [ 7970, 8679) |**************************************+
Info: [ 8679, 9388) |**************************************************+
Info: [ 9388, 10097) |*******************************************+
Info: [ 10097, 10806) |************************************+
Info: [ 10806, 11515) |*********************************+
Info: [ 11515, 12224) |*********************************************+
Info: [ 12224, 12933) |*******************************************************+
Info: [ 12933, 13642) |************************************************************
Info: [ 13642, 14351) |***********************************************+
Info: [ 14351, 15060) |*******************************************************+
Info: Checksum: 0xa43a0715
Info: Routing globals...
Info: routing clock net $glbnet$sdram_clk$TRELLIS_IO_OUT using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 60996 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 779 220 | 779 220 | 60909| 1.71 1.71|
Info: 2000 | 1342 657 | 563 437 | 60847| 1.81 3.52|
Info: 3000 | 1810 1189 | 468 532 | 60809| 1.68 5.20|
Info: 4000 | 2410 1589 | 600 400 | 60716| 1.04 6.24|
Info: 5000 | 3188 1811 | 778 222 | 60655| 0.97 7.21|
Info: 6000 | 3847 2152 | 659 341 | 60532| 1.49 8.70|
Info: 7000 | 4559 2440 | 712 288 | 60470| 1.39 10.08|
Info: 8000 | 5243 2756 | 684 316 | 60375| 1.36 11.44|
Info: 9000 | 5893 3106 | 650 350 | 60334| 1.67 13.11|
Info: 10000 | 6535 3464 | 642 358 | 60262| 1.78 14.89|
Info: 11000 | 7121 3878 | 586 414 | 60216| 1.60 16.49|
Info: 12000 | 7643 4356 | 522 478 | 60128| 2.20 18.69|
Info: 13000 | 8185 4814 | 542 458 | 60042| 2.04 20.73|
Info: 14000 | 8633 5366 | 448 552 | 59938| 4.32 25.05|
Info: 15000 | 9139 5860 | 506 494 | 59685| 4.42 29.47|
Info: 16000 | 9663 6336 | 524 476 | 59526| 2.74 32.21|
Info: 17000 | 10010 6989 | 347 653 | 59114| 3.06 35.27|
Info: 18000 | 10417 7582 | 407 593 | 58751| 3.55 38.82|
Info: 19000 | 10746 8253 | 329 671 | 58521| 2.49 41.30|
Info: 20000 | 11015 8984 | 269 731 | 58019| 3.15 44.45|
Info: 21000 | 11219 9780 | 204 796 | 57855| 1.59 46.04|
Info: 22000 | 11362 10637 | 143 857 | 57456| 1.47 47.51|
Info: 23000 | 11578 11421 | 216 784 | 56932| 1.64 49.15|
Info: 24000 | 11830 12169 | 252 748 | 56339| 2.01 51.16|
Info: 25000 | 12061 12938 | 231 769 | 55745| 2.66 53.82|
Info: 26000 | 12287 13712 | 226 774 | 55161| 2.35 56.17|
Info: 27000 | 12451 14548 | 164 836 | 54453| 1.49 57.66|
Info: 28000 | 12557 15442 | 106 894 | 53688| 1.02 58.68|
Info: 29000 | 12599 16400 | 42 958 | 52763| 0.54 59.22|
Info: 30000 | 12655 17344 | 56 944 | 51874| 0.66 59.88|
Info: 31000 | 12769 18230 | 114 886 | 51065| 1.03 60.91|
Info: 32000 | 12865 19134 | 96 904 | 50261| 0.61 61.52|
Info: 33000 | 12943 20056 | 78 922 | 49374| 0.58 62.10|
Info: 34000 | 12991 21008 | 48 952 | 48537| 0.73 62.83|
Info: 35000 | 13078 21921 | 87 913 | 47845| 0.61 63.44|
Info: 36000 | 13177 22822 | 99 901 | 47142| 0.63 64.07|
Info: 37000 | 13319 23680 | 142 858 | 46427| 0.90 64.97|
Info: 38000 | 13402 24597 | 83 917 | 45762| 0.56 65.53|
Info: 39000 | 13486 25513 | 84 916 | 45020| 0.43 65.96|
Info: 40000 | 13595 26404 | 109 891 | 44200| 0.60 66.56|
Info: 41000 | 13698 27301 | 103 897 | 43426| 0.51 67.07|
Info: 42000 | 13788 28211 | 90 910 | 42586| 0.56 67.62|
Info: 43000 | 13903 29096 | 115 885 | 41990| 0.48 68.10|
Info: 44000 | 14035 29964 | 132 868 | 41443| 0.62 68.72|
Info: 45000 | 14161 30838 | 126 874 | 40654| 0.47 69.19|
Info: 46000 | 14283 31716 | 122 878 | 39905| 0.52 69.71|
Info: 47000 | 14449 32550 | 166 834 | 39147| 0.54 70.25|
Info: 48000 | 14654 33345 | 205 795 | 38667| 0.88 71.13|
Info: 49000 | 14817 34182 | 163 837 | 38454| 0.53 71.66|
Info: 50000 | 14970 35029 | 153 847 | 37937| 0.71 72.38|
Info: 51000 | 15136 35863 | 166 834 | 37232| 0.62 73.00|
Info: 52000 | 15302 36697 | 166 834 | 36617| 0.62 73.62|
Info: 53000 | 15496 37503 | 194 806 | 35957| 0.63 74.25|
Info: 54000 | 15717 38282 | 221 779 | 35528| 1.49 75.74|
Info: 55000 | 15919 39079 | 202 797 | 34856| 0.56 76.30|
Info: 56000 | 16082 39916 | 163 837 | 34264| 0.59 76.89|
Info: 57000 | 16264 40733 | 182 817 | 33906| 0.52 77.41|
Info: 58000 | 16444 41549 | 180 816 | 33185| 0.62 78.03|
Info: 59000 | 16706 42277 | 262 728 | 32696| 0.79 78.82|
Info: 60000 | 16945 43025 | 239 748 | 32083| 0.61 79.43|
Info: 61000 | 17180 43783 | 235 758 | 31527| 0.88 80.32|
Info: 62000 | 17406 44538 | 226 755 | 31244| 0.82 81.14|
Info: 63000 | 17636 45299 | 230 761 | 30727| 0.97 82.11|
Info: 64000 | 17851 46077 | 215 778 | 30183| 0.66 82.76|
Info: 65000 | 18115 46805 | 264 728 | 29741| 0.83 83.60|
Info: 66000 | 18363 47517 | 248 712 | 29194| 0.74 84.33|
Info: 67000 | 18569 48295 | 206 778 | 28589| 0.64 84.97|
Info: 68000 | 18811 49041 | 242 746 | 28222| 0.90 85.87|
Info: 69000 | 18986 49832 | 175 791 | 27749| 1.01 86.89|
Info: 70000 | 19206 50578 | 220 746 | 27071| 0.76 87.65|
Info: 71000 | 19490 51234 | 284 656 | 26543| 0.92 88.57|
Info: 72000 | 19657 52006 | 167 772 | 25772| 0.80 89.36|
Info: 73000 | 19874 52743 | 217 737 | 25220| 1.00 90.36|
Info: 74000 | 20092 53465 | 218 722 | 24656| 0.86 91.22|
Info: 75000 | 20277 54194 | 185 729 | 24004| 0.66 91.88|
Info: 76000 | 20448 54958 | 171 764 | 23315| 0.73 92.61|
Info: 77000 | 20655 55681 | 207 723 | 22737| 0.56 93.17|
Info: 78000 | 20837 56454 | 182 773 | 22137| 0.62 93.79|
Info: 79000 | 21066 57200 | 229 746 | 21708| 1.03 94.83|
Info: 80000 | 21236 57994 | 170 794 | 21142| 0.73 95.56|
Info: 81000 | 21490 58707 | 254 713 | 20537| 0.86 96.41|
Info: 82000 | 21665 59496 | 175 789 | 19795| 0.66 97.08|
Info: 83000 | 21950 60192 | 285 696 | 19531| 1.15 98.23|
Info: 84000 | 22173 60948 | 223 756 | 18976| 1.04 99.27|
Info: 85000 | 22386 61689 | 213 741 | 18457| 1.19 100.46|
Info: 86000 | 22565 62489 | 179 800 | 17972| 0.73 101.19|
Info: 87000 | 22741 63292 | 176 803 | 17498| 0.68 101.87|
Info: 88000 | 22953 64065 | 212 773 | 17097| 1.32 103.19|
Info: 89000 | 23184 64787 | 231 722 | 16488| 0.85 104.04|
Info: 90000 | 23417 65545 | 233 758 | 16143| 1.07 105.11|
Info: 91000 | 23656 66294 | 239 749 | 15776| 1.59 106.70|
Info: 92000 | 23789 67076 | 133 782 | 15019| 0.64 107.34|
Info: 93000 | 23974 67859 | 185 783 | 14338| 0.75 108.10|
Info: 94000 | 24244 68567 | 270 708 | 13995| 1.11 109.21|
Info: 95000 | 24504 69285 | 260 718 | 13570| 0.90 110.11|
Info: 96000 | 24857 69932 | 353 647 | 13665| 2.42 112.53|
Info: 97000 | 25093 70696 | 236 764 | 13561| 1.25 113.78|
Info: 98000 | 25376 71403 | 283 707 | 13143| 1.57 115.35|
Info: 99000 | 25692 72087 | 316 684 | 12897| 1.66 117.01|
Info: 100000 | 26002 72745 | 310 658 | 12635| 1.45 118.46|
Info: 101000 | 26155 73501 | 153 756 | 11936| 0.66 119.12|
Info: 102000 | 26301 74279 | 146 778 | 11317| 0.67 119.79|
Info: 103000 | 26469 75018 | 168 739 | 10694| 0.84 120.63|
Info: 104000 | 26660 75793 | 191 775 | 10005| 0.78 121.42|
Info: 105000 | 26949 76500 | 289 707 | 9844| 1.43 122.85|
Info: 106000 | 27274 77175 | 325 675 | 9449| 1.67 124.52|
Info: 107000 | 27515 77896 | 241 721 | 8932| 1.43 125.95|
Info: 108000 | 27656 78722 | 141 826 | 8246| 0.83 126.78|
Info: 109000 | 27788 79565 | 132 843 | 7519| 0.70 127.48|
Info: 110000 | 28073 80280 | 285 715 | 7305| 1.51 129.00|
Info: 111000 | 28410 80943 | 337 663 | 7092| 1.27 130.27|
Info: 112000 | 28738 81615 | 328 672 | 6999| 1.72 131.99|
Info: 113000 | 29117 82236 | 379 621 | 6856| 1.36 133.35|
Info: 114000 | 29439 82914 | 322 678 | 6695| 1.26 134.61|
Info: 115000 | 29752 83591 | 313 677 | 6239| 1.17 135.78|
Info: 116000 | 30063 84280 | 311 689 | 5836| 0.90 136.67|
Info: 117000 | 30284 85059 | 221 779 | 5219| 1.08 137.75|
Info: 118000 | 30690 85653 | 406 594 | 5053| 1.24 138.99|
Info: 119000 | 31045 86298 | 355 645 | 4903| 1.19 140.17|
Info: 120000 | 31457 86886 | 412 588 | 4672| 1.52 141.70|
Info: 121000 | 31893 87450 | 436 564 | 4524| 1.60 143.30|
Info: 122000 | 32295 88048 | 402 598 | 4344| 1.74 145.04|
Info: 123000 | 32740 88603 | 445 555 | 4204| 2.30 147.34|
Info: 124000 | 33117 89226 | 377 623 | 3936| 1.49 148.84|
Info: 125000 | 33412 89931 | 295 705 | 3721| 1.52 150.35|
Info: 126000 | 33756 90587 | 344 656 | 3391| 1.48 151.83|
Info: 127000 | 33957 91358 | 201 771 | 2815| 1.13 152.96|
Info: 128000 | 34271 92003 | 314 645 | 2733| 1.53 154.49|
Info: 129000 | 34549 92710 | 278 707 | 2581| 1.40 155.89|
Info: 130000 | 34849 93338 | 300 628 | 2142| 1.60 157.49|
Info: 131000 | 35080 94011 | 231 673 | 1575| 1.17 158.66|
Info: 132000 | 35279 94729 | 199 718 | 1256| 1.16 159.82|
Info: 133000 | 35511 95467 | 232 738 | 1009| 1.68 161.50|
Info: 134000 | 35800 96152 | 289 685 | 807| 1.57 163.07|
Info: 135000 | 36100 96793 | 300 641 | 532| 1.36 164.43|
Info: 136000 | 36358 97481 | 258 688 | 203| 1.64 166.07|
Info: 136490 | 36470 97820 | 112 339 | 0| 0.78 166.85|
Info: Routing complete.
Info: Router1 time 166.85s
Info: Checksum: 0x8bfbcb4f
Info: Critical path report for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT' (posedge -> posedge):
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source u_arbiter_wide.m_addr_TRELLIS_FF_Q_3.Q
Info: routing 1.09 1.49 Net u_arbiter_wide.m_addr[3] (33,3) -> (38,8)
Info: Sink u_sdram_backend.w_cache_valid[2]_LUT4_C_D_LUT4_Z.B
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 1.67 Source u_sdram_backend.w_cache_valid[2]_LUT4_C_D_LUT4_Z.F
Info: routing 0.45 2.12 Net u_sdram_backend.w_cache_valid[2]_LUT4_C_D[3] (38,8) -> (38,8)
Info: Sink u_sdram_backend.w_cache_valid[2]_LUT4_C.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 2.30 Source u_sdram_backend.w_cache_valid[2]_LUT4_C.F
Info: routing 0.37 2.67 Net u_sdram_backend.w_cache_valid[2]_LUT4_C_Z[2] (38,8) -> (38,7)
Info: Sink u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 2.85 Source u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D.F
Info: routing 0.03 2.88 Net u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z[3] (38,7) -> (38,7)
Info: Sink u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 3.06 Source u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D.F
Info: routing 0.56 3.62 Net u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z[3] (38,7) -> (39,9)
Info: Sink u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 3.80 Source u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D.F
Info: routing 0.03 3.84 Net u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z[3] (39,9) -> (39,9)
Info: Sink u_sdram_backend.w_cache_valid[3]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.02 Source u_sdram_backend.w_cache_valid[3]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.F
Info: routing 1.38 5.39 Net u_sdram_backend.w_cache_valid[3]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z[2] (39,9) -> (21,9)
Info: Sink u_sdram_backend.w_cache_valid[0]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 5.57 Source u_sdram_backend.w_cache_valid[0]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.F
Info: routing 0.80 6.37 Net u_sdram_backend.w_cache_hit_LUT4_B_Z[3] (21,9) -> (24,9)
Info: Sink u_sdram_backend.w_cache_hit_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 6.55 Source u_sdram_backend.w_cache_hit_LUT4_Z.F
Info: routing 0.68 7.23 Net u_sdram_backend.w_alloc_ptr_TRELLIS_FF_Q_CE[0] (24,9) -> (24,7)
Info: Sink u_sdram_backend.w_cache_hit_LUT4_C.C
Info: Defined in:
Info: hardware/v2/nms/rtl/sdram_unified_backend.v:184.10-184.21
Info: logic 0.18 7.41 Source u_sdram_backend.w_cache_hit_LUT4_C.F
Info: routing 0.38 7.80 Net u_sdram_backend.w_cache_hit_LUT4_C_Z[0] (24,7) -> (24,7)
Info: Sink u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z.C
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 7.98 Source u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z.F
Info: routing 1.30 9.27 Net u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D[3] (24,7) -> (21,21)
Info: Sink u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_D.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 9.45 Source u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_D.F
Info: routing 2.07 11.52 Net u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_D_Z[3] (21,21) -> (21,55)
Info: Sink u_sdram_backend.ctrl_wdata_TRELLIS_FF_Q_15.CE
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: setup 0.00 11.52 Source u_sdram_backend.ctrl_wdata_TRELLIS_FF_Q_15.CE
Info: 2.38 ns logic, 9.15 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$sdram_clk$TRELLIS_IO_OUT':
Info: type curr total name
Info: source 0.00 0.00 Source ext_rst_n$tr_io.O
Info: routing 1.01 1.01 Net ext_rst_n$TRELLIS_IO_IN (0,14) -> (2,17)
Info: Sink ext_rst_n_LUT4_D.D
Info: Defined in:
Info: hardware/v2/rtl/reset_sync.v:18.17-18.26
Info: logic 0.18 1.19 Source ext_rst_n_LUT4_D.F
Info: routing 3.63 4.82 Net ext_rst_n_LUT4_D_Z (2,17) -> (33,64)
Info: Sink ext_rst_n_LUT4_D_Z_TRELLIS_FF_LSR_DI_TRELLIS_FF_Q.LSR
Info: setup 0.29 5.10 Source ext_rst_n_LUT4_D_Z_TRELLIS_FF_LSR_DI_TRELLIS_FF_Q.LSR
Info: 0.47 ns logic, 4.64 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$sdram_clk$TRELLIS_IO_OUT' -> '<async>':
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source u_spi_bridge.byte_idx_TRELLIS_FF_Q_2.Q
Info: routing 0.81 1.21 Net u_spi_bridge.byte_idx[2] (32,54) -> (32,47)
Info: Sink u_dataflow_core.u_dep_mgr.reg_required_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 1.38 Source u_dataflow_core.u_dep_mgr.reg_required_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_Z.F
Info: routing 0.50 1.88 Net u_dataflow_core.u_dep_mgr.reg_required_TRELLIS_FF_Q_CE_LUT4_Z_C[3] (32,47) -> (32,47)
Info: Sink u_spi_bridge.soft_rst_pulse_TRELLIS_FF_Q_DI_PFUMX_Z_C0_PFUMX_C0_Z_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 2.06 Source u_spi_bridge.soft_rst_pulse_TRELLIS_FF_Q_DI_PFUMX_Z_C0_PFUMX_C0_Z_LUT4_Z.F
Info: routing 1.65 3.72 Net host_mem_ready_LUT4_B_1_Z_LUT4_C_Z[1] (32,47) -> (24,55)
Info: Sink spi_miso_LUT4_Z_D_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 3.90 Source spi_miso_LUT4_Z_D_LUT4_Z.F
Info: routing 1.09 4.99 Net spi_miso_LUT4_Z_B[3] (24,55) -> (24,60)
Info: Sink spi_miso_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 5.17 Source spi_miso_LUT4_Z.F
Info: routing 1.85 7.02 Net spi_miso$TRELLIS_IO_OUT (24,60) -> (0,62)
Info: Sink spi_miso$tr_io.I
Info: Defined in:
Info: hardware/v2/nms/rtl/fpga_neural_v2_top.v:55.17-55.25
Info: 1.12 ns logic, 5.90 ns routing
Info: Max frequency for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT': 86.78 MHz (PASS at 64.00 MHz)
Info: Max delay <async> -> posedge $glbnet$sdram_clk$TRELLIS_IO_OUT: 5.10 ns
Info: Max delay posedge $glbnet$sdram_clk$TRELLIS_IO_OUT -> <async> : 7.02 ns
Info: Slack histogram:
Info: legend: * represents 57 endpoint(s)
Info: + represents [1,57) endpoint(s)
Info: [ 4102, 4643) |+
Info: [ 4643, 5184) |*+
Info: [ 5184, 5725) |****+
Info: [ 5725, 6266) |*******+
Info: [ 6266, 6807) |******+
Info: [ 6807, 7348) |****+
Info: [ 7348, 7889) |****+
Info: [ 7889, 8430) |***********+
Info: [ 8430, 8971) |**************+
Info: [ 8971, 9512) |**********************+
Info: [ 9512, 10053) |********************************+
Info: [ 10053, 10594) |*****************************************+
Info: [ 10594, 11135) |************************************************+
Info: [ 11135, 11676) |*************************************+
Info: [ 11676, 12217) |********************************************+
Info: [ 12217, 12758) |********************************************+
Info: [ 12758, 13299) |************************************************************
Info: [ 13299, 13840) |*********************************************************+
Info: [ 13840, 14381) |***********************************************************+
Info: [ 14381, 14922) |*****************************************************+
Info: Program finished normally.
hardware/v2/nms/synthesis/nms_multiproc_n8/nextpnr_seed5.log
+496
View File
@@ -0,0 +1,496 @@
Info: constraining clock net 'osc_clk' to 16.00 MHz
Info: Logic utilisation before packing:
Info: Total LUT4s: 10214/43848 23%
Info: logic LUTs: 5504/43848 12%
Info: carry LUTs: 2772/43848 6%
Info: RAM LUTs: 1292/ 5481 23%
Info: RAMW LUTs: 646/10962 5%
Info: Total DFFs: 11126/43848 25%
Info: Packing IOs..
Info: $sdram_dq[15]$iobuf_i: sdram_dq_$_TBUF__Y.Y
Info: pin 'sdram_dq[15]$tr_io' constrained to Bel 'X0/Y59/PIOB'.
Info: $sdram_dq[14]$iobuf_i: sdram_dq_$_TBUF__Y_15.Y
Info: pin 'sdram_dq[14]$tr_io' constrained to Bel 'X0/Y59/PIOC'.
Info: $sdram_dq[13]$iobuf_i: sdram_dq_$_TBUF__Y_14.Y
Info: pin 'sdram_dq[13]$tr_io' constrained to Bel 'X0/Y59/PIOA'.
Info: $sdram_dq[12]$iobuf_i: sdram_dq_$_TBUF__Y_13.Y
Info: pin 'sdram_dq[12]$tr_io' constrained to Bel 'X0/Y53/PIOA'.
Info: $sdram_dq[11]$iobuf_i: sdram_dq_$_TBUF__Y_12.Y
Info: pin 'sdram_dq[11]$tr_io' constrained to Bel 'X0/Y44/PIOD'.
Info: $sdram_dq[10]$iobuf_i: sdram_dq_$_TBUF__Y_11.Y
Info: pin 'sdram_dq[10]$tr_io' constrained to Bel 'X0/Y44/PIOC'.
Info: $sdram_dq[9]$iobuf_i: sdram_dq_$_TBUF__Y_10.Y
Info: pin 'sdram_dq[9]$tr_io' constrained to Bel 'X0/Y44/PIOA'.
Info: $sdram_dq[8]$iobuf_i: sdram_dq_$_TBUF__Y_9.Y
Info: pin 'sdram_dq[8]$tr_io' constrained to Bel 'X0/Y41/PIOD'.
Info: $sdram_dq[7]$iobuf_i: sdram_dq_$_TBUF__Y_8.Y
Info: pin 'sdram_dq[7]$tr_io' constrained to Bel 'X0/Y41/PIOB'.
Info: $sdram_dq[6]$iobuf_i: sdram_dq_$_TBUF__Y_7.Y
Info: pin 'sdram_dq[6]$tr_io' constrained to Bel 'X0/Y41/PIOC'.
Info: $sdram_dq[5]$iobuf_i: sdram_dq_$_TBUF__Y_6.Y
Info: pin 'sdram_dq[5]$tr_io' constrained to Bel 'X0/Y41/PIOA'.
Info: $sdram_dq[4]$iobuf_i: sdram_dq_$_TBUF__Y_5.Y
Info: pin 'sdram_dq[4]$tr_io' constrained to Bel 'X0/Y38/PIOD'.
Info: $sdram_dq[3]$iobuf_i: sdram_dq_$_TBUF__Y_4.Y
Info: pin 'sdram_dq[3]$tr_io' constrained to Bel 'X0/Y38/PIOB'.
Info: $sdram_dq[2]$iobuf_i: sdram_dq_$_TBUF__Y_3.Y
Info: pin 'sdram_dq[2]$tr_io' constrained to Bel 'X0/Y29/PIOD'.
Info: $sdram_dq[1]$iobuf_i: sdram_dq_$_TBUF__Y_2.Y
Info: pin 'sdram_dq[1]$tr_io' constrained to Bel 'X0/Y29/PIOB'.
Info: $sdram_dq[0]$iobuf_i: sdram_dq_$_TBUF__Y_1.Y
Info: pin 'sdram_dq[0]$tr_io' constrained to Bel 'X0/Y26/PIOD'.
Info: pin 'spi_sclk$tr_io' constrained to Bel 'X0/Y62/PIOC'.
Info: pin 'spi_mosi$tr_io' constrained to Bel 'X0/Y62/PIOB'.
Info: pin 'spi_miso$tr_io' constrained to Bel 'X0/Y62/PIOD'.
Info: pin 'spi_cs_n$tr_io' constrained to Bel 'X0/Y65/PIOA'.
Info: pin 'sdram_we_n$tr_io' constrained to Bel 'X0/Y14/PIOD'.
Info: pin 'sdram_ras_n$tr_io' constrained to Bel 'X0/Y14/PIOA'.
Info: pin 'sdram_dqm[1]$tr_io' constrained to Bel 'X0/Y62/PIOA'.
Info: pin 'sdram_dqm[0]$tr_io' constrained to Bel 'X0/Y59/PIOD'.
Info: pin 'sdram_cs_n$tr_io' constrained to Bel 'X0/Y11/PIOD'.
Info: pin 'sdram_clk$tr_io' constrained to Bel 'X0/Y38/PIOA'.
Info: pin 'sdram_cke$tr_io' constrained to Bel 'X0/Y11/PIOC'.
Info: pin 'sdram_cas_n$tr_io' constrained to Bel 'X0/Y14/PIOC'.
Info: pin 'sdram_ba[1]$tr_io' constrained to Bel 'X0/Y17/PIOC'.
Info: pin 'sdram_ba[0]$tr_io' constrained to Bel 'X0/Y17/PIOA'.
Info: pin 'sdram_a[12]$tr_io' constrained to Bel 'X0/Y35/PIOB'.
Info: pin 'sdram_a[11]$tr_io' constrained to Bel 'X0/Y26/PIOB'.
Info: pin 'sdram_a[10]$tr_io' constrained to Bel 'X0/Y26/PIOC'.
Info: pin 'sdram_a[9]$tr_io' constrained to Bel 'X0/Y26/PIOA'.
Info: pin 'sdram_a[8]$tr_io' constrained to Bel 'X0/Y23/PIOD'.
Info: pin 'sdram_a[7]$tr_io' constrained to Bel 'X0/Y23/PIOB'.
Info: pin 'sdram_a[6]$tr_io' constrained to Bel 'X0/Y23/PIOA'.
Info: pin 'sdram_a[5]$tr_io' constrained to Bel 'X0/Y20/PIOD'.
Info: pin 'sdram_a[4]$tr_io' constrained to Bel 'X0/Y20/PIOB'.
Info: pin 'sdram_a[3]$tr_io' constrained to Bel 'X0/Y20/PIOC'.
Info: pin 'sdram_a[2]$tr_io' constrained to Bel 'X0/Y20/PIOA'.
Info: pin 'sdram_a[1]$tr_io' constrained to Bel 'X0/Y17/PIOD'.
Info: pin 'sdram_a[0]$tr_io' constrained to Bel 'X0/Y17/PIOB'.
Info: pin 'pll_locked$tr_io' constrained to Bel 'X0/Y65/PIOC'.
Info: pin 'osc_clk$tr_io' constrained to Bel 'X0/Y29/PIOC'.
Info: pin 'ext_rst_n$tr_io' constrained to Bel 'X0/Y14/PIOB'.
Info: pin 'data_ready$tr_io' constrained to Bel 'X0/Y32/PIOA'.
Info: placed PLL 'u_pll.pll_i' at bel 'X1/Y4/EHXPLL_UL'
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 3832 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Input frequency of PLL 'u_pll.pll_i' is constrained to 16.0 MHz
Info: Derived frequency constraint of 64.0 MHz for net sdram_clk$TRELLIS_IO_OUT
Info: Promoting globals...
Info: promoting clock net sdram_clk$TRELLIS_IO_OUT to global network
Info: Checksum: 0x94c17baa
Info: Device utilisation:
Info: TRELLIS_IO: 47/ 245 19%
Info: DCCA: 1/ 56 1%
Info: DP16KD: 0/ 108 0%
Info: MULT18X18D: 64/ 72 88%
Info: ALU54B: 0/ 36 0%
Info: EHXPLLL: 1/ 4 25%
Info: EXTREFB: 0/ 2 0%
Info: DCUA: 0/ 2 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 0/ 160 0%
Info: SIOLOGIC: 0/ 85 0%
Info: GSR: 0/ 1 0%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 0/ 1 0%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 11126/ 43848 25%
Info: TRELLIS_COMB: 11032/ 43848 25%
Info: TRELLIS_RAMW: 323/ 5481 5%
Info: Placed 48 cells based on constraints.
Info: Creating initial analytic placement for 12988 cells, random placement wirelen = 1043784.
Info: at initial placer iter 0, wirelen = 5080
Info: at initial placer iter 1, wirelen = 4377
Info: at initial placer iter 2, wirelen = 4638
Info: at initial placer iter 3, wirelen = 4185
Info: Running main analytical placer, max placement attempts per cell = 63811104.
Info: at iteration #1, type ALL: wirelen solved = 4214, spread = 247664, legal = 272433; time = 2.46s
Info: at iteration #2, type ALL: wirelen solved = 24149, spread = 178924, legal = 201152; time = 2.42s
Info: at iteration #3, type ALL: wirelen solved = 36562, spread = 161244, legal = 192387; time = 2.37s
Info: at iteration #4, type ALL: wirelen solved = 42127, spread = 157207, legal = 191028; time = 2.21s
Info: at iteration #5, type ALL: wirelen solved = 44685, spread = 150646, legal = 190429; time = 2.36s
Info: at iteration #6, type ALL: wirelen solved = 46248, spread = 147139, legal = 184742; time = 2.42s
Info: at iteration #7, type ALL: wirelen solved = 47804, spread = 143452, legal = 175975; time = 2.34s
Info: at iteration #8, type ALL: wirelen solved = 48274, spread = 141842, legal = 174385; time = 2.52s
Info: at iteration #9, type ALL: wirelen solved = 49520, spread = 141575, legal = 175008; time = 2.33s
Info: at iteration #10, type ALL: wirelen solved = 50936, spread = 141119, legal = 173434; time = 2.18s
Info: at iteration #11, type ALL: wirelen solved = 52450, spread = 150865, legal = 172748; time = 2.12s
Info: at iteration #12, type ALL: wirelen solved = 56545, spread = 147920, legal = 173315; time = 2.25s
Info: at iteration #13, type ALL: wirelen solved = 56787, spread = 148420, legal = 174241; time = 2.08s
Info: at iteration #14, type ALL: wirelen solved = 57365, spread = 147884, legal = 171572; time = 2.26s
Info: at iteration #15, type ALL: wirelen solved = 58497, spread = 148560, legal = 172108; time = 2.20s
Info: at iteration #16, type ALL: wirelen solved = 59177, spread = 148894, legal = 170475; time = 2.25s
Info: at iteration #17, type ALL: wirelen solved = 59385, spread = 149640, legal = 174354; time = 2.23s
Info: at iteration #18, type ALL: wirelen solved = 60807, spread = 149212, legal = 168991; time = 2.17s
Info: at iteration #19, type ALL: wirelen solved = 61771, spread = 150779, legal = 171342; time = 2.12s
Info: at iteration #20, type ALL: wirelen solved = 62731, spread = 152966, legal = 172004; time = 2.19s
Info: at iteration #21, type ALL: wirelen solved = 64349, spread = 155288, legal = 172363; time = 2.13s
Info: at iteration #22, type ALL: wirelen solved = 65674, spread = 155148, legal = 172577; time = 2.07s
Info: at iteration #23, type ALL: wirelen solved = 65848, spread = 153894, legal = 170470; time = 2.29s
Info: HeAP Placer Time: 58.03s
Info: of which solving equations: 11.00s
Info: of which spreading cells: 2.07s
Info: of which strict legalisation: 39.98s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 2410, wirelen = 168991
Info: at iteration #5: temp = 0.000000, timing cost = 1854, wirelen = 157600
Info: at iteration #10: temp = 0.000000, timing cost = 1750, wirelen = 154942
Info: at iteration #15: temp = 0.000000, timing cost = 1701, wirelen = 154093
Info: at iteration #20: temp = 0.000000, timing cost = 1687, wirelen = 153692
Info: at iteration #25: temp = 0.000000, timing cost = 1678, wirelen = 153558
Info: at iteration #30: temp = 0.000000, timing cost = 1674, wirelen = 153480
Info: at iteration #35: temp = 0.000000, timing cost = 1672, wirelen = 153424
Info: at iteration #36: temp = 0.000000, timing cost = 1670, wirelen = 153426
Info: SA placement time 60.39s
Info: Max frequency for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT': 63.30 MHz (FAIL at 64.00 MHz)
Info: Max delay <async> -> posedge $glbnet$sdram_clk$TRELLIS_IO_OUT: 7.10 ns
Info: Max delay posedge $glbnet$sdram_clk$TRELLIS_IO_OUT -> <async> : 8.62 ns
Info: Slack histogram:
Info: legend: * represents 61 endpoint(s)
Info: + represents [1,61) endpoint(s)
Info: [ -174, 588) |+
Info: [ 588, 1350) |+
Info: [ 1350, 2112) |+
Info: [ 2112, 2874) |**+
Info: [ 2874, 3636) |***+
Info: [ 3636, 4398) |***+
Info: [ 4398, 5160) |*******+
Info: [ 5160, 5922) |*******+
Info: [ 5922, 6684) |*********+
Info: [ 6684, 7446) |**************+
Info: [ 7446, 8208) |****************************+
Info: [ 8208, 8970) |*************************************+
Info: [ 8970, 9732) |*****************************************************+
Info: [ 9732, 10494) |***************************************+
Info: [ 10494, 11256) |**********************************+
Info: [ 11256, 12018) |****************************************************+
Info: [ 12018, 12780) |**********************************************************+
Info: [ 12780, 13542) |************************************************************
Info: [ 13542, 14304) |*****************************************************+
Info: [ 14304, 15066) |*******************************************************+
Info: Checksum: 0xb074bd6f
Info: Routing globals...
Info: routing clock net $glbnet$sdram_clk$TRELLIS_IO_OUT using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 60833 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 556 443 | 556 443 | 60735| 1.75 1.75|
Info: 2000 | 1200 799 | 644 356 | 60593| 1.18 2.93|
Info: 3000 | 1895 1104 | 695 305 | 60446| 1.14 4.07|
Info: 4000 | 2433 1566 | 538 462 | 60312| 1.23 5.30|
Info: 5000 | 2835 2164 | 402 598 | 60186| 1.17 6.47|
Info: 6000 | 3376 2623 | 541 459 | 60112| 1.60 8.07|
Info: 7000 | 3968 3031 | 592 408 | 60027| 1.66 9.72|
Info: 8000 | 4536 3463 | 568 432 | 59926| 1.70 11.42|
Info: 9000 | 5099 3900 | 563 437 | 59798| 2.57 13.99|
Info: 10000 | 5514 4485 | 415 585 | 59705| 2.29 16.28|
Info: 11000 | 6007 4992 | 493 507 | 59549| 2.23 18.51|
Info: 12000 | 6452 5547 | 445 555 | 59285| 2.13 20.64|
Info: 13000 | 6884 6115 | 432 568 | 59063| 2.31 22.95|
Info: 14000 | 7259 6740 | 375 625 | 58674| 2.24 25.19|
Info: 15000 | 7600 7399 | 341 659 | 58369| 4.05 29.24|
Info: 16000 | 7875 8124 | 275 725 | 57913| 2.80 32.04|
Info: 17000 | 8090 8909 | 215 785 | 57262| 1.83 33.87|
Info: 18000 | 8271 9728 | 181 819 | 56572| 2.15 36.01|
Info: 19000 | 8452 10547 | 181 819 | 55902| 1.07 37.08|
Info: 20000 | 8554 11445 | 102 898 | 55057| 0.79 37.87|
Info: 21000 | 8711 12288 | 157 843 | 54472| 1.64 39.51|
Info: 22000 | 8813 13186 | 102 898 | 53870| 0.88 40.39|
Info: 23000 | 8927 14072 | 114 886 | 53186| 0.59 40.98|
Info: 24000 | 9060 14939 | 133 867 | 52397| 0.97 41.95|
Info: 25000 | 9140 15859 | 80 920 | 51574| 0.64 42.59|
Info: 26000 | 9239 16760 | 99 901 | 50745| 1.00 43.59|
Info: 27000 | 9324 17675 | 85 915 | 49976| 0.84 44.43|
Info: 28000 | 9416 18583 | 92 908 | 49187| 1.11 45.53|
Info: 29000 | 9505 19494 | 89 911 | 48389| 0.61 46.15|
Info: 30000 | 9578 20421 | 73 927 | 47578| 0.50 46.65|
Info: 31000 | 9664 21335 | 86 914 | 46740| 0.47 47.12|
Info: 32000 | 9746 22253 | 82 918 | 45995| 1.19 48.31|
Info: 33000 | 9806 23193 | 60 940 | 45104| 0.50 48.81|
Info: 34000 | 9899 24100 | 93 907 | 44246| 0.56 49.36|
Info: 35000 | 10003 24996 | 104 896 | 43466| 0.74 50.11|
Info: 36000 | 10113 25886 | 110 890 | 42673| 0.60 50.71|
Info: 37000 | 10244 26755 | 131 869 | 41933| 1.02 51.74|
Info: 38000 | 10338 27661 | 94 906 | 41224| 0.63 52.36|
Info: 39000 | 10434 28565 | 96 904 | 40496| 0.67 53.03|
Info: 40000 | 10540 29459 | 106 894 | 39710| 0.58 53.61|
Info: 41000 | 10656 30343 | 116 884 | 38913| 0.55 54.17|
Info: 42000 | 10790 31209 | 134 866 | 38228| 0.62 54.79|
Info: 43000 | 10955 32044 | 165 835 | 37720| 0.71 55.50|
Info: 44000 | 11115 32884 | 160 840 | 37079| 1.15 56.66|
Info: 45000 | 11297 33702 | 182 818 | 36333| 0.56 57.22|
Info: 46000 | 11407 34592 | 110 890 | 35955| 0.56 57.79|
Info: 47000 | 11693 35306 | 286 714 | 35607| 1.05 58.84|
Info: 48000 | 11868 36131 | 175 825 | 34954| 0.66 59.49|
Info: 49000 | 12059 36940 | 191 809 | 34504| 0.81 60.31|
Info: 50000 | 12268 37731 | 209 791 | 34009| 0.84 61.15|
Info: 51000 | 12455 38532 | 187 801 | 33437| 0.74 61.88|
Info: 52000 | 12689 39284 | 234 752 | 32859| 0.74 62.62|
Info: 53000 | 12894 40061 | 205 777 | 32228| 0.75 63.37|
Info: 54000 | 13125 40827 | 231 766 | 31644| 0.71 64.09|
Info: 55000 | 13382 41560 | 257 733 | 31154| 0.99 65.07|
Info: 56000 | 13683 42249 | 301 689 | 30716| 1.04 66.12|
Info: 57000 | 14031 42863 | 348 614 | 30504| 1.48 67.60|
Info: 58000 | 14285 43580 | 254 717 | 30513| 1.11 68.71|
Info: 59000 | 14548 44317 | 263 737 | 30266| 2.46 71.18|
Info: 60000 | 14733 45116 | 185 799 | 29536| 1.22 72.39|
Info: 61000 | 14947 45861 | 214 745 | 28925| 0.82 73.22|
Info: 62000 | 15191 46595 | 244 734 | 28445| 1.34 74.56|
Info: 63000 | 15410 47325 | 219 730 | 27828| 0.63 75.18|
Info: 64000 | 15665 48026 | 255 701 | 27424| 0.93 76.11|
Info: 65000 | 15890 48743 | 225 717 | 26783| 0.72 76.83|
Info: 66000 | 16177 49430 | 287 687 | 26491| 1.89 78.72|
Info: 67000 | 16412 50167 | 235 737 | 25989| 1.56 80.28|
Info: 68000 | 16615 50918 | 203 751 | 25442| 1.24 81.53|
Info: 69000 | 16938 51592 | 323 674 | 25328| 1.53 83.06|
Info: 70000 | 17252 52261 | 314 669 | 24978| 1.10 84.16|
Info: 71000 | 17471 53028 | 219 767 | 24599| 1.04 85.20|
Info: 72000 | 17744 53745 | 273 717 | 24119| 1.10 86.30|
Info: 73000 | 17964 54521 | 220 776 | 23745| 1.34 87.64|
Info: 74000 | 18153 55294 | 189 773 | 23106| 0.83 88.47|
Info: 75000 | 18343 56016 | 190 722 | 22517| 0.68 89.15|
Info: 76000 | 18534 56770 | 191 754 | 21966| 0.83 89.98|
Info: 77000 | 18707 57550 | 173 780 | 21392| 0.70 90.68|
Info: 78000 | 18980 58270 | 273 720 | 21125| 1.39 92.08|
Info: 79000 | 19162 59008 | 182 738 | 20483| 1.00 93.08|
Info: 80000 | 19386 59769 | 224 761 | 19939| 0.90 93.98|
Info: 81000 | 19671 60475 | 285 706 | 19584| 1.17 95.15|
Info: 82000 | 19846 61275 | 175 800 | 18939| 0.75 95.90|
Info: 83000 | 20098 62009 | 252 734 | 18719| 1.37 97.27|
Info: 84000 | 20428 62679 | 330 670 | 18636| 1.83 99.10|
Info: 85000 | 20579 63495 | 151 816 | 17894| 0.73 99.84|
Info: 86000 | 20768 64280 | 189 785 | 17457| 1.15 100.99|
Info: 87000 | 21094 64954 | 326 674 | 17449| 1.48 102.47|
Info: 88000 | 21360 65688 | 266 734 | 17426| 2.19 104.66|
Info: 89000 | 21545 66477 | 185 789 | 16900| 0.87 105.52|
Info: 90000 | 21780 67227 | 235 750 | 16576| 1.05 106.57|
Info: 91000 | 22081 67905 | 301 678 | 16160| 1.32 107.89|
Info: 92000 | 22403 68583 | 322 678 | 16018| 2.17 110.06|
Info: 93000 | 22552 69392 | 149 809 | 15242| 0.63 110.69|
Info: 94000 | 22814 70127 | 262 735 | 14772| 3.96 114.65|
Info: 95000 | 23025 70879 | 211 752 | 14307| 0.86 115.51|
Info: 96000 | 23283 71579 | 258 700 | 14001| 1.13 116.64|
Info: 97000 | 23503 72327 | 220 748 | 13623| 1.07 117.71|
Info: 98000 | 23778 73015 | 275 688 | 13180| 1.24 118.95|
Info: 99000 | 24060 73733 | 282 718 | 13089| 2.48 121.43|
Info: 100000 | 24310 74483 | 250 750 | 12749| 1.45 122.89|
Info: 101000 | 24512 75203 | 202 720 | 12086| 0.88 123.77|
Info: 102000 | 24642 75942 | 130 739 | 11312| 0.56 124.32|
Info: 103000 | 24826 76677 | 184 735 | 10621| 0.67 124.99|
Info: 104000 | 25082 77371 | 256 694 | 10270| 1.80 126.79|
Info: 105000 | 25354 78098 | 272 727 | 10076| 1.19 127.98|
Info: 106000 | 25614 78822 | 260 724 | 9898| 5.51 133.49|
Info: 107000 | 25953 79482 | 339 660 | 9920| 3.07 136.56|
Info: 108000 | 26223 80212 | 270 730 | 9881| 1.73 138.29|
Info: 109000 | 26543 80892 | 320 680 | 9667| 1.47 139.77|
Info: 110000 | 26891 81544 | 348 652 | 9600| 1.76 141.52|
Info: 111000 | 27327 82108 | 436 564 | 9399| 2.00 143.52|
Info: 112000 | 27521 82860 | 194 752 | 8788| 0.90 144.42|
Info: 113000 | 27673 83694 | 152 834 | 8252| 0.66 145.08|
Info: 114000 | 27868 84489 | 195 795 | 7729| 1.23 146.31|
Info: 115000 | 28255 85096 | 387 607 | 7364| 1.36 147.67|
Info: 116000 | 28695 85656 | 440 560 | 7186| 1.79 149.46|
Info: 117000 | 29057 86294 | 362 638 | 7069| 1.73 151.19|
Info: 118000 | 29392 86959 | 335 665 | 7194| 4.57 155.76|
Info: 119000 | 29751 87600 | 359 641 | 7039| 4.11 159.87|
Info: 120000 | 30176 88175 | 425 575 | 6929| 2.17 162.04|
Info: 121000 | 30598 88753 | 422 578 | 6824| 2.40 164.44|
Info: 122000 | 30976 89375 | 378 622 | 6662| 2.01 166.45|
Info: 123000 | 31313 90030 | 337 655 | 6377| 1.31 167.76|
Info: 124000 | 31584 90759 | 271 729 | 5879| 0.97 168.73|
Info: 125000 | 31985 91358 | 401 599 | 5836| 2.14 170.87|
Info: 126000 | 32155 92188 | 170 830 | 5267| 0.84 171.71|
Info: 127000 | 32540 92803 | 385 615 | 5145| 2.02 173.73|
Info: 128000 | 32915 93428 | 375 625 | 4991| 2.82 176.54|
Info: 129000 | 33236 94107 | 321 679 | 4996| 1.78 178.32|
Info: 130000 | 33644 94699 | 408 592 | 4896| 1.88 180.20|
Info: 131000 | 34005 95338 | 361 639 | 4916| 1.87 182.07|
Info: 132000 | 34302 96041 | 297 703 | 4709| 1.37 183.44|
Info: 133000 | 34724 96619 | 422 578 | 4662| 2.17 185.61|
Info: 134000 | 35089 97254 | 365 635 | 4591| 2.29 187.91|
Info: 135000 | 35527 97816 | 438 562 | 4566| 2.03 189.94|
Info: 136000 | 35815 98528 | 288 712 | 4456| 1.63 191.57|
Info: 137000 | 36119 99224 | 304 696 | 4415| 2.22 193.79|
Info: 138000 | 36479 99864 | 360 640 | 4367| 2.73 196.52|
Info: 139000 | 36918 100425 | 439 561 | 4317| 2.62 199.14|
Info: 140000 | 37254 101089 | 336 664 | 3954| 1.43 200.57|
Info: 141000 | 37544 101799 | 290 710 | 3566| 1.23 201.80|
Info: 142000 | 37935 102408 | 391 609 | 3405| 2.02 203.82|
Info: 143000 | 38096 103199 | 161 791 | 2759| 0.82 204.64|
Info: 144000 | 38338 103888 | 242 689 | 2451| 1.71 206.35|
Info: 145000 | 38618 104537 | 280 649 | 1955| 2.14 208.50|
Info: 146000 | 38958 105157 | 340 620 | 1729| 1.66 210.15|
Info: 147000 | 39232 105817 | 274 660 | 1325| 1.79 211.95|
Info: 148000 | 39628 106414 | 396 597 | 1371| 2.79 214.73|
Info: 149000 | 39954 107043 | 326 629 | 1048| 2.09 216.82|
Info: 150000 | 40179 107712 | 225 669 | 474| 1.36 218.19|
Info: 151000 | 40401 108400 | 222 688 | 14| 1.31 219.49|
Info: 151015 | 40402 108413 | 1 13 | 0| 0.16 219.66|
Info: Routing complete.
Info: Router1 time 219.66s
Info: Checksum: 0x648b8b0a
Info: Critical path report for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT' (posedge -> posedge):
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source u_arbiter_wide.m_addr_TRELLIS_FF_Q_11.Q
Info: routing 0.96 1.36 Net u_arbiter_wide.m_addr[11] (33,5) -> (29,7)
Info: Sink u_sdram_backend.w_cache_valid[2]_LUT4_C_D_LUT4_Z.A
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 1.54 Source u_sdram_backend.w_cache_valid[2]_LUT4_C_D_LUT4_Z.F
Info: routing 0.45 1.99 Net u_sdram_backend.w_cache_valid[2]_LUT4_C_D[3] (29,7) -> (29,7)
Info: Sink u_sdram_backend.w_cache_valid[2]_LUT4_C.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 2.17 Source u_sdram_backend.w_cache_valid[2]_LUT4_C.F
Info: routing 0.38 2.55 Net u_sdram_backend.w_cache_valid[2]_LUT4_C_Z[2] (29,7) -> (29,7)
Info: Sink u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 2.73 Source u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D.F
Info: routing 0.63 3.37 Net u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z[3] (29,7) -> (30,7)
Info: Sink u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 3.55 Source u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D.F
Info: routing 0.45 4.00 Net u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z[3] (30,7) -> (30,7)
Info: Sink u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.18 Source u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D.F
Info: routing 0.71 4.89 Net u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z[3] (30,7) -> (30,5)
Info: Sink u_sdram_backend.w_cache_valid[3]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 5.07 Source u_sdram_backend.w_cache_valid[3]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.F
Info: routing 1.12 6.19 Net u_sdram_backend.w_cache_valid[3]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z[2] (30,5) -> (21,9)
Info: Sink u_sdram_backend.w_cache_valid[0]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 6.37 Source u_sdram_backend.w_cache_valid[0]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.F
Info: routing 0.96 7.33 Net u_sdram_backend.w_cache_hit_LUT4_B_Z[3] (21,9) -> (25,7)
Info: Sink u_sdram_backend.w_cache_hit_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 7.51 Source u_sdram_backend.w_cache_hit_LUT4_Z.F
Info: routing 0.47 7.97 Net u_sdram_backend.w_alloc_ptr_TRELLIS_FF_Q_CE[0] (25,7) -> (25,7)
Info: Sink u_sdram_backend.w_cache_hit_LUT4_C.C
Info: Defined in:
Info: hardware/v2/nms/rtl/sdram_unified_backend.v:184.10-184.21
Info: logic 0.18 8.15 Source u_sdram_backend.w_cache_hit_LUT4_C.F
Info: routing 0.34 8.50 Net u_sdram_backend.w_cache_hit_LUT4_C_Z[0] (25,7) -> (25,7)
Info: Sink u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z.C
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 8.68 Source u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z.F
Info: routing 1.63 10.30 Net u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D[3] (25,7) -> (22,21)
Info: Sink u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_D.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 10.48 Source u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_D.F
Info: routing 1.86 12.34 Net u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_D_Z[3] (22,21) -> (23,49)
Info: Sink u_sdram_backend.ctrl_wdata_TRELLIS_FF_Q_9.CE
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: setup 0.00 12.34 Source u_sdram_backend.ctrl_wdata_TRELLIS_FF_Q_9.CE
Info: 2.38 ns logic, 9.97 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$sdram_clk$TRELLIS_IO_OUT':
Info: type curr total name
Info: source 0.00 0.00 Source ext_rst_n$tr_io.O
Info: routing 0.92 0.92 Net ext_rst_n$TRELLIS_IO_IN (0,14) -> (2,16)
Info: Sink ext_rst_n_LUT4_D.D
Info: Defined in:
Info: hardware/v2/rtl/reset_sync.v:18.17-18.26
Info: logic 0.18 1.10 Source ext_rst_n_LUT4_D.F
Info: routing 4.13 5.23 Net ext_rst_n_LUT4_D_Z (2,16) -> (36,59)
Info: Sink ext_rst_n_LUT4_D_Z_TRELLIS_FF_LSR_DI_TRELLIS_FF_Q.LSR
Info: setup 0.29 5.51 Source ext_rst_n_LUT4_D_Z_TRELLIS_FF_LSR_DI_TRELLIS_FF_Q.LSR
Info: 0.47 ns logic, 5.05 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$sdram_clk$TRELLIS_IO_OUT' -> '<async>':
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source u_spi_bridge.byte_idx_TRELLIS_FF_Q_3.Q
Info: routing 1.14 1.53 Net u_spi_bridge.byte_idx[3] (33,50) -> (35,42)
Info: Sink u_dataflow_core.u_dep_mgr.reg_required_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_Z.C
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 1.71 Source u_dataflow_core.u_dep_mgr.reg_required_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_Z.F
Info: routing 0.36 2.07 Net u_dataflow_core.u_dep_mgr.reg_required_TRELLIS_FF_Q_CE_LUT4_Z_C[3] (35,42) -> (35,42)
Info: Sink u_spi_bridge.soft_rst_pulse_TRELLIS_FF_Q_DI_PFUMX_Z_C0_PFUMX_C0_Z_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 2.25 Source u_spi_bridge.soft_rst_pulse_TRELLIS_FF_Q_DI_PFUMX_Z_C0_PFUMX_C0_Z_LUT4_Z.F
Info: routing 1.51 3.76 Net host_mem_ready_LUT4_B_1_Z_LUT4_C_Z[1] (35,42) -> (26,52)
Info: Sink spi_miso_LUT4_Z_D_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 3.94 Source spi_miso_LUT4_Z_D_LUT4_Z.F
Info: routing 0.68 4.62 Net spi_miso_LUT4_Z_B[3] (26,52) -> (27,54)
Info: Sink spi_miso_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.80 Source spi_miso_LUT4_Z.F
Info: routing 2.16 6.97 Net spi_miso$TRELLIS_IO_OUT (27,54) -> (0,62)
Info: Sink spi_miso$tr_io.I
Info: Defined in:
Info: hardware/v2/nms/rtl/fpga_neural_v2_top.v:55.17-55.25
Info: 1.12 ns logic, 5.85 ns routing
Info: Max frequency for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT': 81.04 MHz (PASS at 64.00 MHz)
Info: Max delay <async> -> posedge $glbnet$sdram_clk$TRELLIS_IO_OUT: 5.51 ns
Info: Max delay posedge $glbnet$sdram_clk$TRELLIS_IO_OUT -> <async> : 6.97 ns
Info: Slack histogram:
Info: legend: * represents 69 endpoint(s)
Info: + represents [1,69) endpoint(s)
Info: [ 3285, 3867) |+
Info: [ 3867, 4449) |+
Info: [ 4449, 5031) |*+
Info: [ 5031, 5613) |****+
Info: [ 5613, 6195) |*****+
Info: [ 6195, 6777) |***+
Info: [ 6777, 7359) |***+
Info: [ 7359, 7941) |*******+
Info: [ 7941, 8523) |*********+
Info: [ 8523, 9105) |**************+
Info: [ 9105, 9687) |************************+
Info: [ 9687, 10269) |*******************************+
Info: [ 10269, 10851) |*********************************+
Info: [ 10851, 11433) |**************************************+
Info: [ 11433, 12015) |********************************+
Info: [ 12015, 12597) |******************************************+
Info: [ 12597, 13179) |************************************************************
Info: [ 13179, 13761) |****************************************************+
Info: [ 13761, 14343) |****************************************************+
Info: [ 14343, 14925) |*********************************************+
Info: Program finished normally.
hardware/v2/nms/synthesis/nms_multiproc_n8/nextpnr_seed6.log
+477
View File
@@ -0,0 +1,477 @@
Info: constraining clock net 'osc_clk' to 16.00 MHz
Info: Logic utilisation before packing:
Info: Total LUT4s: 10214/43848 23%
Info: logic LUTs: 5504/43848 12%
Info: carry LUTs: 2772/43848 6%
Info: RAM LUTs: 1292/ 5481 23%
Info: RAMW LUTs: 646/10962 5%
Info: Total DFFs: 11126/43848 25%
Info: Packing IOs..
Info: $sdram_dq[15]$iobuf_i: sdram_dq_$_TBUF__Y.Y
Info: pin 'sdram_dq[15]$tr_io' constrained to Bel 'X0/Y59/PIOB'.
Info: $sdram_dq[14]$iobuf_i: sdram_dq_$_TBUF__Y_15.Y
Info: pin 'sdram_dq[14]$tr_io' constrained to Bel 'X0/Y59/PIOC'.
Info: $sdram_dq[13]$iobuf_i: sdram_dq_$_TBUF__Y_14.Y
Info: pin 'sdram_dq[13]$tr_io' constrained to Bel 'X0/Y59/PIOA'.
Info: $sdram_dq[12]$iobuf_i: sdram_dq_$_TBUF__Y_13.Y
Info: pin 'sdram_dq[12]$tr_io' constrained to Bel 'X0/Y53/PIOA'.
Info: $sdram_dq[11]$iobuf_i: sdram_dq_$_TBUF__Y_12.Y
Info: pin 'sdram_dq[11]$tr_io' constrained to Bel 'X0/Y44/PIOD'.
Info: $sdram_dq[10]$iobuf_i: sdram_dq_$_TBUF__Y_11.Y
Info: pin 'sdram_dq[10]$tr_io' constrained to Bel 'X0/Y44/PIOC'.
Info: $sdram_dq[9]$iobuf_i: sdram_dq_$_TBUF__Y_10.Y
Info: pin 'sdram_dq[9]$tr_io' constrained to Bel 'X0/Y44/PIOA'.
Info: $sdram_dq[8]$iobuf_i: sdram_dq_$_TBUF__Y_9.Y
Info: pin 'sdram_dq[8]$tr_io' constrained to Bel 'X0/Y41/PIOD'.
Info: $sdram_dq[7]$iobuf_i: sdram_dq_$_TBUF__Y_8.Y
Info: pin 'sdram_dq[7]$tr_io' constrained to Bel 'X0/Y41/PIOB'.
Info: $sdram_dq[6]$iobuf_i: sdram_dq_$_TBUF__Y_7.Y
Info: pin 'sdram_dq[6]$tr_io' constrained to Bel 'X0/Y41/PIOC'.
Info: $sdram_dq[5]$iobuf_i: sdram_dq_$_TBUF__Y_6.Y
Info: pin 'sdram_dq[5]$tr_io' constrained to Bel 'X0/Y41/PIOA'.
Info: $sdram_dq[4]$iobuf_i: sdram_dq_$_TBUF__Y_5.Y
Info: pin 'sdram_dq[4]$tr_io' constrained to Bel 'X0/Y38/PIOD'.
Info: $sdram_dq[3]$iobuf_i: sdram_dq_$_TBUF__Y_4.Y
Info: pin 'sdram_dq[3]$tr_io' constrained to Bel 'X0/Y38/PIOB'.
Info: $sdram_dq[2]$iobuf_i: sdram_dq_$_TBUF__Y_3.Y
Info: pin 'sdram_dq[2]$tr_io' constrained to Bel 'X0/Y29/PIOD'.
Info: $sdram_dq[1]$iobuf_i: sdram_dq_$_TBUF__Y_2.Y
Info: pin 'sdram_dq[1]$tr_io' constrained to Bel 'X0/Y29/PIOB'.
Info: $sdram_dq[0]$iobuf_i: sdram_dq_$_TBUF__Y_1.Y
Info: pin 'sdram_dq[0]$tr_io' constrained to Bel 'X0/Y26/PIOD'.
Info: pin 'spi_sclk$tr_io' constrained to Bel 'X0/Y62/PIOC'.
Info: pin 'spi_mosi$tr_io' constrained to Bel 'X0/Y62/PIOB'.
Info: pin 'spi_miso$tr_io' constrained to Bel 'X0/Y62/PIOD'.
Info: pin 'spi_cs_n$tr_io' constrained to Bel 'X0/Y65/PIOA'.
Info: pin 'sdram_we_n$tr_io' constrained to Bel 'X0/Y14/PIOD'.
Info: pin 'sdram_ras_n$tr_io' constrained to Bel 'X0/Y14/PIOA'.
Info: pin 'sdram_dqm[1]$tr_io' constrained to Bel 'X0/Y62/PIOA'.
Info: pin 'sdram_dqm[0]$tr_io' constrained to Bel 'X0/Y59/PIOD'.
Info: pin 'sdram_cs_n$tr_io' constrained to Bel 'X0/Y11/PIOD'.
Info: pin 'sdram_clk$tr_io' constrained to Bel 'X0/Y38/PIOA'.
Info: pin 'sdram_cke$tr_io' constrained to Bel 'X0/Y11/PIOC'.
Info: pin 'sdram_cas_n$tr_io' constrained to Bel 'X0/Y14/PIOC'.
Info: pin 'sdram_ba[1]$tr_io' constrained to Bel 'X0/Y17/PIOC'.
Info: pin 'sdram_ba[0]$tr_io' constrained to Bel 'X0/Y17/PIOA'.
Info: pin 'sdram_a[12]$tr_io' constrained to Bel 'X0/Y35/PIOB'.
Info: pin 'sdram_a[11]$tr_io' constrained to Bel 'X0/Y26/PIOB'.
Info: pin 'sdram_a[10]$tr_io' constrained to Bel 'X0/Y26/PIOC'.
Info: pin 'sdram_a[9]$tr_io' constrained to Bel 'X0/Y26/PIOA'.
Info: pin 'sdram_a[8]$tr_io' constrained to Bel 'X0/Y23/PIOD'.
Info: pin 'sdram_a[7]$tr_io' constrained to Bel 'X0/Y23/PIOB'.
Info: pin 'sdram_a[6]$tr_io' constrained to Bel 'X0/Y23/PIOA'.
Info: pin 'sdram_a[5]$tr_io' constrained to Bel 'X0/Y20/PIOD'.
Info: pin 'sdram_a[4]$tr_io' constrained to Bel 'X0/Y20/PIOB'.
Info: pin 'sdram_a[3]$tr_io' constrained to Bel 'X0/Y20/PIOC'.
Info: pin 'sdram_a[2]$tr_io' constrained to Bel 'X0/Y20/PIOA'.
Info: pin 'sdram_a[1]$tr_io' constrained to Bel 'X0/Y17/PIOD'.
Info: pin 'sdram_a[0]$tr_io' constrained to Bel 'X0/Y17/PIOB'.
Info: pin 'pll_locked$tr_io' constrained to Bel 'X0/Y65/PIOC'.
Info: pin 'osc_clk$tr_io' constrained to Bel 'X0/Y29/PIOC'.
Info: pin 'ext_rst_n$tr_io' constrained to Bel 'X0/Y14/PIOB'.
Info: pin 'data_ready$tr_io' constrained to Bel 'X0/Y32/PIOA'.
Info: placed PLL 'u_pll.pll_i' at bel 'X1/Y4/EHXPLL_UL'
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 3832 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Input frequency of PLL 'u_pll.pll_i' is constrained to 16.0 MHz
Info: Derived frequency constraint of 64.0 MHz for net sdram_clk$TRELLIS_IO_OUT
Info: Promoting globals...
Info: promoting clock net sdram_clk$TRELLIS_IO_OUT to global network
Info: Checksum: 0x94c17baa
Info: Device utilisation:
Info: TRELLIS_IO: 47/ 245 19%
Info: DCCA: 1/ 56 1%
Info: DP16KD: 0/ 108 0%
Info: MULT18X18D: 64/ 72 88%
Info: ALU54B: 0/ 36 0%
Info: EHXPLLL: 1/ 4 25%
Info: EXTREFB: 0/ 2 0%
Info: DCUA: 0/ 2 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 0/ 160 0%
Info: SIOLOGIC: 0/ 85 0%
Info: GSR: 0/ 1 0%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 0/ 1 0%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 11126/ 43848 25%
Info: TRELLIS_COMB: 11032/ 43848 25%
Info: TRELLIS_RAMW: 323/ 5481 5%
Info: Placed 48 cells based on constraints.
Info: Creating initial analytic placement for 12988 cells, random placement wirelen = 1044652.
Info: at initial placer iter 0, wirelen = 5280
Info: at initial placer iter 1, wirelen = 4360
Info: at initial placer iter 2, wirelen = 5262
Info: at initial placer iter 3, wirelen = 4454
Info: Running main analytical placer, max placement attempts per cell = 63811104.
Info: at iteration #1, type ALL: wirelen solved = 4204, spread = 246475, legal = 274125; time = 2.50s
Info: at iteration #2, type ALL: wirelen solved = 24622, spread = 177167, legal = 204851; time = 2.31s
Info: at iteration #3, type ALL: wirelen solved = 36505, spread = 161781, legal = 191698; time = 2.38s
Info: at iteration #4, type ALL: wirelen solved = 41334, spread = 153159, legal = 188970; time = 2.45s
Info: at iteration #5, type ALL: wirelen solved = 43843, spread = 152824, legal = 179079; time = 2.33s
Info: at iteration #6, type ALL: wirelen solved = 45257, spread = 148502, legal = 186237; time = 2.30s
Info: at iteration #7, type ALL: wirelen solved = 46885, spread = 146060, legal = 181834; time = 2.23s
Info: at iteration #8, type ALL: wirelen solved = 47663, spread = 144546, legal = 178795; time = 2.37s
Info: at iteration #9, type ALL: wirelen solved = 48667, spread = 144199, legal = 176735; time = 2.39s
Info: at iteration #10, type ALL: wirelen solved = 50708, spread = 150241, legal = 170421; time = 2.27s
Info: at iteration #11, type ALL: wirelen solved = 53301, spread = 148087, legal = 167741; time = 2.46s
Info: at iteration #12, type ALL: wirelen solved = 53483, spread = 147113, legal = 171570; time = 2.21s
Info: at iteration #13, type ALL: wirelen solved = 54857, spread = 147551, legal = 170197; time = 2.14s
Info: at iteration #14, type ALL: wirelen solved = 55749, spread = 147265, legal = 169849; time = 2.20s
Info: at iteration #15, type ALL: wirelen solved = 56557, spread = 148534, legal = 171719; time = 2.26s
Info: at iteration #16, type ALL: wirelen solved = 57887, spread = 149707, legal = 165620; time = 2.03s
Info: at iteration #17, type ALL: wirelen solved = 58702, spread = 151418, legal = 166143; time = 2.11s
Info: at iteration #18, type ALL: wirelen solved = 60024, spread = 151536, legal = 167225; time = 2.02s
Info: at iteration #19, type ALL: wirelen solved = 60885, spread = 150644, legal = 167940; time = 2.07s
Info: at iteration #20, type ALL: wirelen solved = 62672, spread = 150346, legal = 166332; time = 2.08s
Info: at iteration #21, type ALL: wirelen solved = 62797, spread = 151345, legal = 164876; time = 2.17s
Info: at iteration #22, type ALL: wirelen solved = 63283, spread = 151253, legal = 164735; time = 2.23s
Info: at iteration #23, type ALL: wirelen solved = 63477, spread = 151051, legal = 164754; time = 2.10s
Info: at iteration #24, type ALL: wirelen solved = 63737, spread = 151318, legal = 162134; time = 2.12s
Info: at iteration #25, type ALL: wirelen solved = 64507, spread = 151870, legal = 166026; time = 2.17s
Info: at iteration #26, type ALL: wirelen solved = 66646, spread = 151640, legal = 164115; time = 2.18s
Info: at iteration #27, type ALL: wirelen solved = 66670, spread = 152586, legal = 164181; time = 2.06s
Info: at iteration #28, type ALL: wirelen solved = 67729, spread = 152532, legal = 164585; time = 2.06s
Info: at iteration #29, type ALL: wirelen solved = 68030, spread = 152817, legal = 162699; time = 2.07s
Info: HeAP Placer Time: 71.47s
Info: of which solving equations: 13.50s
Info: of which spreading cells: 2.56s
Info: of which strict legalisation: 49.25s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 2075, wirelen = 162134
Info: at iteration #5: temp = 0.000000, timing cost = 1985, wirelen = 151169
Info: at iteration #10: temp = 0.000000, timing cost = 2081, wirelen = 148799
Info: at iteration #15: temp = 0.000000, timing cost = 2093, wirelen = 147854
Info: at iteration #20: temp = 0.000000, timing cost = 2132, wirelen = 147472
Info: at iteration #25: temp = 0.000000, timing cost = 2114, wirelen = 147348
Info: at iteration #28: temp = 0.000000, timing cost = 2110, wirelen = 147293
Info: SA placement time 48.80s
Info: Max frequency for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT': 67.25 MHz (PASS at 64.00 MHz)
Info: Max delay <async> -> posedge $glbnet$sdram_clk$TRELLIS_IO_OUT: 7.04 ns
Info: Max delay posedge $glbnet$sdram_clk$TRELLIS_IO_OUT -> <async> : 7.87 ns
Info: Slack histogram:
Info: legend: * represents 59 endpoint(s)
Info: + represents [1,59) endpoint(s)
Info: [ 756, 1471) |+
Info: [ 1471, 2186) |+
Info: [ 2186, 2901) |**+
Info: [ 2901, 3616) |***+
Info: [ 3616, 4331) |***+
Info: [ 4331, 5046) |*****+
Info: [ 5046, 5761) |*****+
Info: [ 5761, 6476) |******+
Info: [ 6476, 7191) |**********+
Info: [ 7191, 7906) |************+
Info: [ 7906, 8621) |****************************+
Info: [ 8621, 9336) |*********************************************+
Info: [ 9336, 10051) |******************************************************+
Info: [ 10051, 10766) |*********************************************+
Info: [ 10766, 11481) |***************************************+
Info: [ 11481, 12196) |******************************************************+
Info: [ 12196, 12911) |*******************************************************+
Info: [ 12911, 13626) |************************************************************
Info: [ 13626, 14341) |**********************************************+
Info: [ 14341, 15056) |********************************************************+
Info: Checksum: 0x1540039b
Info: Routing globals...
Info: routing clock net $glbnet$sdram_clk$TRELLIS_IO_OUT using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 61116 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 580 419 | 580 419 | 60971| 2.18 2.18|
Info: 2000 | 1300 699 | 720 280 | 60868| 0.87 3.06|
Info: 3000 | 1891 1108 | 591 409 | 60666| 1.49 4.54|
Info: 4000 | 2633 1366 | 742 258 | 60591| 0.97 5.51|
Info: 5000 | 3356 1643 | 723 277 | 60549| 1.37 6.88|
Info: 6000 | 3917 2082 | 561 439 | 60458| 1.93 8.81|
Info: 7000 | 4450 2549 | 533 467 | 60339| 2.25 11.06|
Info: 8000 | 4990 3009 | 540 460 | 60241| 2.74 13.80|
Info: 9000 | 5454 3545 | 464 536 | 60107| 1.66 15.46|
Info: 10000 | 6009 3990 | 555 445 | 59867| 1.83 17.29|
Info: 11000 | 6388 4611 | 379 621 | 59676| 1.40 18.69|
Info: 12000 | 6830 5169 | 442 558 | 59567| 2.23 20.92|
Info: 13000 | 7158 5841 | 328 672 | 59295| 2.67 23.58|
Info: 14000 | 7533 6466 | 375 625 | 58880| 1.97 25.56|
Info: 15000 | 7853 7146 | 320 680 | 58444| 2.20 27.76|
Info: 16000 | 8178 7821 | 325 675 | 57977| 2.93 30.68|
Info: 17000 | 8472 8527 | 294 706 | 57626| 2.72 33.40|
Info: 18000 | 8678 9321 | 206 794 | 56959| 2.04 35.44|
Info: 19000 | 8864 10135 | 186 814 | 56247| 1.60 37.05|
Info: 20000 | 9001 10998 | 137 863 | 55630| 1.51 38.56|
Info: 21000 | 9168 11831 | 167 833 | 54922| 1.56 40.12|
Info: 22000 | 9263 12736 | 95 905 | 54225| 0.91 41.04|
Info: 23000 | 9429 13570 | 166 834 | 53544| 1.22 42.26|
Info: 24000 | 9494 14505 | 65 935 | 52764| 0.57 42.83|
Info: 25000 | 9556 15443 | 62 938 | 51860| 0.54 43.37|
Info: 26000 | 9702 16297 | 146 854 | 51236| 1.31 44.68|
Info: 27000 | 9821 17178 | 119 881 | 50415| 0.92 45.60|
Info: 28000 | 9889 18110 | 68 932 | 49597| 0.50 46.10|
Info: 29000 | 9980 19019 | 91 909 | 48768| 0.74 46.84|
Info: 30000 | 10048 19951 | 68 932 | 47904| 0.58 47.42|
Info: 31000 | 10130 20869 | 82 918 | 47580| 0.61 48.03|
Info: 32000 | 10206 21793 | 76 924 | 46754| 0.64 48.67|
Info: 33000 | 10325 22674 | 119 881 | 46113| 0.81 49.48|
Info: 34000 | 10395 23604 | 70 930 | 45245| 0.64 50.12|
Info: 35000 | 10492 24507 | 97 903 | 44508| 0.62 50.74|
Info: 36000 | 10595 25404 | 103 897 | 43739| 0.59 51.33|
Info: 37000 | 10696 26303 | 101 899 | 43035| 0.58 51.90|
Info: 38000 | 10825 27174 | 129 871 | 42223| 0.86 52.76|
Info: 39000 | 10963 28036 | 138 862 | 41638| 1.19 53.95|
Info: 40000 | 11068 28931 | 105 895 | 40828| 0.63 54.58|
Info: 41000 | 11213 29786 | 145 855 | 40045| 0.66 55.24|
Info: 42000 | 11404 30595 | 191 809 | 39461| 1.09 56.33|
Info: 43000 | 11516 31483 | 112 888 | 38658| 0.58 56.91|
Info: 44000 | 11639 32360 | 123 877 | 37982| 0.60 57.51|
Info: 45000 | 11850 33149 | 211 789 | 37257| 0.74 58.25|
Info: 46000 | 12005 33994 | 155 845 | 36545| 0.69 58.95|
Info: 47000 | 12217 34782 | 212 788 | 35871| 0.72 59.66|
Info: 48000 | 12442 35556 | 225 774 | 35395| 0.72 60.38|
Info: 49000 | 12663 36333 | 221 777 | 34760| 0.59 60.97|
Info: 50000 | 12865 37131 | 202 798 | 34299| 0.63 61.60|
Info: 51000 | 13064 37932 | 199 801 | 33768| 0.65 62.26|
Info: 52000 | 13345 38646 | 281 714 | 33335| 0.67 62.93|
Info: 53000 | 13650 39325 | 305 679 | 32774| 0.72 63.64|
Info: 54000 | 13853 40109 | 203 784 | 32072| 0.89 64.53|
Info: 55000 | 14076 40876 | 223 767 | 31582| 0.71 65.24|
Info: 56000 | 14343 41603 | 267 727 | 31014| 0.90 66.14|
Info: 57000 | 14583 42349 | 240 746 | 30542| 0.71 66.85|
Info: 58000 | 14793 43123 | 210 774 | 29839| 0.93 67.78|
Info: 59000 | 15046 43814 | 253 691 | 29281| 1.01 68.78|
Info: 60000 | 15275 44537 | 229 723 | 28646| 0.76 69.55|
Info: 61000 | 15490 45273 | 215 736 | 27945| 0.68 70.23|
Info: 62000 | 15722 46010 | 232 737 | 27352| 0.79 71.01|
Info: 63000 | 15922 46781 | 200 771 | 26804| 0.63 71.65|
Info: 64000 | 16109 47543 | 187 762 | 26191| 0.81 72.45|
Info: 65000 | 16283 48308 | 174 765 | 25474| 0.53 72.98|
Info: 66000 | 16440 49093 | 157 785 | 24925| 0.88 73.86|
Info: 67000 | 16586 49876 | 146 783 | 24156| 0.66 74.52|
Info: 68000 | 16733 50692 | 147 816 | 23786| 0.84 75.36|
Info: 69000 | 16851 51523 | 118 831 | 23248| 0.61 75.97|
Info: 70000 | 17025 52325 | 174 802 | 22497| 0.74 76.71|
Info: 71000 | 17245 53088 | 220 763 | 22131| 1.14 77.85|
Info: 72000 | 17440 53864 | 195 776 | 21639| 0.73 78.58|
Info: 73000 | 17598 54680 | 158 816 | 20977| 0.77 79.35|
Info: 74000 | 17790 55456 | 192 776 | 20505| 0.87 80.22|
Info: 75000 | 17977 56231 | 187 775 | 19814| 0.79 81.01|
Info: 76000 | 18181 56982 | 204 751 | 19242| 0.75 81.76|
Info: 77000 | 18401 57733 | 220 751 | 18779| 1.10 82.86|
Info: 78000 | 18547 58529 | 146 796 | 18012| 0.88 83.74|
Info: 79000 | 18738 59319 | 191 790 | 17487| 0.90 84.64|
Info: 80000 | 19077 59948 | 339 629 | 17160| 1.49 86.13|
Info: 81000 | 19274 60718 | 197 770 | 16515| 0.88 87.01|
Info: 82000 | 19547 61418 | 273 700 | 16160| 1.41 88.41|
Info: 83000 | 19785 62180 | 238 762 | 16037| 1.46 89.87|
Info: 84000 | 19942 62944 | 157 764 | 15326| 0.70 90.58|
Info: 85000 | 20071 63762 | 129 818 | 14566| 0.54 91.11|
Info: 86000 | 20198 64597 | 127 835 | 13939| 0.67 91.78|
Info: 87000 | 20432 65312 | 234 715 | 13393| 0.94 92.73|
Info: 88000 | 20717 66008 | 285 696 | 13013| 1.23 93.96|
Info: 89000 | 20976 66749 | 259 741 | 12869| 1.34 95.30|
Info: 90000 | 21198 67509 | 222 760 | 12421| 1.02 96.32|
Info: 91000 | 21427 68247 | 229 738 | 12063| 1.08 97.40|
Info: 92000 | 21640 68975 | 213 728 | 11637| 1.02 98.42|
Info: 93000 | 21793 69733 | 153 758 | 10899| 0.60 99.02|
Info: 94000 | 22016 70460 | 223 727 | 10506| 0.97 99.99|
Info: 95000 | 22273 71153 | 257 693 | 9977| 1.09 101.08|
Info: 96000 | 22549 71877 | 276 724 | 10014| 1.38 102.45|
Info: 97000 | 22840 72584 | 291 707 | 9649| 1.57 104.02|
Info: 98000 | 23131 73293 | 291 709 | 9459| 1.45 105.47|
Info: 99000 | 23433 73991 | 302 698 | 9278| 1.33 106.80|
Info: 100000 | 23608 74800 | 175 809 | 8942| 0.88 107.68|
Info: 101000 | 23792 75581 | 184 781 | 8302| 0.85 108.53|
Info: 102000 | 23983 76372 | 191 791 | 7707| 0.71 109.24|
Info: 103000 | 24241 77112 | 258 740 | 7173| 1.39 110.62|
Info: 104000 | 24476 77877 | 235 765 | 7228| 1.66 112.28|
Info: 105000 | 24800 78553 | 324 676 | 6952| 1.73 114.01|
Info: 106000 | 25184 79169 | 384 616 | 6741| 1.70 115.71|
Info: 107000 | 25400 79953 | 216 784 | 6598| 1.32 117.03|
Info: 108000 | 25597 80746 | 197 793 | 6145| 0.98 118.01|
Info: 109000 | 25756 81587 | 159 841 | 5375| 0.51 118.52|
Info: 110000 | 26109 82234 | 353 647 | 5176| 1.39 119.90|
Info: 111000 | 26472 82871 | 363 637 | 4984| 1.48 121.38|
Info: 112000 | 26797 83546 | 325 675 | 4878| 1.25 122.63|
Info: 113000 | 27071 84272 | 274 726 | 4722| 1.35 123.98|
Info: 114000 | 27427 84916 | 356 644 | 4591| 1.70 125.68|
Info: 115000 | 27711 85632 | 284 716 | 4508| 1.48 127.16|
Info: 116000 | 28066 86277 | 355 645 | 4442| 1.44 128.60|
Info: 117000 | 28523 86820 | 457 543 | 4324| 1.63 130.24|
Info: 118000 | 28754 87589 | 231 769 | 3726| 0.94 131.18|
Info: 119000 | 28996 88347 | 242 758 | 3740| 1.36 132.54|
Info: 120000 | 29250 89093 | 254 746 | 3151| 0.74 133.28|
Info: 121000 | 29479 89802 | 229 709 | 2695| 1.15 134.43|
Info: 122000 | 29761 90479 | 282 677 | 2473| 1.50 135.93|
Info: 123000 | 29951 91178 | 190 699 | 1885| 1.12 137.05|
Info: 124000 | 30144 91866 | 193 688 | 1242| 1.19 138.24|
Info: 125000 | 30434 92535 | 290 669 | 986| 1.20 139.44|
Info: 126000 | 30708 93211 | 274 676 | 735| 1.83 141.27|
Info: 127000 | 30985 93898 | 277 687 | 434| 1.70 142.96|
Info: 128000 | 31322 94513 | 337 615 | 203| 2.00 144.97|
Info: 128372 | 31390 94782 | 68 269 | 0| 0.52 145.49|
Info: Routing complete.
Info: Router1 time 145.49s
Info: Checksum: 0x304736b9
Info: Critical path report for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT' (posedge -> posedge):
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source u_arbiter_wide.m_addr_TRELLIS_FF_Q_11.Q
Info: routing 0.70 1.10 Net u_arbiter_wide.m_addr[11] (39,7) -> (41,7)
Info: Sink u_sdram_backend.w_cache_valid[2]_LUT4_C_D_LUT4_Z.A
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 1.27 Source u_sdram_backend.w_cache_valid[2]_LUT4_C_D_LUT4_Z.F
Info: routing 0.60 1.88 Net u_sdram_backend.w_cache_valid[2]_LUT4_C_D[3] (41,7) -> (41,7)
Info: Sink u_sdram_backend.w_cache_valid[2]_LUT4_C.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 2.06 Source u_sdram_backend.w_cache_valid[2]_LUT4_C.F
Info: routing 0.35 2.41 Net u_sdram_backend.w_cache_valid[2]_LUT4_C_Z[2] (41,7) -> (41,8)
Info: Sink u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 2.59 Source u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D.F
Info: routing 0.38 2.97 Net u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z[3] (41,8) -> (41,7)
Info: Sink u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 3.15 Source u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D.F
Info: routing 0.31 3.46 Net u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z[3] (41,7) -> (42,7)
Info: Sink u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 3.64 Source u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D.F
Info: routing 0.31 3.95 Net u_sdram_backend.w_cache_valid[2]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z[3] (42,7) -> (42,7)
Info: Sink u_sdram_backend.w_cache_valid[3]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.13 Source u_sdram_backend.w_cache_valid[3]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.F
Info: routing 1.33 5.45 Net u_sdram_backend.w_cache_valid[3]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z[2] (42,7) -> (29,16)
Info: Sink u_sdram_backend.w_cache_valid[0]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 5.63 Source u_sdram_backend.w_cache_valid[0]_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_D_Z_LUT4_Z.F
Info: routing 1.11 6.74 Net u_sdram_backend.w_cache_hit_LUT4_B_Z[3] (29,16) -> (28,5)
Info: Sink u_sdram_backend.w_cache_hit_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 6.92 Source u_sdram_backend.w_cache_hit_LUT4_Z.F
Info: routing 0.56 7.49 Net u_sdram_backend.w_alloc_ptr_TRELLIS_FF_Q_CE[0] (28,5) -> (25,5)
Info: Sink u_sdram_backend.w_cache_hit_LUT4_C.C
Info: Defined in:
Info: hardware/v2/nms/rtl/sdram_unified_backend.v:184.10-184.21
Info: logic 0.18 7.67 Source u_sdram_backend.w_cache_hit_LUT4_C.F
Info: routing 0.03 7.70 Net u_sdram_backend.w_cache_hit_LUT4_C_Z[0] (25,5) -> (25,5)
Info: Sink u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z.C
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 7.88 Source u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z.F
Info: routing 0.84 8.72 Net u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D[3] (25,5) -> (24,9)
Info: Sink u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_D.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 8.90 Source u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_D.F
Info: routing 2.37 11.27 Net u_sdram_backend.ar_req_pending_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_D_Z[3] (24,9) -> (23,52)
Info: Sink u_sdram_backend.ctrl_wdata_TRELLIS_FF_Q_8.CE
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: setup 0.00 11.27 Source u_sdram_backend.ctrl_wdata_TRELLIS_FF_Q_8.CE
Info: 2.38 ns logic, 8.90 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$sdram_clk$TRELLIS_IO_OUT':
Info: type curr total name
Info: source 0.00 0.00 Source ext_rst_n$tr_io.O
Info: routing 1.22 1.22 Net ext_rst_n$TRELLIS_IO_IN (0,14) -> (2,18)
Info: Sink ext_rst_n_LUT4_D.D
Info: Defined in:
Info: hardware/v2/rtl/reset_sync.v:18.17-18.26
Info: logic 0.18 1.40 Source ext_rst_n_LUT4_D.F
Info: routing 3.72 5.12 Net ext_rst_n_LUT4_D_Z (2,18) -> (32,60)
Info: Sink ext_rst_n_LUT4_D_Z_TRELLIS_FF_LSR_DI_TRELLIS_FF_Q.LSR
Info: setup 0.29 5.41 Source ext_rst_n_LUT4_D_Z_TRELLIS_FF_LSR_DI_TRELLIS_FF_Q.LSR
Info: 0.47 ns logic, 4.94 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$sdram_clk$TRELLIS_IO_OUT' -> '<async>':
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source u_spi_bridge.byte_idx_TRELLIS_FF_Q_3.Q
Info: routing 1.38 1.78 Net u_spi_bridge.byte_idx[3] (35,52) -> (36,43)
Info: Sink u_dataflow_core.u_dep_mgr.reg_required_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_Z.C
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 1.96 Source u_dataflow_core.u_dep_mgr.reg_required_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_Z.F
Info: routing 0.64 2.60 Net u_dataflow_core.u_dep_mgr.reg_required_TRELLIS_FF_Q_CE_LUT4_Z_C[3] (36,43) -> (36,43)
Info: Sink u_spi_bridge.soft_rst_pulse_TRELLIS_FF_Q_DI_PFUMX_Z_C0_PFUMX_C0_Z_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 2.78 Source u_spi_bridge.soft_rst_pulse_TRELLIS_FF_Q_DI_PFUMX_Z_C0_PFUMX_C0_Z_LUT4_Z.F
Info: routing 1.53 4.30 Net host_mem_ready_LUT4_B_1_Z_LUT4_C_Z[1] (36,43) -> (27,54)
Info: Sink spi_miso_LUT4_Z_D_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.48 Source spi_miso_LUT4_Z_D_LUT4_Z.F
Info: routing 0.85 5.33 Net spi_miso_LUT4_Z_B[3] (27,54) -> (27,54)
Info: Sink spi_miso_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 5.51 Source spi_miso_LUT4_Z.F
Info: routing 2.08 7.59 Net spi_miso$TRELLIS_IO_OUT (27,54) -> (0,62)
Info: Sink spi_miso$tr_io.I
Info: Defined in:
Info: hardware/v2/nms/rtl/fpga_neural_v2_top.v:55.17-55.25
Info: 1.12 ns logic, 6.48 ns routing
Info: Max frequency for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT': 88.70 MHz (PASS at 64.00 MHz)
Info: Max delay <async> -> posedge $glbnet$sdram_clk$TRELLIS_IO_OUT: 5.41 ns
Info: Max delay posedge $glbnet$sdram_clk$TRELLIS_IO_OUT -> <async> : 7.59 ns
Info: Slack histogram:
Info: legend: * represents 58 endpoint(s)
Info: + represents [1,58) endpoint(s)
Info: [ 4351, 4880) |+
Info: [ 4880, 5409) |*+
Info: [ 5409, 5938) |****+
Info: [ 5938, 6467) |****+
Info: [ 6467, 6996) |****+
Info: [ 6996, 7525) |****+
Info: [ 7525, 8054) |*******+
Info: [ 8054, 8583) |**********+
Info: [ 8583, 9112) |******************+
Info: [ 9112, 9641) |********************+
Info: [ 9641, 10170) |**************************+
Info: [ 10170, 10699) |*****************************************+
Info: [ 10699, 11228) |*******************************************+
Info: [ 11228, 11757) |***************************************+
Info: [ 11757, 12286) |******************************************+
Info: [ 12286, 12815) |*******************************************************+
Info: [ 12815, 13344) |************************************************************
Info: [ 13344, 13873) |******************************************************+
Info: [ 13873, 14402) |*****************************************************+
Info: [ 14402, 14931) |***************************************************+
Info: Program finished normally.
hardware/v2/nms/synthesis/nms_multiproc_n8/nextpnr_seed7.log
+483
View File
@@ -0,0 +1,483 @@
Info: constraining clock net 'osc_clk' to 16.00 MHz
Info: Logic utilisation before packing:
Info: Total LUT4s: 10214/43848 23%
Info: logic LUTs: 5504/43848 12%
Info: carry LUTs: 2772/43848 6%
Info: RAM LUTs: 1292/ 5481 23%
Info: RAMW LUTs: 646/10962 5%
Info: Total DFFs: 11126/43848 25%
Info: Packing IOs..
Info: $sdram_dq[15]$iobuf_i: sdram_dq_$_TBUF__Y.Y
Info: pin 'sdram_dq[15]$tr_io' constrained to Bel 'X0/Y59/PIOB'.
Info: $sdram_dq[14]$iobuf_i: sdram_dq_$_TBUF__Y_15.Y
Info: pin 'sdram_dq[14]$tr_io' constrained to Bel 'X0/Y59/PIOC'.
Info: $sdram_dq[13]$iobuf_i: sdram_dq_$_TBUF__Y_14.Y
Info: pin 'sdram_dq[13]$tr_io' constrained to Bel 'X0/Y59/PIOA'.
Info: $sdram_dq[12]$iobuf_i: sdram_dq_$_TBUF__Y_13.Y
Info: pin 'sdram_dq[12]$tr_io' constrained to Bel 'X0/Y53/PIOA'.
Info: $sdram_dq[11]$iobuf_i: sdram_dq_$_TBUF__Y_12.Y
Info: pin 'sdram_dq[11]$tr_io' constrained to Bel 'X0/Y44/PIOD'.
Info: $sdram_dq[10]$iobuf_i: sdram_dq_$_TBUF__Y_11.Y
Info: pin 'sdram_dq[10]$tr_io' constrained to Bel 'X0/Y44/PIOC'.
Info: $sdram_dq[9]$iobuf_i: sdram_dq_$_TBUF__Y_10.Y
Info: pin 'sdram_dq[9]$tr_io' constrained to Bel 'X0/Y44/PIOA'.
Info: $sdram_dq[8]$iobuf_i: sdram_dq_$_TBUF__Y_9.Y
Info: pin 'sdram_dq[8]$tr_io' constrained to Bel 'X0/Y41/PIOD'.
Info: $sdram_dq[7]$iobuf_i: sdram_dq_$_TBUF__Y_8.Y
Info: pin 'sdram_dq[7]$tr_io' constrained to Bel 'X0/Y41/PIOB'.
Info: $sdram_dq[6]$iobuf_i: sdram_dq_$_TBUF__Y_7.Y
Info: pin 'sdram_dq[6]$tr_io' constrained to Bel 'X0/Y41/PIOC'.
Info: $sdram_dq[5]$iobuf_i: sdram_dq_$_TBUF__Y_6.Y
Info: pin 'sdram_dq[5]$tr_io' constrained to Bel 'X0/Y41/PIOA'.
Info: $sdram_dq[4]$iobuf_i: sdram_dq_$_TBUF__Y_5.Y
Info: pin 'sdram_dq[4]$tr_io' constrained to Bel 'X0/Y38/PIOD'.
Info: $sdram_dq[3]$iobuf_i: sdram_dq_$_TBUF__Y_4.Y
Info: pin 'sdram_dq[3]$tr_io' constrained to Bel 'X0/Y38/PIOB'.
Info: $sdram_dq[2]$iobuf_i: sdram_dq_$_TBUF__Y_3.Y
Info: pin 'sdram_dq[2]$tr_io' constrained to Bel 'X0/Y29/PIOD'.
Info: $sdram_dq[1]$iobuf_i: sdram_dq_$_TBUF__Y_2.Y
Info: pin 'sdram_dq[1]$tr_io' constrained to Bel 'X0/Y29/PIOB'.
Info: $sdram_dq[0]$iobuf_i: sdram_dq_$_TBUF__Y_1.Y
Info: pin 'sdram_dq[0]$tr_io' constrained to Bel 'X0/Y26/PIOD'.
Info: pin 'spi_sclk$tr_io' constrained to Bel 'X0/Y62/PIOC'.
Info: pin 'spi_mosi$tr_io' constrained to Bel 'X0/Y62/PIOB'.
Info: pin 'spi_miso$tr_io' constrained to Bel 'X0/Y62/PIOD'.
Info: pin 'spi_cs_n$tr_io' constrained to Bel 'X0/Y65/PIOA'.
Info: pin 'sdram_we_n$tr_io' constrained to Bel 'X0/Y14/PIOD'.
Info: pin 'sdram_ras_n$tr_io' constrained to Bel 'X0/Y14/PIOA'.
Info: pin 'sdram_dqm[1]$tr_io' constrained to Bel 'X0/Y62/PIOA'.
Info: pin 'sdram_dqm[0]$tr_io' constrained to Bel 'X0/Y59/PIOD'.
Info: pin 'sdram_cs_n$tr_io' constrained to Bel 'X0/Y11/PIOD'.
Info: pin 'sdram_clk$tr_io' constrained to Bel 'X0/Y38/PIOA'.
Info: pin 'sdram_cke$tr_io' constrained to Bel 'X0/Y11/PIOC'.
Info: pin 'sdram_cas_n$tr_io' constrained to Bel 'X0/Y14/PIOC'.
Info: pin 'sdram_ba[1]$tr_io' constrained to Bel 'X0/Y17/PIOC'.
Info: pin 'sdram_ba[0]$tr_io' constrained to Bel 'X0/Y17/PIOA'.
Info: pin 'sdram_a[12]$tr_io' constrained to Bel 'X0/Y35/PIOB'.
Info: pin 'sdram_a[11]$tr_io' constrained to Bel 'X0/Y26/PIOB'.
Info: pin 'sdram_a[10]$tr_io' constrained to Bel 'X0/Y26/PIOC'.
Info: pin 'sdram_a[9]$tr_io' constrained to Bel 'X0/Y26/PIOA'.
Info: pin 'sdram_a[8]$tr_io' constrained to Bel 'X0/Y23/PIOD'.
Info: pin 'sdram_a[7]$tr_io' constrained to Bel 'X0/Y23/PIOB'.
Info: pin 'sdram_a[6]$tr_io' constrained to Bel 'X0/Y23/PIOA'.
Info: pin 'sdram_a[5]$tr_io' constrained to Bel 'X0/Y20/PIOD'.
Info: pin 'sdram_a[4]$tr_io' constrained to Bel 'X0/Y20/PIOB'.
Info: pin 'sdram_a[3]$tr_io' constrained to Bel 'X0/Y20/PIOC'.
Info: pin 'sdram_a[2]$tr_io' constrained to Bel 'X0/Y20/PIOA'.
Info: pin 'sdram_a[1]$tr_io' constrained to Bel 'X0/Y17/PIOD'.
Info: pin 'sdram_a[0]$tr_io' constrained to Bel 'X0/Y17/PIOB'.
Info: pin 'pll_locked$tr_io' constrained to Bel 'X0/Y65/PIOC'.
Info: pin 'osc_clk$tr_io' constrained to Bel 'X0/Y29/PIOC'.
Info: pin 'ext_rst_n$tr_io' constrained to Bel 'X0/Y14/PIOB'.
Info: pin 'data_ready$tr_io' constrained to Bel 'X0/Y32/PIOA'.
Info: placed PLL 'u_pll.pll_i' at bel 'X1/Y4/EHXPLL_UL'
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 3832 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Input frequency of PLL 'u_pll.pll_i' is constrained to 16.0 MHz
Info: Derived frequency constraint of 64.0 MHz for net sdram_clk$TRELLIS_IO_OUT
Info: Promoting globals...
Info: promoting clock net sdram_clk$TRELLIS_IO_OUT to global network
Info: Checksum: 0x94c17baa
Info: Device utilisation:
Info: TRELLIS_IO: 47/ 245 19%
Info: DCCA: 1/ 56 1%
Info: DP16KD: 0/ 108 0%
Info: MULT18X18D: 64/ 72 88%
Info: ALU54B: 0/ 36 0%
Info: EHXPLLL: 1/ 4 25%
Info: EXTREFB: 0/ 2 0%
Info: DCUA: 0/ 2 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 0/ 160 0%
Info: SIOLOGIC: 0/ 85 0%
Info: GSR: 0/ 1 0%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 0/ 1 0%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 11126/ 43848 25%
Info: TRELLIS_COMB: 11032/ 43848 25%
Info: TRELLIS_RAMW: 323/ 5481 5%
Info: Placed 48 cells based on constraints.
Info: Creating initial analytic placement for 12988 cells, random placement wirelen = 1053392.
Info: at initial placer iter 0, wirelen = 5555
Info: at initial placer iter 1, wirelen = 4516
Info: at initial placer iter 2, wirelen = 4429
Info: at initial placer iter 3, wirelen = 4262
Info: Running main analytical placer, max placement attempts per cell = 63811104.
Info: at iteration #1, type ALL: wirelen solved = 4424, spread = 247928, legal = 275928; time = 2.40s
Info: at iteration #2, type ALL: wirelen solved = 24319, spread = 179348, legal = 203024; time = 2.25s
Info: at iteration #3, type ALL: wirelen solved = 35499, spread = 159120, legal = 192044; time = 2.28s
Info: at iteration #4, type ALL: wirelen solved = 40771, spread = 154160, legal = 178925; time = 2.26s
Info: at iteration #5, type ALL: wirelen solved = 44129, spread = 146515, legal = 176181; time = 2.28s
Info: at iteration #6, type ALL: wirelen solved = 45093, spread = 144565, legal = 181883; time = 2.52s
Info: at iteration #7, type ALL: wirelen solved = 45987, spread = 142963, legal = 175882; time = 2.28s
Info: at iteration #8, type ALL: wirelen solved = 47159, spread = 143253, legal = 175754; time = 2.33s
Info: at iteration #9, type ALL: wirelen solved = 48955, spread = 140925, legal = 171037; time = 2.33s
Info: at iteration #10, type ALL: wirelen solved = 49460, spread = 140512, legal = 172723; time = 2.34s
Info: at iteration #11, type ALL: wirelen solved = 50632, spread = 146752, legal = 166175; time = 2.28s
Info: at iteration #12, type ALL: wirelen solved = 54078, spread = 146806, legal = 167521; time = 2.19s
Info: at iteration #13, type ALL: wirelen solved = 55396, spread = 147391, legal = 167355; time = 2.04s
Info: at iteration #14, type ALL: wirelen solved = 55701, spread = 147090, legal = 164998; time = 2.06s
Info: at iteration #15, type ALL: wirelen solved = 56575, spread = 147546, legal = 164133; time = 2.26s
Info: at iteration #16, type ALL: wirelen solved = 57261, spread = 147512, legal = 168258; time = 2.15s
Info: at iteration #17, type ALL: wirelen solved = 59021, spread = 149287, legal = 165627; time = 2.05s
Info: at iteration #18, type ALL: wirelen solved = 59784, spread = 150779, legal = 167575; time = 2.14s
Info: at iteration #19, type ALL: wirelen solved = 61383, spread = 153184, legal = 166316; time = 2.25s
Info: at iteration #20, type ALL: wirelen solved = 62775, spread = 153167, legal = 168696; time = 2.07s
Info: HeAP Placer Time: 50.19s
Info: of which solving equations: 9.63s
Info: of which spreading cells: 1.77s
Info: of which strict legalisation: 34.54s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 2983, wirelen = 164133
Info: at iteration #5: temp = 0.000000, timing cost = 2022, wirelen = 154522
Info: at iteration #10: temp = 0.000000, timing cost = 1986, wirelen = 152061
Info: at iteration #15: temp = 0.000000, timing cost = 1950, wirelen = 151144
Info: at iteration #20: temp = 0.000000, timing cost = 1926, wirelen = 150788
Info: at iteration #25: temp = 0.000000, timing cost = 1916, wirelen = 150606
Info: at iteration #30: temp = 0.000000, timing cost = 1911, wirelen = 150524
Info: at iteration #32: temp = 0.000000, timing cost = 1909, wirelen = 150510
Info: SA placement time 53.43s
Info: Max frequency for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT': 64.82 MHz (PASS at 64.00 MHz)
Info: Max delay <async> -> posedge $glbnet$sdram_clk$TRELLIS_IO_OUT: 6.98 ns
Info: Max delay posedge $glbnet$sdram_clk$TRELLIS_IO_OUT -> <async> : 8.62 ns
Info: Slack histogram:
Info: legend: * represents 68 endpoint(s)
Info: + represents [1,68) endpoint(s)
Info: [ 198, 941) |+
Info: [ 941, 1684) |*+
Info: [ 1684, 2427) |**+
Info: [ 2427, 3170) |*+
Info: [ 3170, 3913) |**+
Info: [ 3913, 4656) |***+
Info: [ 4656, 5399) |*****+
Info: [ 5399, 6142) |*****+
Info: [ 6142, 6885) |*****+
Info: [ 6885, 7628) |***********+
Info: [ 7628, 8371) |********************+
Info: [ 8371, 9114) |****************************+
Info: [ 9114, 9857) |*********************************************+
Info: [ 9857, 10600) |*******************************************+
Info: [ 10600, 11343) |**********************************+
Info: [ 11343, 12086) |************************************************+
Info: [ 12086, 12829) |************************************************************
Info: [ 12829, 13572) |********************************************************+
Info: [ 13572, 14315) |*****************************************+
Info: [ 14315, 15058) |************************************************+
Info: Checksum: 0xd1fabc33
Info: Routing globals...
Info: routing clock net $glbnet$sdram_clk$TRELLIS_IO_OUT using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 60844 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 719 280 | 719 280 | 60748| 1.90 1.90|
Info: 2000 | 1448 551 | 729 271 | 60627| 1.03 2.93|
Info: 3000 | 1957 1042 | 509 491 | 60529| 0.84 3.77|
Info: 4000 | 2653 1346 | 696 304 | 60409| 1.05 4.83|
Info: 5000 | 3304 1695 | 651 349 | 60277| 0.91 5.74|
Info: 6000 | 3913 2086 | 609 391 | 60084| 1.40 7.14|
Info: 7000 | 4476 2523 | 563 437 | 60043| 1.34 8.48|
Info: 8000 | 4866 3133 | 390 610 | 59829| 1.58 10.06|
Info: 9000 | 5364 3635 | 498 502 | 59735| 1.53 11.59|
Info: 10000 | 5843 4156 | 479 521 | 59565| 1.38 12.97|
Info: 11000 | 6231 4768 | 388 612 | 59415| 1.61 14.59|
Info: 12000 | 6692 5307 | 461 539 | 59145| 1.89 16.48|
Info: 13000 | 7085 5914 | 393 607 | 58875| 2.50 18.98|
Info: 14000 | 7407 6592 | 322 678 | 58506| 3.24 22.22|
Info: 15000 | 7666 7333 | 259 741 | 57888| 2.96 25.18|
Info: 16000 | 7826 8173 | 160 840 | 57158| 1.06 26.24|
Info: 17000 | 8001 8998 | 175 825 | 56451| 1.33 27.57|
Info: 18000 | 8140 9859 | 139 861 | 55710| 1.48 29.05|
Info: 19000 | 8324 10675 | 184 816 | 55016| 1.54 30.59|
Info: 20000 | 8536 11463 | 212 788 | 54452| 1.30 31.89|
Info: 21000 | 8655 12344 | 119 881 | 53638| 0.85 32.75|
Info: 22000 | 8837 13162 | 182 818 | 52907| 0.87 33.62|
Info: 23000 | 8914 14085 | 77 923 | 52039| 0.92 34.53|
Info: 24000 | 8984 15015 | 70 930 | 51246| 0.65 35.18|
Info: 25000 | 9089 15910 | 105 895 | 50517| 0.51 35.69|
Info: 26000 | 9148 16851 | 59 941 | 49630| 0.46 36.15|
Info: 27000 | 9225 17774 | 77 923 | 48785| 0.48 36.63|
Info: 28000 | 9357 18642 | 132 868 | 48112| 0.68 37.31|
Info: 29000 | 9433 19566 | 76 924 | 47264| 0.52 37.83|
Info: 30000 | 9524 20475 | 91 909 | 46588| 0.45 38.27|
Info: 31000 | 9626 21373 | 102 898 | 45805| 0.64 38.92|
Info: 32000 | 9716 22283 | 90 910 | 45016| 0.64 39.56|
Info: 33000 | 9806 23193 | 90 910 | 44283| 0.53 40.09|
Info: 34000 | 9941 24058 | 135 865 | 43526| 0.57 40.66|
Info: 35000 | 10065 24934 | 124 876 | 42734| 0.43 41.09|
Info: 36000 | 10146 25853 | 81 919 | 41850| 0.47 41.57|
Info: 37000 | 10271 26728 | 125 875 | 41138| 0.49 42.06|
Info: 38000 | 10444 27555 | 173 827 | 40379| 0.49 42.55|
Info: 39000 | 10608 28391 | 164 836 | 39798| 0.91 43.46|
Info: 40000 | 10777 29222 | 169 831 | 39052| 0.54 44.01|
Info: 41000 | 10883 30116 | 106 894 | 38492| 0.84 44.85|
Info: 42000 | 11081 30918 | 198 802 | 37952| 0.78 45.63|
Info: 43000 | 11239 31760 | 158 842 | 37240| 0.51 46.14|
Info: 44000 | 11401 32595 | 162 835 | 36625| 0.52 46.66|
Info: 45000 | 11561 33435 | 160 840 | 35994| 0.52 47.19|
Info: 46000 | 11778 34218 | 217 783 | 35477| 0.59 47.78|
Info: 47000 | 12020 34976 | 242 758 | 34841| 0.55 48.33|
Info: 48000 | 12171 35825 | 151 849 | 34398| 0.69 49.02|
Info: 49000 | 12365 36631 | 194 806 | 33741| 0.60 49.62|
Info: 50000 | 12509 37483 | 144 852 | 33084| 0.57 50.20|
Info: 51000 | 12724 38251 | 215 768 | 32426| 0.54 50.74|
Info: 52000 | 12950 39010 | 226 759 | 31837| 0.91 51.65|
Info: 53000 | 13161 39785 | 211 775 | 31313| 0.69 52.34|
Info: 54000 | 13402 40531 | 241 746 | 30683| 0.61 52.95|
Info: 55000 | 13616 41307 | 214 776 | 30214| 0.72 53.67|
Info: 56000 | 13811 42103 | 195 796 | 29704| 0.56 54.23|
Info: 57000 | 14015 42871 | 204 768 | 29215| 0.86 55.09|
Info: 58000 | 14267 43596 | 252 725 | 28898| 1.10 56.19|
Info: 59000 | 14457 44333 | 190 737 | 28240| 0.92 57.12|
Info: 60000 | 14686 45094 | 229 761 | 27678| 0.81 57.92|
Info: 61000 | 14937 45812 | 251 718 | 27291| 0.86 58.79|
Info: 62000 | 15168 46556 | 231 744 | 26715| 0.81 59.60|
Info: 63000 | 15395 47289 | 227 733 | 26220| 0.97 60.57|
Info: 64000 | 15580 48065 | 185 776 | 25724| 0.74 61.32|
Info: 65000 | 15732 48850 | 152 785 | 24985| 0.68 62.00|
Info: 66000 | 15947 49582 | 215 732 | 24509| 0.88 62.88|
Info: 67000 | 16182 50293 | 235 711 | 24010| 0.86 63.75|
Info: 68000 | 16352 51047 | 170 754 | 23351| 0.52 64.26|
Info: 69000 | 16526 51785 | 174 738 | 22671| 0.65 64.91|
Info: 70000 | 16643 52599 | 117 814 | 21824| 0.51 65.42|
Info: 71000 | 16846 53373 | 203 774 | 21291| 0.89 66.31|
Info: 72000 | 17099 54105 | 253 732 | 20761| 1.08 67.39|
Info: 73000 | 17287 54882 | 188 777 | 20248| 0.79 68.18|
Info: 74000 | 17553 55607 | 266 725 | 19934| 1.14 69.32|
Info: 75000 | 17759 56374 | 206 767 | 19268| 0.64 69.97|
Info: 76000 | 17953 57174 | 194 800 | 19088| 1.03 70.99|
Info: 77000 | 18189 57929 | 236 755 | 18654| 1.13 72.12|
Info: 78000 | 18408 58699 | 219 770 | 18101| 0.78 72.90|
Info: 79000 | 18622 59426 | 214 727 | 17461| 0.66 73.56|
Info: 80000 | 18797 60199 | 175 773 | 16836| 0.85 74.41|
Info: 81000 | 18979 60994 | 182 795 | 16475| 0.93 75.33|
Info: 82000 | 19231 61715 | 252 721 | 16060| 2.37 77.71|
Info: 83000 | 19401 62510 | 170 795 | 15379| 0.61 78.32|
Info: 84000 | 19575 63311 | 174 801 | 14770| 0.87 79.18|
Info: 85000 | 19714 64113 | 139 802 | 14035| 0.62 79.81|
Info: 86000 | 19913 64850 | 199 737 | 13528| 0.80 80.61|
Info: 87000 | 20215 65524 | 302 674 | 13358| 1.12 81.73|
Info: 88000 | 20514 66204 | 299 680 | 12947| 1.33 83.06|
Info: 89000 | 20848 66870 | 334 666 | 12777| 1.42 84.48|
Info: 90000 | 21094 67605 | 246 735 | 12370| 1.06 85.54|
Info: 91000 | 21320 68308 | 226 703 | 11788| 0.87 86.40|
Info: 92000 | 21449 69106 | 129 798 | 11119| 0.62 87.03|
Info: 93000 | 21612 69861 | 163 755 | 10393| 0.49 87.52|
Info: 94000 | 21900 70530 | 288 669 | 9925| 1.18 88.70|
Info: 95000 | 22234 71183 | 334 653 | 9665| 1.46 90.16|
Info: 96000 | 22609 71808 | 375 625 | 9539| 1.39 91.55|
Info: 97000 | 22976 72441 | 367 633 | 9545| 1.56 93.11|
Info: 98000 | 23307 73110 | 331 669 | 9408| 1.71 94.82|
Info: 99000 | 23597 73802 | 290 692 | 9102| 1.42 96.25|
Info: 100000 | 23740 74633 | 143 831 | 8406| 0.56 96.81|
Info: 101000 | 23944 75415 | 204 782 | 7803| 0.76 97.57|
Info: 102000 | 24227 76126 | 283 711 | 7686| 1.67 99.24|
Info: 103000 | 24597 76756 | 370 630 | 7300| 2.19 101.43|
Info: 104000 | 25003 77350 | 406 594 | 7372| 1.27 102.70|
Info: 105000 | 25360 77993 | 357 643 | 7294| 1.89 104.59|
Info: 106000 | 25714 78639 | 354 646 | 7211| 2.14 106.73|
Info: 107000 | 26138 79215 | 424 576 | 6998| 1.83 108.56|
Info: 108000 | 26537 79816 | 399 601 | 6893| 1.72 110.28|
Info: 109000 | 26889 80464 | 352 648 | 6777| 1.63 111.91|
Info: 110000 | 27249 81104 | 360 640 | 6645| 1.77 113.68|
Info: 111000 | 27434 81909 | 185 805 | 6078| 0.84 114.53|
Info: 112000 | 27698 82645 | 264 736 | 5913| 1.17 115.69|
Info: 113000 | 27874 83469 | 176 824 | 5284| 0.74 116.43|
Info: 114000 | 28254 84089 | 380 620 | 5323| 1.73 118.17|
Info: 115000 | 28644 84699 | 390 610 | 5005| 1.41 119.58|
Info: 116000 | 29081 85262 | 437 563 | 4774| 1.66 121.25|
Info: 117000 | 29477 85866 | 396 604 | 4738| 1.42 122.66|
Info: 118000 | 29808 86535 | 331 669 | 4813| 1.43 124.10|
Info: 119000 | 30169 87174 | 361 639 | 4616| 1.62 125.71|
Info: 120000 | 30602 87741 | 433 567 | 4506| 1.85 127.56|
Info: 121000 | 31070 88273 | 468 532 | 4338| 1.96 129.52|
Info: 122000 | 31567 88776 | 497 503 | 4260| 1.75 131.27|
Info: 123000 | 31939 89404 | 372 628 | 3940| 1.82 133.09|
Info: 124000 | 32256 90087 | 317 683 | 3678| 1.21 134.31|
Info: 125000 | 32533 90810 | 277 723 | 3159| 0.91 135.22|
Info: 126000 | 32860 91473 | 327 663 | 2952| 1.59 136.81|
Info: 127000 | 33118 92130 | 258 657 | 2468| 1.57 138.38|
Info: 128000 | 33320 92823 | 202 693 | 1915| 0.88 139.26|
Info: 129000 | 33564 93491 | 244 668 | 1483| 1.41 140.67|
Info: 130000 | 33883 94139 | 319 648 | 1296| 2.60 143.27|
Info: 131000 | 34150 94809 | 267 670 | 921| 1.45 144.72|
Info: 132000 | 34415 95485 | 265 676 | 635| 1.30 146.02|
Info: 133000 | 34656 96165 | 241 680 | 127| 1.15 147.17|
Info: 133280 | 34709 96371 | 53 206 | 0| 0.39 147.56|
Info: Routing complete.
Info: Router1 time 147.56s
Info: Checksum: 0xfb5f883d
Info: Critical path report for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT' (posedge -> posedge):
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source u_dataflow_core.GEN_SLOT[4].u_mm.act_resident_tag_TRELLIS_FF_Q_7.Q
Info: routing 1.28 1.67 Net u_dataflow_core.GEN_SLOT[0].u_mm.buf_valid_LUT4_C_Z_LUT4_D_Z_PFUMX_BLUT_Z_LUT4_Z_D_LUT4_Z_1_D_LUT4_Z_3_D[1] (36,35) -> (35,40)
Info: Sink u_dataflow_core.GEN_SLOT[7].u_mm.buf_valid_LUT4_C_Z_LUT4_D_Z_PFUMX_BLUT_Z_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 1.85 Source u_dataflow_core.GEN_SLOT[7].u_mm.buf_valid_LUT4_C_Z_LUT4_D_Z_PFUMX_BLUT_Z_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z.F
Info: routing 0.45 2.30 Net u_dataflow_core.GEN_SLOT[7].u_mm.buf_valid_LUT4_C_Z_LUT4_D_Z_PFUMX_BLUT_Z_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D[2] (35,40) -> (35,40)
Info: Sink u_dataflow_core.GEN_SLOT[7].u_mm.buf_valid_LUT4_C_Z_LUT4_D_Z_PFUMX_BLUT_Z_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 2.48 Source u_dataflow_core.GEN_SLOT[7].u_mm.buf_valid_LUT4_C_Z_LUT4_D_Z_PFUMX_BLUT_Z_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z.F
Info: routing 0.86 3.34 Net u_dataflow_core.GEN_SLOT[7].u_mm.buf_valid_LUT4_C_Z_LUT4_D_Z_PFUMX_BLUT_Z_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D[3] (35,40) -> (34,38)
Info: Sink u_dataflow_core.GEN_SLOT[7].u_mm.buf_valid_LUT4_C_Z_LUT4_D_Z_PFUMX_BLUT_Z_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 3.52 Source u_dataflow_core.GEN_SLOT[7].u_mm.buf_valid_LUT4_C_Z_LUT4_D_Z_PFUMX_BLUT_Z_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D_LUT4_Z.F
Info: routing 0.45 3.98 Net u_dataflow_core.GEN_SLOT[7].u_mm.buf_valid_LUT4_C_Z_LUT4_D_Z_PFUMX_BLUT_Z_LUT4_Z_D_LUT4_Z_D_LUT4_Z_D[3] (34,38) -> (34,38)
Info: Sink u_dataflow_core.GEN_SLOT[7].u_mm.buf_valid_LUT4_C_Z_LUT4_D_Z_PFUMX_BLUT_Z_LUT4_Z_D_LUT4_Z_D_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.16 Source u_dataflow_core.GEN_SLOT[7].u_mm.buf_valid_LUT4_C_Z_LUT4_D_Z_PFUMX_BLUT_Z_LUT4_Z_D_LUT4_Z_D_LUT4_Z.F
Info: routing 0.67 4.83 Net u_dataflow_core.GEN_SLOT[7].u_mm.buf_valid_LUT4_C_Z_LUT4_D_Z_PFUMX_BLUT_Z_LUT4_Z_D_LUT4_Z_D[3] (34,38) -> (34,38)
Info: Sink u_dataflow_core.GEN_SLOT[7].u_mm.buf_valid_LUT4_C_Z_LUT4_D_Z_PFUMX_BLUT_Z_LUT4_Z_D_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 5.01 Source u_dataflow_core.GEN_SLOT[7].u_mm.buf_valid_LUT4_C_Z_LUT4_D_Z_PFUMX_BLUT_Z_LUT4_Z_D_LUT4_Z.F
Info: routing 0.99 5.99 Net u_dataflow_core.GEN_SLOT[7].u_mm.buf_valid_LUT4_C_Z_LUT4_D_Z_PFUMX_BLUT_Z_LUT4_Z_D[3] (34,38) -> (32,33)
Info: Sink u_dataflow_core.GEN_SLOT[7].u_mm.buf_valid_LUT4_C_Z_LUT4_D_Z_PFUMX_BLUT_Z_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 6.17 Source u_dataflow_core.GEN_SLOT[7].u_mm.buf_valid_LUT4_C_Z_LUT4_D_Z_PFUMX_BLUT_Z_LUT4_Z.F
Info: routing 1.43 7.60 Net u_dataflow_core.GEN_SLOT[7].u_mm.buf_valid_LUT4_C_Z_LUT4_D_Z_PFUMX_BLUT_Z[2] (32,33) -> (32,24)
Info: Sink u_dataflow_core.GEN_SLOT[7].u_mm.buf_valid_LUT4_C_Z_LUT4_D_Z_PFUMX_BLUT_Z_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 7.78 Source u_dataflow_core.GEN_SLOT[7].u_mm.buf_valid_LUT4_C_Z_LUT4_D_Z_PFUMX_BLUT_Z_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_Z.F
Info: routing 1.01 8.79 Net u_dataflow_core.GEN_SLOT[7].u_mm.buf_valid_LUT4_C_Z_LUT4_D_Z_PFUMX_BLUT_Z_CCU2C_COUT_CIN_CCU2C_COUT_B1 (32,24) -> (29,24)
Info: Sink u_dataflow_core.GEN_SLOT[7].u_mm.buf_valid_LUT4_C_Z_LUT4_D_Z_PFUMX_BLUT_Z_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.B
Info: logic 0.35 9.15 Source u_dataflow_core.GEN_SLOT[7].u_mm.buf_valid_LUT4_C_Z_LUT4_D_Z_PFUMX_BLUT_Z_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 9.15 Net u_dataflow_core.GEN_SLOT[7].u_mm.buf_valid_LUT4_C_Z_LUT4_D_Z_PFUMX_BLUT_Z_CCU2C_COUT_CIN (29,24) -> (29,24)
Info: Sink u_dataflow_core.GEN_SLOT[7].u_mm.buf_valid_LUT4_C_Z_LUT4_D_Z_PFUMX_BLUT_Z_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:173.26-173.45
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 9.20 Source u_dataflow_core.GEN_SLOT[7].u_mm.buf_valid_LUT4_C_Z_LUT4_D_Z_PFUMX_BLUT_Z_CCU2C_COUT$CCU2_COMB0.FCO
Info: routing 0.00 9.20 Net u_dataflow_core.GEN_SLOT[7].u_mm.buf_valid_LUT4_C_Z_LUT4_D_Z_PFUMX_BLUT_Z_CCU2C_COUT$CCU2_FCI_INT (29,24) -> (29,24)
Info: Sink u_dataflow_core.GEN_SLOT[7].u_mm.buf_valid_LUT4_C_Z_LUT4_D_Z_PFUMX_BLUT_Z_CCU2C_COUT$CCU2_COMB1.FCI
Info: logic 0.00 9.20 Source u_dataflow_core.GEN_SLOT[7].u_mm.buf_valid_LUT4_C_Z_LUT4_D_Z_PFUMX_BLUT_Z_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 9.20 Net $nextpnr_CCU2C_101$CIN (29,24) -> (29,24)
Info: Sink $nextpnr_CCU2C_101$CCU2_COMB0.FCI
Info: logic 0.33 9.53 Source $nextpnr_CCU2C_101$CCU2_COMB0.F
Info: routing 0.72 10.25 Net u_dataflow_core.GEN_SLOT[7].u_mm.buf_valid_LUT4_C_Z[4] (29,24) -> (28,23)
Info: Sink u_dataflow_core.GEN_SLOT[7].u_mm.buf_valid_LUT4_C_Z_LUT4_D.M
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.19 10.45 Source u_dataflow_core.GEN_SLOT[7].u_mm.buf_valid_LUT4_C_Z_LUT4_D.OFX
Info: routing 0.47 10.91 Net u_dataflow_core.GEN_SLOT[7].u_mm.buf_valid_LUT4_C_Z_LUT4_D_Z_PFUMX_BLUT_Z[4] (28,23) -> (28,24)
Info: Sink u_dataflow_core.GEN_SLOT[7].u_mm.rd_pending_TRELLIS_FF_Q_DI_PFUMX_Z_BLUT_LUT4_Z.M
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.19 11.11 Source u_dataflow_core.GEN_SLOT[7].u_mm.rd_pending_TRELLIS_FF_Q_DI_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: routing 0.57 11.67 Net u_dataflow_core.GEN_SLOT[7].u_mm.rd_pending_TRELLIS_FF_Q_DI[1] (28,24) -> (28,20)
Info: Sink u_dataflow_core.GEN_SLOT[7].u_mm.rd_pending_TRELLIS_FF_Q_DI_LUT4_D.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 11.85 Source u_dataflow_core.GEN_SLOT[7].u_mm.rd_pending_TRELLIS_FF_Q_DI_LUT4_D.F
Info: routing 0.50 12.35 Net u_dataflow_core.GEN_SLOT[7].u_mm.rd_pending_TRELLIS_FF_Q_DI_LUT4_D_Z (28,20) -> (26,20)
Info: Sink u_dataflow_core.u_act_mem.rd_addr_flat_TRELLIS_FF_Q_19.CE
Info: setup 0.00 12.35 Source u_dataflow_core.u_act_mem.rd_addr_flat_TRELLIS_FF_Q_19.CE
Info: 2.96 ns logic, 9.39 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$sdram_clk$TRELLIS_IO_OUT':
Info: type curr total name
Info: source 0.00 0.00 Source ext_rst_n$tr_io.O
Info: routing 1.35 1.35 Net ext_rst_n$TRELLIS_IO_IN (0,14) -> (2,18)
Info: Sink ext_rst_n_LUT4_D.D
Info: Defined in:
Info: hardware/v2/rtl/reset_sync.v:18.17-18.26
Info: logic 0.18 1.52 Source ext_rst_n_LUT4_D.F
Info: routing 4.15 5.68 Net ext_rst_n_LUT4_D_Z (2,18) -> (31,60)
Info: Sink ext_rst_n_LUT4_D_Z_TRELLIS_FF_LSR_DI_TRELLIS_FF_Q.LSR
Info: setup 0.29 5.96 Source ext_rst_n_LUT4_D_Z_TRELLIS_FF_LSR_DI_TRELLIS_FF_Q.LSR
Info: 0.47 ns logic, 5.49 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$sdram_clk$TRELLIS_IO_OUT' -> '<async>':
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source u_spi_bridge.byte_idx_TRELLIS_FF_Q_2.Q
Info: routing 1.42 1.82 Net u_spi_bridge.byte_idx[2] (32,52) -> (33,41)
Info: Sink u_dataflow_core.u_dep_mgr.reg_required_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 2.00 Source u_dataflow_core.u_dep_mgr.reg_required_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_Z.F
Info: routing 0.50 2.50 Net u_dataflow_core.u_dep_mgr.reg_required_TRELLIS_FF_Q_CE_LUT4_Z_C[3] (33,41) -> (33,41)
Info: Sink u_spi_bridge.soft_rst_pulse_TRELLIS_FF_Q_DI_PFUMX_Z_C0_PFUMX_C0_Z_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 2.68 Source u_spi_bridge.soft_rst_pulse_TRELLIS_FF_Q_DI_PFUMX_Z_C0_PFUMX_C0_Z_LUT4_Z.F
Info: routing 1.25 3.93 Net host_mem_ready_LUT4_B_1_Z_LUT4_C_Z[1] (33,41) -> (27,54)
Info: Sink spi_miso_LUT4_Z_D_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.11 Source spi_miso_LUT4_Z_D_LUT4_Z.F
Info: routing 0.81 4.92 Net spi_miso_LUT4_Z_B[3] (27,54) -> (28,56)
Info: Sink spi_miso_LUT4_Z.D
Info: Defined in:
Info: /root/tools_cache/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 5.10 Source spi_miso_LUT4_Z.F
Info: routing 2.16 7.26 Net spi_miso$TRELLIS_IO_OUT (28,56) -> (0,62)
Info: Sink spi_miso$tr_io.I
Info: Defined in:
Info: hardware/v2/nms/rtl/fpga_neural_v2_top.v:55.17-55.25
Info: 1.12 ns logic, 6.14 ns routing
Info: Max frequency for clock '$glbnet$sdram_clk$TRELLIS_IO_OUT': 80.97 MHz (PASS at 64.00 MHz)
Info: Max delay <async> -> posedge $glbnet$sdram_clk$TRELLIS_IO_OUT: 5.96 ns
Info: Max delay posedge $glbnet$sdram_clk$TRELLIS_IO_OUT -> <async> : 7.26 ns
Info: Slack histogram:
Info: legend: * represents 76 endpoint(s)
Info: + represents [1,76) endpoint(s)
Info: [ 3275, 3858) |+
Info: [ 3858, 4441) |+
Info: [ 4441, 5024) |+
Info: [ 5024, 5607) |***+
Info: [ 5607, 6190) |*****+
Info: [ 6190, 6773) |****+
Info: [ 6773, 7356) |***+
Info: [ 7356, 7939) |****+
Info: [ 7939, 8522) |*******+
Info: [ 8522, 9105) |************+
Info: [ 9105, 9688) |****************+
Info: [ 9688, 10271) |*************************+
Info: [ 10271, 10854) |********************************+
Info: [ 10854, 11437) |**************************************+
Info: [ 11437, 12020) |******************************+
Info: [ 12020, 12603) |***********************************+
Info: [ 12603, 13186) |************************************************************
Info: [ 13186, 13769) |*************************************************+
Info: [ 13769, 14352) |************************************************+
Info: [ 14352, 14935) |****************************************+
Info: Program finished normally.
hardware/v2/nms/synthesis/nms_multiproc_n8/top.config
+337719
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hardware/v2/nms/synthesis/nms_multiproc_n8/top.json
+687435
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hardware/v2/nms/synthesis/nms_multiproc_n8/yosys.log
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