docs: real P&R signoff for the result-writeback engine (EXP-0088)

Real in-context P&R confirms the result-writeback engine (EXP-0088)
closes timing with essentially zero cost: WNS=+0.099962ns (vs
EXP-0086's +0.095707ns), WHS=+0.036275ns, 0 failing endpoints. 6642
LUTs (+260 for the new engine), 16 DSP48E1 unchanged. This is now the
current, trustworthy signoff, promoted over EXP-0086/0087's own
pointers in both docs.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC

docs/ARCHITECTURE_ANALYSIS.md

@@ -1,10 +1,11 @@
 # FPGA-Neural V3 — Architecture Analysis: Timing, Bottlenecks, and Recommended Interventions
 
 Scope: the current, real, P&R-verified V3 design (`hardware/v3/`, branch
-`v3-artix7`), updated through EXP-0086 (32-bit DDR3 widening, functionally
-complete AND real timing CLOSED). The current real, trustworthy *timing*
-signoff is now EXP-0086 (32-bit, 155.039MHz, WNS +0.096ns), replacing the
-prior EXP-0083 16-bit-era pointer. Every number in this document is either
+`v3-artix7`), updated through EXP-0088 (result-writeback engine, real,
+closed timing). The current real, trustworthy *timing* signoff is now
+EXP-0088 (32-bit, 155.039MHz, WNS +0.100ns), replacing EXP-0086's own
+pointer (which itself replaced EXP-0083's 16-bit-era one). Every number
+in this document is either
 directly measured (real simulation trace, real P&R report) or a calculation
 built from directly-measured building blocks — the two are labeled
 explicitly throughout. Nothing here is guessed.
@@ -81,7 +82,8 @@ absorbed the gap the look-ahead used to hide.
 | 0082 | + denser activation packing (2 tiles/burst, EXP-0081) | +0.068 | 5437 | 16 | pre-DDRManager baseline |
 | 0083 | + DDRManager phase 1 (`ddr_prefetch_mgr.v`, single-slot look-ahead prefetch) | +0.073 | 5644 | 16 | 16-bit/155.039MHz — superseded by EXP-0086 below |
 | 0084 | 32-bit DDR3 widening (2 chips) + clock speedup to 172.414MHz | -0.618 (FAILED) | 6418 | 16 | functionally verified (real xsim), real timing NOT closed — root cause is the clock speedup, not the width; see §5.4.1. |
-| 0086 | 32-bit DDR3 widening, clock period reverted to 3225ps/155.039MHz | **+0.096 (CLOSED)** | 6382 | 16 | **current, trustworthy signoff** — real, closed timing, full 2× real bandwidth (§5.4.1). Also uncovered and fixed a real recurrence of the stale-import bug (whole-tree, triggered by MIG regeneration) — see CLAUDE.md. |
+| 0086 | 32-bit DDR3 widening, clock period reverted to 3225ps/155.039MHz | +0.096 (CLOSED) | 6382 | 16 | real, closed timing, full 2× real bandwidth (§5.4.1). Also uncovered and fixed a real recurrence of the stale-import bug (whole-tree, triggered by MIG regeneration) — see CLAUDE.md. Superseded by 0088 below. |
+| 0088 | + result-writeback engine (`result_writeback.v`, removes the last hard N-scaling pin blocker, §4.6/§5.3) | **+0.100 (CLOSED)** | 6642 | 16 | **current, trustworthy signoff** — essentially unchanged margin, zero real timing cost for closing the pin-scaling blocker. |
 
 **Observation**: WNS does not move monotonically with LUT count (0.056 →
 0.013 → 0.030 → 0.068 → 0.073 while LUTs only ever grow) — this is normal P&R behavior
@@ -495,7 +497,15 @@ against `burst_mem_model32.v`. Also re-verified at the full N=2 system
 level (`tb_n2_system_ddr3.v`, real xsim against the real, closed
 32-bit/3225ps DDR3 model) to confirm the writeback engine behaves
 correctly under real shared-bus arbitration contention between 2 slots
-— see `hardware/v2/logs/experiments.log` EXP-0088 for the real result.
+— **8/8 PASS, 0 errors**.
+
+**Real P&R signoff**: **WNS = +0.099962ns, WHS = +0.036275ns**, 0
+failing endpoints, "All user specified timing constraints are met" —
+essentially unchanged from EXP-0086's own +0.095707ns (real, closed,
+not a regression). 6642 LUTs (+260 vs EXP-0086, expected), 16 DSP48E1
+(unchanged). This is now the current, trustworthy P&R signoff,
+superseding EXP-0086/0087. See `hardware/v2/logs/experiments.log`
+EXP-0088 for the full real result.
 
 ### 5.4 [DONE] Widening the physical DDR3 channel: 32-bit single channel vs. a second independent 16-bit channel — **functionally complete AND real timing closed (EXP-0084 → EXP-0086)**
 

docs/PHYSICAL_REALIZATION.md

@@ -165,7 +165,7 @@ these from an ESP32 doing real JTAG bit-banging (TAP state machine, IR/DR
 shifting) rather than a bench programmer — that firmware is separate,
 software-side work, not covered here.
 
-## 3. Real timing signoff (EXP-0086, the current, trustworthy number — real 32-bit DDR3 channel, CLOSED)
+## 3. Real timing signoff (EXP-0088, the current, trustworthy number — real 32-bit DDR3 channel + result-writeback engine, CLOSED)
 
 Real in-context Vivado place-and-route (not out-of-context, not estimated):
 
@@ -173,16 +173,16 @@ Real in-context Vivado place-and-route (not out-of-context, not estimated):
 |---|---|
 | DDR3 PHY clock (sys_clk_p/n) | **310.078 MHz** (3.225ns period) |
 | Compute domain clock (ui_clk/clk_pll_i, PLL-derived 2:1 from sys_clk) | **155.039 MHz** |
-| WNS (setup slack) | **+0.095707 ns** — real, closed. Re-verify with a fresh P&R after ANY further logic addition. |
+| WNS (setup slack) | **+0.099962 ns** — real, closed. Re-verify with a fresh P&R after ANY further logic addition. |
 | WHS (hold slack) | +0.036275 ns |
-| Failing endpoints | 0 of 25172 (setup), 0 of 25169 (hold), 0 of 9505 (pulse width) |
-| LUTs used | 6382 / 63400 (10.07%) |
+| Failing endpoints | 0 of 27868 (setup), 0 of 27865 (hold), 0 of 10529 (pulse width) |
+| LUTs used | 6642 / 63400 (10.48%) |
 | DSP48E1 used | 16 / 240 (6.67%) — 8 per compute core × 2 cores, unchanged since EXP-0059 |
-| Bonded IOB used | 119 / 207 (57.49%) |
 | Block RAM used | 0 |
 | STARTUPE2 used | 1 / 1 (100%) — the config-flash bridge |
 | DDR3 channel width | **32-bit real physical channel** (two MT41J128M16JT-125:K chips) — see §3.1 |
 | Real physical bandwidth ceiling | **~2.48 GB/s** (2× EXP-0083's 16-bit ~1.24 GB/s, real, closed timing — not a projection) |
+| Result writeback | **real, into DDR3** (EXP-0088, `result_writeback.v`) — no longer literal top-level pins, see §4.6/§5.3 of `docs/ARCHITECTURE_ANALYSIS.md` |
 
 Signoff history (every real change, same target, in-context P&R):
 
@@ -195,7 +195,8 @@ Signoff history (every real change, same target, in-context P&R):
 | 0082 (+denser activation packing) | +0.068 | 5437 | 16 |
 | 0083 (+DDRManager phase 1, `ddr_prefetch_mgr.v`, 16-bit) | +0.073 | 5644 | 16 |
 | 0084 (32-bit DDR3 widening, 2900ps/172.414MHz) | -0.618 (FAILED) | 6418 | 16 |
-| 0086 (32-bit DDR3 widening, clock reverted to 3225ps/155.039MHz) | **+0.096 (CLOSED)** | 6382 | 16 |
+| 0086 (32-bit DDR3 widening, clock reverted to 3225ps/155.039MHz) | +0.096 (CLOSED) | 6382 | 16 |
+| 0088 (+result-writeback engine, `result_writeback.v`) | **+0.100 (CLOSED)** | 6642 | 16 |
 
 ### 3.1 Real 32-bit DDR3 widening — functionally verified AND timing CLOSED (EXP-0084 → EXP-0086)
 

hardware/v2/logs/experiments.log

@@ -5918,3 +5918,33 @@ disturb the closed EXP-0086 timing), then real N=2/4/8/16 core-count
 scaling tests (each with its own real P&R signoff, per the user's own
 standing directive), then the 4x4 hybrid systolic architecture
 (docs/ARCHITECTURE_ANALYSIS.md S5.6, currently exploratory/not built).
+
+EXP-0088 (continued) -- real P&R signoff for the result-writeback
+engine: CLOSED, no regression
+
+Real, in-context P&R (synth_design + opt_design + place_design +
+route_design, xc7a100tcsg324-2, EXP-0088's real committed RTL/XDC):
+**WNS = +0.099962ns, WHS = +0.036275ns**, 0 failing endpoints out of
+27868 (setup) / 27865 (hold) / 10529 (pulse width). "All user specified
+timing constraints are met." Real utilization: 6642 LUTs (vs EXP-0086's
+6382, +260, expected for the new result_writeback.v logic added to
+both slots), 16 DSP48E1 (unchanged, writeback adds no DSP usage).
+Essentially unchanged margin from EXP-0086's own +0.095707ns (tiny
++0.004ns difference, normal P&R placement-seed variance, not a real
+effect of this change) -- the real, hard N-scaling pin blocker is now
+closed with ZERO real timing cost.
+
+DECISION: confirmed keep. This is now the real, current, trustworthy
+P&R signoff, superseding EXP-0086/0087's own (which didn't yet include
+result_writeback.v).
+
+next_action: real N=2/4/8/16 core-count scaling tests (each with its
+own real P&R signoff) OR the 4x4 hybrid systolic architecture
+(docs/ARCHITECTURE_ANALYSIS.md S5.6) -- per the user's own explicit
+reprioritization (2026-09-20), the systolic architecture is next,
+scoped to a first, isolated, standalone-verified deliverable
+(systolic_group.v: one group of 4 weight-sharing PEs, broadcast
+design confirmed by the user -- NOT a literal PE-to-PE systolic shift
+register -- verified in isolation before any Director/SPI-protocol
+integration, matching this project's own "one variable at a time"
+discipline).