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n16-timing-closure

v21

v22

v3-artix7

v22-final

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• 3cdaeaee35 test(v2): final benchmark campaign - real end-to-end characterization (EXP-0014) micheleandClaude Sonnet 5 2026-09-05 19:58:30 +02:00
• 91bbbe2fe5 feat(v2): M10 Optimization - data-driven findings, completes the V2 roadmap micheleandClaude Sonnet 5 2026-09-05 18:58:10 +02:00
• 84794a3d25 docs(v2): M9 full benchmark - V1 vs V2 comparison table (§32) micheleandClaude Sonnet 5 2026-09-05 15:17:14 +02:00
• 6cff2c8a7c feat(v2): M8 PSRAM integration - real V1 backend shared across concurrent slots micheleandClaude Sonnet 5 2026-09-05 15:13:11 +02:00
• 77baa8fc16 feat(v2): M7 Dataflow Core - full M1-M6 integration, wake-up loop closed end-to-end micheleandClaude Sonnet 5 2026-09-05 15:05:28 +02:00
• 8af16d3a12 feat(v2): M6 Dependency Manager, multi-dependency wake-up micheleandClaude Sonnet 5 2026-09-05 14:51:02 +02:00
• 2e4cedc761 feat(v2): M5 Neural Director, first-free job scheduling micheleandClaude Sonnet 5 2026-09-05 14:46:32 +02:00
• 175f697ae1 feat(v2): M4 Memory Manager + Prefetch Engine, real V1 PSRAM backend micheleandClaude Sonnet 5 2026-09-05 14:39:29 +02:00
• 5f0d7f101c feat(v2): M3 activation/weight/result buffers, real BRAM mapping micheleandClaude Sonnet 5 2026-09-05 14:19:11 +02:00
• 3026dcd997 feat(v2): M2 Neural Processor Array, N_PROCESSORS resource sweep micheleandClaude Sonnet 5 2026-09-05 14:15:11 +02:00
• dc0b331d3e feat(v2): scaffold hardware/v1 frozen baseline + M1 Neural Processor micheleandClaude Sonnet 5 2026-09-05 14:06:53 +02:00
• 07a48e401f fix: close 7 zero-value/mid-run guard gaps found in re-certification campaign micheleandClaude Sonnet 5 2026-09-04 20:29:05 +02:00
• 77e74db637 docs: final certification verdict for the re-certification campaign micheleandClaude Sonnet 5 2026-09-04 19:59:58 +02:00
• 8d20a7bfbf docs: certify C.9-C.14 + cross-cutting analyses D micheleandClaude Sonnet 5 2026-09-04 18:53:58 +02:00
• f0a66363de test: certify spi_neuron_top mux/pins (C.8), find critical BUG-007 micheleandClaude Sonnet 5 2026-09-04 18:50:06 +02:00
• 95849c9002 docs: certify SPI slave/engine (C.7), confirm len=0 is properly guarded micheleandClaude Sonnet 5 2026-09-04 14:54:56 +02:00
• 6db44efcfd test: certify graph_engine gather/guard (C.6), find related BUG-006 micheleandClaude Sonnet 5 2026-09-04 14:52:52 +02:00
• f81d7fa1b3 test: certify layer_sequencer chain (C.5), find critical BUG-005 micheleandClaude Sonnet 5 2026-09-04 14:47:41 +02:00
• b528901510 test: certify mem_arbiter priority order (C.4) micheleandClaude Sonnet 5 2026-09-04 14:41:44 +02:00
• 3dd75e9e0d test: certify memory subsystem addressing (C.3) micheleandClaude Sonnet 5 2026-09-04 14:33:05 +02:00
• 14c8d87194 test: certify runtime width early-termination (C.2), document BUG-003/004 micheleandClaude Sonnet 5 2026-09-04 14:27:14 +02:00
• 20b0b1f4c0 test: certify mac_unit/mac8 datapath (C.1), confirm real N_INPUTS=0 guard gap micheleandClaude Sonnet 5 2026-09-04 13:42:57 +02:00
• 313a1994a4 docs: certification campaign Phase 0 -- real inventory, new regression harness micheleandClaude Sonnet 5 2026-09-04 13:26:11 +02:00
• b029e3d95a fix: make flash SPI bus electrically independent, drop USRMCLK/CCLK reuse (Phase F7) micheleandClaude Sonnet 5 2026-09-04 10:16:31 +02:00
• 97a21be240 feat: flash boot/persistence subsystem (SPI master, copy engine, CRC32 slot catalog) micheleandClaude Sonnet 5 2026-09-04 08:37:19 +02:00
• 55c827bedf feat: PSRAM page-mode reads + graph engine (Type #2) + real pinout/IRQ pins micheleandClaude Sonnet 5 2026-09-03 17:12:05 +02:00
• 7e2711fa27 feat: widen ADDR_WIDTH to 23 bits for full 8MB PSRAM addressing micheleandClaude Sonnet 5 2026-09-02 21:00:46 +02:00
• f6edc01613 docs: Phase 7 placement-seed sweep + hardware design document micheleandClaude Sonnet 5 2026-09-02 20:54:52 +02:00
• a918c3f1e9 feat: configurable activation functions + runtime-configurable network topology micheleandClaude Sonnet 5 2026-09-02 20:18:24 +02:00
• 1ddaa9adfd feat: real-toolchain Fmax check for Phase 5 spi_neuron_top michele 2026-09-02 20:17:52 +02:00
• cfd5e98a0e feat: add FPGA-Neural benchmark tooling + same-tier ECP5 P2/P4/P8 results michele 2026-09-02 19:48:03 +02:00
• 233d6ff7fb feat: complete Phase 5 multi-layer network (RUN_NETWORK) + fix STATUS race michele 2026-09-02 19:47:36 +02:00
• a2bd60e305 feat: complete Phase 4 SPI RTL (engine, arbiter, top) + real-RAM e2e test micheleandClaude Sonnet 5 2026-09-02 15:44:03 +02:00
• d716eb04dd feat: add spi_slave.v physical layer (Phase 4 SPI RTL, part 1/N) micheleandClaude Sonnet 5 2026-09-02 15:24:17 +02:00
• 87efce3d9b docs: draft SPI protocol v1 for Phase 4 (opcodes, register map) micheleandClaude Sonnet 5 2026-09-02 15:04:37 +02:00
• 661363f637 feat: extend neuron_memory to support N_NEURONS>1 (Phase 3) micheleandClaude Sonnet 5 2026-09-02 14:50:45 +02:00
• 1a6f0ba2ef fix: guard neuron_parallel against invalid N_INPUTS/PARALLEL combos micheleandClaude Sonnet 5 2026-09-02 14:41:49 +02:00
• 9b9859a104 test: add Phase 2 parameter sweep for neuron_parallel, update roadmap micheleandClaude Sonnet 5 2026-09-02 14:24:43 +02:00
• 4b5cd4e558 fix: rewrite layer_tb and neuron_parallel_tb for current INT8 architecture micheleandClaude Sonnet 5 2026-09-02 14:16:34 +02:00
• 896f56c675 fix: correct byte/word address conversion in neuron_memory_tb preload tasks micheleandClaude Sonnet 5 2026-09-02 14:08:13 +02:00
• 16769eaa4b working with memory michele 2026-09-02 13:09:20 +02:00
• d4ae2417a4 test: validate parametric 32x4 layer with parallelism 8 michele 2026-09-02 09:27:04 +02:00