feat: widen ADDR_WIDTH to 23 bits for full 8MB PSRAM addressing

Bumps ADDR_WIDTH's default from 22 to 23 bits across every RTL
module (neuron_memory, layer_sequencer, spi_engine, spi_neuron_top,
mem_arbiter, int8_memory_access, memory_interface, psram_controller,
memory_model) and every testbench that mirrors it, so the system's
byte-address space reaches the full 8 MiB the recommended PSRAM part
(ISSI IS66WVE4M16EBLL-70BLI, docs/FPGA-Neural-Hardware-Design.md §3)
actually provides -- previously only 4 MiB (half the chip) was
reachable, since int8_memory_access.v's byte->word address shift
(addr >> 1) turned the old 22-bit byte address into only 21 real word
bits, one short of the chip's real 22-bit word address (A0-A21). At
23 bits, that same shift lands exactly on all 22 chip address lines,
so the whole part is usable now instead of deferred to a future
widening.

Also fixes a stray 22'd11-sized literal in layer_sequencer.v's
descriptor-table address increment (numerically already safe via
Verilog's zero-extension, but now correctly unsized so it always
matches ADDR_WIDTH instead of silently assuming 22).

Updated docs/FPGA-NeuralNetwork-Engine.md's SPI protocol address-field
note (23 bits, top 1 reserved bit instead of 2) and
docs/FPGA-Neural-Hardware-Design.md's PSRAM section (the "chip has
one spare address line" framing is gone now that all 22 are wired
and used).

Full regression (all 11 ADDR_WIDTH-touching testbenches, plus a
Yosys elaboration check of spi_neuron_top with the new default and
no override) passes clean.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01WQV3vS9TXaGDJ5cRfnfidt

docs/FPGA-Neural-Hardware-Design.md

@@ -89,15 +89,17 @@ not** plug into this controller without a rewrite.
   RTL change needed.
 - TSOP-44/48 package — hand-solderable-adjacent, real distributor
   listings (DigiKey, Mouser) at time of writing.
-- **Address bus note:** the chip is 4M×16 words (8 MB total,
-  needs a real 22-bit word address, A0–A21). The current RTL's
-  `ADDR_WIDTH=22` is a **byte** address (4 MiB space) that
-  `int8_memory_access.v` right-shifts by 1 (`addr >> 1`) into a word
-  address before it reaches `psram_controller` — so only **21**
-  word-address bits are actually driven today. Wire all 22 chip
-  address balls, but the chip's topmost line (A21) stays unused/tied
-  low until `ADDR_WIDTH` is widened to 23 to use the chip's full
-  8 MB instead of today's 4 MiB. Free headroom, not a defect.
+- **Address bus (2026-09-02: full addressing, all 22 chip lines
+  wired):** the chip is 4M×16 words (8 MB total), needing a
+  real 22-bit word address, A0–A21. `ADDR_WIDTH` is now **23**
+  bits across every module (`rtl/neuron_memory.v`,
+  `rtl/psram_controller.v`, etc. — bumped from the earlier 22-bit/
+  4 MiB default specifically to reach the full chip).
+  `int8_memory_access.v` right-shifts the 23-bit **byte** address by
+  1 (`addr >> 1`) into a 22-bit **word** address before it reaches
+  `psram_controller` — that 22-bit word address maps exactly onto
+  the chip's real A0–A21, with nothing left unconnected. Full
+  8 MB is addressable today, not deferred.
 
 **Fallback: ISSI IS61WV6416DBLL / IS61WV102416BLL** (true async
 SRAM, not pseudo-SRAM) — electrically drop-in on the same
@@ -214,7 +216,7 @@ Before schematic capture, someone needs to:
 
 | Signal group | Port(s) | Count | Target bank (TBD) |
 |---|---|---|---|
-| PSRAM address | `psram_a[21:0]` | 22 | one bank |
+| PSRAM address | `psram_a[21:0]` (port is `[22:0]`, bit 22 always 0 post-shift — see §3) | 22 | one bank |
 | PSRAM data | `psram_dq[15:0]` | 16 | same or adjacent bank |
 | PSRAM control | `psram_ce_n/oe_n/we_n/lb_n/ub_n/zz_n` | 6 | same bank as above |
 | Application SPI | `sclk/mosi/miso/cs_n` | 4 | any bank, NOT the config-SPI bank (§6) |
@@ -244,9 +246,12 @@ sizes are decided.
 
 ## 9. Open items before schematic capture
 
-- [ ] Decide real PSRAM density needed (drives whether `ADDR_WIDTH`
-      stays 22 or can shrink, and whether the fallback true-SRAM
-      part in §3 is sufficient instead of the pseudo-SRAM)
+- [x] `ADDR_WIDTH` set to 23 (full 8 MB) across all RTL modules
+      and testbenches, matching the recommended part's real capacity
+      (2026-09-02) — see §3.
+- [ ] If the fallback true-SRAM part in §3 is used instead (smaller
+      density), decide whether to shrink `ADDR_WIDTH` back down to
+      match it or keep 23 with the extra range simply unused.
 - [ ] Real `.lpf` pin assignment (§7) and a synthesis run against it
       (current benchmark results all use auto-placed I/O)
 - [ ] Confirm PSRAM/SPI signal integrity at whatever clock is

docs/FPGA-NeuralNetwork-Engine.md

@@ -400,9 +400,10 @@ here). The FPGA is always SPI slave. One command per CS-low period;
 byte 0 of every transaction is the opcode.
 
 **Multi-byte fields** are big-endian (most significant byte first).
-Byte addresses are `ADDR_WIDTH`-bit (22 bits today, from
-`rtl/neuron_memory.v`), carried in a 3-byte field with the top 2 bits
-reserved as 0.
+Byte addresses are `ADDR_WIDTH`-bit (23 bits today, from
+`rtl/neuron_memory.v` — sized for a full 8 MiB PSRAM, see
+`docs/FPGA-Neural-Hardware-Design.md` §3), carried in a 3-byte field
+with the top bit reserved as 0.
 
 **Length is explicit**, not CS-edge-delimited: `WRITE_RAM`/`READ_RAM`
 carry a 2-byte length field, so the SPI controller only needs a byte

rtl/int8_memory_access.v

@@ -1,5 +1,5 @@
 module int8_memory_access #(
-    parameter ADDR_WIDTH = 22
+    parameter ADDR_WIDTH = 23
 )(
     input  wire                  clk,
     input  wire                  rst,

rtl/layer_sequencer.v

@@ -45,7 +45,7 @@
 // ================================================================
 
 module layer_sequencer #(
-    parameter ADDR_WIDTH = 22,
+    parameter ADDR_WIDTH = 23,
     parameter DATA_WIDTH = 8,
     parameter N_WIDTH    = 256,   // = neuron_memory's N_INPUTS = N_NEURONS
     parameter N_LAYERS   = 4
@@ -314,7 +314,7 @@ module layer_sequencer #(
                                 cur_sel         <= write_sel;
                                 write_sel       <= ~write_sel;
                                 layer_idx       <= layer_idx + 8'd1;
-                                desc_table_addr <= desc_table_addr + 22'd11;
+                                desc_table_addr <= desc_table_addr + 11;
                                 desc_byte_idx   <= 4'd0;
 
                                 state <= ST_READ_DESC;

rtl/mem_arbiter.v

@@ -29,7 +29,7 @@
 // ================================================================
 
 module mem_arbiter #(
-    parameter ADDR_WIDTH = 22
+    parameter ADDR_WIDTH = 23
 )(
     input wire clk,
     input wire rst,

rtl/memory_interface.v

@@ -1,5 +1,5 @@
 module memory_interface #(
-    parameter ADDR_WIDTH = 22,
+    parameter ADDR_WIDTH = 23,
     parameter DATA_WIDTH = 16
 )(
     input  wire                   clk,

rtl/memory_model.v

@@ -1,5 +1,5 @@
 module memory_model #(
-    parameter ADDR_WIDTH   = 22,
+    parameter ADDR_WIDTH   = 23,
     parameter DATA_WIDTH   = 16,
     parameter DEPTH        = 4096,
     parameter READ_LATENCY = 2

rtl/neuron_memory.v

@@ -1,7 +1,7 @@
 `timescale 1ns/1ps
 
 module neuron_memory #(
-    parameter ADDR_WIDTH = 22,
+    parameter ADDR_WIDTH = 23,
     parameter DATA_WIDTH = 8,
     parameter N_INPUTS   = 32,
     parameter N_NEURONS  = 1,

rtl/psram_controller.v

@@ -1,5 +1,5 @@
 module psram_controller #(
-    parameter ADDR_WIDTH   = 22,
+    parameter ADDR_WIDTH   = 23,
     parameter DATA_WIDTH   = 16,
     parameter CLK_FREQ_MHZ = 80
 )(

rtl/spi_engine.v

@@ -32,7 +32,7 @@
 // ================================================================
 
 module spi_engine #(
-    parameter ADDR_WIDTH = 22,
+    parameter ADDR_WIDTH = 23,
     parameter DATA_WIDTH = 8,
     parameter N_INPUTS   = 32,
     parameter N_NEURONS  = 1,

rtl/spi_neuron_top.v

@@ -17,7 +17,7 @@
 // ================================================================
 
 module spi_neuron_top #(
-    parameter ADDR_WIDTH     = 22,
+    parameter ADDR_WIDTH     = 23,
     parameter DATA_WIDTH     = 8,
     parameter N_INPUTS       = 32,
     parameter N_NEURONS      = 1,

sim/int8_memory_access.vcd

@@ -1,5 +1,5 @@
 $date
-	Wed Sep  2 12:39:25 2026
+	Wed Sep  2 20:58:26 2026
 $end
 $version
 	Icarus Verilog
@@ -17,10 +17,10 @@ $var wire 16 & mem_wdata [15:0] $end
 $var wire 1 ' mem_ub_n $end
 $var wire 1 ( mem_req $end
 $var wire 1 ) mem_lb_n $end
-$var wire 22 * mem_addr [21:0] $end
+$var wire 23 * mem_addr [22:0] $end
 $var parameter 32 + ADDR_WIDTH $end
 $var real 1 , CLK_PERIOD $end
-$var reg 22 - addr [21:0] $end
+$var reg 23 - addr [22:0] $end
 $var reg 1 . clk $end
 $var reg 16 / model_rdata [15:0] $end
 $var reg 1 0 model_ready $end
@@ -30,7 +30,7 @@ $var reg 8 3 wdata [7:0] $end
 $var reg 1 4 wr $end
 $var integer 32 5 i [31:0] $end
 $scope module dut $end
-$var wire 22 6 addr [21:0] $end
+$var wire 23 6 addr [22:0] $end
 $var wire 1 . clk $end
 $var wire 16 7 mem_rdata [15:0] $end
 $var wire 1 " mem_ready $end
@@ -41,8 +41,8 @@ $var wire 1 4 wr $end
 $var parameter 32 9 ADDR_WIDTH $end
 $var parameter 2 : STATE_IDLE $end
 $var parameter 2 ; STATE_WAIT $end
-$var reg 22 < addr_reg [21:0] $end
-$var reg 22 = mem_addr [21:0] $end
+$var reg 23 < addr_reg [22:0] $end
+$var reg 23 = mem_addr [22:0] $end
 $var reg 1 ) mem_lb_n $end
 $var reg 1 ( mem_req $end
 $var reg 1 ' mem_ub_n $end
@@ -53,11 +53,11 @@ $var reg 1 # ready $end
 $var reg 2 @ state [1:0] $end
 $upscope $end
 $scope task read_byte $end
-$var reg 22 A byte_addr [21:0] $end
+$var reg 23 A byte_addr [22:0] $end
 $var reg 8 B expected [7:0] $end
 $upscope $end
 $scope task write_byte $end
-$var reg 22 C byte_addr [21:0] $end
+$var reg 23 C byte_addr [22:0] $end
 $var reg 8 D data [7:0] $end
 $upscope $end
 $upscope $end
@@ -66,9 +66,9 @@ $comment Show the parameter values. $end
 $dumpall
 b1 ;
 b0 :
-b10110 9
+b10111 9
 r12.5 ,
-b10110 +
+b10111 +
 $end
 #0
 $dumpvars

sim/int8_memory_access_tb.v

@@ -2,7 +2,7 @@
 
 module tb;
 
-    localparam ADDR_WIDTH = 22;
+    localparam ADDR_WIDTH = 23;
     localparam CLK_PERIOD = 12.5;
 
     reg clk;

sim/int8_psram_integration.vcd

@@ -1,5 +1,5 @@
 $date
-	Wed Sep  2 12:45:33 2026
+	Wed Sep  2 20:58:55 2026
 $end
 $version
 	Icarus Verilog
@@ -22,10 +22,10 @@ $var wire 1 + psram_mem_req $end
 $var wire 1 , psram_mem_ready $end
 $var wire 16 - psram_mem_rdata [15:0] $end
 $var wire 1 . psram_mem_lb_n $end
-$var wire 22 / psram_mem_addr [21:0] $end
+$var wire 23 / psram_mem_addr [22:0] $end
 $var wire 1 0 psram_lb_n $end
 $var wire 1 1 psram_ce_n $end
-$var wire 22 2 psram_a [21:0] $end
+$var wire 23 2 psram_a [22:0] $end
 $var wire 1 3 mem_wr $end
 $var wire 16 4 mem_wdata [15:0] $end
 $var wire 1 5 mem_ub_n $end
@@ -33,11 +33,11 @@ $var wire 1 6 mem_req $end
 $var wire 1 7 mem_ready $end
 $var wire 16 8 mem_rdata [15:0] $end
 $var wire 1 9 mem_lb_n $end
-$var wire 22 : mem_addr [21:0] $end
+$var wire 23 : mem_addr [22:0] $end
 $var parameter 32 ; ADDR_WIDTH $end
 $var real 1 < CLK_PERIOD $end
 $var parameter 32 = DATA_WIDTH $end
-$var reg 22 > addr [21:0] $end
+$var reg 23 > addr [22:0] $end
 $var reg 1 ? clk $end
 $var reg 1 @ req $end
 $var reg 1 A rst $end
@@ -47,7 +47,7 @@ $var reg 1 D wr $end
 $var integer 32 E i [31:0] $end
 $var integer 32 F test_addr [31:0] $end
 $scope module int8_access $end
-$var wire 22 G addr [21:0] $end
+$var wire 23 G addr [22:0] $end
 $var wire 1 ? clk $end
 $var wire 1 @ req $end
 $var wire 1 A rst $end
@@ -58,8 +58,8 @@ $var wire 16 I mem_rdata [15:0] $end
 $var parameter 32 J ADDR_WIDTH $end
 $var parameter 2 K STATE_IDLE $end
 $var parameter 2 L STATE_WAIT $end
-$var reg 22 M addr_reg [21:0] $end
-$var reg 22 N mem_addr [21:0] $end
+$var reg 23 M addr_reg [22:0] $end
+$var reg 23 N mem_addr [22:0] $end
 $var reg 1 9 mem_lb_n $end
 $var reg 1 6 mem_req $end
 $var reg 1 5 mem_ub_n $end
@@ -70,7 +70,7 @@ $var reg 1 " ready $end
 $var reg 2 Q state [1:0] $end
 $upscope $end
 $scope module memory_if $end
-$var wire 22 R addr [21:0] $end
+$var wire 23 R addr [22:0] $end
 $var wire 1 ? clk $end
 $var wire 1 9 lb_n $end
 $var wire 1 6 req $end
@@ -84,7 +84,7 @@ $var parameter 32 U ADDR_WIDTH $end
 $var parameter 32 V DATA_WIDTH $end
 $var parameter 2 W STATE_IDLE $end
 $var parameter 2 X STATE_WAIT $end
-$var reg 22 Y mem_addr [21:0] $end
+$var reg 23 Y mem_addr [22:0] $end
 $var reg 1 . mem_lb_n $end
 $var reg 1 + mem_req $end
 $var reg 1 * mem_ub_n $end
@@ -103,7 +103,7 @@ $var wire 1 & ub_n $end
 $var wire 1 ' oe_n $end
 $var wire 1 0 lb_n $end
 $var wire 1 1 ce_n $end
-$var wire 22 ^ a [21:0] $end
+$var wire 23 ^ a [22:0] $end
 $var parameter 32 _ ADDR_WIDTH $end
 $var parameter 32 ` DATA_WIDTH $end
 $var parameter 32 a DEPTH $end
@@ -122,7 +122,7 @@ $var real 1 m TWC_NS $end
 $var real 1 n TWPH_NS $end
 $var real 1 o TWP_NS $end
 $var real 1 p TWR_NS $end
-$var reg 22 q active_addr [21:0] $end
+$var reg 23 q active_addr [22:0] $end
 $var reg 16 r active_wdata [15:0] $end
 $var reg 1 s dq_oe $end
 $var reg 16 t dq_out [15:0] $end
@@ -140,17 +140,17 @@ $var real 1 !" oe_low_time $end
 $var real 1 "" powerup_time $end
 $var real 1 #" we_high_time $end
 $var real 1 $" we_low_time $end
-$scope begin $unm_blk_59 $end
+$scope begin $unm_blk_23 $end
 $var real 1 %" access_time $end
 $upscope $end
-$scope begin $unm_blk_71 $end
+$scope begin $unm_blk_35 $end
 $var real 1 &" data_setup $end
 $var real 1 '" write_width $end
 $upscope $end
 $upscope $end
 $scope module psram_ctrl $end
 $var wire 1 ? clk $end
-$var wire 22 (" mem_addr [21:0] $end
+$var wire 23 (" mem_addr [22:0] $end
 $var wire 1 . mem_lb_n $end
 $var wire 1 + mem_req $end
 $var wire 1 * mem_ub_n $end
@@ -169,14 +169,14 @@ $var parameter 3 2" STATE_INIT $end
 $var parameter 3 3" STATE_READ $end
 $var parameter 3 4" STATE_WRITE $end
 $var parameter 3 5" STATE_WRITE_WAIT $end
-$var reg 22 6" address_reg [21:0] $end
+$var reg 23 6" address_reg [22:0] $end
 $var reg 14 7" counter [13:0] $end
 $var reg 1 8" dq_oe $end
 $var reg 16 9" dq_out [15:0] $end
 $var reg 1 :" lb_reg $end
 $var reg 16 ;" mem_rdata [15:0] $end
 $var reg 1 , mem_ready $end
-$var reg 22 <" psram_a [21:0] $end
+$var reg 23 <" psram_a [22:0] $end
 $var reg 1 1 psram_ce_n $end
 $var reg 1 0 psram_lb_n $end
 $var reg 1 ' psram_oe_n $end
@@ -189,11 +189,11 @@ $var reg 16 ?" wdata_reg [15:0] $end
 $var reg 1 @" wr_reg $end
 $upscope $end
 $scope task read_byte $end
-$var reg 22 A" byte_addr [21:0] $end
+$var reg 23 A" byte_addr [22:0] $end
 $var reg 8 B" expected [7:0] $end
 $upscope $end
 $scope task write_byte $end
-$var reg 22 C" byte_addr [21:0] $end
+$var reg 23 C" byte_addr [22:0] $end
 $var reg 8 D" data [7:0] $end
 $upscope $end
 $upscope $end
@@ -209,7 +209,7 @@ b10111011100000 0"
 b10000 /"
 b1110 ."
 b1010000 -"
-b10110 ,"
+b10111 ,"
 b110 +"
 r0 p
 r46 o
@@ -228,17 +228,17 @@ r70 c
 r70 b
 b100000000000000 a
 b10000 `
-b10110 _
+b10111 _
 b1 X
 b0 W
 b10000 V
-b10110 U
+b10111 U
 b1 L
 b0 K
-b10110 J
+b10111 J
 b10000 =
 r12.5 <
-b10110 ;
+b10111 ;
 $end
 #0
 $dumpvars

sim/int8_psram_integration_tb.v

@@ -2,7 +2,7 @@
 
 module tb;
 
-    localparam ADDR_WIDTH = 22;
+    localparam ADDR_WIDTH = 23;
     localparam DATA_WIDTH = 16;
     localparam CLK_PERIOD = 12.5; // 80 MHz
 

sim/layer.vcd

@@ -1,5 +1,5 @@
 $date
-	Wed Sep  2 20:14:10 2026
+	Wed Sep  2 20:58:26 2026
 $end
 $version
 	Icarus Verilog

sim/layer_sequencer.vcd

@@ -1,5 +1,5 @@
 $date
-	Wed Sep  2 20:13:54 2026
+	Wed Sep  2 20:58:00 2026
 $end
 $version
 	Icarus Verilog
@@ -13,35 +13,35 @@ $var wire 1 " seq_busy $end
 $var wire 1 # ram_wr $end
 $var wire 8 $ ram_wdata [7:0] $end
 $var wire 1 % ram_req $end
-$var wire 22 & ram_addr [21:0] $end
-$var wire 22 ' nm_x_base [21:0] $end
-$var wire 22 ( nm_w_base [21:0] $end
+$var wire 23 & ram_addr [22:0] $end
+$var wire 23 ' nm_x_base [22:0] $end
+$var wire 23 ( nm_w_base [22:0] $end
 $var wire 1 ) nm_start $end
 $var wire 16 * nm_n_neurons [15:0] $end
 $var wire 16 + nm_n_inputs [15:0] $end
-$var wire 22 , nm_bias_addr [21:0] $end
+$var wire 23 , nm_bias_addr [22:0] $end
 $var wire 2 - nm_activation [1:0] $end
 $var parameter 32 . ADDR_WIDTH $end
-$var parameter 22 / BUF_A_BASE $end
-$var parameter 22 0 BUF_B_BASE $end
+$var parameter 23 / BUF_A_BASE $end
+$var parameter 23 0 BUF_B_BASE $end
 $var real 1 1 CLK_PERIOD $end
 $var parameter 32 2 DATA_WIDTH $end
-$var parameter 22 3 L0_BIAS_ADDR $end
-$var parameter 22 4 L0_W_BASE $end
-$var parameter 22 5 L1_BIAS_ADDR $end
-$var parameter 22 6 L1_W_BASE $end
+$var parameter 23 3 L0_BIAS_ADDR $end
+$var parameter 23 4 L0_W_BASE $end
+$var parameter 23 5 L1_BIAS_ADDR $end
+$var parameter 23 6 L1_W_BASE $end
 $var parameter 32 7 N_LAYERS $end
 $var parameter 32 8 N_WIDTH $end
 $var parameter 1 9 RAM_IDLE $end
 $var parameter 1 : RAM_WAIT $end
-$var parameter 22 ; TABLE_BASE $end
-$var parameter 22 < X_BASE $end
-$var reg 22 = buf_a_base [21:0] $end
-$var reg 22 > buf_b_base [21:0] $end
+$var parameter 23 ; TABLE_BASE $end
+$var parameter 23 < X_BASE $end
+$var reg 23 = buf_a_base [22:0] $end
+$var reg 23 > buf_b_base [22:0] $end
 $var reg 1 ? clk $end
 $var reg 1 @ nm_busy $end
 $var reg 1 A nm_done $end
-$var reg 22 B ram_addr_latched [21:0] $end
+$var reg 23 B ram_addr_latched [22:0] $end
 $var reg 8 C ram_rdata [7:0] $end
 $var reg 1 D ram_ready $end
 $var reg 1 E ram_state $end
@@ -52,8 +52,8 @@ $var reg 8 I run_num_layers [7:0] $end
 $var reg 1 J run_start $end
 $var reg 1 K seq_busy_dropped_early $end
 $var reg 32 L staged_y [31:0] $end
-$var reg 22 M table_base [21:0] $end
-$var reg 22 N x_base [21:0] $end
+$var reg 23 M table_base [22:0] $end
+$var reg 23 N x_base [22:0] $end
 $var reg 32 O y_bus [31:0] $end
 $var integer 32 P errors [31:0] $end
 $var integer 32 Q errors_before [31:0] $end
@@ -61,8 +61,8 @@ $var integer 32 R i [31:0] $end
 $var integer 32 S nm_delay [31:0] $end
 $var integer 32 T seq_done_count [31:0] $end
 $scope module u_dut $end
-$var wire 22 U buf_a_base [21:0] $end
-$var wire 22 V buf_b_base [21:0] $end
+$var wire 23 U buf_a_base [22:0] $end
+$var wire 23 V buf_b_base [22:0] $end
 $var wire 1 ? clk $end
 $var wire 1 @ nm_busy $end
 $var wire 1 A nm_done $end
@@ -71,8 +71,8 @@ $var wire 1 D ram_ready $end
 $var wire 1 H rst $end
 $var wire 8 X run_num_layers [7:0] $end
 $var wire 1 J run_start $end
-$var wire 22 Y table_base [21:0] $end
-$var wire 22 Z x_base [21:0] $end
+$var wire 23 Y table_base [22:0] $end
+$var wire 23 Z x_base [22:0] $end
 $var wire 32 [ y_bus [31:0] $end
 $var parameter 32 \ ADDR_WIDTH $end
 $var parameter 32 ] DATA_WIDTH $end
@@ -90,19 +90,19 @@ $var reg 24 h bias_addr_acc [23:0] $end
 $var reg 3 i copy_idx [2:0] $end
 $var reg 1 j cur_sel $end
 $var reg 4 k desc_byte_idx [3:0] $end
-$var reg 22 l desc_table_addr [21:0] $end
+$var reg 23 l desc_table_addr [22:0] $end
 $var reg 8 m layer_idx [7:0] $end
 $var reg 16 n n_inputs_acc [15:0] $end
 $var reg 16 o n_neurons_acc [15:0] $end
 $var reg 2 p nm_activation [1:0] $end
-$var reg 22 q nm_bias_addr [21:0] $end
+$var reg 23 q nm_bias_addr [22:0] $end
 $var reg 16 r nm_n_inputs [15:0] $end
 $var reg 16 s nm_n_neurons [15:0] $end
 $var reg 1 ) nm_start $end
-$var reg 22 t nm_w_base [21:0] $end
-$var reg 22 u nm_x_base [21:0] $end
+$var reg 23 t nm_w_base [22:0] $end
+$var reg 23 u nm_x_base [22:0] $end
 $var reg 8 v num_layers_reg [7:0] $end
-$var reg 22 w ram_addr [21:0] $end
+$var reg 23 w ram_addr [22:0] $end
 $var reg 1 % ram_req $end
 $var reg 8 x ram_wdata [7:0] $end
 $var reg 1 # ram_wr $end
@@ -136,7 +136,7 @@ b101 `
 b100 _
 b100 ^
 b1000 ]
-b10110 \
+b10111 \
 b10000 <
 b100000000 ;
 1:
@@ -151,7 +151,7 @@ b1000 2
 r12.5 1
 b1100000000 0
 b1000000000 /
-b10110 .
+b10111 .
 $end
 #0
 $dumpvars
@@ -345,15 +345,15 @@ b10 |
 #168750
 0E
 1D
-bx000000 C
-bx000000 W
+bx0000000 C
+bx0000000 W
 1?
 #175000
 0?
 #181250
 b1 y
 b1 k
-bx0000000000000000000000 z
+bx00000000000000000000000 z
 0D
 1?
 #187500
@@ -384,7 +384,7 @@ b10000 W
 #231250
 b1 y
 b10 k
-bx0000000001000000000000 z
+bx00000000001000000000000 z
 0D
 1?
 #237500
@@ -437,15 +437,15 @@ b100000011 B
 #318750
 0E
 1D
-bx000000 C
-bx000000 W
+bx0000000 C
+bx0000000 W
 1?
 #325000
 0?
 #331250
 b1 y
 b100 k
-bx0000000000000000000000 h
+bx00000000000000000000000 h
 0D
 1?
 #337500
@@ -476,7 +476,7 @@ b100000 W
 #381250
 b1 y
 b101 k
-bx0000000010000000000000 h
+bx00000000010000000000000 h
 0D
 1?
 #387500
@@ -799,8 +799,8 @@ b100001011 B
 #906250
 0E
 1D
-bx000000 C
-bx000000 W
+bx0000000 C
+bx0000000 W
 1?
 #912500
 0?
@@ -838,7 +838,7 @@ b110000 W
 0D
 b1 y
 b10 k
-bx0000000011000000000000 z
+bx00000000011000000000000 z
 1?
 #975000
 0?
@@ -890,8 +890,8 @@ b100001110 B
 #1056250
 0E
 1D
-bx000000 C
-bx000000 W
+bx0000000 C
+bx0000000 W
 1?
 #1062500
 0?
@@ -929,7 +929,7 @@ b1000000 W
 0D
 b1 y
 b101 k
-bx0000000100000000000000 h
+bx00000000100000000000000 h
 1?
 #1125000
 0?
@@ -1372,8 +1372,8 @@ b11 X
 #1818750
 0E
 1D
-bx000000 C
-bx000000 W
+bx0000000 C
+bx0000000 W
 1?
 #1825000
 0J
@@ -1411,7 +1411,7 @@ b10000 W
 #1881250
 b1 y
 b10 k
-bx0000000001000000000000 z
+bx00000000001000000000000 z
 0D
 1?
 #1887500
@@ -1464,8 +1464,8 @@ b100000011 B
 #1968750
 0E
 1D
-bx000000 C
-bx000000 W
+bx0000000 C
+bx0000000 W
 1?
 #1975000
 0?
@@ -1502,7 +1502,7 @@ b100000 W
 #2031250
 b1 y
 b101 k
-bx0000000010000000000000 h
+bx00000000010000000000000 h
 0D
 1?
 #2037500

sim/layer_sequencer_tb.v

@@ -25,7 +25,7 @@
 
 module tb;
 
-    localparam ADDR_WIDTH = 22;
+    localparam ADDR_WIDTH = 23;
     localparam DATA_WIDTH = 8;
     localparam N_WIDTH    = 4;
     localparam N_LAYERS   = 4;

sim/memory_interface_tb.v

@@ -2,7 +2,7 @@
 
 module memory_interface_tb;
 
-    parameter ADDR_WIDTH = 22;
+    parameter ADDR_WIDTH = 23;
     parameter DATA_WIDTH = 16;
 
     reg clk;

sim/neuron_memory.vcd

@@ -1,5 +1,5 @@
 $date
-	Wed Sep  2 20:14:05 2026
+	Wed Sep  2 20:58:09 2026
 $end
 $version
 	Icarus Verilog
@@ -21,12 +21,12 @@ $var wire 1 * psram_mem_ready $end
 $var wire 16 + psram_mem_rdata [15:0] $end
 $var wire 1 , psram_lb_n $end
 $var wire 1 - psram_ce_n $end
-$var wire 22 . psram_a [21:0] $end
+$var wire 23 . psram_a [22:0] $end
 $var wire 1 / neuron_mem_wr $end
 $var wire 8 0 neuron_mem_wdata [7:0] $end
 $var wire 1 1 neuron_mem_req $end
 $var wire 8 2 neuron_mem_rdata [7:0] $end
-$var wire 22 3 neuron_mem_addr [21:0] $end
+$var wire 23 3 neuron_mem_addr [22:0] $end
 $var wire 1 4 memory_ready $end
 $var wire 16 5 memory_rdata [15:0] $end
 $var wire 1 6 memory_mem_wr $end
@@ -34,38 +34,38 @@ $var wire 16 7 memory_mem_wdata [15:0] $end
 $var wire 1 8 memory_mem_ub_n $end
 $var wire 1 9 memory_mem_req $end
 $var wire 1 : memory_mem_lb_n $end
-$var wire 22 ; memory_mem_addr [21:0] $end
+$var wire 23 ; memory_mem_addr [22:0] $end
 $var wire 1 < master_wr $end
 $var wire 16 = master_wdata [15:0] $end
 $var wire 1 > master_ub_n $end
 $var wire 1 ? master_req $end
 $var wire 1 @ master_lb_n $end
-$var wire 22 A master_addr [21:0] $end
+$var wire 23 A master_addr [22:0] $end
 $var wire 1 B done $end
 $var wire 1 C busy $end
 $var parameter 32 D ADDR_WIDTH $end
 $var real 1 E CLK_PERIOD $end
 $var parameter 32 F DATA_WIDTH $end
-$var reg 22 G bias_addr [21:0] $end
+$var reg 23 G bias_addr [22:0] $end
 $var reg 1 H clk $end
 $var reg 16 I n_inputs_real [15:0] $end
 $var reg 1 J rst $end
 $var reg 1 K start $end
-$var reg 22 L tb_mem_addr [21:0] $end
+$var reg 23 L tb_mem_addr [22:0] $end
 $var reg 1 M tb_mem_lb_n $end
 $var reg 1 N tb_mem_req $end
 $var reg 1 O tb_mem_ub_n $end
 $var reg 16 P tb_mem_wdata [15:0] $end
 $var reg 1 Q tb_mem_wr $end
 $var reg 1 R use_neuron_master $end
-$var reg 22 S w_base [21:0] $end
-$var reg 22 T x_base [21:0] $end
+$var reg 23 S w_base [22:0] $end
+$var reg 23 T x_base [22:0] $end
 $var integer 32 U cycles_full_nm [31:0] $end
 $var integer 32 V cycles_reduced_nm [31:0] $end
 $var integer 32 W t_done_nm [31:0] $end
 $var integer 32 X t_start_nm [31:0] $end
 $scope module u_memory_if $end
-$var wire 22 Y addr [21:0] $end
+$var wire 23 Y addr [22:0] $end
 $var wire 1 H clk $end
 $var wire 1 @ lb_n $end
 $var wire 1 ? req $end
@@ -79,7 +79,7 @@ $var parameter 32 \ ADDR_WIDTH $end
 $var parameter 32 ] DATA_WIDTH $end
 $var parameter 2 ^ STATE_IDLE $end
 $var parameter 2 _ STATE_WAIT $end
-$var reg 22 ` mem_addr [21:0] $end
+$var reg 23 ` mem_addr [22:0] $end
 $var reg 1 : mem_lb_n $end
 $var reg 1 9 mem_req $end
 $var reg 1 8 mem_ub_n $end
@@ -91,9 +91,9 @@ $var reg 2 c state [1:0] $end
 $upscope $end
 $scope module u_neuron $end
 $var wire 2 d activation [1:0] $end
-$var wire 22 e bias_addr [21:0] $end
+$var wire 23 e bias_addr [22:0] $end
 $var wire 1 H clk $end
-$var wire 22 f mem_addr [21:0] $end
+$var wire 23 f mem_addr [22:0] $end
 $var wire 8 g mem_rdata [7:0] $end
 $var wire 1 ! mem_ready $end
 $var wire 1 1 mem_req $end
@@ -103,8 +103,8 @@ $var wire 16 i n_inputs_real [15:0] $end
 $var wire 16 j n_neurons_real [15:0] $end
 $var wire 1 J rst $end
 $var wire 1 K start $end
-$var wire 22 k w_base [21:0] $end
-$var wire 22 l x_base [21:0] $end
+$var wire 23 k w_base [22:0] $end
+$var wire 23 l x_base [22:0] $end
 $var wire 8 m y_bus [7:0] $end
 $var wire 256 n x_bus [255:0] $end
 $var wire 256 o w_bus [255:0] $end
@@ -119,7 +119,7 @@ $var wire 1 w access_mem_ub_n $end
 $var wire 1 x access_mem_req $end
 $var wire 16 y access_mem_rdata [15:0] $end
 $var wire 1 z access_mem_lb_n $end
-$var wire 22 { access_mem_addr [21:0] $end
+$var wire 23 { access_mem_addr [22:0] $end
 $var parameter 32 | ACC_WIDTH $end
 $var parameter 32 } ADDR_WIDTH $end
 $var parameter 32 ~ DATA_WIDTH $end
@@ -133,11 +133,11 @@ $var parameter 4 '" STATE_READ_W $end
 $var parameter 4 (" STATE_READ_X $end
 $var parameter 4 )" STATE_START_N $end
 $var parameter 4 *" STATE_WAIT_N $end
-$var reg 22 +" access_addr [21:0] $end
+$var reg 23 +" access_addr [22:0] $end
 $var reg 1 ," access_req $end
 $var reg 8 -" access_wdata [7:0] $end
 $var reg 1 ." access_wr $end
-$var reg 22 /" bias_group_addr [21:0] $end
+$var reg 23 /" bias_group_addr [22:0] $end
 $var reg 8 0" bias_reg [7:0] $end
 $var reg 1 C busy $end
 $var reg 1 B done $end
@@ -145,7 +145,7 @@ $var reg 6 1" index [5:0] $end
 $var reg 1 2" neuron_index $end
 $var reg 1 3" neuron_start $end
 $var reg 4 4" state [3:0] $end
-$var reg 22 5" w_group_base [21:0] $end
+$var reg 23 5" w_group_base [22:0] $end
 $var integer 32 6" rst_i [31:0] $end
 $scope begin GEN_BUS[0] $end
 $var parameter 2 7" i $end
@@ -247,7 +247,7 @@ $scope begin GEN_Y_BUS[0] $end
 $var parameter 2 W" j $end
 $upscope $end
 $scope module u_mem $end
-$var wire 22 X" addr [21:0] $end
+$var wire 23 X" addr [22:0] $end
 $var wire 1 H clk $end
 $var wire 16 Y" mem_rdata [15:0] $end
 $var wire 1 ! mem_ready $end
@@ -258,8 +258,8 @@ $var wire 1 ." wr $end
 $var parameter 32 [" ADDR_WIDTH $end
 $var parameter 2 \" STATE_IDLE $end
 $var parameter 2 ]" STATE_WAIT $end
-$var reg 22 ^" addr_reg [21:0] $end
-$var reg 22 _" mem_addr [21:0] $end
+$var reg 23 ^" addr_reg [22:0] $end
+$var reg 23 _" mem_addr [22:0] $end
 $var reg 1 z mem_lb_n $end
 $var reg 1 x mem_req $end
 $var reg 1 w mem_ub_n $end
@@ -484,7 +484,7 @@ $var wire 1 ( ub_n $end
 $var wire 1 ) oe_n $end
 $var wire 1 , lb_n $end
 $var wire 1 - ce_n $end
-$var wire 22 ($ a [21:0] $end
+$var wire 23 ($ a [22:0] $end
 $var parameter 32 )$ ADDR_WIDTH $end
 $var parameter 32 *$ DATA_WIDTH $end
 $var parameter 32 +$ DEPTH $end
@@ -503,7 +503,7 @@ $var real 1 7$ TWC_NS $end
 $var real 1 8$ TWPH_NS $end
 $var real 1 9$ TWP_NS $end
 $var real 1 :$ TWR_NS $end
-$var reg 22 ;$ active_addr [21:0] $end
+$var reg 23 ;$ active_addr [22:0] $end
 $var reg 16 <$ active_wdata [15:0] $end
 $var reg 1 =$ dq_oe $end
 $var reg 16 >$ dq_out [15:0] $end
@@ -531,7 +531,7 @@ $upscope $end
 $upscope $end
 $scope module u_psram_ctrl $end
 $var wire 1 H clk $end
-$var wire 22 P$ mem_addr [21:0] $end
+$var wire 23 P$ mem_addr [22:0] $end
 $var wire 1 : mem_lb_n $end
 $var wire 1 9 mem_req $end
 $var wire 1 8 mem_ub_n $end
@@ -550,14 +550,14 @@ $var parameter 3 Z$ STATE_INIT $end
 $var parameter 3 [$ STATE_READ $end
 $var parameter 3 \$ STATE_WRITE $end
 $var parameter 3 ]$ STATE_WRITE_WAIT $end
-$var reg 22 ^$ address_reg [21:0] $end
+$var reg 23 ^$ address_reg [22:0] $end
 $var reg 14 _$ counter [13:0] $end
 $var reg 1 `$ dq_oe $end
 $var reg 16 a$ dq_out [15:0] $end
 $var reg 1 b$ lb_reg $end
 $var reg 16 c$ mem_rdata [15:0] $end
 $var reg 1 * mem_ready $end
-$var reg 22 d$ psram_a [21:0] $end
+$var reg 23 d$ psram_a [22:0] $end
 $var reg 1 - psram_ce_n $end
 $var reg 1 , psram_lb_n $end
 $var reg 1 ) psram_oe_n $end
@@ -570,27 +570,27 @@ $var reg 16 g$ wdata_reg [15:0] $end
 $var reg 1 h$ wr_reg $end
 $upscope $end
 $scope task preload_bias $end
-$var reg 22 i$ addr_i [21:0] $end
+$var reg 23 i$ addr_i [22:0] $end
 $var reg 8 j$ value [7:0] $end
 $upscope $end
 $scope task preload_vector $end
-$var reg 22 k$ base [21:0] $end
+$var reg 23 k$ base [22:0] $end
 $var reg 8 l$ value [7:0] $end
 $var integer 32 m$ k [31:0] $end
 $upscope $end
 $scope task preload_vector_n $end
-$var reg 22 n$ base [21:0] $end
+$var reg 23 n$ base [22:0] $end
 $var reg 8 o$ value [7:0] $end
 $var integer 32 p$ k [31:0] $end
 $var integer 32 q$ len [31:0] $end
 $upscope $end
 $scope task preload_weights $end
-$var reg 22 r$ base [21:0] $end
+$var reg 23 r$ base [22:0] $end
 $var reg 8 s$ value [7:0] $end
 $var integer 32 t$ k [31:0] $end
 $upscope $end
 $scope task preload_x_pattern $end
-$var reg 22 u$ base [21:0] $end
+$var reg 23 u$ base [22:0] $end
 $var reg 8 v$ v0 [7:0] $end
 $var reg 8 w$ v1 [7:0] $end
 $var integer 32 x$ k [31:0] $end
@@ -605,7 +605,7 @@ $var reg 128 |$ test_name [127:0] $end
 $var integer 32 }$ elapsed_cycles [31:0] $end
 $upscope $end
 $scope task tb_write_word $end
-$var reg 22 ~$ addr_i [21:0] $end
+$var reg 23 ~$ addr_i [22:0] $end
 $var reg 16 !% data_i [15:0] $end
 $upscope $end
 $upscope $end
@@ -621,7 +621,7 @@ b10111011100000 X$
 b10000 W$
 b1110 V$
 b1010000 U$
-b10110 T$
+b10111 T$
 b110 S$
 r0 :$
 r46 9$
@@ -640,7 +640,7 @@ r70 -$
 r70 ,$
 b100000000000000 +$
 b10000 *$
-b10110 )$
+b10111 )$
 b0 &$
 b10 %$
 b1 $$
@@ -705,7 +705,7 @@ b0 o"
 b100000 n"
 b1 ]"
 b0 \"
-b10110 ["
+b10111 ["
 b0 W"
 b11111 V"
 b11110 U"
@@ -750,15 +750,15 @@ b1 #"
 b100000 ""
 b1 !"
 b1000 ~
-b10110 }
+b10111 }
 b100000 |
 b1 _
 b0 ^
 b10000 ]
-b10110 \
+b10111 \
 b10000 F
 r12.5 E
-b10110 D
+b10111 D
 $end
 #0
 $dumpvars

sim/neuron_memory_multi.vcd

@@ -1,5 +1,5 @@
 $date
-	Wed Sep  2 20:14:10 2026
+	Wed Sep  2 20:58:13 2026
 $end
 $version
 	Icarus Verilog
@@ -21,12 +21,12 @@ $var wire 1 * psram_mem_ready $end
 $var wire 16 + psram_mem_rdata [15:0] $end
 $var wire 1 , psram_lb_n $end
 $var wire 1 - psram_ce_n $end
-$var wire 22 . psram_a [21:0] $end
+$var wire 23 . psram_a [22:0] $end
 $var wire 1 / neuron_mem_wr $end
 $var wire 8 0 neuron_mem_wdata [7:0] $end
 $var wire 1 1 neuron_mem_req $end
 $var wire 8 2 neuron_mem_rdata [7:0] $end
-$var wire 22 3 neuron_mem_addr [21:0] $end
+$var wire 23 3 neuron_mem_addr [22:0] $end
 $var wire 1 4 memory_ready $end
 $var wire 16 5 memory_rdata [15:0] $end
 $var wire 1 6 memory_mem_wr $end
@@ -34,13 +34,13 @@ $var wire 16 7 memory_mem_wdata [15:0] $end
 $var wire 1 8 memory_mem_ub_n $end
 $var wire 1 9 memory_mem_req $end
 $var wire 1 : memory_mem_lb_n $end
-$var wire 22 ; memory_mem_addr [21:0] $end
+$var wire 23 ; memory_mem_addr [22:0] $end
 $var wire 1 < master_wr $end
 $var wire 16 = master_wdata [15:0] $end
 $var wire 1 > master_ub_n $end
 $var wire 1 ? master_req $end
 $var wire 1 @ master_lb_n $end
-$var wire 22 A master_addr [21:0] $end
+$var wire 23 A master_addr [22:0] $end
 $var wire 1 B done $end
 $var wire 1 C busy $end
 $var parameter 32 D ADDR_WIDTH $end
@@ -48,21 +48,21 @@ $var real 1 E CLK_PERIOD $end
 $var parameter 32 F DATA_WIDTH $end
 $var parameter 32 G N_INPUTS $end
 $var parameter 32 H N_NEURONS $end
-$var reg 22 I bias_addr [21:0] $end
+$var reg 23 I bias_addr [22:0] $end
 $var reg 1 J clk $end
 $var reg 1 K rst $end
 $var reg 1 L start $end
-$var reg 22 M tb_mem_addr [21:0] $end
+$var reg 23 M tb_mem_addr [22:0] $end
 $var reg 1 N tb_mem_lb_n $end
 $var reg 1 O tb_mem_req $end
 $var reg 1 P tb_mem_ub_n $end
 $var reg 16 Q tb_mem_wdata [15:0] $end
 $var reg 1 R tb_mem_wr $end
 $var reg 1 S use_neuron_master $end
-$var reg 22 T w_base [21:0] $end
-$var reg 22 U x_base [21:0] $end
+$var reg 23 T w_base [22:0] $end
+$var reg 23 U x_base [22:0] $end
 $scope module u_memory_if $end
-$var wire 22 V addr [21:0] $end
+$var wire 23 V addr [22:0] $end
 $var wire 1 J clk $end
 $var wire 1 @ lb_n $end
 $var wire 1 ? req $end
@@ -76,7 +76,7 @@ $var parameter 32 Y ADDR_WIDTH $end
 $var parameter 32 Z DATA_WIDTH $end
 $var parameter 2 [ STATE_IDLE $end
 $var parameter 2 \ STATE_WAIT $end
-$var reg 22 ] mem_addr [21:0] $end
+$var reg 23 ] mem_addr [22:0] $end
 $var reg 1 : mem_lb_n $end
 $var reg 1 9 mem_req $end
 $var reg 1 8 mem_ub_n $end
@@ -88,9 +88,9 @@ $var reg 2 ` state [1:0] $end
 $upscope $end
 $scope module u_neuron $end
 $var wire 2 a activation [1:0] $end
-$var wire 22 b bias_addr [21:0] $end
+$var wire 23 b bias_addr [22:0] $end
 $var wire 1 J clk $end
-$var wire 22 c mem_addr [21:0] $end
+$var wire 23 c mem_addr [22:0] $end
 $var wire 8 d mem_rdata [7:0] $end
 $var wire 1 ! mem_ready $end
 $var wire 1 1 mem_req $end
@@ -100,8 +100,8 @@ $var wire 16 f n_inputs_real [15:0] $end
 $var wire 16 g n_neurons_real [15:0] $end
 $var wire 1 K rst $end
 $var wire 1 L start $end
-$var wire 22 h w_base [21:0] $end
-$var wire 22 i x_base [21:0] $end
+$var wire 23 h w_base [22:0] $end
+$var wire 23 i x_base [22:0] $end
 $var wire 24 j y_bus [23:0] $end
 $var wire 256 k x_bus [255:0] $end
 $var wire 256 l w_bus [255:0] $end
@@ -116,7 +116,7 @@ $var wire 1 t access_mem_ub_n $end
 $var wire 1 u access_mem_req $end
 $var wire 16 v access_mem_rdata [15:0] $end
 $var wire 1 w access_mem_lb_n $end
-$var wire 22 x access_mem_addr [21:0] $end
+$var wire 23 x access_mem_addr [22:0] $end
 $var parameter 32 y ACC_WIDTH $end
 $var parameter 32 z ADDR_WIDTH $end
 $var parameter 32 { DATA_WIDTH $end
@@ -130,11 +130,11 @@ $var parameter 4 $" STATE_READ_W $end
 $var parameter 4 %" STATE_READ_X $end
 $var parameter 4 &" STATE_START_N $end
 $var parameter 4 '" STATE_WAIT_N $end
-$var reg 22 (" access_addr [21:0] $end
+$var reg 23 (" access_addr [22:0] $end
 $var reg 1 )" access_req $end
 $var reg 8 *" access_wdata [7:0] $end
 $var reg 1 +" access_wr $end
-$var reg 22 ," bias_group_addr [21:0] $end
+$var reg 23 ," bias_group_addr [22:0] $end
 $var reg 8 -" bias_reg [7:0] $end
 $var reg 1 C busy $end
 $var reg 1 B done $end
@@ -142,7 +142,7 @@ $var reg 6 ." index [5:0] $end
 $var reg 2 /" neuron_index [1:0] $end
 $var reg 1 0" neuron_start $end
 $var reg 4 1" state [3:0] $end
-$var reg 22 2" w_group_base [21:0] $end
+$var reg 23 2" w_group_base [22:0] $end
 $var integer 32 3" rst_i [31:0] $end
 $scope begin GEN_BUS[0] $end
 $var parameter 2 4" i $end
@@ -250,7 +250,7 @@ $scope begin GEN_Y_BUS[2] $end
 $var parameter 3 V" j $end
 $upscope $end
 $scope module u_mem $end
-$var wire 22 W" addr [21:0] $end
+$var wire 23 W" addr [22:0] $end
 $var wire 1 J clk $end
 $var wire 16 X" mem_rdata [15:0] $end
 $var wire 1 ! mem_ready $end
@@ -261,8 +261,8 @@ $var wire 1 +" wr $end
 $var parameter 32 Z" ADDR_WIDTH $end
 $var parameter 2 [" STATE_IDLE $end
 $var parameter 2 \" STATE_WAIT $end
-$var reg 22 ]" addr_reg [21:0] $end
-$var reg 22 ^" mem_addr [21:0] $end
+$var reg 23 ]" addr_reg [22:0] $end
+$var reg 23 ^" mem_addr [22:0] $end
 $var reg 1 w mem_lb_n $end
 $var reg 1 u mem_req $end
 $var reg 1 t mem_ub_n $end
@@ -487,7 +487,7 @@ $var wire 1 ( ub_n $end
 $var wire 1 ) oe_n $end
 $var wire 1 , lb_n $end
 $var wire 1 - ce_n $end
-$var wire 22 '$ a [21:0] $end
+$var wire 23 '$ a [22:0] $end
 $var parameter 32 ($ ADDR_WIDTH $end
 $var parameter 32 )$ DATA_WIDTH $end
 $var parameter 32 *$ DEPTH $end
@@ -506,7 +506,7 @@ $var real 1 6$ TWC_NS $end
 $var real 1 7$ TWPH_NS $end
 $var real 1 8$ TWP_NS $end
 $var real 1 9$ TWR_NS $end
-$var reg 22 :$ active_addr [21:0] $end
+$var reg 23 :$ active_addr [22:0] $end
 $var reg 16 ;$ active_wdata [15:0] $end
 $var reg 1 <$ dq_oe $end
 $var reg 16 =$ dq_out [15:0] $end
@@ -534,7 +534,7 @@ $upscope $end
 $upscope $end
 $scope module u_psram_ctrl $end
 $var wire 1 J clk $end
-$var wire 22 O$ mem_addr [21:0] $end
+$var wire 23 O$ mem_addr [22:0] $end
 $var wire 1 : mem_lb_n $end
 $var wire 1 9 mem_req $end
 $var wire 1 8 mem_ub_n $end
@@ -553,14 +553,14 @@ $var parameter 3 Y$ STATE_INIT $end
 $var parameter 3 Z$ STATE_READ $end
 $var parameter 3 [$ STATE_WRITE $end
 $var parameter 3 \$ STATE_WRITE_WAIT $end
-$var reg 22 ]$ address_reg [21:0] $end
+$var reg 23 ]$ address_reg [22:0] $end
 $var reg 14 ^$ counter [13:0] $end
 $var reg 1 _$ dq_oe $end
 $var reg 16 `$ dq_out [15:0] $end
 $var reg 1 a$ lb_reg $end
 $var reg 16 b$ mem_rdata [15:0] $end
 $var reg 1 * mem_ready $end
-$var reg 22 c$ psram_a [21:0] $end
+$var reg 23 c$ psram_a [22:0] $end
 $var reg 1 - psram_ce_n $end
 $var reg 1 , psram_lb_n $end
 $var reg 1 ) psram_oe_n $end
@@ -576,17 +576,17 @@ $scope task preload_bias_3 $end
 $var reg 8 h$ b0 [7:0] $end
 $var reg 8 i$ b1 [7:0] $end
 $var reg 8 j$ b2 [7:0] $end
-$var reg 22 k$ base [21:0] $end
+$var reg 23 k$ base [22:0] $end
 $upscope $end
 $scope task preload_weights_n $end
-$var reg 22 l$ base [21:0] $end
-$var reg 22 m$ neuron_base [21:0] $end
+$var reg 23 l$ base [22:0] $end
+$var reg 23 m$ neuron_base [22:0] $end
 $var reg 8 n$ value [7:0] $end
 $var integer 32 o$ k [31:0] $end
 $var integer 32 p$ n [31:0] $end
 $upscope $end
 $scope task preload_x $end
-$var reg 22 q$ base [21:0] $end
+$var reg 23 q$ base [22:0] $end
 $var integer 32 r$ k [31:0] $end
 $upscope $end
 $scope task run_and_check $end
@@ -596,7 +596,7 @@ $var reg 8 u$ expected2 [7:0] $end
 $var integer 32 v$ errors_local [31:0] $end
 $upscope $end
 $scope task tb_write_word $end
-$var reg 22 w$ addr_i [21:0] $end
+$var reg 23 w$ addr_i [22:0] $end
 $var reg 16 x$ data_i [15:0] $end
 $upscope $end
 $upscope $end
@@ -612,7 +612,7 @@ b10111011100000 W$
 b10000 V$
 b1110 U$
 b1010000 T$
-b10110 S$
+b10111 S$
 b110 R$
 r0 9$
 r46 8$
@@ -631,7 +631,7 @@ r70 ,$
 r70 +$
 b100000000000000 *$
 b10000 )$
-b10110 ($
+b10111 ($
 b0 %$
 b10 $$
 b1 #$
@@ -696,7 +696,7 @@ b0 n"
 b100000 m"
 b1 \"
 b0 ["
-b10110 Z"
+b10111 Z"
 b10 V"
 b1 U"
 b0 T"
@@ -743,17 +743,17 @@ b11 ~
 b100000 }
 b10 |
 b1000 {
-b10110 z
+b10111 z
 b100000 y
 b1 \
 b0 [
 b10000 Z
-b10110 Y
+b10111 Y
 b11 H
 b100000 G
 b10000 F
 r12.5 E
-b10110 D
+b10111 D
 $end
 #0
 $dumpvars

sim/neuron_memory_multi_tb.v

@@ -20,7 +20,7 @@
 
 module tb;
 
-    localparam ADDR_WIDTH = 22;
+    localparam ADDR_WIDTH = 23;
     localparam DATA_WIDTH = 16;
     localparam CLK_PERIOD = 12.5; // 80 MHz
 

sim/neuron_memory_tb.v

@@ -2,7 +2,7 @@
 
 module tb;
 
-    localparam ADDR_WIDTH = 22;
+    localparam ADDR_WIDTH = 23;
     localparam DATA_WIDTH = 16;
     localparam CLK_PERIOD = 12.5; // 80 MHz
 

sim/parameter_sweep.vcd

@@ -1,5 +1,5 @@
 $date
-	Wed Sep  2 20:14:10 2026
+	Wed Sep  2 20:58:26 2026
 $end
 $version
 	Icarus Verilog

sim/psram_controller.vcd

@@ -1,5 +1,5 @@
 $date
-	Wed Sep  2 12:33:48 2026
+	Wed Sep  2 20:58:44 2026
 $end
 $version
 	Icarus Verilog
@@ -15,14 +15,14 @@ $var wire 1 $ psram_ub_n $end
 $var wire 1 % psram_oe_n $end
 $var wire 1 & psram_lb_n $end
 $var wire 1 ' psram_ce_n $end
-$var wire 22 ( psram_a [21:0] $end
+$var wire 23 ( psram_a [22:0] $end
 $var wire 1 ) mem_ready $end
 $var wire 16 * mem_rdata [15:0] $end
 $var parameter 32 + ADDR_WIDTH $end
 $var real 1 , CLK_PERIOD $end
 $var parameter 32 - DATA_WIDTH $end
 $var reg 1 . clk $end
-$var reg 22 / mem_addr [21:0] $end
+$var reg 23 / mem_addr [22:0] $end
 $var reg 1 0 mem_lb_n $end
 $var reg 1 1 mem_req $end
 $var reg 1 2 mem_ub_n $end
@@ -34,7 +34,7 @@ $var integer 32 7 stress_addr [31:0] $end
 $var integer 32 8 stress_i [31:0] $end
 $scope module dut $end
 $var wire 1 . clk $end
-$var wire 22 9 mem_addr [21:0] $end
+$var wire 23 9 mem_addr [22:0] $end
 $var wire 1 0 mem_lb_n $end
 $var wire 1 1 mem_req $end
 $var wire 1 2 mem_ub_n $end
@@ -53,14 +53,14 @@ $var parameter 3 C STATE_INIT $end
 $var parameter 3 D STATE_READ $end
 $var parameter 3 E STATE_WRITE $end
 $var parameter 3 F STATE_WRITE_WAIT $end
-$var reg 22 G address_reg [21:0] $end
+$var reg 23 G address_reg [22:0] $end
 $var reg 14 H counter [13:0] $end
 $var reg 1 I dq_oe $end
 $var reg 16 J dq_out [15:0] $end
 $var reg 1 K lb_reg $end
 $var reg 16 L mem_rdata [15:0] $end
 $var reg 1 ) mem_ready $end
-$var reg 22 M psram_a [21:0] $end
+$var reg 23 M psram_a [22:0] $end
 $var reg 1 ' psram_ce_n $end
 $var reg 1 & psram_lb_n $end
 $var reg 1 % psram_oe_n $end
@@ -73,7 +73,7 @@ $var reg 16 P wdata_reg [15:0] $end
 $var reg 1 Q wr_reg $end
 $upscope $end
 $scope module memory $end
-$var wire 22 R a [21:0] $end
+$var wire 23 R a [22:0] $end
 $var wire 1 ' ce_n $end
 $var wire 1 . clk $end
 $var wire 16 S dq [15:0] $end
@@ -100,7 +100,7 @@ $var real 1 b TWC_NS $end
 $var real 1 c TWPH_NS $end
 $var real 1 d TWP_NS $end
 $var real 1 e TWR_NS $end
-$var reg 22 f active_addr [21:0] $end
+$var reg 23 f active_addr [22:0] $end
 $var reg 16 g active_wdata [15:0] $end
 $var reg 1 h dq_oe $end
 $var reg 16 i dq_out [15:0] $end
@@ -118,20 +118,20 @@ $var real 1 t oe_low_time $end
 $var real 1 u powerup_time $end
 $var real 1 v we_high_time $end
 $var real 1 w we_low_time $end
-$scope begin $unm_blk_23 $end
+$scope begin $unm_blk_41 $end
 $var real 1 x access_time $end
 $upscope $end
-$scope begin $unm_blk_35 $end
+$scope begin $unm_blk_53 $end
 $var real 1 y data_setup $end
 $var real 1 z write_width $end
 $upscope $end
 $upscope $end
 $scope task read_word $end
-$var reg 22 { addr [21:0] $end
+$var reg 23 { addr [22:0] $end
 $var reg 16 | expected [15:0] $end
 $upscope $end
 $scope task write_word $end
-$var reg 22 } addr [21:0] $end
+$var reg 23 } addr [22:0] $end
 $var reg 16 ~ data [15:0] $end
 $var reg 1 !" lb $end
 $var reg 1 "" ub $end
@@ -157,7 +157,7 @@ r70 X
 r70 W
 b100000000000000 V
 b10000 U
-b10110 T
+b10111 T
 b100 F
 b11 E
 b10 D
@@ -167,11 +167,11 @@ b10111011100000 A
 b10000 @
 b1110 ?
 b1010000 >
-b10110 =
+b10111 =
 b110 <
 b10000 -
 r12.5 ,
-b10110 +
+b10111 +
 $end
 #0
 $dumpvars

sim/psram_controller_tb.v

@@ -2,7 +2,7 @@
 
 module tb;
 
-    localparam ADDR_WIDTH = 22;
+    localparam ADDR_WIDTH = 23;
     localparam DATA_WIDTH = 16;
     localparam CLK_PERIOD = 12.5; // 80 MHz
 

sim/psram_model.v

@@ -1,7 +1,7 @@
 `timescale 1ns/1ps
 
 module psram_model #(
-    parameter ADDR_WIDTH = 22,
+    parameter ADDR_WIDTH = 23,
     parameter DATA_WIDTH = 16,
     parameter DEPTH      = 16384
 )(

sim/spi_engine_tb.v

@@ -30,7 +30,7 @@
 
 module tb;
 
-    localparam ADDR_WIDTH = 22;
+    localparam ADDR_WIDTH = 23;
     localparam DATA_WIDTH = 8;
     localparam N_INPUTS   = 32;
     localparam N_NEURONS  = 3;

sim/spi_neuron_top_runnetwork_tb.v

@@ -38,7 +38,7 @@
 
 module tb;
 
-    localparam ADDR_WIDTH     = 22;
+    localparam ADDR_WIDTH     = 23;
     localparam DATA_WIDTH     = 8;
     localparam N_INPUTS       = 4;
     localparam N_NEURONS      = 4;

sim/spi_neuron_top_tb.v

@@ -23,7 +23,7 @@
 
 module tb;
 
-    localparam ADDR_WIDTH     = 22;
+    localparam ADDR_WIDTH     = 23;
     localparam DATA_WIDTH     = 8;
     localparam N_INPUTS       = 32;
     localparam N_NEURONS      = 1;

sim/spi_slave.vcd

@@ -1,5 +1,5 @@
 $date
-	Wed Sep  2 20:13:54 2026
+	Wed Sep  2 20:58:00 2026
 $end
 $version
 	Icarus Verilog