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FPGA-Neural/sim/layer.vcd
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micheleandClaude Sonnet 5 7e2711fa27 feat: widen ADDR_WIDTH to 23 bits for full 8MB PSRAM addressing 
Bumps ADDR_WIDTH's default from 22 to 23 bits across every RTL
module (neuron_memory, layer_sequencer, spi_engine, spi_neuron_top,
mem_arbiter, int8_memory_access, memory_interface, psram_controller,
memory_model) and every testbench that mirrors it, so the system's
byte-address space reaches the full 8 MiB the recommended PSRAM part
(ISSI IS66WVE4M16EBLL-70BLI, docs/FPGA-Neural-Hardware-Design.md §3)
actually provides -- previously only 4 MiB (half the chip) was
reachable, since int8_memory_access.v's byte->word address shift
(addr >> 1) turned the old 22-bit byte address into only 21 real word
bits, one short of the chip's real 22-bit word address (A0-A21). At
23 bits, that same shift lands exactly on all 22 chip address lines,
so the whole part is usable now instead of deferred to a future
widening.

Also fixes a stray 22'd11-sized literal in layer_sequencer.v's
descriptor-table address increment (numerically already safe via
Verilog's zero-extension, but now correctly unsized so it always
matches ADDR_WIDTH instead of silently assuming 22).

Updated docs/FPGA-NeuralNetwork-Engine.md's SPI protocol address-field
note (23 bits, top 1 reserved bit instead of 2) and
docs/FPGA-Neural-Hardware-Design.md's PSRAM section (the "chip has
one spare address line" framing is gone now that all 22 are wired
and used).

Full regression (all 11 ADDR_WIDTH-touching testbenches, plus a
Yosys elaboration check of spi_neuron_top with the new default and
no override) passes clean.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01WQV3vS9TXaGDJ5cRfnfidt
2026-09-02 21:00:46 +02:00

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$date
Wed Sep 2 20:58:26 2026
$end
$version
Icarus Verilog
$end
$timescale
1ps
$end
$scope module tb $end
$var wire 64 ! y_bus [63:0] $end
$var wire 1 " done $end
$var wire 1 # busy $end
$var parameter 32 $ ACC_WIDTH $end
$var parameter 32 % DATA_WIDTH $end
$var parameter 32 & N_INPUTS $end
$var parameter 32 ' N_NEURONS $end
$var parameter 32 ( PARALLEL $end
$var reg 64 ) bias_bus [63:0] $end
$var reg 1 * clk $end
$var reg 1 + rst $end
$var reg 1 , start $end
$var reg 2048 - weights_bus [2047:0] $end
$var reg 256 . x_bus [255:0] $end
$var integer 32 / errors [31:0] $end
$var integer 32 0 i [31:0] $end
$scope module dut $end
$var wire 64 1 bias_bus [63:0] $end
$var wire 1 * clk $end
$var wire 1 + rst $end
$var wire 1 , start $end
$var wire 2048 2 weights_bus [2047:0] $end
$var wire 256 3 x_bus [255:0] $end
$var wire 64 4 y_bus [63:0] $end
$var wire 8 5 neuron_done [7:0] $end
$var wire 8 6 neuron_busy [7:0] $end
$var wire 1 " done $end
$var wire 1 # busy $end
$var parameter 32 7 ACC_WIDTH $end
$var parameter 32 8 DATA_WIDTH $end
$var parameter 32 9 N_INPUTS $end
$var parameter 32 : N_NEURONS $end
$var parameter 32 ; PARALLEL $end
$scope begin GEN_NEURON[0] $end
$var parameter 2 < n $end
$scope module u_neuron $end
$var wire 2 = activation [1:0] $end
$var wire 8 > bias [7:0] $end
$var wire 1 * clk $end
$var wire 16 ? n_inputs_real [15:0] $end
$var wire 1 + rst $end
$var wire 1 , start $end
$var wire 256 @ w_bus [255:0] $end
$var wire 256 A x_bus [255:0] $end
$var wire 64 B x_group [63:0] $end
$var wire 64 C w_group [63:0] $end
$var wire 16 D groups_real [15:0] $end
$var wire 32 E final_acc [31:0] $end
$var wire 32 F bias_ext [31:0] $end
$var wire 32 G acc_next [31:0] $end
$var parameter 32 H ACC_WIDTH $end
$var parameter 2 I ACT_NONE $end
$var parameter 2 J ACT_RELU $end
$var parameter 32 K DATA_WIDTH $end
$var parameter 32 L GROUPS $end
$var parameter 32 M GROUP_INDEX_WIDTH $end
$var parameter 32 N N_INPUTS $end
$var parameter 32 O PARALLEL $end
$var reg 32 P acc [31:0] $end
$var reg 1 Q busy $end
$var reg 1 R done $end
$var reg 2 S group_index [1:0] $end
$var reg 8 T y [7:0] $end
$scope module u_mac8 $end
$var wire 32 U acc_in [31:0] $end
$var wire 64 V w_bus [63:0] $end
$var wire 64 W x_bus [63:0] $end
$var wire 32 X acc_out [31:0] $end
$var parameter 32 Y ACC_WIDTH $end
$var parameter 32 Z DATA_WIDTH $end
$var parameter 32 [ PARALLEL $end
$var parameter 32 \ TREE_LEVELS $end
$scope begin GEN_MAC[0] $end
$var parameter 2 ] i $end
$scope module u_mac $end
$var wire 32 ^ acc_in [31:0] $end
$var wire 8 _ w [7:0] $end
$var wire 8 ` x [7:0] $end
$var wire 32 a product_ext [31:0] $end
$var wire 16 b product [15:0] $end
$var wire 32 c acc_out [31:0] $end
$var parameter 32 d ACC_WIDTH $end
$var parameter 32 e DATA_WIDTH $end
$var parameter 64 f PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[1] $end
$var parameter 2 g i $end
$scope module u_mac $end
$var wire 32 h acc_in [31:0] $end
$var wire 8 i w [7:0] $end
$var wire 8 j x [7:0] $end
$var wire 32 k product_ext [31:0] $end
$var wire 16 l product [15:0] $end
$var wire 32 m acc_out [31:0] $end
$var parameter 32 n ACC_WIDTH $end
$var parameter 32 o DATA_WIDTH $end
$var parameter 64 p PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[2] $end
$var parameter 3 q i $end
$scope module u_mac $end
$var wire 32 r acc_in [31:0] $end
$var wire 8 s w [7:0] $end
$var wire 8 t x [7:0] $end
$var wire 32 u product_ext [31:0] $end
$var wire 16 v product [15:0] $end
$var wire 32 w acc_out [31:0] $end
$var parameter 32 x ACC_WIDTH $end
$var parameter 32 y DATA_WIDTH $end
$var parameter 64 z PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[3] $end
$var parameter 3 { i $end
$scope module u_mac $end
$var wire 32 | acc_in [31:0] $end
$var wire 8 } w [7:0] $end
$var wire 8 ~ x [7:0] $end
$var wire 32 !" product_ext [31:0] $end
$var wire 16 "" product [15:0] $end
$var wire 32 #" acc_out [31:0] $end
$var parameter 32 $" ACC_WIDTH $end
$var parameter 32 %" DATA_WIDTH $end
$var parameter 64 &" PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[4] $end
$var parameter 4 '" i $end
$scope module u_mac $end
$var wire 32 (" acc_in [31:0] $end
$var wire 8 )" w [7:0] $end
$var wire 8 *" x [7:0] $end
$var wire 32 +" product_ext [31:0] $end
$var wire 16 ," product [15:0] $end
$var wire 32 -" acc_out [31:0] $end
$var parameter 32 ." ACC_WIDTH $end
$var parameter 32 /" DATA_WIDTH $end
$var parameter 64 0" PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[5] $end
$var parameter 4 1" i $end
$scope module u_mac $end
$var wire 32 2" acc_in [31:0] $end
$var wire 8 3" w [7:0] $end
$var wire 8 4" x [7:0] $end
$var wire 32 5" product_ext [31:0] $end
$var wire 16 6" product [15:0] $end
$var wire 32 7" acc_out [31:0] $end
$var parameter 32 8" ACC_WIDTH $end
$var parameter 32 9" DATA_WIDTH $end
$var parameter 64 :" PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[6] $end
$var parameter 4 ;" i $end
$scope module u_mac $end
$var wire 32 <" acc_in [31:0] $end
$var wire 8 =" w [7:0] $end
$var wire 8 >" x [7:0] $end
$var wire 32 ?" product_ext [31:0] $end
$var wire 16 @" product [15:0] $end
$var wire 32 A" acc_out [31:0] $end
$var parameter 32 B" ACC_WIDTH $end
$var parameter 32 C" DATA_WIDTH $end
$var parameter 64 D" PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[7] $end
$var parameter 4 E" i $end
$scope module u_mac $end
$var wire 32 F" acc_in [31:0] $end
$var wire 8 G" w [7:0] $end
$var wire 8 H" x [7:0] $end
$var wire 32 I" product_ext [31:0] $end
$var wire 16 J" product [15:0] $end
$var wire 32 K" acc_out [31:0] $end
$var parameter 32 L" ACC_WIDTH $end
$var parameter 32 M" DATA_WIDTH $end
$var parameter 64 N" PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_INPUT[0] $end
$var parameter 2 O" i $end
$upscope $end
$scope begin GEN_TREE_INPUT[1] $end
$var parameter 2 P" i $end
$upscope $end
$scope begin GEN_TREE_INPUT[2] $end
$var parameter 3 Q" i $end
$upscope $end
$scope begin GEN_TREE_INPUT[3] $end
$var parameter 3 R" i $end
$upscope $end
$scope begin GEN_TREE_INPUT[4] $end
$var parameter 4 S" i $end
$upscope $end
$scope begin GEN_TREE_INPUT[5] $end
$var parameter 4 T" i $end
$upscope $end
$scope begin GEN_TREE_INPUT[6] $end
$var parameter 4 U" i $end
$upscope $end
$scope begin GEN_TREE_INPUT[7] $end
$var parameter 4 V" i $end
$upscope $end
$scope begin GEN_TREE_LEVEL[0] $end
$var parameter 2 W" level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 X" node $end
$upscope $end
$scope begin GEN_TREE_NODE[1] $end
$var parameter 2 Y" node $end
$upscope $end
$scope begin GEN_TREE_NODE[2] $end
$var parameter 3 Z" node $end
$upscope $end
$scope begin GEN_TREE_NODE[3] $end
$var parameter 3 [" node $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_LEVEL[1] $end
$var parameter 2 \" level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 ]" node $end
$upscope $end
$scope begin GEN_TREE_NODE[1] $end
$var parameter 2 ^" node $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_LEVEL[2] $end
$var parameter 3 _" level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 `" node $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$scope begin GEN_NEURON[1] $end
$var parameter 2 a" n $end
$scope module u_neuron $end
$var wire 2 b" activation [1:0] $end
$var wire 8 c" bias [7:0] $end
$var wire 1 * clk $end
$var wire 16 d" n_inputs_real [15:0] $end
$var wire 1 + rst $end
$var wire 1 , start $end
$var wire 256 e" w_bus [255:0] $end
$var wire 256 f" x_bus [255:0] $end
$var wire 64 g" x_group [63:0] $end
$var wire 64 h" w_group [63:0] $end
$var wire 16 i" groups_real [15:0] $end
$var wire 32 j" final_acc [31:0] $end
$var wire 32 k" bias_ext [31:0] $end
$var wire 32 l" acc_next [31:0] $end
$var parameter 32 m" ACC_WIDTH $end
$var parameter 2 n" ACT_NONE $end
$var parameter 2 o" ACT_RELU $end
$var parameter 32 p" DATA_WIDTH $end
$var parameter 32 q" GROUPS $end
$var parameter 32 r" GROUP_INDEX_WIDTH $end
$var parameter 32 s" N_INPUTS $end
$var parameter 32 t" PARALLEL $end
$var reg 32 u" acc [31:0] $end
$var reg 1 v" busy $end
$var reg 1 w" done $end
$var reg 2 x" group_index [1:0] $end
$var reg 8 y" y [7:0] $end
$scope module u_mac8 $end
$var wire 32 z" acc_in [31:0] $end
$var wire 64 {" w_bus [63:0] $end
$var wire 64 |" x_bus [63:0] $end
$var wire 32 }" acc_out [31:0] $end
$var parameter 32 ~" ACC_WIDTH $end
$var parameter 32 !# DATA_WIDTH $end
$var parameter 32 "# PARALLEL $end
$var parameter 32 ## TREE_LEVELS $end
$scope begin GEN_MAC[0] $end
$var parameter 2 $# i $end
$scope module u_mac $end
$var wire 32 %# acc_in [31:0] $end
$var wire 8 &# w [7:0] $end
$var wire 8 '# x [7:0] $end
$var wire 32 (# product_ext [31:0] $end
$var wire 16 )# product [15:0] $end
$var wire 32 *# acc_out [31:0] $end
$var parameter 32 +# ACC_WIDTH $end
$var parameter 32 ,# DATA_WIDTH $end
$var parameter 64 -# PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[1] $end
$var parameter 2 .# i $end
$scope module u_mac $end
$var wire 32 /# acc_in [31:0] $end
$var wire 8 0# w [7:0] $end
$var wire 8 1# x [7:0] $end
$var wire 32 2# product_ext [31:0] $end
$var wire 16 3# product [15:0] $end
$var wire 32 4# acc_out [31:0] $end
$var parameter 32 5# ACC_WIDTH $end
$var parameter 32 6# DATA_WIDTH $end
$var parameter 64 7# PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[2] $end
$var parameter 3 8# i $end
$scope module u_mac $end
$var wire 32 9# acc_in [31:0] $end
$var wire 8 :# w [7:0] $end
$var wire 8 ;# x [7:0] $end
$var wire 32 <# product_ext [31:0] $end
$var wire 16 =# product [15:0] $end
$var wire 32 ># acc_out [31:0] $end
$var parameter 32 ?# ACC_WIDTH $end
$var parameter 32 @# DATA_WIDTH $end
$var parameter 64 A# PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[3] $end
$var parameter 3 B# i $end
$scope module u_mac $end
$var wire 32 C# acc_in [31:0] $end
$var wire 8 D# w [7:0] $end
$var wire 8 E# x [7:0] $end
$var wire 32 F# product_ext [31:0] $end
$var wire 16 G# product [15:0] $end
$var wire 32 H# acc_out [31:0] $end
$var parameter 32 I# ACC_WIDTH $end
$var parameter 32 J# DATA_WIDTH $end
$var parameter 64 K# PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[4] $end
$var parameter 4 L# i $end
$scope module u_mac $end
$var wire 32 M# acc_in [31:0] $end
$var wire 8 N# w [7:0] $end
$var wire 8 O# x [7:0] $end
$var wire 32 P# product_ext [31:0] $end
$var wire 16 Q# product [15:0] $end
$var wire 32 R# acc_out [31:0] $end
$var parameter 32 S# ACC_WIDTH $end
$var parameter 32 T# DATA_WIDTH $end
$var parameter 64 U# PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[5] $end
$var parameter 4 V# i $end
$scope module u_mac $end
$var wire 32 W# acc_in [31:0] $end
$var wire 8 X# w [7:0] $end
$var wire 8 Y# x [7:0] $end
$var wire 32 Z# product_ext [31:0] $end
$var wire 16 [# product [15:0] $end
$var wire 32 \# acc_out [31:0] $end
$var parameter 32 ]# ACC_WIDTH $end
$var parameter 32 ^# DATA_WIDTH $end
$var parameter 64 _# PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[6] $end
$var parameter 4 `# i $end
$scope module u_mac $end
$var wire 32 a# acc_in [31:0] $end
$var wire 8 b# w [7:0] $end
$var wire 8 c# x [7:0] $end
$var wire 32 d# product_ext [31:0] $end
$var wire 16 e# product [15:0] $end
$var wire 32 f# acc_out [31:0] $end
$var parameter 32 g# ACC_WIDTH $end
$var parameter 32 h# DATA_WIDTH $end
$var parameter 64 i# PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[7] $end
$var parameter 4 j# i $end
$scope module u_mac $end
$var wire 32 k# acc_in [31:0] $end
$var wire 8 l# w [7:0] $end
$var wire 8 m# x [7:0] $end
$var wire 32 n# product_ext [31:0] $end
$var wire 16 o# product [15:0] $end
$var wire 32 p# acc_out [31:0] $end
$var parameter 32 q# ACC_WIDTH $end
$var parameter 32 r# DATA_WIDTH $end
$var parameter 64 s# PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_INPUT[0] $end
$var parameter 2 t# i $end
$upscope $end
$scope begin GEN_TREE_INPUT[1] $end
$var parameter 2 u# i $end
$upscope $end
$scope begin GEN_TREE_INPUT[2] $end
$var parameter 3 v# i $end
$upscope $end
$scope begin GEN_TREE_INPUT[3] $end
$var parameter 3 w# i $end
$upscope $end
$scope begin GEN_TREE_INPUT[4] $end
$var parameter 4 x# i $end
$upscope $end
$scope begin GEN_TREE_INPUT[5] $end
$var parameter 4 y# i $end
$upscope $end
$scope begin GEN_TREE_INPUT[6] $end
$var parameter 4 z# i $end
$upscope $end
$scope begin GEN_TREE_INPUT[7] $end
$var parameter 4 {# i $end
$upscope $end
$scope begin GEN_TREE_LEVEL[0] $end
$var parameter 2 |# level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 }# node $end
$upscope $end
$scope begin GEN_TREE_NODE[1] $end
$var parameter 2 ~# node $end
$upscope $end
$scope begin GEN_TREE_NODE[2] $end
$var parameter 3 !$ node $end
$upscope $end
$scope begin GEN_TREE_NODE[3] $end
$var parameter 3 "$ node $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_LEVEL[1] $end
$var parameter 2 #$ level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 $$ node $end
$upscope $end
$scope begin GEN_TREE_NODE[1] $end
$var parameter 2 %$ node $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_LEVEL[2] $end
$var parameter 3 &$ level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 '$ node $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$scope begin GEN_NEURON[2] $end
$var parameter 3 ($ n $end
$scope module u_neuron $end
$var wire 2 )$ activation [1:0] $end
$var wire 8 *$ bias [7:0] $end
$var wire 1 * clk $end
$var wire 16 +$ n_inputs_real [15:0] $end
$var wire 1 + rst $end
$var wire 1 , start $end
$var wire 256 ,$ w_bus [255:0] $end
$var wire 256 -$ x_bus [255:0] $end
$var wire 64 .$ x_group [63:0] $end
$var wire 64 /$ w_group [63:0] $end
$var wire 16 0$ groups_real [15:0] $end
$var wire 32 1$ final_acc [31:0] $end
$var wire 32 2$ bias_ext [31:0] $end
$var wire 32 3$ acc_next [31:0] $end
$var parameter 32 4$ ACC_WIDTH $end
$var parameter 2 5$ ACT_NONE $end
$var parameter 2 6$ ACT_RELU $end
$var parameter 32 7$ DATA_WIDTH $end
$var parameter 32 8$ GROUPS $end
$var parameter 32 9$ GROUP_INDEX_WIDTH $end
$var parameter 32 :$ N_INPUTS $end
$var parameter 32 ;$ PARALLEL $end
$var reg 32 <$ acc [31:0] $end
$var reg 1 =$ busy $end
$var reg 1 >$ done $end
$var reg 2 ?$ group_index [1:0] $end
$var reg 8 @$ y [7:0] $end
$scope module u_mac8 $end
$var wire 32 A$ acc_in [31:0] $end
$var wire 64 B$ w_bus [63:0] $end
$var wire 64 C$ x_bus [63:0] $end
$var wire 32 D$ acc_out [31:0] $end
$var parameter 32 E$ ACC_WIDTH $end
$var parameter 32 F$ DATA_WIDTH $end
$var parameter 32 G$ PARALLEL $end
$var parameter 32 H$ TREE_LEVELS $end
$scope begin GEN_MAC[0] $end
$var parameter 2 I$ i $end
$scope module u_mac $end
$var wire 32 J$ acc_in [31:0] $end
$var wire 8 K$ w [7:0] $end
$var wire 8 L$ x [7:0] $end
$var wire 32 M$ product_ext [31:0] $end
$var wire 16 N$ product [15:0] $end
$var wire 32 O$ acc_out [31:0] $end
$var parameter 32 P$ ACC_WIDTH $end
$var parameter 32 Q$ DATA_WIDTH $end
$var parameter 64 R$ PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[1] $end
$var parameter 2 S$ i $end
$scope module u_mac $end
$var wire 32 T$ acc_in [31:0] $end
$var wire 8 U$ w [7:0] $end
$var wire 8 V$ x [7:0] $end
$var wire 32 W$ product_ext [31:0] $end
$var wire 16 X$ product [15:0] $end
$var wire 32 Y$ acc_out [31:0] $end
$var parameter 32 Z$ ACC_WIDTH $end
$var parameter 32 [$ DATA_WIDTH $end
$var parameter 64 \$ PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[2] $end
$var parameter 3 ]$ i $end
$scope module u_mac $end
$var wire 32 ^$ acc_in [31:0] $end
$var wire 8 _$ w [7:0] $end
$var wire 8 `$ x [7:0] $end
$var wire 32 a$ product_ext [31:0] $end
$var wire 16 b$ product [15:0] $end
$var wire 32 c$ acc_out [31:0] $end
$var parameter 32 d$ ACC_WIDTH $end
$var parameter 32 e$ DATA_WIDTH $end
$var parameter 64 f$ PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[3] $end
$var parameter 3 g$ i $end
$scope module u_mac $end
$var wire 32 h$ acc_in [31:0] $end
$var wire 8 i$ w [7:0] $end
$var wire 8 j$ x [7:0] $end
$var wire 32 k$ product_ext [31:0] $end
$var wire 16 l$ product [15:0] $end
$var wire 32 m$ acc_out [31:0] $end
$var parameter 32 n$ ACC_WIDTH $end
$var parameter 32 o$ DATA_WIDTH $end
$var parameter 64 p$ PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[4] $end
$var parameter 4 q$ i $end
$scope module u_mac $end
$var wire 32 r$ acc_in [31:0] $end
$var wire 8 s$ w [7:0] $end
$var wire 8 t$ x [7:0] $end
$var wire 32 u$ product_ext [31:0] $end
$var wire 16 v$ product [15:0] $end
$var wire 32 w$ acc_out [31:0] $end
$var parameter 32 x$ ACC_WIDTH $end
$var parameter 32 y$ DATA_WIDTH $end
$var parameter 64 z$ PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[5] $end
$var parameter 4 {$ i $end
$scope module u_mac $end
$var wire 32 |$ acc_in [31:0] $end
$var wire 8 }$ w [7:0] $end
$var wire 8 ~$ x [7:0] $end
$var wire 32 !% product_ext [31:0] $end
$var wire 16 "% product [15:0] $end
$var wire 32 #% acc_out [31:0] $end
$var parameter 32 $% ACC_WIDTH $end
$var parameter 32 %% DATA_WIDTH $end
$var parameter 64 &% PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[6] $end
$var parameter 4 '% i $end
$scope module u_mac $end
$var wire 32 (% acc_in [31:0] $end
$var wire 8 )% w [7:0] $end
$var wire 8 *% x [7:0] $end
$var wire 32 +% product_ext [31:0] $end
$var wire 16 ,% product [15:0] $end
$var wire 32 -% acc_out [31:0] $end
$var parameter 32 .% ACC_WIDTH $end
$var parameter 32 /% DATA_WIDTH $end
$var parameter 64 0% PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[7] $end
$var parameter 4 1% i $end
$scope module u_mac $end
$var wire 32 2% acc_in [31:0] $end
$var wire 8 3% w [7:0] $end
$var wire 8 4% x [7:0] $end
$var wire 32 5% product_ext [31:0] $end
$var wire 16 6% product [15:0] $end
$var wire 32 7% acc_out [31:0] $end
$var parameter 32 8% ACC_WIDTH $end
$var parameter 32 9% DATA_WIDTH $end
$var parameter 64 :% PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_INPUT[0] $end
$var parameter 2 ;% i $end
$upscope $end
$scope begin GEN_TREE_INPUT[1] $end
$var parameter 2 <% i $end
$upscope $end
$scope begin GEN_TREE_INPUT[2] $end
$var parameter 3 =% i $end
$upscope $end
$scope begin GEN_TREE_INPUT[3] $end
$var parameter 3 >% i $end
$upscope $end
$scope begin GEN_TREE_INPUT[4] $end
$var parameter 4 ?% i $end
$upscope $end
$scope begin GEN_TREE_INPUT[5] $end
$var parameter 4 @% i $end
$upscope $end
$scope begin GEN_TREE_INPUT[6] $end
$var parameter 4 A% i $end
$upscope $end
$scope begin GEN_TREE_INPUT[7] $end
$var parameter 4 B% i $end
$upscope $end
$scope begin GEN_TREE_LEVEL[0] $end
$var parameter 2 C% level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 D% node $end
$upscope $end
$scope begin GEN_TREE_NODE[1] $end
$var parameter 2 E% node $end
$upscope $end
$scope begin GEN_TREE_NODE[2] $end
$var parameter 3 F% node $end
$upscope $end
$scope begin GEN_TREE_NODE[3] $end
$var parameter 3 G% node $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_LEVEL[1] $end
$var parameter 2 H% level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 I% node $end
$upscope $end
$scope begin GEN_TREE_NODE[1] $end
$var parameter 2 J% node $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_LEVEL[2] $end
$var parameter 3 K% level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 L% node $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$scope begin GEN_NEURON[3] $end
$var parameter 3 M% n $end
$scope module u_neuron $end
$var wire 2 N% activation [1:0] $end
$var wire 8 O% bias [7:0] $end
$var wire 1 * clk $end
$var wire 16 P% n_inputs_real [15:0] $end
$var wire 1 + rst $end
$var wire 1 , start $end
$var wire 256 Q% w_bus [255:0] $end
$var wire 256 R% x_bus [255:0] $end
$var wire 64 S% x_group [63:0] $end
$var wire 64 T% w_group [63:0] $end
$var wire 16 U% groups_real [15:0] $end
$var wire 32 V% final_acc [31:0] $end
$var wire 32 W% bias_ext [31:0] $end
$var wire 32 X% acc_next [31:0] $end
$var parameter 32 Y% ACC_WIDTH $end
$var parameter 2 Z% ACT_NONE $end
$var parameter 2 [% ACT_RELU $end
$var parameter 32 \% DATA_WIDTH $end
$var parameter 32 ]% GROUPS $end
$var parameter 32 ^% GROUP_INDEX_WIDTH $end
$var parameter 32 _% N_INPUTS $end
$var parameter 32 `% PARALLEL $end
$var reg 32 a% acc [31:0] $end
$var reg 1 b% busy $end
$var reg 1 c% done $end
$var reg 2 d% group_index [1:0] $end
$var reg 8 e% y [7:0] $end
$scope module u_mac8 $end
$var wire 32 f% acc_in [31:0] $end
$var wire 64 g% w_bus [63:0] $end
$var wire 64 h% x_bus [63:0] $end
$var wire 32 i% acc_out [31:0] $end
$var parameter 32 j% ACC_WIDTH $end
$var parameter 32 k% DATA_WIDTH $end
$var parameter 32 l% PARALLEL $end
$var parameter 32 m% TREE_LEVELS $end
$scope begin GEN_MAC[0] $end
$var parameter 2 n% i $end
$scope module u_mac $end
$var wire 32 o% acc_in [31:0] $end
$var wire 8 p% w [7:0] $end
$var wire 8 q% x [7:0] $end
$var wire 32 r% product_ext [31:0] $end
$var wire 16 s% product [15:0] $end
$var wire 32 t% acc_out [31:0] $end
$var parameter 32 u% ACC_WIDTH $end
$var parameter 32 v% DATA_WIDTH $end
$var parameter 64 w% PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[1] $end
$var parameter 2 x% i $end
$scope module u_mac $end
$var wire 32 y% acc_in [31:0] $end
$var wire 8 z% w [7:0] $end
$var wire 8 {% x [7:0] $end
$var wire 32 |% product_ext [31:0] $end
$var wire 16 }% product [15:0] $end
$var wire 32 ~% acc_out [31:0] $end
$var parameter 32 !& ACC_WIDTH $end
$var parameter 32 "& DATA_WIDTH $end
$var parameter 64 #& PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[2] $end
$var parameter 3 $& i $end
$scope module u_mac $end
$var wire 32 %& acc_in [31:0] $end
$var wire 8 && w [7:0] $end
$var wire 8 '& x [7:0] $end
$var wire 32 (& product_ext [31:0] $end
$var wire 16 )& product [15:0] $end
$var wire 32 *& acc_out [31:0] $end
$var parameter 32 +& ACC_WIDTH $end
$var parameter 32 ,& DATA_WIDTH $end
$var parameter 64 -& PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[3] $end
$var parameter 3 .& i $end
$scope module u_mac $end
$var wire 32 /& acc_in [31:0] $end
$var wire 8 0& w [7:0] $end
$var wire 8 1& x [7:0] $end
$var wire 32 2& product_ext [31:0] $end
$var wire 16 3& product [15:0] $end
$var wire 32 4& acc_out [31:0] $end
$var parameter 32 5& ACC_WIDTH $end
$var parameter 32 6& DATA_WIDTH $end
$var parameter 64 7& PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[4] $end
$var parameter 4 8& i $end
$scope module u_mac $end
$var wire 32 9& acc_in [31:0] $end
$var wire 8 :& w [7:0] $end
$var wire 8 ;& x [7:0] $end
$var wire 32 <& product_ext [31:0] $end
$var wire 16 =& product [15:0] $end
$var wire 32 >& acc_out [31:0] $end
$var parameter 32 ?& ACC_WIDTH $end
$var parameter 32 @& DATA_WIDTH $end
$var parameter 64 A& PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[5] $end
$var parameter 4 B& i $end
$scope module u_mac $end
$var wire 32 C& acc_in [31:0] $end
$var wire 8 D& w [7:0] $end
$var wire 8 E& x [7:0] $end
$var wire 32 F& product_ext [31:0] $end
$var wire 16 G& product [15:0] $end
$var wire 32 H& acc_out [31:0] $end
$var parameter 32 I& ACC_WIDTH $end
$var parameter 32 J& DATA_WIDTH $end
$var parameter 64 K& PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[6] $end
$var parameter 4 L& i $end
$scope module u_mac $end
$var wire 32 M& acc_in [31:0] $end
$var wire 8 N& w [7:0] $end
$var wire 8 O& x [7:0] $end
$var wire 32 P& product_ext [31:0] $end
$var wire 16 Q& product [15:0] $end
$var wire 32 R& acc_out [31:0] $end
$var parameter 32 S& ACC_WIDTH $end
$var parameter 32 T& DATA_WIDTH $end
$var parameter 64 U& PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[7] $end
$var parameter 4 V& i $end
$scope module u_mac $end
$var wire 32 W& acc_in [31:0] $end
$var wire 8 X& w [7:0] $end
$var wire 8 Y& x [7:0] $end
$var wire 32 Z& product_ext [31:0] $end
$var wire 16 [& product [15:0] $end
$var wire 32 \& acc_out [31:0] $end
$var parameter 32 ]& ACC_WIDTH $end
$var parameter 32 ^& DATA_WIDTH $end
$var parameter 64 _& PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_INPUT[0] $end
$var parameter 2 `& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[1] $end
$var parameter 2 a& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[2] $end
$var parameter 3 b& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[3] $end
$var parameter 3 c& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[4] $end
$var parameter 4 d& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[5] $end
$var parameter 4 e& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[6] $end
$var parameter 4 f& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[7] $end
$var parameter 4 g& i $end
$upscope $end
$scope begin GEN_TREE_LEVEL[0] $end
$var parameter 2 h& level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 i& node $end
$upscope $end
$scope begin GEN_TREE_NODE[1] $end
$var parameter 2 j& node $end
$upscope $end
$scope begin GEN_TREE_NODE[2] $end
$var parameter 3 k& node $end
$upscope $end
$scope begin GEN_TREE_NODE[3] $end
$var parameter 3 l& node $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_LEVEL[1] $end
$var parameter 2 m& level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 n& node $end
$upscope $end
$scope begin GEN_TREE_NODE[1] $end
$var parameter 2 o& node $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_LEVEL[2] $end
$var parameter 3 p& level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 q& node $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$scope begin GEN_NEURON[4] $end
$var parameter 4 r& n $end
$scope module u_neuron $end
$var wire 2 s& activation [1:0] $end
$var wire 8 t& bias [7:0] $end
$var wire 1 * clk $end
$var wire 16 u& n_inputs_real [15:0] $end
$var wire 1 + rst $end
$var wire 1 , start $end
$var wire 256 v& w_bus [255:0] $end
$var wire 256 w& x_bus [255:0] $end
$var wire 64 x& x_group [63:0] $end
$var wire 64 y& w_group [63:0] $end
$var wire 16 z& groups_real [15:0] $end
$var wire 32 {& final_acc [31:0] $end
$var wire 32 |& bias_ext [31:0] $end
$var wire 32 }& acc_next [31:0] $end
$var parameter 32 ~& ACC_WIDTH $end
$var parameter 2 !' ACT_NONE $end
$var parameter 2 "' ACT_RELU $end
$var parameter 32 #' DATA_WIDTH $end
$var parameter 32 $' GROUPS $end
$var parameter 32 %' GROUP_INDEX_WIDTH $end
$var parameter 32 &' N_INPUTS $end
$var parameter 32 '' PARALLEL $end
$var reg 32 (' acc [31:0] $end
$var reg 1 )' busy $end
$var reg 1 *' done $end
$var reg 2 +' group_index [1:0] $end
$var reg 8 ,' y [7:0] $end
$scope module u_mac8 $end
$var wire 32 -' acc_in [31:0] $end
$var wire 64 .' w_bus [63:0] $end
$var wire 64 /' x_bus [63:0] $end
$var wire 32 0' acc_out [31:0] $end
$var parameter 32 1' ACC_WIDTH $end
$var parameter 32 2' DATA_WIDTH $end
$var parameter 32 3' PARALLEL $end
$var parameter 32 4' TREE_LEVELS $end
$scope begin GEN_MAC[0] $end
$var parameter 2 5' i $end
$scope module u_mac $end
$var wire 32 6' acc_in [31:0] $end
$var wire 8 7' w [7:0] $end
$var wire 8 8' x [7:0] $end
$var wire 32 9' product_ext [31:0] $end
$var wire 16 :' product [15:0] $end
$var wire 32 ;' acc_out [31:0] $end
$var parameter 32 <' ACC_WIDTH $end
$var parameter 32 =' DATA_WIDTH $end
$var parameter 64 >' PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[1] $end
$var parameter 2 ?' i $end
$scope module u_mac $end
$var wire 32 @' acc_in [31:0] $end
$var wire 8 A' w [7:0] $end
$var wire 8 B' x [7:0] $end
$var wire 32 C' product_ext [31:0] $end
$var wire 16 D' product [15:0] $end
$var wire 32 E' acc_out [31:0] $end
$var parameter 32 F' ACC_WIDTH $end
$var parameter 32 G' DATA_WIDTH $end
$var parameter 64 H' PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[2] $end
$var parameter 3 I' i $end
$scope module u_mac $end
$var wire 32 J' acc_in [31:0] $end
$var wire 8 K' w [7:0] $end
$var wire 8 L' x [7:0] $end
$var wire 32 M' product_ext [31:0] $end
$var wire 16 N' product [15:0] $end
$var wire 32 O' acc_out [31:0] $end
$var parameter 32 P' ACC_WIDTH $end
$var parameter 32 Q' DATA_WIDTH $end
$var parameter 64 R' PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[3] $end
$var parameter 3 S' i $end
$scope module u_mac $end
$var wire 32 T' acc_in [31:0] $end
$var wire 8 U' w [7:0] $end
$var wire 8 V' x [7:0] $end
$var wire 32 W' product_ext [31:0] $end
$var wire 16 X' product [15:0] $end
$var wire 32 Y' acc_out [31:0] $end
$var parameter 32 Z' ACC_WIDTH $end
$var parameter 32 [' DATA_WIDTH $end
$var parameter 64 \' PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[4] $end
$var parameter 4 ]' i $end
$scope module u_mac $end
$var wire 32 ^' acc_in [31:0] $end
$var wire 8 _' w [7:0] $end
$var wire 8 `' x [7:0] $end
$var wire 32 a' product_ext [31:0] $end
$var wire 16 b' product [15:0] $end
$var wire 32 c' acc_out [31:0] $end
$var parameter 32 d' ACC_WIDTH $end
$var parameter 32 e' DATA_WIDTH $end
$var parameter 64 f' PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[5] $end
$var parameter 4 g' i $end
$scope module u_mac $end
$var wire 32 h' acc_in [31:0] $end
$var wire 8 i' w [7:0] $end
$var wire 8 j' x [7:0] $end
$var wire 32 k' product_ext [31:0] $end
$var wire 16 l' product [15:0] $end
$var wire 32 m' acc_out [31:0] $end
$var parameter 32 n' ACC_WIDTH $end
$var parameter 32 o' DATA_WIDTH $end
$var parameter 64 p' PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[6] $end
$var parameter 4 q' i $end
$scope module u_mac $end
$var wire 32 r' acc_in [31:0] $end
$var wire 8 s' w [7:0] $end
$var wire 8 t' x [7:0] $end
$var wire 32 u' product_ext [31:0] $end
$var wire 16 v' product [15:0] $end
$var wire 32 w' acc_out [31:0] $end
$var parameter 32 x' ACC_WIDTH $end
$var parameter 32 y' DATA_WIDTH $end
$var parameter 64 z' PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[7] $end
$var parameter 4 {' i $end
$scope module u_mac $end
$var wire 32 |' acc_in [31:0] $end
$var wire 8 }' w [7:0] $end
$var wire 8 ~' x [7:0] $end
$var wire 32 !( product_ext [31:0] $end
$var wire 16 "( product [15:0] $end
$var wire 32 #( acc_out [31:0] $end
$var parameter 32 $( ACC_WIDTH $end
$var parameter 32 %( DATA_WIDTH $end
$var parameter 64 &( PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_INPUT[0] $end
$var parameter 2 '( i $end
$upscope $end
$scope begin GEN_TREE_INPUT[1] $end
$var parameter 2 (( i $end
$upscope $end
$scope begin GEN_TREE_INPUT[2] $end
$var parameter 3 )( i $end
$upscope $end
$scope begin GEN_TREE_INPUT[3] $end
$var parameter 3 *( i $end
$upscope $end
$scope begin GEN_TREE_INPUT[4] $end
$var parameter 4 +( i $end
$upscope $end
$scope begin GEN_TREE_INPUT[5] $end
$var parameter 4 ,( i $end
$upscope $end
$scope begin GEN_TREE_INPUT[6] $end
$var parameter 4 -( i $end
$upscope $end
$scope begin GEN_TREE_INPUT[7] $end
$var parameter 4 .( i $end
$upscope $end
$scope begin GEN_TREE_LEVEL[0] $end
$var parameter 2 /( level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 0( node $end
$upscope $end
$scope begin GEN_TREE_NODE[1] $end
$var parameter 2 1( node $end
$upscope $end
$scope begin GEN_TREE_NODE[2] $end
$var parameter 3 2( node $end
$upscope $end
$scope begin GEN_TREE_NODE[3] $end
$var parameter 3 3( node $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_LEVEL[1] $end
$var parameter 2 4( level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 5( node $end
$upscope $end
$scope begin GEN_TREE_NODE[1] $end
$var parameter 2 6( node $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_LEVEL[2] $end
$var parameter 3 7( level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 8( node $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$scope begin GEN_NEURON[5] $end
$var parameter 4 9( n $end
$scope module u_neuron $end
$var wire 2 :( activation [1:0] $end
$var wire 8 ;( bias [7:0] $end
$var wire 1 * clk $end
$var wire 16 <( n_inputs_real [15:0] $end
$var wire 1 + rst $end
$var wire 1 , start $end
$var wire 256 =( w_bus [255:0] $end
$var wire 256 >( x_bus [255:0] $end
$var wire 64 ?( x_group [63:0] $end
$var wire 64 @( w_group [63:0] $end
$var wire 16 A( groups_real [15:0] $end
$var wire 32 B( final_acc [31:0] $end
$var wire 32 C( bias_ext [31:0] $end
$var wire 32 D( acc_next [31:0] $end
$var parameter 32 E( ACC_WIDTH $end
$var parameter 2 F( ACT_NONE $end
$var parameter 2 G( ACT_RELU $end
$var parameter 32 H( DATA_WIDTH $end
$var parameter 32 I( GROUPS $end
$var parameter 32 J( GROUP_INDEX_WIDTH $end
$var parameter 32 K( N_INPUTS $end
$var parameter 32 L( PARALLEL $end
$var reg 32 M( acc [31:0] $end
$var reg 1 N( busy $end
$var reg 1 O( done $end
$var reg 2 P( group_index [1:0] $end
$var reg 8 Q( y [7:0] $end
$scope module u_mac8 $end
$var wire 32 R( acc_in [31:0] $end
$var wire 64 S( w_bus [63:0] $end
$var wire 64 T( x_bus [63:0] $end
$var wire 32 U( acc_out [31:0] $end
$var parameter 32 V( ACC_WIDTH $end
$var parameter 32 W( DATA_WIDTH $end
$var parameter 32 X( PARALLEL $end
$var parameter 32 Y( TREE_LEVELS $end
$scope begin GEN_MAC[0] $end
$var parameter 2 Z( i $end
$scope module u_mac $end
$var wire 32 [( acc_in [31:0] $end
$var wire 8 \( w [7:0] $end
$var wire 8 ]( x [7:0] $end
$var wire 32 ^( product_ext [31:0] $end
$var wire 16 _( product [15:0] $end
$var wire 32 `( acc_out [31:0] $end
$var parameter 32 a( ACC_WIDTH $end
$var parameter 32 b( DATA_WIDTH $end
$var parameter 64 c( PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[1] $end
$var parameter 2 d( i $end
$scope module u_mac $end
$var wire 32 e( acc_in [31:0] $end
$var wire 8 f( w [7:0] $end
$var wire 8 g( x [7:0] $end
$var wire 32 h( product_ext [31:0] $end
$var wire 16 i( product [15:0] $end
$var wire 32 j( acc_out [31:0] $end
$var parameter 32 k( ACC_WIDTH $end
$var parameter 32 l( DATA_WIDTH $end
$var parameter 64 m( PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[2] $end
$var parameter 3 n( i $end
$scope module u_mac $end
$var wire 32 o( acc_in [31:0] $end
$var wire 8 p( w [7:0] $end
$var wire 8 q( x [7:0] $end
$var wire 32 r( product_ext [31:0] $end
$var wire 16 s( product [15:0] $end
$var wire 32 t( acc_out [31:0] $end
$var parameter 32 u( ACC_WIDTH $end
$var parameter 32 v( DATA_WIDTH $end
$var parameter 64 w( PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[3] $end
$var parameter 3 x( i $end
$scope module u_mac $end
$var wire 32 y( acc_in [31:0] $end
$var wire 8 z( w [7:0] $end
$var wire 8 {( x [7:0] $end
$var wire 32 |( product_ext [31:0] $end
$var wire 16 }( product [15:0] $end
$var wire 32 ~( acc_out [31:0] $end
$var parameter 32 !) ACC_WIDTH $end
$var parameter 32 ") DATA_WIDTH $end
$var parameter 64 #) PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[4] $end
$var parameter 4 $) i $end
$scope module u_mac $end
$var wire 32 %) acc_in [31:0] $end
$var wire 8 &) w [7:0] $end
$var wire 8 ') x [7:0] $end
$var wire 32 () product_ext [31:0] $end
$var wire 16 )) product [15:0] $end
$var wire 32 *) acc_out [31:0] $end
$var parameter 32 +) ACC_WIDTH $end
$var parameter 32 ,) DATA_WIDTH $end
$var parameter 64 -) PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[5] $end
$var parameter 4 .) i $end
$scope module u_mac $end
$var wire 32 /) acc_in [31:0] $end
$var wire 8 0) w [7:0] $end
$var wire 8 1) x [7:0] $end
$var wire 32 2) product_ext [31:0] $end
$var wire 16 3) product [15:0] $end
$var wire 32 4) acc_out [31:0] $end
$var parameter 32 5) ACC_WIDTH $end
$var parameter 32 6) DATA_WIDTH $end
$var parameter 64 7) PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[6] $end
$var parameter 4 8) i $end
$scope module u_mac $end
$var wire 32 9) acc_in [31:0] $end
$var wire 8 :) w [7:0] $end
$var wire 8 ;) x [7:0] $end
$var wire 32 <) product_ext [31:0] $end
$var wire 16 =) product [15:0] $end
$var wire 32 >) acc_out [31:0] $end
$var parameter 32 ?) ACC_WIDTH $end
$var parameter 32 @) DATA_WIDTH $end
$var parameter 64 A) PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[7] $end
$var parameter 4 B) i $end
$scope module u_mac $end
$var wire 32 C) acc_in [31:0] $end
$var wire 8 D) w [7:0] $end
$var wire 8 E) x [7:0] $end
$var wire 32 F) product_ext [31:0] $end
$var wire 16 G) product [15:0] $end
$var wire 32 H) acc_out [31:0] $end
$var parameter 32 I) ACC_WIDTH $end
$var parameter 32 J) DATA_WIDTH $end
$var parameter 64 K) PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_INPUT[0] $end
$var parameter 2 L) i $end
$upscope $end
$scope begin GEN_TREE_INPUT[1] $end
$var parameter 2 M) i $end
$upscope $end
$scope begin GEN_TREE_INPUT[2] $end
$var parameter 3 N) i $end
$upscope $end
$scope begin GEN_TREE_INPUT[3] $end
$var parameter 3 O) i $end
$upscope $end
$scope begin GEN_TREE_INPUT[4] $end
$var parameter 4 P) i $end
$upscope $end
$scope begin GEN_TREE_INPUT[5] $end
$var parameter 4 Q) i $end
$upscope $end
$scope begin GEN_TREE_INPUT[6] $end
$var parameter 4 R) i $end
$upscope $end
$scope begin GEN_TREE_INPUT[7] $end
$var parameter 4 S) i $end
$upscope $end
$scope begin GEN_TREE_LEVEL[0] $end
$var parameter 2 T) level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 U) node $end
$upscope $end
$scope begin GEN_TREE_NODE[1] $end
$var parameter 2 V) node $end
$upscope $end
$scope begin GEN_TREE_NODE[2] $end
$var parameter 3 W) node $end
$upscope $end
$scope begin GEN_TREE_NODE[3] $end
$var parameter 3 X) node $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_LEVEL[1] $end
$var parameter 2 Y) level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 Z) node $end
$upscope $end
$scope begin GEN_TREE_NODE[1] $end
$var parameter 2 [) node $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_LEVEL[2] $end
$var parameter 3 \) level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 ]) node $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$scope begin GEN_NEURON[6] $end
$var parameter 4 ^) n $end
$scope module u_neuron $end
$var wire 2 _) activation [1:0] $end
$var wire 8 `) bias [7:0] $end
$var wire 1 * clk $end
$var wire 16 a) n_inputs_real [15:0] $end
$var wire 1 + rst $end
$var wire 1 , start $end
$var wire 256 b) w_bus [255:0] $end
$var wire 256 c) x_bus [255:0] $end
$var wire 64 d) x_group [63:0] $end
$var wire 64 e) w_group [63:0] $end
$var wire 16 f) groups_real [15:0] $end
$var wire 32 g) final_acc [31:0] $end
$var wire 32 h) bias_ext [31:0] $end
$var wire 32 i) acc_next [31:0] $end
$var parameter 32 j) ACC_WIDTH $end
$var parameter 2 k) ACT_NONE $end
$var parameter 2 l) ACT_RELU $end
$var parameter 32 m) DATA_WIDTH $end
$var parameter 32 n) GROUPS $end
$var parameter 32 o) GROUP_INDEX_WIDTH $end
$var parameter 32 p) N_INPUTS $end
$var parameter 32 q) PARALLEL $end
$var reg 32 r) acc [31:0] $end
$var reg 1 s) busy $end
$var reg 1 t) done $end
$var reg 2 u) group_index [1:0] $end
$var reg 8 v) y [7:0] $end
$scope module u_mac8 $end
$var wire 32 w) acc_in [31:0] $end
$var wire 64 x) w_bus [63:0] $end
$var wire 64 y) x_bus [63:0] $end
$var wire 32 z) acc_out [31:0] $end
$var parameter 32 {) ACC_WIDTH $end
$var parameter 32 |) DATA_WIDTH $end
$var parameter 32 }) PARALLEL $end
$var parameter 32 ~) TREE_LEVELS $end
$scope begin GEN_MAC[0] $end
$var parameter 2 !* i $end
$scope module u_mac $end
$var wire 32 "* acc_in [31:0] $end
$var wire 8 #* w [7:0] $end
$var wire 8 $* x [7:0] $end
$var wire 32 %* product_ext [31:0] $end
$var wire 16 &* product [15:0] $end
$var wire 32 '* acc_out [31:0] $end
$var parameter 32 (* ACC_WIDTH $end
$var parameter 32 )* DATA_WIDTH $end
$var parameter 64 ** PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[1] $end
$var parameter 2 +* i $end
$scope module u_mac $end
$var wire 32 ,* acc_in [31:0] $end
$var wire 8 -* w [7:0] $end
$var wire 8 .* x [7:0] $end
$var wire 32 /* product_ext [31:0] $end
$var wire 16 0* product [15:0] $end
$var wire 32 1* acc_out [31:0] $end
$var parameter 32 2* ACC_WIDTH $end
$var parameter 32 3* DATA_WIDTH $end
$var parameter 64 4* PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[2] $end
$var parameter 3 5* i $end
$scope module u_mac $end
$var wire 32 6* acc_in [31:0] $end
$var wire 8 7* w [7:0] $end
$var wire 8 8* x [7:0] $end
$var wire 32 9* product_ext [31:0] $end
$var wire 16 :* product [15:0] $end
$var wire 32 ;* acc_out [31:0] $end
$var parameter 32 <* ACC_WIDTH $end
$var parameter 32 =* DATA_WIDTH $end
$var parameter 64 >* PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[3] $end
$var parameter 3 ?* i $end
$scope module u_mac $end
$var wire 32 @* acc_in [31:0] $end
$var wire 8 A* w [7:0] $end
$var wire 8 B* x [7:0] $end
$var wire 32 C* product_ext [31:0] $end
$var wire 16 D* product [15:0] $end
$var wire 32 E* acc_out [31:0] $end
$var parameter 32 F* ACC_WIDTH $end
$var parameter 32 G* DATA_WIDTH $end
$var parameter 64 H* PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[4] $end
$var parameter 4 I* i $end
$scope module u_mac $end
$var wire 32 J* acc_in [31:0] $end
$var wire 8 K* w [7:0] $end
$var wire 8 L* x [7:0] $end
$var wire 32 M* product_ext [31:0] $end
$var wire 16 N* product [15:0] $end
$var wire 32 O* acc_out [31:0] $end
$var parameter 32 P* ACC_WIDTH $end
$var parameter 32 Q* DATA_WIDTH $end
$var parameter 64 R* PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[5] $end
$var parameter 4 S* i $end
$scope module u_mac $end
$var wire 32 T* acc_in [31:0] $end
$var wire 8 U* w [7:0] $end
$var wire 8 V* x [7:0] $end
$var wire 32 W* product_ext [31:0] $end
$var wire 16 X* product [15:0] $end
$var wire 32 Y* acc_out [31:0] $end
$var parameter 32 Z* ACC_WIDTH $end
$var parameter 32 [* DATA_WIDTH $end
$var parameter 64 \* PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[6] $end
$var parameter 4 ]* i $end
$scope module u_mac $end
$var wire 32 ^* acc_in [31:0] $end
$var wire 8 _* w [7:0] $end
$var wire 8 `* x [7:0] $end
$var wire 32 a* product_ext [31:0] $end
$var wire 16 b* product [15:0] $end
$var wire 32 c* acc_out [31:0] $end
$var parameter 32 d* ACC_WIDTH $end
$var parameter 32 e* DATA_WIDTH $end
$var parameter 64 f* PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[7] $end
$var parameter 4 g* i $end
$scope module u_mac $end
$var wire 32 h* acc_in [31:0] $end
$var wire 8 i* w [7:0] $end
$var wire 8 j* x [7:0] $end
$var wire 32 k* product_ext [31:0] $end
$var wire 16 l* product [15:0] $end
$var wire 32 m* acc_out [31:0] $end
$var parameter 32 n* ACC_WIDTH $end
$var parameter 32 o* DATA_WIDTH $end
$var parameter 64 p* PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_INPUT[0] $end
$var parameter 2 q* i $end
$upscope $end
$scope begin GEN_TREE_INPUT[1] $end
$var parameter 2 r* i $end
$upscope $end
$scope begin GEN_TREE_INPUT[2] $end
$var parameter 3 s* i $end
$upscope $end
$scope begin GEN_TREE_INPUT[3] $end
$var parameter 3 t* i $end
$upscope $end
$scope begin GEN_TREE_INPUT[4] $end
$var parameter 4 u* i $end
$upscope $end
$scope begin GEN_TREE_INPUT[5] $end
$var parameter 4 v* i $end
$upscope $end
$scope begin GEN_TREE_INPUT[6] $end
$var parameter 4 w* i $end
$upscope $end
$scope begin GEN_TREE_INPUT[7] $end
$var parameter 4 x* i $end
$upscope $end
$scope begin GEN_TREE_LEVEL[0] $end
$var parameter 2 y* level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 z* node $end
$upscope $end
$scope begin GEN_TREE_NODE[1] $end
$var parameter 2 {* node $end
$upscope $end
$scope begin GEN_TREE_NODE[2] $end
$var parameter 3 |* node $end
$upscope $end
$scope begin GEN_TREE_NODE[3] $end
$var parameter 3 }* node $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_LEVEL[1] $end
$var parameter 2 ~* level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 !+ node $end
$upscope $end
$scope begin GEN_TREE_NODE[1] $end
$var parameter 2 "+ node $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_LEVEL[2] $end
$var parameter 3 #+ level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 $+ node $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$scope begin GEN_NEURON[7] $end
$var parameter 4 %+ n $end
$scope module u_neuron $end
$var wire 2 &+ activation [1:0] $end
$var wire 8 '+ bias [7:0] $end
$var wire 1 * clk $end
$var wire 16 (+ n_inputs_real [15:0] $end
$var wire 1 + rst $end
$var wire 1 , start $end
$var wire 256 )+ w_bus [255:0] $end
$var wire 256 *+ x_bus [255:0] $end
$var wire 64 ++ x_group [63:0] $end
$var wire 64 ,+ w_group [63:0] $end
$var wire 16 -+ groups_real [15:0] $end
$var wire 32 .+ final_acc [31:0] $end
$var wire 32 /+ bias_ext [31:0] $end
$var wire 32 0+ acc_next [31:0] $end
$var parameter 32 1+ ACC_WIDTH $end
$var parameter 2 2+ ACT_NONE $end
$var parameter 2 3+ ACT_RELU $end
$var parameter 32 4+ DATA_WIDTH $end
$var parameter 32 5+ GROUPS $end
$var parameter 32 6+ GROUP_INDEX_WIDTH $end
$var parameter 32 7+ N_INPUTS $end
$var parameter 32 8+ PARALLEL $end
$var reg 32 9+ acc [31:0] $end
$var reg 1 :+ busy $end
$var reg 1 ;+ done $end
$var reg 2 <+ group_index [1:0] $end
$var reg 8 =+ y [7:0] $end
$scope module u_mac8 $end
$var wire 32 >+ acc_in [31:0] $end
$var wire 64 ?+ w_bus [63:0] $end
$var wire 64 @+ x_bus [63:0] $end
$var wire 32 A+ acc_out [31:0] $end
$var parameter 32 B+ ACC_WIDTH $end
$var parameter 32 C+ DATA_WIDTH $end
$var parameter 32 D+ PARALLEL $end
$var parameter 32 E+ TREE_LEVELS $end
$scope begin GEN_MAC[0] $end
$var parameter 2 F+ i $end
$scope module u_mac $end
$var wire 32 G+ acc_in [31:0] $end
$var wire 8 H+ w [7:0] $end
$var wire 8 I+ x [7:0] $end
$var wire 32 J+ product_ext [31:0] $end
$var wire 16 K+ product [15:0] $end
$var wire 32 L+ acc_out [31:0] $end
$var parameter 32 M+ ACC_WIDTH $end
$var parameter 32 N+ DATA_WIDTH $end
$var parameter 64 O+ PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[1] $end
$var parameter 2 P+ i $end
$scope module u_mac $end
$var wire 32 Q+ acc_in [31:0] $end
$var wire 8 R+ w [7:0] $end
$var wire 8 S+ x [7:0] $end
$var wire 32 T+ product_ext [31:0] $end
$var wire 16 U+ product [15:0] $end
$var wire 32 V+ acc_out [31:0] $end
$var parameter 32 W+ ACC_WIDTH $end
$var parameter 32 X+ DATA_WIDTH $end
$var parameter 64 Y+ PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[2] $end
$var parameter 3 Z+ i $end
$scope module u_mac $end
$var wire 32 [+ acc_in [31:0] $end
$var wire 8 \+ w [7:0] $end
$var wire 8 ]+ x [7:0] $end
$var wire 32 ^+ product_ext [31:0] $end
$var wire 16 _+ product [15:0] $end
$var wire 32 `+ acc_out [31:0] $end
$var parameter 32 a+ ACC_WIDTH $end
$var parameter 32 b+ DATA_WIDTH $end
$var parameter 64 c+ PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[3] $end
$var parameter 3 d+ i $end
$scope module u_mac $end
$var wire 32 e+ acc_in [31:0] $end
$var wire 8 f+ w [7:0] $end
$var wire 8 g+ x [7:0] $end
$var wire 32 h+ product_ext [31:0] $end
$var wire 16 i+ product [15:0] $end
$var wire 32 j+ acc_out [31:0] $end
$var parameter 32 k+ ACC_WIDTH $end
$var parameter 32 l+ DATA_WIDTH $end
$var parameter 64 m+ PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[4] $end
$var parameter 4 n+ i $end
$scope module u_mac $end
$var wire 32 o+ acc_in [31:0] $end
$var wire 8 p+ w [7:0] $end
$var wire 8 q+ x [7:0] $end
$var wire 32 r+ product_ext [31:0] $end
$var wire 16 s+ product [15:0] $end
$var wire 32 t+ acc_out [31:0] $end
$var parameter 32 u+ ACC_WIDTH $end
$var parameter 32 v+ DATA_WIDTH $end
$var parameter 64 w+ PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[5] $end
$var parameter 4 x+ i $end
$scope module u_mac $end
$var wire 32 y+ acc_in [31:0] $end
$var wire 8 z+ w [7:0] $end
$var wire 8 {+ x [7:0] $end
$var wire 32 |+ product_ext [31:0] $end
$var wire 16 }+ product [15:0] $end
$var wire 32 ~+ acc_out [31:0] $end
$var parameter 32 !, ACC_WIDTH $end
$var parameter 32 ", DATA_WIDTH $end
$var parameter 64 #, PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[6] $end
$var parameter 4 $, i $end
$scope module u_mac $end
$var wire 32 %, acc_in [31:0] $end
$var wire 8 &, w [7:0] $end
$var wire 8 ', x [7:0] $end
$var wire 32 (, product_ext [31:0] $end
$var wire 16 ), product [15:0] $end
$var wire 32 *, acc_out [31:0] $end
$var parameter 32 +, ACC_WIDTH $end
$var parameter 32 ,, DATA_WIDTH $end
$var parameter 64 -, PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[7] $end
$var parameter 4 ., i $end
$scope module u_mac $end
$var wire 32 /, acc_in [31:0] $end
$var wire 8 0, w [7:0] $end
$var wire 8 1, x [7:0] $end
$var wire 32 2, product_ext [31:0] $end
$var wire 16 3, product [15:0] $end
$var wire 32 4, acc_out [31:0] $end
$var parameter 32 5, ACC_WIDTH $end
$var parameter 32 6, DATA_WIDTH $end
$var parameter 64 7, PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_INPUT[0] $end
$var parameter 2 8, i $end
$upscope $end
$scope begin GEN_TREE_INPUT[1] $end
$var parameter 2 9, i $end
$upscope $end
$scope begin GEN_TREE_INPUT[2] $end
$var parameter 3 :, i $end
$upscope $end
$scope begin GEN_TREE_INPUT[3] $end
$var parameter 3 ;, i $end
$upscope $end
$scope begin GEN_TREE_INPUT[4] $end
$var parameter 4 <, i $end
$upscope $end
$scope begin GEN_TREE_INPUT[5] $end
$var parameter 4 =, i $end
$upscope $end
$scope begin GEN_TREE_INPUT[6] $end
$var parameter 4 >, i $end
$upscope $end
$scope begin GEN_TREE_INPUT[7] $end
$var parameter 4 ?, i $end
$upscope $end
$scope begin GEN_TREE_LEVEL[0] $end
$var parameter 2 @, level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 A, node $end
$upscope $end
$scope begin GEN_TREE_NODE[1] $end
$var parameter 2 B, node $end
$upscope $end
$scope begin GEN_TREE_NODE[2] $end
$var parameter 3 C, node $end
$upscope $end
$scope begin GEN_TREE_NODE[3] $end
$var parameter 3 D, node $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_LEVEL[1] $end
$var parameter 2 E, level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 F, node $end
$upscope $end
$scope begin GEN_TREE_NODE[1] $end
$var parameter 2 G, node $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_LEVEL[2] $end
$var parameter 3 H, level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 I, node $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$scope task run_layer $end
$upscope $end
$upscope $end
$enddefinitions $end
$comment Show the parameter values. $end
$dumpall
b0 I,
b10 H,
b1 G,
b0 F,
b1 E,
b11 D,
b10 C,
b1 B,
b0 A,
b0 @,
b111 ?,
b110 >,
b101 =,
b100 <,
b11 ;,
b10 :,
b1 9,
b0 8,
b10000 7,
b1000 6,
b100000 5,
b111 .,
b10000 -,
b1000 ,,
b100000 +,
b110 $,
b10000 #,
b1000 ",
b100000 !,
b101 x+
b10000 w+
b1000 v+
b100000 u+
b100 n+
b10000 m+
b1000 l+
b100000 k+
b11 d+
b10000 c+
b1000 b+
b100000 a+
b10 Z+
b10000 Y+
b1000 X+
b100000 W+
b1 P+
b10000 O+
b1000 N+
b100000 M+
b0 F+
b11 E+
b1000 D+
b1000 C+
b100000 B+
b1000 8+
b100000 7+
b10 6+
b100 5+
b1000 4+
b1 3+
b0 2+
b100000 1+
b111 %+
b0 $+
b10 #+
b1 "+
b0 !+
b1 ~*
b11 }*
b10 |*
b1 {*
b0 z*
b0 y*
b111 x*
b110 w*
b101 v*
b100 u*
b11 t*
b10 s*
b1 r*
b0 q*
b10000 p*
b1000 o*
b100000 n*
b111 g*
b10000 f*
b1000 e*
b100000 d*
b110 ]*
b10000 \*
b1000 [*
b100000 Z*
b101 S*
b10000 R*
b1000 Q*
b100000 P*
b100 I*
b10000 H*
b1000 G*
b100000 F*
b11 ?*
b10000 >*
b1000 =*
b100000 <*
b10 5*
b10000 4*
b1000 3*
b100000 2*
b1 +*
b10000 **
b1000 )*
b100000 (*
b0 !*
b11 ~)
b1000 })
b1000 |)
b100000 {)
b1000 q)
b100000 p)
b10 o)
b100 n)
b1000 m)
b1 l)
b0 k)
b100000 j)
b110 ^)
b0 ])
b10 \)
b1 [)
b0 Z)
b1 Y)
b11 X)
b10 W)
b1 V)
b0 U)
b0 T)
b111 S)
b110 R)
b101 Q)
b100 P)
b11 O)
b10 N)
b1 M)
b0 L)
b10000 K)
b1000 J)
b100000 I)
b111 B)
b10000 A)
b1000 @)
b100000 ?)
b110 8)
b10000 7)
b1000 6)
b100000 5)
b101 .)
b10000 -)
b1000 ,)
b100000 +)
b100 $)
b10000 #)
b1000 ")
b100000 !)
b11 x(
b10000 w(
b1000 v(
b100000 u(
b10 n(
b10000 m(
b1000 l(
b100000 k(
b1 d(
b10000 c(
b1000 b(
b100000 a(
b0 Z(
b11 Y(
b1000 X(
b1000 W(
b100000 V(
b1000 L(
b100000 K(
b10 J(
b100 I(
b1000 H(
b1 G(
b0 F(
b100000 E(
b101 9(
b0 8(
b10 7(
b1 6(
b0 5(
b1 4(
b11 3(
b10 2(
b1 1(
b0 0(
b0 /(
b111 .(
b110 -(
b101 ,(
b100 +(
b11 *(
b10 )(
b1 ((
b0 '(
b10000 &(
b1000 %(
b100000 $(
b111 {'
b10000 z'
b1000 y'
b100000 x'
b110 q'
b10000 p'
b1000 o'
b100000 n'
b101 g'
b10000 f'
b1000 e'
b100000 d'
b100 ]'
b10000 \'
b1000 ['
b100000 Z'
b11 S'
b10000 R'
b1000 Q'
b100000 P'
b10 I'
b10000 H'
b1000 G'
b100000 F'
b1 ?'
b10000 >'
b1000 ='
b100000 <'
b0 5'
b11 4'
b1000 3'
b1000 2'
b100000 1'
b1000 ''
b100000 &'
b10 %'
b100 $'
b1000 #'
b1 "'
b0 !'
b100000 ~&
b100 r&
b0 q&
b10 p&
b1 o&
b0 n&
b1 m&
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