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7e2711fa2734241e5388cb768a7e03a4cd50acdc
FPGA-Neural/sim/parameter_sweep.vcd
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micheleandClaude Sonnet 5 7e2711fa27 feat: widen ADDR_WIDTH to 23 bits for full 8MB PSRAM addressing 
Bumps ADDR_WIDTH's default from 22 to 23 bits across every RTL
module (neuron_memory, layer_sequencer, spi_engine, spi_neuron_top,
mem_arbiter, int8_memory_access, memory_interface, psram_controller,
memory_model) and every testbench that mirrors it, so the system's
byte-address space reaches the full 8 MiB the recommended PSRAM part
(ISSI IS66WVE4M16EBLL-70BLI, docs/FPGA-Neural-Hardware-Design.md §3)
actually provides -- previously only 4 MiB (half the chip) was
reachable, since int8_memory_access.v's byte->word address shift
(addr >> 1) turned the old 22-bit byte address into only 21 real word
bits, one short of the chip's real 22-bit word address (A0-A21). At
23 bits, that same shift lands exactly on all 22 chip address lines,
so the whole part is usable now instead of deferred to a future
widening.

Also fixes a stray 22'd11-sized literal in layer_sequencer.v's
descriptor-table address increment (numerically already safe via
Verilog's zero-extension, but now correctly unsized so it always
matches ADDR_WIDTH instead of silently assuming 22).

Updated docs/FPGA-NeuralNetwork-Engine.md's SPI protocol address-field
note (23 bits, top 1 reserved bit instead of 2) and
docs/FPGA-Neural-Hardware-Design.md's PSRAM section (the "chip has
one spare address line" framing is gone now that all 22 are wired
and used).

Full regression (all 11 ADDR_WIDTH-touching testbenches, plus a
Yosys elaboration check of spi_neuron_top with the new default and
no override) passes clean.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01WQV3vS9TXaGDJ5cRfnfidt
2026-09-02 21:00:46 +02:00

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$date
Wed Sep 2 20:58:26 2026
$end
$version
Icarus Verilog
$end
$timescale
1ps
$end
$scope module tb $end
$var wire 8 ! y_g [7:0] $end
$var wire 8 " y_f [7:0] $end
$var wire 8 # y_d [7:0] $end
$var wire 8 $ y_a [7:0] $end
$var wire 1 % done_g $end
$var wire 1 & done_f $end
$var wire 1 ' done_d $end
$var wire 1 ( done_a $end
$var wire 1 ) busy_g $end
$var wire 1 * busy_f $end
$var wire 1 + busy_d $end
$var wire 1 , busy_a $end
$var parameter 32 - A_ACC_WIDTH $end
$var parameter 32 . A_DATA_WIDTH $end
$var parameter 32 / A_N_INPUTS $end
$var parameter 32 0 A_PARALLEL $end
$var parameter 32 1 D_ACC_WIDTH $end
$var parameter 32 2 D_DATA_WIDTH $end
$var parameter 32 3 D_N_INPUTS $end
$var parameter 32 4 D_PARALLEL $end
$var parameter 32 5 F_ACC_WIDTH $end
$var parameter 32 6 F_DATA_WIDTH $end
$var parameter 32 7 F_N_INPUTS $end
$var parameter 32 8 F_PARALLEL $end
$var parameter 32 9 G_ACC_WIDTH $end
$var parameter 32 : G_DATA_WIDTH $end
$var parameter 32 ; G_N_INPUTS $end
$var parameter 32 < G_PARALLEL $end
$var reg 8 = bias_a [7:0] $end
$var reg 8 > bias_d [7:0] $end
$var reg 8 ? bias_f [7:0] $end
$var reg 8 @ bias_g [7:0] $end
$var reg 1 A clk $end
$var reg 1 B rst $end
$var reg 1 C start_a $end
$var reg 1 D start_d $end
$var reg 1 E start_f $end
$var reg 1 F start_g $end
$var reg 256 G w_bus_a [255:0] $end
$var reg 512 H w_bus_d [511:0] $end
$var reg 256 I w_bus_f [255:0] $end
$var reg 256 J w_bus_g [255:0] $end
$var reg 256 K x_bus_a [255:0] $end
$var reg 512 L x_bus_d [511:0] $end
$var reg 256 M x_bus_f [255:0] $end
$var reg 256 N x_bus_g [255:0] $end
$var integer 32 O count [31:0] $end
$var integer 32 P errors [31:0] $end
$scope module u_a $end
$var wire 2 Q activation [1:0] $end
$var wire 8 R bias [7:0] $end
$var wire 1 A clk $end
$var wire 16 S n_inputs_real [15:0] $end
$var wire 1 B rst $end
$var wire 1 C start $end
$var wire 256 T w_bus [255:0] $end
$var wire 256 U x_bus [255:0] $end
$var wire 64 V x_group [63:0] $end
$var wire 64 W w_group [63:0] $end
$var wire 16 X groups_real [15:0] $end
$var wire 32 Y final_acc [31:0] $end
$var wire 32 Z bias_ext [31:0] $end
$var wire 32 [ acc_next [31:0] $end
$var parameter 32 \ ACC_WIDTH $end
$var parameter 2 ] ACT_NONE $end
$var parameter 2 ^ ACT_RELU $end
$var parameter 32 _ DATA_WIDTH $end
$var parameter 32 ` GROUPS $end
$var parameter 32 a GROUP_INDEX_WIDTH $end
$var parameter 32 b N_INPUTS $end
$var parameter 32 c PARALLEL $end
$var reg 32 d acc [31:0] $end
$var reg 1 , busy $end
$var reg 1 ( done $end
$var reg 2 e group_index [1:0] $end
$var reg 8 f y [7:0] $end
$scope module u_mac8 $end
$var wire 32 g acc_in [31:0] $end
$var wire 64 h w_bus [63:0] $end
$var wire 64 i x_bus [63:0] $end
$var wire 32 j acc_out [31:0] $end
$var parameter 32 k ACC_WIDTH $end
$var parameter 32 l DATA_WIDTH $end
$var parameter 32 m PARALLEL $end
$var parameter 32 n TREE_LEVELS $end
$scope begin GEN_MAC[0] $end
$var parameter 2 o i $end
$scope module u_mac $end
$var wire 32 p acc_in [31:0] $end
$var wire 8 q w [7:0] $end
$var wire 8 r x [7:0] $end
$var wire 32 s product_ext [31:0] $end
$var wire 16 t product [15:0] $end
$var wire 32 u acc_out [31:0] $end
$var parameter 32 v ACC_WIDTH $end
$var parameter 32 w DATA_WIDTH $end
$var parameter 64 x PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[1] $end
$var parameter 2 y i $end
$scope module u_mac $end
$var wire 32 z acc_in [31:0] $end
$var wire 8 { w [7:0] $end
$var wire 8 | x [7:0] $end
$var wire 32 } product_ext [31:0] $end
$var wire 16 ~ product [15:0] $end
$var wire 32 !" acc_out [31:0] $end
$var parameter 32 "" ACC_WIDTH $end
$var parameter 32 #" DATA_WIDTH $end
$var parameter 64 $" PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[2] $end
$var parameter 3 %" i $end
$scope module u_mac $end
$var wire 32 &" acc_in [31:0] $end
$var wire 8 '" w [7:0] $end
$var wire 8 (" x [7:0] $end
$var wire 32 )" product_ext [31:0] $end
$var wire 16 *" product [15:0] $end
$var wire 32 +" acc_out [31:0] $end
$var parameter 32 ," ACC_WIDTH $end
$var parameter 32 -" DATA_WIDTH $end
$var parameter 64 ." PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[3] $end
$var parameter 3 /" i $end
$scope module u_mac $end
$var wire 32 0" acc_in [31:0] $end
$var wire 8 1" w [7:0] $end
$var wire 8 2" x [7:0] $end
$var wire 32 3" product_ext [31:0] $end
$var wire 16 4" product [15:0] $end
$var wire 32 5" acc_out [31:0] $end
$var parameter 32 6" ACC_WIDTH $end
$var parameter 32 7" DATA_WIDTH $end
$var parameter 64 8" PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[4] $end
$var parameter 4 9" i $end
$scope module u_mac $end
$var wire 32 :" acc_in [31:0] $end
$var wire 8 ;" w [7:0] $end
$var wire 8 <" x [7:0] $end
$var wire 32 =" product_ext [31:0] $end
$var wire 16 >" product [15:0] $end
$var wire 32 ?" acc_out [31:0] $end
$var parameter 32 @" ACC_WIDTH $end
$var parameter 32 A" DATA_WIDTH $end
$var parameter 64 B" PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[5] $end
$var parameter 4 C" i $end
$scope module u_mac $end
$var wire 32 D" acc_in [31:0] $end
$var wire 8 E" w [7:0] $end
$var wire 8 F" x [7:0] $end
$var wire 32 G" product_ext [31:0] $end
$var wire 16 H" product [15:0] $end
$var wire 32 I" acc_out [31:0] $end
$var parameter 32 J" ACC_WIDTH $end
$var parameter 32 K" DATA_WIDTH $end
$var parameter 64 L" PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[6] $end
$var parameter 4 M" i $end
$scope module u_mac $end
$var wire 32 N" acc_in [31:0] $end
$var wire 8 O" w [7:0] $end
$var wire 8 P" x [7:0] $end
$var wire 32 Q" product_ext [31:0] $end
$var wire 16 R" product [15:0] $end
$var wire 32 S" acc_out [31:0] $end
$var parameter 32 T" ACC_WIDTH $end
$var parameter 32 U" DATA_WIDTH $end
$var parameter 64 V" PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[7] $end
$var parameter 4 W" i $end
$scope module u_mac $end
$var wire 32 X" acc_in [31:0] $end
$var wire 8 Y" w [7:0] $end
$var wire 8 Z" x [7:0] $end
$var wire 32 [" product_ext [31:0] $end
$var wire 16 \" product [15:0] $end
$var wire 32 ]" acc_out [31:0] $end
$var parameter 32 ^" ACC_WIDTH $end
$var parameter 32 _" DATA_WIDTH $end
$var parameter 64 `" PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_INPUT[0] $end
$var parameter 2 a" i $end
$upscope $end
$scope begin GEN_TREE_INPUT[1] $end
$var parameter 2 b" i $end
$upscope $end
$scope begin GEN_TREE_INPUT[2] $end
$var parameter 3 c" i $end
$upscope $end
$scope begin GEN_TREE_INPUT[3] $end
$var parameter 3 d" i $end
$upscope $end
$scope begin GEN_TREE_INPUT[4] $end
$var parameter 4 e" i $end
$upscope $end
$scope begin GEN_TREE_INPUT[5] $end
$var parameter 4 f" i $end
$upscope $end
$scope begin GEN_TREE_INPUT[6] $end
$var parameter 4 g" i $end
$upscope $end
$scope begin GEN_TREE_INPUT[7] $end
$var parameter 4 h" i $end
$upscope $end
$scope begin GEN_TREE_LEVEL[0] $end
$var parameter 2 i" level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 j" node $end
$upscope $end
$scope begin GEN_TREE_NODE[1] $end
$var parameter 2 k" node $end
$upscope $end
$scope begin GEN_TREE_NODE[2] $end
$var parameter 3 l" node $end
$upscope $end
$scope begin GEN_TREE_NODE[3] $end
$var parameter 3 m" node $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_LEVEL[1] $end
$var parameter 2 n" level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 o" node $end
$upscope $end
$scope begin GEN_TREE_NODE[1] $end
$var parameter 2 p" node $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_LEVEL[2] $end
$var parameter 3 q" level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 r" node $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$scope module u_d $end
$var wire 2 s" activation [1:0] $end
$var wire 8 t" bias [7:0] $end
$var wire 1 A clk $end
$var wire 16 u" n_inputs_real [15:0] $end
$var wire 1 B rst $end
$var wire 1 D start $end
$var wire 512 v" w_bus [511:0] $end
$var wire 512 w" x_bus [511:0] $end
$var wire 256 x" x_group [255:0] $end
$var wire 256 y" w_group [255:0] $end
$var wire 16 z" groups_real [15:0] $end
$var wire 32 {" final_acc [31:0] $end
$var wire 32 |" bias_ext [31:0] $end
$var wire 32 }" acc_next [31:0] $end
$var parameter 32 ~" ACC_WIDTH $end
$var parameter 2 !# ACT_NONE $end
$var parameter 2 "# ACT_RELU $end
$var parameter 32 ## DATA_WIDTH $end
$var parameter 32 $# GROUPS $end
$var parameter 32 %# GROUP_INDEX_WIDTH $end
$var parameter 32 &# N_INPUTS $end
$var parameter 32 '# PARALLEL $end
$var reg 32 (# acc [31:0] $end
$var reg 1 + busy $end
$var reg 1 ' done $end
$var reg 1 )# group_index $end
$var reg 8 *# y [7:0] $end
$scope module u_mac8 $end
$var wire 32 +# acc_in [31:0] $end
$var wire 256 ,# w_bus [255:0] $end
$var wire 256 -# x_bus [255:0] $end
$var wire 32 .# acc_out [31:0] $end
$var parameter 32 /# ACC_WIDTH $end
$var parameter 32 0# DATA_WIDTH $end
$var parameter 32 1# PARALLEL $end
$var parameter 32 2# TREE_LEVELS $end
$scope begin GEN_MAC[0] $end
$var parameter 2 3# i $end
$scope module u_mac $end
$var wire 32 4# acc_in [31:0] $end
$var wire 8 5# w [7:0] $end
$var wire 8 6# x [7:0] $end
$var wire 32 7# product_ext [31:0] $end
$var wire 16 8# product [15:0] $end
$var wire 32 9# acc_out [31:0] $end
$var parameter 32 :# ACC_WIDTH $end
$var parameter 32 ;# DATA_WIDTH $end
$var parameter 64 <# PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[1] $end
$var parameter 2 =# i $end
$scope module u_mac $end
$var wire 32 ># acc_in [31:0] $end
$var wire 8 ?# w [7:0] $end
$var wire 8 @# x [7:0] $end
$var wire 32 A# product_ext [31:0] $end
$var wire 16 B# product [15:0] $end
$var wire 32 C# acc_out [31:0] $end
$var parameter 32 D# ACC_WIDTH $end
$var parameter 32 E# DATA_WIDTH $end
$var parameter 64 F# PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[2] $end
$var parameter 3 G# i $end
$scope module u_mac $end
$var wire 32 H# acc_in [31:0] $end
$var wire 8 I# w [7:0] $end
$var wire 8 J# x [7:0] $end
$var wire 32 K# product_ext [31:0] $end
$var wire 16 L# product [15:0] $end
$var wire 32 M# acc_out [31:0] $end
$var parameter 32 N# ACC_WIDTH $end
$var parameter 32 O# DATA_WIDTH $end
$var parameter 64 P# PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[3] $end
$var parameter 3 Q# i $end
$scope module u_mac $end
$var wire 32 R# acc_in [31:0] $end
$var wire 8 S# w [7:0] $end
$var wire 8 T# x [7:0] $end
$var wire 32 U# product_ext [31:0] $end
$var wire 16 V# product [15:0] $end
$var wire 32 W# acc_out [31:0] $end
$var parameter 32 X# ACC_WIDTH $end
$var parameter 32 Y# DATA_WIDTH $end
$var parameter 64 Z# PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[4] $end
$var parameter 4 [# i $end
$scope module u_mac $end
$var wire 32 \# acc_in [31:0] $end
$var wire 8 ]# w [7:0] $end
$var wire 8 ^# x [7:0] $end
$var wire 32 _# product_ext [31:0] $end
$var wire 16 `# product [15:0] $end
$var wire 32 a# acc_out [31:0] $end
$var parameter 32 b# ACC_WIDTH $end
$var parameter 32 c# DATA_WIDTH $end
$var parameter 64 d# PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[5] $end
$var parameter 4 e# i $end
$scope module u_mac $end
$var wire 32 f# acc_in [31:0] $end
$var wire 8 g# w [7:0] $end
$var wire 8 h# x [7:0] $end
$var wire 32 i# product_ext [31:0] $end
$var wire 16 j# product [15:0] $end
$var wire 32 k# acc_out [31:0] $end
$var parameter 32 l# ACC_WIDTH $end
$var parameter 32 m# DATA_WIDTH $end
$var parameter 64 n# PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[6] $end
$var parameter 4 o# i $end
$scope module u_mac $end
$var wire 32 p# acc_in [31:0] $end
$var wire 8 q# w [7:0] $end
$var wire 8 r# x [7:0] $end
$var wire 32 s# product_ext [31:0] $end
$var wire 16 t# product [15:0] $end
$var wire 32 u# acc_out [31:0] $end
$var parameter 32 v# ACC_WIDTH $end
$var parameter 32 w# DATA_WIDTH $end
$var parameter 64 x# PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[7] $end
$var parameter 4 y# i $end
$scope module u_mac $end
$var wire 32 z# acc_in [31:0] $end
$var wire 8 {# w [7:0] $end
$var wire 8 |# x [7:0] $end
$var wire 32 }# product_ext [31:0] $end
$var wire 16 ~# product [15:0] $end
$var wire 32 !$ acc_out [31:0] $end
$var parameter 32 "$ ACC_WIDTH $end
$var parameter 32 #$ DATA_WIDTH $end
$var parameter 64 $$ PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[8] $end
$var parameter 5 %$ i $end
$scope module u_mac $end
$var wire 32 &$ acc_in [31:0] $end
$var wire 8 '$ w [7:0] $end
$var wire 8 ($ x [7:0] $end
$var wire 32 )$ product_ext [31:0] $end
$var wire 16 *$ product [15:0] $end
$var wire 32 +$ acc_out [31:0] $end
$var parameter 32 ,$ ACC_WIDTH $end
$var parameter 32 -$ DATA_WIDTH $end
$var parameter 64 .$ PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[9] $end
$var parameter 5 /$ i $end
$scope module u_mac $end
$var wire 32 0$ acc_in [31:0] $end
$var wire 8 1$ w [7:0] $end
$var wire 8 2$ x [7:0] $end
$var wire 32 3$ product_ext [31:0] $end
$var wire 16 4$ product [15:0] $end
$var wire 32 5$ acc_out [31:0] $end
$var parameter 32 6$ ACC_WIDTH $end
$var parameter 32 7$ DATA_WIDTH $end
$var parameter 64 8$ PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[10] $end
$var parameter 5 9$ i $end
$scope module u_mac $end
$var wire 32 :$ acc_in [31:0] $end
$var wire 8 ;$ w [7:0] $end
$var wire 8 <$ x [7:0] $end
$var wire 32 =$ product_ext [31:0] $end
$var wire 16 >$ product [15:0] $end
$var wire 32 ?$ acc_out [31:0] $end
$var parameter 32 @$ ACC_WIDTH $end
$var parameter 32 A$ DATA_WIDTH $end
$var parameter 64 B$ PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[11] $end
$var parameter 5 C$ i $end
$scope module u_mac $end
$var wire 32 D$ acc_in [31:0] $end
$var wire 8 E$ w [7:0] $end
$var wire 8 F$ x [7:0] $end
$var wire 32 G$ product_ext [31:0] $end
$var wire 16 H$ product [15:0] $end
$var wire 32 I$ acc_out [31:0] $end
$var parameter 32 J$ ACC_WIDTH $end
$var parameter 32 K$ DATA_WIDTH $end
$var parameter 64 L$ PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[12] $end
$var parameter 5 M$ i $end
$scope module u_mac $end
$var wire 32 N$ acc_in [31:0] $end
$var wire 8 O$ w [7:0] $end
$var wire 8 P$ x [7:0] $end
$var wire 32 Q$ product_ext [31:0] $end
$var wire 16 R$ product [15:0] $end
$var wire 32 S$ acc_out [31:0] $end
$var parameter 32 T$ ACC_WIDTH $end
$var parameter 32 U$ DATA_WIDTH $end
$var parameter 64 V$ PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[13] $end
$var parameter 5 W$ i $end
$scope module u_mac $end
$var wire 32 X$ acc_in [31:0] $end
$var wire 8 Y$ w [7:0] $end
$var wire 8 Z$ x [7:0] $end
$var wire 32 [$ product_ext [31:0] $end
$var wire 16 \$ product [15:0] $end
$var wire 32 ]$ acc_out [31:0] $end
$var parameter 32 ^$ ACC_WIDTH $end
$var parameter 32 _$ DATA_WIDTH $end
$var parameter 64 `$ PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[14] $end
$var parameter 5 a$ i $end
$scope module u_mac $end
$var wire 32 b$ acc_in [31:0] $end
$var wire 8 c$ w [7:0] $end
$var wire 8 d$ x [7:0] $end
$var wire 32 e$ product_ext [31:0] $end
$var wire 16 f$ product [15:0] $end
$var wire 32 g$ acc_out [31:0] $end
$var parameter 32 h$ ACC_WIDTH $end
$var parameter 32 i$ DATA_WIDTH $end
$var parameter 64 j$ PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[15] $end
$var parameter 5 k$ i $end
$scope module u_mac $end
$var wire 32 l$ acc_in [31:0] $end
$var wire 8 m$ w [7:0] $end
$var wire 8 n$ x [7:0] $end
$var wire 32 o$ product_ext [31:0] $end
$var wire 16 p$ product [15:0] $end
$var wire 32 q$ acc_out [31:0] $end
$var parameter 32 r$ ACC_WIDTH $end
$var parameter 32 s$ DATA_WIDTH $end
$var parameter 64 t$ PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[16] $end
$var parameter 6 u$ i $end
$scope module u_mac $end
$var wire 32 v$ acc_in [31:0] $end
$var wire 8 w$ w [7:0] $end
$var wire 8 x$ x [7:0] $end
$var wire 32 y$ product_ext [31:0] $end
$var wire 16 z$ product [15:0] $end
$var wire 32 {$ acc_out [31:0] $end
$var parameter 32 |$ ACC_WIDTH $end
$var parameter 32 }$ DATA_WIDTH $end
$var parameter 64 ~$ PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[17] $end
$var parameter 6 !% i $end
$scope module u_mac $end
$var wire 32 "% acc_in [31:0] $end
$var wire 8 #% w [7:0] $end
$var wire 8 $% x [7:0] $end
$var wire 32 %% product_ext [31:0] $end
$var wire 16 &% product [15:0] $end
$var wire 32 '% acc_out [31:0] $end
$var parameter 32 (% ACC_WIDTH $end
$var parameter 32 )% DATA_WIDTH $end
$var parameter 64 *% PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[18] $end
$var parameter 6 +% i $end
$scope module u_mac $end
$var wire 32 ,% acc_in [31:0] $end
$var wire 8 -% w [7:0] $end
$var wire 8 .% x [7:0] $end
$var wire 32 /% product_ext [31:0] $end
$var wire 16 0% product [15:0] $end
$var wire 32 1% acc_out [31:0] $end
$var parameter 32 2% ACC_WIDTH $end
$var parameter 32 3% DATA_WIDTH $end
$var parameter 64 4% PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[19] $end
$var parameter 6 5% i $end
$scope module u_mac $end
$var wire 32 6% acc_in [31:0] $end
$var wire 8 7% w [7:0] $end
$var wire 8 8% x [7:0] $end
$var wire 32 9% product_ext [31:0] $end
$var wire 16 :% product [15:0] $end
$var wire 32 ;% acc_out [31:0] $end
$var parameter 32 <% ACC_WIDTH $end
$var parameter 32 =% DATA_WIDTH $end
$var parameter 64 >% PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[20] $end
$var parameter 6 ?% i $end
$scope module u_mac $end
$var wire 32 @% acc_in [31:0] $end
$var wire 8 A% w [7:0] $end
$var wire 8 B% x [7:0] $end
$var wire 32 C% product_ext [31:0] $end
$var wire 16 D% product [15:0] $end
$var wire 32 E% acc_out [31:0] $end
$var parameter 32 F% ACC_WIDTH $end
$var parameter 32 G% DATA_WIDTH $end
$var parameter 64 H% PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[21] $end
$var parameter 6 I% i $end
$scope module u_mac $end
$var wire 32 J% acc_in [31:0] $end
$var wire 8 K% w [7:0] $end
$var wire 8 L% x [7:0] $end
$var wire 32 M% product_ext [31:0] $end
$var wire 16 N% product [15:0] $end
$var wire 32 O% acc_out [31:0] $end
$var parameter 32 P% ACC_WIDTH $end
$var parameter 32 Q% DATA_WIDTH $end
$var parameter 64 R% PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[22] $end
$var parameter 6 S% i $end
$scope module u_mac $end
$var wire 32 T% acc_in [31:0] $end
$var wire 8 U% w [7:0] $end
$var wire 8 V% x [7:0] $end
$var wire 32 W% product_ext [31:0] $end
$var wire 16 X% product [15:0] $end
$var wire 32 Y% acc_out [31:0] $end
$var parameter 32 Z% ACC_WIDTH $end
$var parameter 32 [% DATA_WIDTH $end
$var parameter 64 \% PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[23] $end
$var parameter 6 ]% i $end
$scope module u_mac $end
$var wire 32 ^% acc_in [31:0] $end
$var wire 8 _% w [7:0] $end
$var wire 8 `% x [7:0] $end
$var wire 32 a% product_ext [31:0] $end
$var wire 16 b% product [15:0] $end
$var wire 32 c% acc_out [31:0] $end
$var parameter 32 d% ACC_WIDTH $end
$var parameter 32 e% DATA_WIDTH $end
$var parameter 64 f% PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[24] $end
$var parameter 6 g% i $end
$scope module u_mac $end
$var wire 32 h% acc_in [31:0] $end
$var wire 8 i% w [7:0] $end
$var wire 8 j% x [7:0] $end
$var wire 32 k% product_ext [31:0] $end
$var wire 16 l% product [15:0] $end
$var wire 32 m% acc_out [31:0] $end
$var parameter 32 n% ACC_WIDTH $end
$var parameter 32 o% DATA_WIDTH $end
$var parameter 64 p% PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[25] $end
$var parameter 6 q% i $end
$scope module u_mac $end
$var wire 32 r% acc_in [31:0] $end
$var wire 8 s% w [7:0] $end
$var wire 8 t% x [7:0] $end
$var wire 32 u% product_ext [31:0] $end
$var wire 16 v% product [15:0] $end
$var wire 32 w% acc_out [31:0] $end
$var parameter 32 x% ACC_WIDTH $end
$var parameter 32 y% DATA_WIDTH $end
$var parameter 64 z% PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[26] $end
$var parameter 6 {% i $end
$scope module u_mac $end
$var wire 32 |% acc_in [31:0] $end
$var wire 8 }% w [7:0] $end
$var wire 8 ~% x [7:0] $end
$var wire 32 !& product_ext [31:0] $end
$var wire 16 "& product [15:0] $end
$var wire 32 #& acc_out [31:0] $end
$var parameter 32 $& ACC_WIDTH $end
$var parameter 32 %& DATA_WIDTH $end
$var parameter 64 && PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[27] $end
$var parameter 6 '& i $end
$scope module u_mac $end
$var wire 32 (& acc_in [31:0] $end
$var wire 8 )& w [7:0] $end
$var wire 8 *& x [7:0] $end
$var wire 32 +& product_ext [31:0] $end
$var wire 16 ,& product [15:0] $end
$var wire 32 -& acc_out [31:0] $end
$var parameter 32 .& ACC_WIDTH $end
$var parameter 32 /& DATA_WIDTH $end
$var parameter 64 0& PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[28] $end
$var parameter 6 1& i $end
$scope module u_mac $end
$var wire 32 2& acc_in [31:0] $end
$var wire 8 3& w [7:0] $end
$var wire 8 4& x [7:0] $end
$var wire 32 5& product_ext [31:0] $end
$var wire 16 6& product [15:0] $end
$var wire 32 7& acc_out [31:0] $end
$var parameter 32 8& ACC_WIDTH $end
$var parameter 32 9& DATA_WIDTH $end
$var parameter 64 :& PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[29] $end
$var parameter 6 ;& i $end
$scope module u_mac $end
$var wire 32 <& acc_in [31:0] $end
$var wire 8 =& w [7:0] $end
$var wire 8 >& x [7:0] $end
$var wire 32 ?& product_ext [31:0] $end
$var wire 16 @& product [15:0] $end
$var wire 32 A& acc_out [31:0] $end
$var parameter 32 B& ACC_WIDTH $end
$var parameter 32 C& DATA_WIDTH $end
$var parameter 64 D& PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[30] $end
$var parameter 6 E& i $end
$scope module u_mac $end
$var wire 32 F& acc_in [31:0] $end
$var wire 8 G& w [7:0] $end
$var wire 8 H& x [7:0] $end
$var wire 32 I& product_ext [31:0] $end
$var wire 16 J& product [15:0] $end
$var wire 32 K& acc_out [31:0] $end
$var parameter 32 L& ACC_WIDTH $end
$var parameter 32 M& DATA_WIDTH $end
$var parameter 64 N& PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[31] $end
$var parameter 6 O& i $end
$scope module u_mac $end
$var wire 32 P& acc_in [31:0] $end
$var wire 8 Q& w [7:0] $end
$var wire 8 R& x [7:0] $end
$var wire 32 S& product_ext [31:0] $end
$var wire 16 T& product [15:0] $end
$var wire 32 U& acc_out [31:0] $end
$var parameter 32 V& ACC_WIDTH $end
$var parameter 32 W& DATA_WIDTH $end
$var parameter 64 X& PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_INPUT[0] $end
$var parameter 2 Y& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[1] $end
$var parameter 2 Z& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[2] $end
$var parameter 3 [& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[3] $end
$var parameter 3 \& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[4] $end
$var parameter 4 ]& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[5] $end
$var parameter 4 ^& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[6] $end
$var parameter 4 _& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[7] $end
$var parameter 4 `& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[8] $end
$var parameter 5 a& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[9] $end
$var parameter 5 b& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[10] $end
$var parameter 5 c& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[11] $end
$var parameter 5 d& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[12] $end
$var parameter 5 e& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[13] $end
$var parameter 5 f& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[14] $end
$var parameter 5 g& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[15] $end
$var parameter 5 h& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[16] $end
$var parameter 6 i& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[17] $end
$var parameter 6 j& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[18] $end
$var parameter 6 k& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[19] $end
$var parameter 6 l& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[20] $end
$var parameter 6 m& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[21] $end
$var parameter 6 n& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[22] $end
$var parameter 6 o& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[23] $end
$var parameter 6 p& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[24] $end
$var parameter 6 q& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[25] $end
$var parameter 6 r& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[26] $end
$var parameter 6 s& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[27] $end
$var parameter 6 t& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[28] $end
$var parameter 6 u& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[29] $end
$var parameter 6 v& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[30] $end
$var parameter 6 w& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[31] $end
$var parameter 6 x& i $end
$upscope $end
$scope begin GEN_TREE_LEVEL[0] $end
$var parameter 2 y& level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 z& node $end
$upscope $end
$scope begin GEN_TREE_NODE[1] $end
$var parameter 2 {& node $end
$upscope $end
$scope begin GEN_TREE_NODE[2] $end
$var parameter 3 |& node $end
$upscope $end
$scope begin GEN_TREE_NODE[3] $end
$var parameter 3 }& node $end
$upscope $end
$scope begin GEN_TREE_NODE[4] $end
$var parameter 4 ~& node $end
$upscope $end
$scope begin GEN_TREE_NODE[5] $end
$var parameter 4 !' node $end
$upscope $end
$scope begin GEN_TREE_NODE[6] $end
$var parameter 4 "' node $end
$upscope $end
$scope begin GEN_TREE_NODE[7] $end
$var parameter 4 #' node $end
$upscope $end
$scope begin GEN_TREE_NODE[8] $end
$var parameter 5 $' node $end
$upscope $end
$scope begin GEN_TREE_NODE[9] $end
$var parameter 5 %' node $end
$upscope $end
$scope begin GEN_TREE_NODE[10] $end
$var parameter 5 &' node $end
$upscope $end
$scope begin GEN_TREE_NODE[11] $end
$var parameter 5 '' node $end
$upscope $end
$scope begin GEN_TREE_NODE[12] $end
$var parameter 5 (' node $end
$upscope $end
$scope begin GEN_TREE_NODE[13] $end
$var parameter 5 )' node $end
$upscope $end
$scope begin GEN_TREE_NODE[14] $end
$var parameter 5 *' node $end
$upscope $end
$scope begin GEN_TREE_NODE[15] $end
$var parameter 5 +' node $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_LEVEL[1] $end
$var parameter 2 ,' level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 -' node $end
$upscope $end
$scope begin GEN_TREE_NODE[1] $end
$var parameter 2 .' node $end
$upscope $end
$scope begin GEN_TREE_NODE[2] $end
$var parameter 3 /' node $end
$upscope $end
$scope begin GEN_TREE_NODE[3] $end
$var parameter 3 0' node $end
$upscope $end
$scope begin GEN_TREE_NODE[4] $end
$var parameter 4 1' node $end
$upscope $end
$scope begin GEN_TREE_NODE[5] $end
$var parameter 4 2' node $end
$upscope $end
$scope begin GEN_TREE_NODE[6] $end
$var parameter 4 3' node $end
$upscope $end
$scope begin GEN_TREE_NODE[7] $end
$var parameter 4 4' node $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_LEVEL[2] $end
$var parameter 3 5' level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 6' node $end
$upscope $end
$scope begin GEN_TREE_NODE[1] $end
$var parameter 2 7' node $end
$upscope $end
$scope begin GEN_TREE_NODE[2] $end
$var parameter 3 8' node $end
$upscope $end
$scope begin GEN_TREE_NODE[3] $end
$var parameter 3 9' node $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_LEVEL[3] $end
$var parameter 3 :' level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 ;' node $end
$upscope $end
$scope begin GEN_TREE_NODE[1] $end
$var parameter 2 <' node $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_LEVEL[4] $end
$var parameter 4 =' level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 >' node $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$scope module u_f $end
$var wire 2 ?' activation [1:0] $end
$var wire 8 @' bias [7:0] $end
$var wire 1 A clk $end
$var wire 16 A' n_inputs_real [15:0] $end
$var wire 1 B rst $end
$var wire 1 E start $end
$var wire 256 B' w_bus [255:0] $end
$var wire 256 C' x_bus [255:0] $end
$var wire 16 D' x_group [15:0] $end
$var wire 16 E' w_group [15:0] $end
$var wire 16 F' groups_real [15:0] $end
$var wire 32 G' final_acc [31:0] $end
$var wire 32 H' bias_ext [31:0] $end
$var wire 32 I' acc_next [31:0] $end
$var parameter 32 J' ACC_WIDTH $end
$var parameter 2 K' ACT_NONE $end
$var parameter 2 L' ACT_RELU $end
$var parameter 32 M' DATA_WIDTH $end
$var parameter 32 N' GROUPS $end
$var parameter 32 O' GROUP_INDEX_WIDTH $end
$var parameter 32 P' N_INPUTS $end
$var parameter 32 Q' PARALLEL $end
$var reg 32 R' acc [31:0] $end
$var reg 1 * busy $end
$var reg 1 & done $end
$var reg 4 S' group_index [3:0] $end
$var reg 8 T' y [7:0] $end
$scope module u_mac8 $end
$var wire 32 U' acc_in [31:0] $end
$var wire 16 V' w_bus [15:0] $end
$var wire 16 W' x_bus [15:0] $end
$var wire 32 X' acc_out [31:0] $end
$var parameter 32 Y' ACC_WIDTH $end
$var parameter 32 Z' DATA_WIDTH $end
$var parameter 32 [' PARALLEL $end
$var parameter 32 \' TREE_LEVELS $end
$scope begin GEN_MAC[0] $end
$var parameter 2 ]' i $end
$scope module u_mac $end
$var wire 32 ^' acc_in [31:0] $end
$var wire 8 _' w [7:0] $end
$var wire 8 `' x [7:0] $end
$var wire 32 a' product_ext [31:0] $end
$var wire 16 b' product [15:0] $end
$var wire 32 c' acc_out [31:0] $end
$var parameter 32 d' ACC_WIDTH $end
$var parameter 32 e' DATA_WIDTH $end
$var parameter 64 f' PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[1] $end
$var parameter 2 g' i $end
$scope module u_mac $end
$var wire 32 h' acc_in [31:0] $end
$var wire 8 i' w [7:0] $end
$var wire 8 j' x [7:0] $end
$var wire 32 k' product_ext [31:0] $end
$var wire 16 l' product [15:0] $end
$var wire 32 m' acc_out [31:0] $end
$var parameter 32 n' ACC_WIDTH $end
$var parameter 32 o' DATA_WIDTH $end
$var parameter 64 p' PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_INPUT[0] $end
$var parameter 2 q' i $end
$upscope $end
$scope begin GEN_TREE_INPUT[1] $end
$var parameter 2 r' i $end
$upscope $end
$scope begin GEN_TREE_LEVEL[0] $end
$var parameter 2 s' level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 t' node $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$scope module u_g $end
$var wire 2 u' activation [1:0] $end
$var wire 8 v' bias [7:0] $end
$var wire 1 A clk $end
$var wire 16 w' n_inputs_real [15:0] $end
$var wire 1 B rst $end
$var wire 1 F start $end
$var wire 256 x' w_bus [255:0] $end
$var wire 256 y' x_bus [255:0] $end
$var wire 32 z' x_group [31:0] $end
$var wire 32 {' w_group [31:0] $end
$var wire 16 |' groups_real [15:0] $end
$var wire 32 }' final_acc [31:0] $end
$var wire 32 ~' bias_ext [31:0] $end
$var wire 32 !( acc_next [31:0] $end
$var parameter 32 "( ACC_WIDTH $end
$var parameter 2 #( ACT_NONE $end
$var parameter 2 $( ACT_RELU $end
$var parameter 32 %( DATA_WIDTH $end
$var parameter 32 &( GROUPS $end
$var parameter 32 '( GROUP_INDEX_WIDTH $end
$var parameter 32 (( N_INPUTS $end
$var parameter 32 )( PARALLEL $end
$var reg 32 *( acc [31:0] $end
$var reg 1 ) busy $end
$var reg 1 % done $end
$var reg 3 +( group_index [2:0] $end
$var reg 8 ,( y [7:0] $end
$scope module u_mac8 $end
$var wire 32 -( acc_in [31:0] $end
$var wire 32 .( w_bus [31:0] $end
$var wire 32 /( x_bus [31:0] $end
$var wire 32 0( acc_out [31:0] $end
$var parameter 32 1( ACC_WIDTH $end
$var parameter 32 2( DATA_WIDTH $end
$var parameter 32 3( PARALLEL $end
$var parameter 32 4( TREE_LEVELS $end
$scope begin GEN_MAC[0] $end
$var parameter 2 5( i $end
$scope module u_mac $end
$var wire 32 6( acc_in [31:0] $end
$var wire 8 7( w [7:0] $end
$var wire 8 8( x [7:0] $end
$var wire 32 9( product_ext [31:0] $end
$var wire 16 :( product [15:0] $end
$var wire 32 ;( acc_out [31:0] $end
$var parameter 32 <( ACC_WIDTH $end
$var parameter 32 =( DATA_WIDTH $end
$var parameter 64 >( PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[1] $end
$var parameter 2 ?( i $end
$scope module u_mac $end
$var wire 32 @( acc_in [31:0] $end
$var wire 8 A( w [7:0] $end
$var wire 8 B( x [7:0] $end
$var wire 32 C( product_ext [31:0] $end
$var wire 16 D( product [15:0] $end
$var wire 32 E( acc_out [31:0] $end
$var parameter 32 F( ACC_WIDTH $end
$var parameter 32 G( DATA_WIDTH $end
$var parameter 64 H( PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[2] $end
$var parameter 3 I( i $end
$scope module u_mac $end
$var wire 32 J( acc_in [31:0] $end
$var wire 8 K( w [7:0] $end
$var wire 8 L( x [7:0] $end
$var wire 32 M( product_ext [31:0] $end
$var wire 16 N( product [15:0] $end
$var wire 32 O( acc_out [31:0] $end
$var parameter 32 P( ACC_WIDTH $end
$var parameter 32 Q( DATA_WIDTH $end
$var parameter 64 R( PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[3] $end
$var parameter 3 S( i $end
$scope module u_mac $end
$var wire 32 T( acc_in [31:0] $end
$var wire 8 U( w [7:0] $end
$var wire 8 V( x [7:0] $end
$var wire 32 W( product_ext [31:0] $end
$var wire 16 X( product [15:0] $end
$var wire 32 Y( acc_out [31:0] $end
$var parameter 32 Z( ACC_WIDTH $end
$var parameter 32 [( DATA_WIDTH $end
$var parameter 64 \( PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_INPUT[0] $end
$var parameter 2 ]( i $end
$upscope $end
$scope begin GEN_TREE_INPUT[1] $end
$var parameter 2 ^( i $end
$upscope $end
$scope begin GEN_TREE_INPUT[2] $end
$var parameter 3 _( i $end
$upscope $end
$scope begin GEN_TREE_INPUT[3] $end
$var parameter 3 `( i $end
$upscope $end
$scope begin GEN_TREE_LEVEL[0] $end
$var parameter 2 a( level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 b( node $end
$upscope $end
$scope begin GEN_TREE_NODE[1] $end
$var parameter 2 c( node $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_LEVEL[1] $end
$var parameter 2 d( level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 e( node $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
$comment Show the parameter values. $end
$dumpall
b0 e(
b1 d(
b1 c(
b0 b(
b0 a(
b11 `(
b10 _(
b1 ^(
b0 ](
b10000 \(
b1000 [(
b100000 Z(
b11 S(
b10000 R(
b1000 Q(
b100000 P(
b10 I(
b10000 H(
b1000 G(
b100000 F(
b1 ?(
b10000 >(
b1000 =(
b100000 <(
b0 5(
b10 4(
b100 3(
b1000 2(
b100000 1(
b100 )(
b100000 ((
b11 '(
b1000 &(
b1000 %(
b1 $(
b0 #(
b100000 "(
b0 t'
b0 s'
b1 r'
b0 q'
b10000 p'
b1000 o'
b100000 n'
b1 g'
b10000 f'
b1000 e'
b100000 d'
b0 ]'
b1 \'
b10 ['
b1000 Z'
b100000 Y'
b10 Q'
b100000 P'
b100 O'
b10000 N'
b1000 M'
b1 L'
b0 K'
b100000 J'
b0 >'
b100 ='
b1 <'
b0 ;'
b11 :'
b11 9'
b10 8'
b1 7'
b0 6'
b10 5'
b111 4'
b110 3'
b101 2'
b100 1'
b11 0'
b10 /'
b1 .'
b0 -'
b1 ,'
b1111 +'
b1110 *'
b1101 )'
b1100 ('
b1011 ''
b1010 &'
b1001 %'
b1000 $'
b111 #'
b110 "'
b101 !'
b100 ~&
b11 }&
b10 |&
b1 {&
b0 z&
b0 y&
b11111 x&
b11110 w&
b11101 v&
b11100 u&
b11011 t&
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$end
#0
$dumpvars
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$end
#5000
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b100000001000000010000000100000001000000010000000100000001 W
b100000001000000010000000100000001000000010000000100000001 h
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b100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 T
b100000001000000010000000100000001000000010000000100000001 V
b100000001000000010000000100000001000000010000000100000001 i
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b100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 U
b100000 O
0B
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b100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 y"
b100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 ,#
b1000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 H
b1000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 v"
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b100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 -#
b1000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 L
b1000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 w"
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b100000001 D'
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0A
#255000
b1010 S'
b10110 G'
b10110 I'
b10110 X'
b10100 R'
b10100 U'
1A
#260000
0A
#265000
b1011 S'
b11000 G'
b11000 I'
b11000 X'
b10110 R'
b10110 U'
1A
#270000
0A
#275000
b1100 S'
b11010 G'
b11010 I'
b11010 X'
b11000 R'
b11000 U'
1A
#280000
0A
#285000
b1101 S'
b11100 G'
b11100 I'
b11100 X'
b11010 R'
b11010 U'
1A
#290000
0A
#295000
b1110 S'
b11110 G'
b11110 I'
b11110 X'
b11100 R'
b11100 U'
1A
#300000
0A
#305000
b1111 S'
b100000 G'
b100000 I'
b100000 X'
b11110 R'
b11110 U'
1A
#310000
0A
#315000
1&
0*
b100000 "
b100000 T'
b100010 G'
b100010 I'
b100010 X'
b100000 R'
b100000 U'
1A
#320000
0A
#325000
0&
b1 Y(
b1 W(
b1 O(
b1 M(
b1 E(
b1 C(
b100 }'
b100 !(
b100 0(
b1 ;(
b1 9(
b1 X(
b1 U(
b1 V(
b1 N(
b1 K(
b1 L(
b1 D(
b1 A(
b1 B(
b1 :(
b1 7(
b1 8(
b1000000010000000100000001 {'
b1000000010000000100000001 .(
b100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 J
b100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 x'
b1000000010000000100000001 z'
b1000000010000000100000001 /(
b100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 N
b100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 y'
b100000 O
1A
#330000
0A
#335000
1F
1A
#340000
0A
#345000
1)
0F
1A
#350000
0A
#355000
b1 +(
b1000 }'
b1000 !(
b1000 0(
b100 *(
b100 -(
1A
#360000
0A
#365000
b10 +(
b1100 }'
b1100 !(
b1100 0(
b1000 *(
b1000 -(
1A
#370000
0A
#375000
b11 +(
b10000 }'
b10000 !(
b10000 0(
b1100 *(
b1100 -(
1A
#380000
0A
#385000
b100 +(
b10100 }'
b10100 !(
b10100 0(
b10000 *(
b10000 -(
1A
#390000
0A
#395000
b101 +(
b11000 }'
b11000 !(
b11000 0(
b10100 *(
b10100 -(
1A
#400000
0A
#405000
b110 +(
b11100 }'
b11100 !(
b11100 0(
b11000 *(
b11000 -(
1A
#410000
0A
#415000
b111 +(
b100000 }'
b100000 !(
b100000 0(
b11100 *(
b11100 -(
1A
#420000
0A
#425000
1%
0)
b100000 !
b100000 ,(
b100100 }'
b100100 !(
b100100 0(
b100000 *(
b100000 -(
1A
#430000
0A
#435000
0%
1A
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