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FPGA-Neural/sim/layer_sequencer.vcd
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micheleandClaude Sonnet 5 7e2711fa27 feat: widen ADDR_WIDTH to 23 bits for full 8MB PSRAM addressing 
Bumps ADDR_WIDTH's default from 22 to 23 bits across every RTL
module (neuron_memory, layer_sequencer, spi_engine, spi_neuron_top,
mem_arbiter, int8_memory_access, memory_interface, psram_controller,
memory_model) and every testbench that mirrors it, so the system's
byte-address space reaches the full 8 MiB the recommended PSRAM part
(ISSI IS66WVE4M16EBLL-70BLI, docs/FPGA-Neural-Hardware-Design.md §3)
actually provides -- previously only 4 MiB (half the chip) was
reachable, since int8_memory_access.v's byte->word address shift
(addr >> 1) turned the old 22-bit byte address into only 21 real word
bits, one short of the chip's real 22-bit word address (A0-A21). At
23 bits, that same shift lands exactly on all 22 chip address lines,
so the whole part is usable now instead of deferred to a future
widening.

Also fixes a stray 22'd11-sized literal in layer_sequencer.v's
descriptor-table address increment (numerically already safe via
Verilog's zero-extension, but now correctly unsized so it always
matches ADDR_WIDTH instead of silently assuming 22).

Updated docs/FPGA-NeuralNetwork-Engine.md's SPI protocol address-field
note (23 bits, top 1 reserved bit instead of 2) and
docs/FPGA-Neural-Hardware-Design.md's PSRAM section (the "chip has
one spare address line" framing is gone now that all 22 are wired
and used).

Full regression (all 11 ADDR_WIDTH-touching testbenches, plus a
Yosys elaboration check of spi_neuron_top with the new default and
no override) passes clean.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01WQV3vS9TXaGDJ5cRfnfidt
2026-09-02 21:00:46 +02:00

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$date
Wed Sep 2 20:58:00 2026
$end
$version
Icarus Verilog
$end
$timescale
1ps
$end
$scope module tb $end
$var wire 1 ! seq_done $end
$var wire 1 " seq_busy $end
$var wire 1 # ram_wr $end
$var wire 8 $ ram_wdata [7:0] $end
$var wire 1 % ram_req $end
$var wire 23 & ram_addr [22:0] $end
$var wire 23 ' nm_x_base [22:0] $end
$var wire 23 ( nm_w_base [22:0] $end
$var wire 1 ) nm_start $end
$var wire 16 * nm_n_neurons [15:0] $end
$var wire 16 + nm_n_inputs [15:0] $end
$var wire 23 , nm_bias_addr [22:0] $end
$var wire 2 - nm_activation [1:0] $end
$var parameter 32 . ADDR_WIDTH $end
$var parameter 23 / BUF_A_BASE $end
$var parameter 23 0 BUF_B_BASE $end
$var real 1 1 CLK_PERIOD $end
$var parameter 32 2 DATA_WIDTH $end
$var parameter 23 3 L0_BIAS_ADDR $end
$var parameter 23 4 L0_W_BASE $end
$var parameter 23 5 L1_BIAS_ADDR $end
$var parameter 23 6 L1_W_BASE $end
$var parameter 32 7 N_LAYERS $end
$var parameter 32 8 N_WIDTH $end
$var parameter 1 9 RAM_IDLE $end
$var parameter 1 : RAM_WAIT $end
$var parameter 23 ; TABLE_BASE $end
$var parameter 23 < X_BASE $end
$var reg 23 = buf_a_base [22:0] $end
$var reg 23 > buf_b_base [22:0] $end
$var reg 1 ? clk $end
$var reg 1 @ nm_busy $end
$var reg 1 A nm_done $end
$var reg 23 B ram_addr_latched [22:0] $end
$var reg 8 C ram_rdata [7:0] $end
$var reg 1 D ram_ready $end
$var reg 1 E ram_state $end
$var reg 8 F ram_wdata_latched [7:0] $end
$var reg 1 G ram_wr_latched $end
$var reg 1 H rst $end
$var reg 8 I run_num_layers [7:0] $end
$var reg 1 J run_start $end
$var reg 1 K seq_busy_dropped_early $end
$var reg 32 L staged_y [31:0] $end
$var reg 23 M table_base [22:0] $end
$var reg 23 N x_base [22:0] $end
$var reg 32 O y_bus [31:0] $end
$var integer 32 P errors [31:0] $end
$var integer 32 Q errors_before [31:0] $end
$var integer 32 R i [31:0] $end
$var integer 32 S nm_delay [31:0] $end
$var integer 32 T seq_done_count [31:0] $end
$scope module u_dut $end
$var wire 23 U buf_a_base [22:0] $end
$var wire 23 V buf_b_base [22:0] $end
$var wire 1 ? clk $end
$var wire 1 @ nm_busy $end
$var wire 1 A nm_done $end
$var wire 8 W ram_rdata [7:0] $end
$var wire 1 D ram_ready $end
$var wire 1 H rst $end
$var wire 8 X run_num_layers [7:0] $end
$var wire 1 J run_start $end
$var wire 23 Y table_base [22:0] $end
$var wire 23 Z x_base [22:0] $end
$var wire 32 [ y_bus [31:0] $end
$var parameter 32 \ ADDR_WIDTH $end
$var parameter 32 ] DATA_WIDTH $end
$var parameter 32 ^ N_LAYERS $end
$var parameter 32 _ N_WIDTH $end
$var parameter 4 ` ST_COPY_ISSUE $end
$var parameter 4 a ST_COPY_WAIT $end
$var parameter 4 b ST_IDLE $end
$var parameter 4 c ST_READ_DESC $end
$var parameter 4 d ST_READ_WAIT $end
$var parameter 4 e ST_START_LAYER $end
$var parameter 4 f ST_WAIT_LAYER $end
$var reg 8 g activation_acc [7:0] $end
$var reg 24 h bias_addr_acc [23:0] $end
$var reg 3 i copy_idx [2:0] $end
$var reg 1 j cur_sel $end
$var reg 4 k desc_byte_idx [3:0] $end
$var reg 23 l desc_table_addr [22:0] $end
$var reg 8 m layer_idx [7:0] $end
$var reg 16 n n_inputs_acc [15:0] $end
$var reg 16 o n_neurons_acc [15:0] $end
$var reg 2 p nm_activation [1:0] $end
$var reg 23 q nm_bias_addr [22:0] $end
$var reg 16 r nm_n_inputs [15:0] $end
$var reg 16 s nm_n_neurons [15:0] $end
$var reg 1 ) nm_start $end
$var reg 23 t nm_w_base [22:0] $end
$var reg 23 u nm_x_base [22:0] $end
$var reg 8 v num_layers_reg [7:0] $end
$var reg 23 w ram_addr [22:0] $end
$var reg 1 % ram_req $end
$var reg 8 x ram_wdata [7:0] $end
$var reg 1 # ram_wr $end
$var reg 1 " seq_busy $end
$var reg 1 ! seq_done $end
$var reg 4 y state [3:0] $end
$var reg 24 z w_base_acc [23:0] $end
$var reg 1 { write_sel $end
$upscope $end
$scope task clk_wait $end
$var integer 32 | k [31:0] $end
$var integer 32 } n [31:0] $end
$upscope $end
$scope task report $end
$var reg 512 ~ label [511:0] $end
$upscope $end
$scope task stage_layer_output $end
$var reg 32 !" val [31:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
$comment Show the parameter values. $end
$dumpall
b100 f
b11 e
b10 d
b1 c
b0 b
b110 a
b101 `
b100 _
b100 ^
b1000 ]
b10111 \
b10000 <
b100000000 ;
1:
09
b100 8
b100 7
b11000000000000 6
b100000000000000 5
b1000000000000 4
b10000000000000 3
b1000 2
r12.5 1
b1100000000 0
b1000000000 /
b10111 .
$end
#0
$dumpvars
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bx }
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bx z
bx y
bx x
bx w
bx v
bx u
bx t
bx s
bx r
bx q
bx p
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bx i
bx h
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b10000 Z
b100000000 Y
b0 X
bx W
b1100000000 V
b1000000000 U
bx T
bx S
b1000000000000 R
bx Q
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b10000 N
b100000000 M
bx L
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bx F
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b1000000000 =
bx -
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bx +
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bx (
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x#
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$end
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#12500
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#37500
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#43750
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#50000
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#56250
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#62500
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#68750
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#75000
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#81250
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#87500
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#93750
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#100000
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#106250
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#112500
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#118750
b101001000111110001010100001011 L
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#125000
b10 I
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#131250
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#137500
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#143750
b10 y
b100000000 &
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1%
b1 |
1?
#150000
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#156250
0%
1E
b0 F
0G
b100000000 B
b10 |
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#162500
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#168750
0E
1D
bx0000000 C
bx0000000 W
1?
#175000
0?
#181250
b1 y
b1 k
bx00000000000000000000000 z
0D
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#187500
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#193750
b10 y
b100000001 &
b100000001 w
1%
1?
#200000
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#206250
0%
1E
b100000001 B
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#212500
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#218750
0E
1D
b10000 C
b10000 W
1?
#225000
0?
#231250
b1 y
b10 k
bx00000000001000000000000 z
0D
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#237500
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#243750
b10 y
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#250000
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#256250
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b100000010 B
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#262500
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#268750
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b0 C
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#275000
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#281250
b1 y
b11 k
0D
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#287500
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#293750
b10 y
b100000011 &
b100000011 w
1%
1?
#300000
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#306250
0%
1E
b100000011 B
1?
#312500
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#318750
0E
1D
bx0000000 C
bx0000000 W
1?
#325000
0?
#331250
b1 y
b100 k
bx00000000000000000000000 h
0D
1?
#337500
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#343750
b10 y
b100000100 &
b100000100 w
1%
1?
#350000
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#356250
0%
1E
b100000100 B
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#362500
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#368750
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b100000 C
b100000 W
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#375000
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#381250
b1 y
b101 k
bx00000000010000000000000 h
0D
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#387500
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#393750
b10 y
b100000101 &
b100000101 w
1%
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#400000
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#406250
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b100000101 B
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#412500
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#437500
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#450000
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#487500
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#543750
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b100001000 &
b100001000 w
1%
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#550000
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#562500
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#575000
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b1001 k
b100 n
0D
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#587500
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#593750
b10 y
b100001001 &
b100001001 w
1%
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#600000
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#606250
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#612500
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#725000
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#731250
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#743750
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#750000
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b101001000111110001010100001011 [
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#762500
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#768750
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b1000000000 &
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b100001111 &
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1%
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1D
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0D
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1E
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1D
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1D
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#1237500
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0%
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0E
1D
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1E
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0E
1D
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0D
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1%
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1E
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1D
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0D
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0?
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1E
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0%
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0E
1D
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#1418750
0D
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#1443750
b11 S
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#1450000
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#1456250
b10 S
1?
#1462500
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#1468750
b1 S
1?
#1475000
0?
#1481250
b0 S
1?
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0?
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#1531250
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1E
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0E
1D
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b101 y
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b1100000001 &
b1100000001 w
1%
1?
#1575000
0?
#1581250
0%
1E
b10110 F
b1100000001 B
1?
#1587500
0?
#1593750
0E
1D
1?
#1600000
0?
#1606250
b101 y
b10 i
0D
1?
#1612500
0?
#1618750
b110 y
b100001 $
b100001 x
b1100000010 &
b1100000010 w
1%
1?
#1625000
0?
#1631250
0%
1E
b100001 F
b1100000010 B
1?
#1637500
0?
#1643750
0E
1D
1?
#1650000
0?
#1656250
b101 y
b11 i
0D
1?
#1662500
0?
#1668750
b110 y
b101100 $
b101100 x
b1100000011 &
b1100000011 w
1%
1?
#1675000
0?
#1681250
0%
1E
b101100 F
b1100000011 B
1?
#1687500
0?
#1693750
0E
1D
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