From 7e2711fa2734241e5388cb768a7e03a4cd50acdc Mon Sep 17 00:00:00 2001 From: Michele Bigi Date: Wed, 2 Sep 2026 21:00:46 +0200 Subject: [PATCH] feat: widen ADDR_WIDTH to 23 bits for full 8MB PSRAM addressing MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Bumps ADDR_WIDTH's default from 22 to 23 bits across every RTL module (neuron_memory, layer_sequencer, spi_engine, spi_neuron_top, mem_arbiter, int8_memory_access, memory_interface, psram_controller, memory_model) and every testbench that mirrors it, so the system's byte-address space reaches the full 8 MiB the recommended PSRAM part (ISSI IS66WVE4M16EBLL-70BLI, docs/FPGA-Neural-Hardware-Design.md §3) actually provides -- previously only 4 MiB (half the chip) was reachable, since int8_memory_access.v's byte->word address shift (addr >> 1) turned the old 22-bit byte address into only 21 real word bits, one short of the chip's real 22-bit word address (A0-A21). At 23 bits, that same shift lands exactly on all 22 chip address lines, so the whole part is usable now instead of deferred to a future widening. Also fixes a stray 22'd11-sized literal in layer_sequencer.v's descriptor-table address increment (numerically already safe via Verilog's zero-extension, but now correctly unsized so it always matches ADDR_WIDTH instead of silently assuming 22). Updated docs/FPGA-NeuralNetwork-Engine.md's SPI protocol address-field note (23 bits, top 1 reserved bit instead of 2) and docs/FPGA-Neural-Hardware-Design.md's PSRAM section (the "chip has one spare address line" framing is gone now that all 22 are wired and used). Full regression (all 11 ADDR_WIDTH-touching testbenches, plus a Yosys elaboration check of spi_neuron_top with the new default and no override) passes clean. Co-Authored-By: Claude Sonnet 5 Claude-Session: https://claude.ai/code/session_01WQV3vS9TXaGDJ5cRfnfidt --- docs/FPGA-Neural-Hardware-Design.md | 31 +- docs/FPGA-NeuralNetwork-Engine.md | 7 +- rtl/int8_memory_access.v | 2 +- rtl/layer_sequencer.v | 4 +- rtl/mem_arbiter.v | 2 +- rtl/memory_interface.v | 2 +- rtl/memory_model.v | 2 +- rtl/neuron_memory.v | 2 +- rtl/psram_controller.v | 2 +- rtl/spi_engine.v | 2 +- rtl/spi_neuron_top.v | 2 +- sim/int8_memory_access.vcd | 20 +- sim/int8_memory_access_tb.v | 2 +- sim/int8_psram_integration.vcd | 48 +- sim/int8_psram_integration_tb.v | 2 +- sim/layer.vcd | 2 +- sim/layer_sequencer.vcd | 98 +-- sim/layer_sequencer_tb.v | 2 +- sim/memory_interface.vcd | 634 +++++++------- sim/memory_interface_tb.v | 2 +- sim/neuron_memory.vcd | 78 +- sim/neuron_memory_multi.vcd | 76 +- sim/neuron_memory_multi_tb.v | 2 +- sim/neuron_memory_tb.v | 2 +- sim/parameter_sweep.vcd | 2 +- sim/psram_controller.vcd | 30 +- sim/psram_controller_tb.v | 2 +- sim/psram_model.v | 2 +- sim/spi_engine.vcd | 649 +++++++------- sim/spi_engine_tb.v | 2 +- sim/spi_neuron_top.vcd | 555 ++++++------ sim/spi_neuron_top_runnetwork.vcd | 1235 +++++++++++++-------------- sim/spi_neuron_top_runnetwork_tb.v | 2 +- sim/spi_neuron_top_tb.v | 2 +- sim/spi_slave.vcd | 2 +- 35 files changed, 1745 insertions(+), 1764 deletions(-) diff --git a/docs/FPGA-Neural-Hardware-Design.md b/docs/FPGA-Neural-Hardware-Design.md index a7544d6..de1f765 100644 --- a/docs/FPGA-Neural-Hardware-Design.md +++ b/docs/FPGA-Neural-Hardware-Design.md @@ -89,15 +89,17 @@ not** plug into this controller without a rewrite. RTL change needed. - TSOP-44/48 package — hand-solderable-adjacent, real distributor listings (DigiKey, Mouser) at time of writing. -- **Address bus note:** the chip is 4M×16 words (8 MB total, - needs a real 22-bit word address, A0–A21). The current RTL's - `ADDR_WIDTH=22` is a **byte** address (4 MiB space) that - `int8_memory_access.v` right-shifts by 1 (`addr >> 1`) into a word - address before it reaches `psram_controller` — so only **21** - word-address bits are actually driven today. Wire all 22 chip - address balls, but the chip's topmost line (A21) stays unused/tied - low until `ADDR_WIDTH` is widened to 23 to use the chip's full - 8 MB instead of today's 4 MiB. Free headroom, not a defect. +- **Address bus (2026-09-02: full addressing, all 22 chip lines + wired):** the chip is 4M×16 words (8 MB total), needing a + real 22-bit word address, A0–A21. `ADDR_WIDTH` is now **23** + bits across every module (`rtl/neuron_memory.v`, + `rtl/psram_controller.v`, etc. — bumped from the earlier 22-bit/ + 4 MiB default specifically to reach the full chip). + `int8_memory_access.v` right-shifts the 23-bit **byte** address by + 1 (`addr >> 1`) into a 22-bit **word** address before it reaches + `psram_controller` — that 22-bit word address maps exactly onto + the chip's real A0–A21, with nothing left unconnected. Full + 8 MB is addressable today, not deferred. **Fallback: ISSI IS61WV6416DBLL / IS61WV102416BLL** (true async SRAM, not pseudo-SRAM) — electrically drop-in on the same @@ -214,7 +216,7 @@ Before schematic capture, someone needs to: | Signal group | Port(s) | Count | Target bank (TBD) | |---|---|---|---| -| PSRAM address | `psram_a[21:0]` | 22 | one bank | +| PSRAM address | `psram_a[21:0]` (port is `[22:0]`, bit 22 always 0 post-shift — see §3) | 22 | one bank | | PSRAM data | `psram_dq[15:0]` | 16 | same or adjacent bank | | PSRAM control | `psram_ce_n/oe_n/we_n/lb_n/ub_n/zz_n` | 6 | same bank as above | | Application SPI | `sclk/mosi/miso/cs_n` | 4 | any bank, NOT the config-SPI bank (§6) | @@ -244,9 +246,12 @@ sizes are decided. ## 9. Open items before schematic capture -- [ ] Decide real PSRAM density needed (drives whether `ADDR_WIDTH` - stays 22 or can shrink, and whether the fallback true-SRAM - part in §3 is sufficient instead of the pseudo-SRAM) +- [x] `ADDR_WIDTH` set to 23 (full 8 MB) across all RTL modules + and testbenches, matching the recommended part's real capacity + (2026-09-02) — see §3. +- [ ] If the fallback true-SRAM part in §3 is used instead (smaller + density), decide whether to shrink `ADDR_WIDTH` back down to + match it or keep 23 with the extra range simply unused. - [ ] Real `.lpf` pin assignment (§7) and a synthesis run against it (current benchmark results all use auto-placed I/O) - [ ] Confirm PSRAM/SPI signal integrity at whatever clock is diff --git a/docs/FPGA-NeuralNetwork-Engine.md b/docs/FPGA-NeuralNetwork-Engine.md index 4780478..dd2d59e 100644 --- a/docs/FPGA-NeuralNetwork-Engine.md +++ b/docs/FPGA-NeuralNetwork-Engine.md @@ -400,9 +400,10 @@ here). The FPGA is always SPI slave. One command per CS-low period; byte 0 of every transaction is the opcode. **Multi-byte fields** are big-endian (most significant byte first). -Byte addresses are `ADDR_WIDTH`-bit (22 bits today, from -`rtl/neuron_memory.v`), carried in a 3-byte field with the top 2 bits -reserved as 0. +Byte addresses are `ADDR_WIDTH`-bit (23 bits today, from +`rtl/neuron_memory.v` — sized for a full 8 MiB PSRAM, see +`docs/FPGA-Neural-Hardware-Design.md` §3), carried in a 3-byte field +with the top bit reserved as 0. **Length is explicit**, not CS-edge-delimited: `WRITE_RAM`/`READ_RAM` carry a 2-byte length field, so the SPI controller only needs a byte diff --git a/rtl/int8_memory_access.v b/rtl/int8_memory_access.v index 7ba5a5c..cfa32b1 100644 --- a/rtl/int8_memory_access.v +++ b/rtl/int8_memory_access.v @@ -1,5 +1,5 @@ module int8_memory_access #( - parameter ADDR_WIDTH = 22 + parameter ADDR_WIDTH = 23 )( input wire clk, input wire rst, diff --git a/rtl/layer_sequencer.v b/rtl/layer_sequencer.v index dbb26c9..caef816 100644 --- a/rtl/layer_sequencer.v +++ b/rtl/layer_sequencer.v @@ -45,7 +45,7 @@ // ================================================================ module layer_sequencer #( - parameter ADDR_WIDTH = 22, + parameter ADDR_WIDTH = 23, parameter DATA_WIDTH = 8, parameter N_WIDTH = 256, // = neuron_memory's N_INPUTS = N_NEURONS parameter N_LAYERS = 4 @@ -314,7 +314,7 @@ module layer_sequencer #( cur_sel <= write_sel; write_sel <= ~write_sel; layer_idx <= layer_idx + 8'd1; - desc_table_addr <= desc_table_addr + 22'd11; + desc_table_addr <= desc_table_addr + 11; desc_byte_idx <= 4'd0; state <= ST_READ_DESC; diff --git a/rtl/mem_arbiter.v b/rtl/mem_arbiter.v index 69056a7..0e1a7cc 100644 --- a/rtl/mem_arbiter.v +++ b/rtl/mem_arbiter.v @@ -29,7 +29,7 @@ // ================================================================ module mem_arbiter #( - parameter ADDR_WIDTH = 22 + parameter ADDR_WIDTH = 23 )( input wire clk, input wire rst, diff --git a/rtl/memory_interface.v b/rtl/memory_interface.v index 828aeac..f9b0d20 100644 --- a/rtl/memory_interface.v +++ b/rtl/memory_interface.v @@ -1,5 +1,5 @@ module memory_interface #( - parameter ADDR_WIDTH = 22, + parameter ADDR_WIDTH = 23, parameter DATA_WIDTH = 16 )( input wire clk, diff --git a/rtl/memory_model.v b/rtl/memory_model.v index c938183..336aa44 100644 --- a/rtl/memory_model.v +++ b/rtl/memory_model.v @@ -1,5 +1,5 @@ module memory_model #( - parameter ADDR_WIDTH = 22, + parameter ADDR_WIDTH = 23, parameter DATA_WIDTH = 16, parameter DEPTH = 4096, parameter READ_LATENCY = 2 diff --git a/rtl/neuron_memory.v b/rtl/neuron_memory.v index 69cd744..c521d77 100644 --- a/rtl/neuron_memory.v +++ b/rtl/neuron_memory.v @@ -1,7 +1,7 @@ `timescale 1ns/1ps module neuron_memory #( - parameter ADDR_WIDTH = 22, + parameter ADDR_WIDTH = 23, parameter DATA_WIDTH = 8, parameter N_INPUTS = 32, parameter N_NEURONS = 1, diff --git a/rtl/psram_controller.v b/rtl/psram_controller.v index 57de1e9..2d9d6c2 100644 --- a/rtl/psram_controller.v +++ b/rtl/psram_controller.v @@ -1,5 +1,5 @@ module psram_controller #( - parameter ADDR_WIDTH = 22, + parameter ADDR_WIDTH = 23, parameter DATA_WIDTH = 16, parameter CLK_FREQ_MHZ = 80 )( diff --git a/rtl/spi_engine.v b/rtl/spi_engine.v index 276a01d..fd514ef 100644 --- a/rtl/spi_engine.v +++ b/rtl/spi_engine.v @@ -32,7 +32,7 @@ // ================================================================ module spi_engine #( - parameter ADDR_WIDTH = 22, + parameter ADDR_WIDTH = 23, parameter DATA_WIDTH = 8, parameter N_INPUTS = 32, parameter N_NEURONS = 1, diff --git a/rtl/spi_neuron_top.v b/rtl/spi_neuron_top.v index 41f857e..afe571f 100644 --- a/rtl/spi_neuron_top.v +++ b/rtl/spi_neuron_top.v @@ -17,7 +17,7 @@ // ================================================================ module spi_neuron_top #( - parameter ADDR_WIDTH = 22, + parameter ADDR_WIDTH = 23, parameter DATA_WIDTH = 8, parameter N_INPUTS = 32, parameter N_NEURONS = 1, diff --git a/sim/int8_memory_access.vcd b/sim/int8_memory_access.vcd index 1b7a8e2..e049e5e 100644 --- a/sim/int8_memory_access.vcd +++ b/sim/int8_memory_access.vcd @@ -1,5 +1,5 @@ $date - Wed Sep 2 12:39:25 2026 + Wed Sep 2 20:58:26 2026 $end $version Icarus Verilog @@ -17,10 +17,10 @@ $var wire 16 & mem_wdata [15:0] $end $var wire 1 ' mem_ub_n $end $var wire 1 ( mem_req $end $var wire 1 ) mem_lb_n $end -$var wire 22 * mem_addr [21:0] $end +$var wire 23 * mem_addr [22:0] $end $var parameter 32 + ADDR_WIDTH $end $var real 1 , CLK_PERIOD $end -$var reg 22 - addr [21:0] $end +$var reg 23 - addr [22:0] $end $var reg 1 . clk $end $var reg 16 / model_rdata [15:0] $end $var reg 1 0 model_ready $end @@ -30,7 +30,7 @@ $var reg 8 3 wdata [7:0] $end $var reg 1 4 wr $end $var integer 32 5 i [31:0] $end $scope module dut $end -$var wire 22 6 addr [21:0] $end +$var wire 23 6 addr [22:0] $end $var wire 1 . clk $end $var wire 16 7 mem_rdata [15:0] $end $var wire 1 " mem_ready $end @@ -41,8 +41,8 @@ $var wire 1 4 wr $end $var parameter 32 9 ADDR_WIDTH $end $var parameter 2 : STATE_IDLE $end $var parameter 2 ; STATE_WAIT $end -$var reg 22 < addr_reg [21:0] $end -$var reg 22 = mem_addr [21:0] $end +$var reg 23 < addr_reg [22:0] $end +$var reg 23 = mem_addr [22:0] $end $var reg 1 ) mem_lb_n $end $var reg 1 ( mem_req $end $var reg 1 ' mem_ub_n $end @@ -53,11 +53,11 @@ $var reg 1 # ready $end $var reg 2 @ state [1:0] $end $upscope $end $scope task read_byte $end -$var reg 22 A byte_addr [21:0] $end +$var reg 23 A byte_addr [22:0] $end $var reg 8 B expected [7:0] $end $upscope $end $scope task write_byte $end -$var reg 22 C byte_addr [21:0] $end +$var reg 23 C byte_addr [22:0] $end $var reg 8 D data [7:0] $end $upscope $end $upscope $end @@ -66,9 +66,9 @@ $comment Show the parameter values. $end $dumpall b1 ; b0 : -b10110 9 +b10111 9 r12.5 , -b10110 + +b10111 + $end #0 $dumpvars diff --git a/sim/int8_memory_access_tb.v b/sim/int8_memory_access_tb.v index 9c374f7..4193b44 100644 --- a/sim/int8_memory_access_tb.v +++ b/sim/int8_memory_access_tb.v @@ -2,7 +2,7 @@ module tb; - localparam ADDR_WIDTH = 22; + localparam ADDR_WIDTH = 23; localparam CLK_PERIOD = 12.5; reg clk; diff --git a/sim/int8_psram_integration.vcd b/sim/int8_psram_integration.vcd index adff748..18bb4a3 100644 --- a/sim/int8_psram_integration.vcd +++ b/sim/int8_psram_integration.vcd @@ -1,5 +1,5 @@ $date - Wed Sep 2 12:45:33 2026 + Wed Sep 2 20:58:55 2026 $end $version Icarus Verilog @@ -22,10 +22,10 @@ $var wire 1 + psram_mem_req $end $var wire 1 , psram_mem_ready $end $var wire 16 - psram_mem_rdata [15:0] $end $var wire 1 . psram_mem_lb_n $end -$var wire 22 / psram_mem_addr [21:0] $end +$var wire 23 / psram_mem_addr [22:0] $end $var wire 1 0 psram_lb_n $end $var wire 1 1 psram_ce_n $end -$var wire 22 2 psram_a [21:0] $end +$var wire 23 2 psram_a [22:0] $end $var wire 1 3 mem_wr $end $var wire 16 4 mem_wdata [15:0] $end $var wire 1 5 mem_ub_n $end @@ -33,11 +33,11 @@ $var wire 1 6 mem_req $end $var wire 1 7 mem_ready $end $var wire 16 8 mem_rdata [15:0] $end $var wire 1 9 mem_lb_n $end -$var wire 22 : mem_addr [21:0] $end +$var wire 23 : mem_addr [22:0] $end $var parameter 32 ; ADDR_WIDTH $end $var real 1 < CLK_PERIOD $end $var parameter 32 = DATA_WIDTH $end -$var reg 22 > addr [21:0] $end +$var reg 23 > addr [22:0] $end $var reg 1 ? clk $end $var reg 1 @ req $end $var reg 1 A rst $end @@ -47,7 +47,7 @@ $var reg 1 D wr $end $var integer 32 E i [31:0] $end $var integer 32 F test_addr [31:0] $end $scope module int8_access $end -$var wire 22 G addr [21:0] $end +$var wire 23 G addr [22:0] $end $var wire 1 ? clk $end $var wire 1 @ req $end $var wire 1 A rst $end @@ -58,8 +58,8 @@ $var wire 16 I mem_rdata [15:0] $end $var parameter 32 J ADDR_WIDTH $end $var parameter 2 K STATE_IDLE $end $var parameter 2 L STATE_WAIT $end -$var reg 22 M addr_reg [21:0] $end -$var reg 22 N mem_addr [21:0] $end +$var reg 23 M addr_reg [22:0] $end +$var reg 23 N mem_addr [22:0] $end $var reg 1 9 mem_lb_n $end $var reg 1 6 mem_req $end $var reg 1 5 mem_ub_n $end @@ -70,7 +70,7 @@ $var reg 1 " ready $end $var reg 2 Q state [1:0] $end $upscope $end $scope module memory_if $end -$var wire 22 R addr [21:0] $end +$var wire 23 R addr [22:0] $end $var wire 1 ? clk $end $var wire 1 9 lb_n $end $var wire 1 6 req $end @@ -84,7 +84,7 @@ $var parameter 32 U ADDR_WIDTH $end $var parameter 32 V DATA_WIDTH $end $var parameter 2 W STATE_IDLE $end $var parameter 2 X STATE_WAIT $end -$var reg 22 Y mem_addr [21:0] $end +$var reg 23 Y mem_addr [22:0] $end $var reg 1 . mem_lb_n $end $var reg 1 + mem_req $end $var reg 1 * mem_ub_n $end @@ -103,7 +103,7 @@ $var wire 1 & ub_n $end $var wire 1 ' oe_n $end $var wire 1 0 lb_n $end $var wire 1 1 ce_n $end -$var wire 22 ^ a [21:0] $end +$var wire 23 ^ a [22:0] $end $var parameter 32 _ ADDR_WIDTH $end $var parameter 32 ` DATA_WIDTH $end $var parameter 32 a DEPTH $end @@ -122,7 +122,7 @@ $var real 1 m TWC_NS $end $var real 1 n TWPH_NS $end $var real 1 o TWP_NS $end $var real 1 p TWR_NS $end -$var reg 22 q active_addr [21:0] $end +$var reg 23 q active_addr [22:0] $end $var reg 16 r active_wdata [15:0] $end $var reg 1 s dq_oe $end $var reg 16 t dq_out [15:0] $end @@ -140,17 +140,17 @@ $var real 1 !" oe_low_time $end $var real 1 "" powerup_time $end $var real 1 #" we_high_time $end $var real 1 $" we_low_time $end -$scope begin $unm_blk_59 $end +$scope begin $unm_blk_23 $end $var real 1 %" access_time $end $upscope $end -$scope begin $unm_blk_71 $end +$scope begin $unm_blk_35 $end $var real 1 &" data_setup $end $var real 1 '" write_width $end $upscope $end $upscope $end $scope module psram_ctrl $end $var wire 1 ? clk $end -$var wire 22 (" mem_addr [21:0] $end +$var wire 23 (" mem_addr [22:0] $end $var wire 1 . mem_lb_n $end $var wire 1 + mem_req $end $var wire 1 * mem_ub_n $end @@ -169,14 +169,14 @@ $var parameter 3 2" STATE_INIT $end $var parameter 3 3" STATE_READ $end $var parameter 3 4" STATE_WRITE $end $var parameter 3 5" STATE_WRITE_WAIT $end -$var reg 22 6" address_reg [21:0] $end +$var reg 23 6" address_reg [22:0] $end $var reg 14 7" counter [13:0] $end $var reg 1 8" dq_oe $end $var reg 16 9" dq_out [15:0] $end $var reg 1 :" lb_reg $end $var reg 16 ;" mem_rdata [15:0] $end $var reg 1 , mem_ready $end -$var reg 22 <" psram_a [21:0] $end +$var reg 23 <" psram_a [22:0] $end $var reg 1 1 psram_ce_n $end $var reg 1 0 psram_lb_n $end $var reg 1 ' psram_oe_n $end @@ -189,11 +189,11 @@ $var reg 16 ?" wdata_reg [15:0] $end $var reg 1 @" wr_reg $end $upscope $end $scope task read_byte $end -$var reg 22 A" byte_addr [21:0] $end +$var reg 23 A" byte_addr [22:0] $end $var reg 8 B" expected [7:0] $end $upscope $end $scope task write_byte $end -$var reg 22 C" byte_addr [21:0] $end +$var reg 23 C" byte_addr [22:0] $end $var reg 8 D" data [7:0] $end $upscope $end $upscope $end @@ -209,7 +209,7 @@ b10111011100000 0" b10000 /" b1110 ." b1010000 -" -b10110 ," +b10111 ," b110 +" r0 p r46 o @@ -228,17 +228,17 @@ r70 c r70 b b100000000000000 a b10000 ` -b10110 _ +b10111 _ b1 X b0 W b10000 V -b10110 U +b10111 U b1 L b0 K -b10110 J +b10111 J b10000 = r12.5 < -b10110 ; +b10111 ; $end #0 $dumpvars diff --git a/sim/int8_psram_integration_tb.v b/sim/int8_psram_integration_tb.v index 65cf794..bb8226c 100644 --- a/sim/int8_psram_integration_tb.v +++ b/sim/int8_psram_integration_tb.v @@ -2,7 +2,7 @@ module tb; - localparam ADDR_WIDTH = 22; + localparam ADDR_WIDTH = 23; localparam DATA_WIDTH = 16; localparam CLK_PERIOD = 12.5; // 80 MHz diff --git a/sim/layer.vcd b/sim/layer.vcd index 89dbde2..a11bddb 100644 --- a/sim/layer.vcd +++ b/sim/layer.vcd @@ -1,5 +1,5 @@ $date - Wed Sep 2 20:14:10 2026 + Wed Sep 2 20:58:26 2026 $end $version Icarus Verilog diff --git a/sim/layer_sequencer.vcd b/sim/layer_sequencer.vcd index 432f219..f9a38c4 100644 --- a/sim/layer_sequencer.vcd +++ b/sim/layer_sequencer.vcd @@ -1,5 +1,5 @@ $date - Wed Sep 2 20:13:54 2026 + Wed Sep 2 20:58:00 2026 $end $version Icarus Verilog @@ -13,35 +13,35 @@ $var wire 1 " seq_busy $end $var wire 1 # ram_wr $end $var wire 8 $ ram_wdata [7:0] $end $var wire 1 % ram_req $end -$var wire 22 & ram_addr [21:0] $end -$var wire 22 ' nm_x_base [21:0] $end -$var wire 22 ( nm_w_base [21:0] $end +$var wire 23 & ram_addr [22:0] $end +$var wire 23 ' nm_x_base [22:0] $end +$var wire 23 ( nm_w_base [22:0] $end $var wire 1 ) nm_start $end $var wire 16 * nm_n_neurons [15:0] $end $var wire 16 + nm_n_inputs [15:0] $end -$var wire 22 , nm_bias_addr [21:0] $end +$var wire 23 , nm_bias_addr [22:0] $end $var wire 2 - nm_activation [1:0] $end $var parameter 32 . ADDR_WIDTH $end -$var parameter 22 / BUF_A_BASE $end -$var parameter 22 0 BUF_B_BASE $end +$var parameter 23 / BUF_A_BASE $end +$var parameter 23 0 BUF_B_BASE $end $var real 1 1 CLK_PERIOD $end $var parameter 32 2 DATA_WIDTH $end -$var parameter 22 3 L0_BIAS_ADDR $end -$var parameter 22 4 L0_W_BASE $end -$var parameter 22 5 L1_BIAS_ADDR $end -$var parameter 22 6 L1_W_BASE $end +$var parameter 23 3 L0_BIAS_ADDR $end +$var parameter 23 4 L0_W_BASE $end +$var parameter 23 5 L1_BIAS_ADDR $end +$var parameter 23 6 L1_W_BASE $end $var parameter 32 7 N_LAYERS $end $var parameter 32 8 N_WIDTH $end $var parameter 1 9 RAM_IDLE $end $var parameter 1 : RAM_WAIT $end -$var parameter 22 ; TABLE_BASE $end -$var parameter 22 < X_BASE $end -$var reg 22 = buf_a_base [21:0] $end -$var reg 22 > buf_b_base [21:0] $end +$var parameter 23 ; TABLE_BASE $end +$var parameter 23 < X_BASE $end +$var reg 23 = buf_a_base [22:0] $end +$var reg 23 > buf_b_base [22:0] $end $var reg 1 ? clk $end $var reg 1 @ nm_busy $end $var reg 1 A nm_done $end -$var reg 22 B ram_addr_latched [21:0] $end +$var reg 23 B ram_addr_latched [22:0] $end $var reg 8 C ram_rdata [7:0] $end $var reg 1 D ram_ready $end $var reg 1 E ram_state $end @@ -52,8 +52,8 @@ $var reg 8 I run_num_layers [7:0] $end $var reg 1 J run_start $end $var reg 1 K seq_busy_dropped_early $end $var reg 32 L staged_y [31:0] $end -$var reg 22 M table_base [21:0] $end -$var reg 22 N x_base [21:0] $end +$var reg 23 M table_base [22:0] $end +$var reg 23 N x_base [22:0] $end $var reg 32 O y_bus [31:0] $end $var integer 32 P errors [31:0] $end $var integer 32 Q errors_before [31:0] $end @@ -61,8 +61,8 @@ $var integer 32 R i [31:0] $end $var integer 32 S nm_delay [31:0] $end $var integer 32 T seq_done_count [31:0] $end $scope module u_dut $end -$var wire 22 U buf_a_base [21:0] $end -$var wire 22 V buf_b_base [21:0] $end +$var wire 23 U buf_a_base [22:0] $end +$var wire 23 V buf_b_base [22:0] $end $var wire 1 ? clk $end $var wire 1 @ nm_busy $end $var wire 1 A nm_done $end @@ -71,8 +71,8 @@ $var wire 1 D ram_ready $end $var wire 1 H rst $end $var wire 8 X run_num_layers [7:0] $end $var wire 1 J run_start $end -$var wire 22 Y table_base [21:0] $end -$var wire 22 Z x_base [21:0] $end +$var wire 23 Y table_base [22:0] $end +$var wire 23 Z x_base [22:0] $end $var wire 32 [ y_bus [31:0] $end $var parameter 32 \ ADDR_WIDTH $end $var parameter 32 ] DATA_WIDTH $end @@ -90,19 +90,19 @@ $var reg 24 h bias_addr_acc [23:0] $end $var reg 3 i copy_idx [2:0] $end $var reg 1 j cur_sel $end $var reg 4 k desc_byte_idx [3:0] $end -$var reg 22 l desc_table_addr [21:0] $end +$var reg 23 l desc_table_addr [22:0] $end $var reg 8 m layer_idx [7:0] $end $var reg 16 n n_inputs_acc [15:0] $end $var reg 16 o n_neurons_acc [15:0] $end $var reg 2 p nm_activation [1:0] $end -$var reg 22 q nm_bias_addr [21:0] $end +$var reg 23 q nm_bias_addr [22:0] $end $var reg 16 r nm_n_inputs [15:0] $end $var reg 16 s nm_n_neurons [15:0] $end $var reg 1 ) nm_start $end -$var reg 22 t nm_w_base [21:0] $end -$var reg 22 u nm_x_base [21:0] $end +$var reg 23 t nm_w_base [22:0] $end +$var reg 23 u nm_x_base [22:0] $end $var reg 8 v num_layers_reg [7:0] $end -$var reg 22 w ram_addr [21:0] $end +$var reg 23 w ram_addr [22:0] $end $var reg 1 % ram_req $end $var reg 8 x ram_wdata [7:0] $end $var reg 1 # ram_wr $end @@ -136,7 +136,7 @@ b101 ` b100 _ b100 ^ b1000 ] -b10110 \ +b10111 \ b10000 < b100000000 ; 1: @@ -151,7 +151,7 @@ b1000 2 r12.5 1 b1100000000 0 b1000000000 / -b10110 . +b10111 . $end #0 $dumpvars @@ -345,15 +345,15 @@ b10 | #168750 0E 1D -bx000000 C -bx000000 W +bx0000000 C +bx0000000 W 1? #175000 0? #181250 b1 y b1 k -bx0000000000000000000000 z +bx00000000000000000000000 z 0D 1? #187500 @@ -384,7 +384,7 @@ b10000 W #231250 b1 y b10 k -bx0000000001000000000000 z +bx00000000001000000000000 z 0D 1? #237500 @@ -437,15 +437,15 @@ b100000011 B #318750 0E 1D -bx000000 C -bx000000 W +bx0000000 C +bx0000000 W 1? #325000 0? #331250 b1 y b100 k -bx0000000000000000000000 h +bx00000000000000000000000 h 0D 1? #337500 @@ -476,7 +476,7 @@ b100000 W #381250 b1 y b101 k -bx0000000010000000000000 h +bx00000000010000000000000 h 0D 1? #387500 @@ -799,8 +799,8 @@ b100001011 B #906250 0E 1D -bx000000 C -bx000000 W +bx0000000 C +bx0000000 W 1? #912500 0? @@ -838,7 +838,7 @@ b110000 W 0D b1 y b10 k -bx0000000011000000000000 z +bx00000000011000000000000 z 1? #975000 0? @@ -890,8 +890,8 @@ b100001110 B #1056250 0E 1D -bx000000 C -bx000000 W +bx0000000 C +bx0000000 W 1? #1062500 0? @@ -929,7 +929,7 @@ b1000000 W 0D b1 y b101 k -bx0000000100000000000000 h +bx00000000100000000000000 h 1? #1125000 0? @@ -1372,8 +1372,8 @@ b11 X #1818750 0E 1D -bx000000 C -bx000000 W +bx0000000 C +bx0000000 W 1? #1825000 0J @@ -1411,7 +1411,7 @@ b10000 W #1881250 b1 y b10 k -bx0000000001000000000000 z +bx00000000001000000000000 z 0D 1? #1887500 @@ -1464,8 +1464,8 @@ b100000011 B #1968750 0E 1D -bx000000 C -bx000000 W +bx0000000 C +bx0000000 W 1? #1975000 0? @@ -1502,7 +1502,7 @@ b100000 W #2031250 b1 y b101 k -bx0000000010000000000000 h +bx00000000010000000000000 h 0D 1? #2037500 diff --git a/sim/layer_sequencer_tb.v b/sim/layer_sequencer_tb.v index 74b3ce1..a6a3d65 100644 --- a/sim/layer_sequencer_tb.v +++ b/sim/layer_sequencer_tb.v @@ -25,7 +25,7 @@ module tb; - localparam ADDR_WIDTH = 22; + localparam ADDR_WIDTH = 23; localparam DATA_WIDTH = 8; localparam N_WIDTH = 4; localparam N_LAYERS = 4; diff --git a/sim/memory_interface.vcd b/sim/memory_interface.vcd index 20b4232..64ff7bc 100644 --- a/sim/memory_interface.vcd +++ b/sim/memory_interface.vcd @@ -1,5 +1,5 @@ $date - Wed Sep 2 11:47:57 2026 + Wed Sep 2 20:58:40 2026 $end $version Icarus Verilog @@ -15,102 +15,110 @@ $var wire 16 $ mem_wdata [15:0] $end $var wire 1 % mem_req $end $var wire 1 & mem_ready $end $var wire 16 ' mem_rdata [15:0] $end -$var wire 22 ( mem_addr [21:0] $end +$var wire 23 ( mem_addr [22:0] $end $var parameter 32 ) ADDR_WIDTH $end $var parameter 32 * DATA_WIDTH $end -$var reg 22 + addr [21:0] $end +$var reg 23 + addr [22:0] $end $var reg 1 , clk $end $var reg 1 - req $end $var reg 1 . rst $end $var reg 16 / wdata [15:0] $end $var reg 1 0 wr $end $scope module dut $end -$var wire 22 1 addr [21:0] $end +$var wire 23 1 addr [22:0] $end $var wire 1 , clk $end +$var wire 1 2 lb_n $end $var wire 1 - req $end $var wire 1 . rst $end -$var wire 16 2 wdata [15:0] $end +$var wire 1 3 ub_n $end +$var wire 16 4 wdata [15:0] $end $var wire 1 0 wr $end $var wire 1 & mem_ready $end -$var wire 16 3 mem_rdata [15:0] $end -$var parameter 32 4 ADDR_WIDTH $end -$var parameter 32 5 DATA_WIDTH $end -$var parameter 2 6 STATE_IDLE $end -$var parameter 2 7 STATE_WAIT $end -$var reg 22 8 mem_addr [21:0] $end +$var wire 16 5 mem_rdata [15:0] $end +$var parameter 32 6 ADDR_WIDTH $end +$var parameter 32 7 DATA_WIDTH $end +$var parameter 2 8 STATE_IDLE $end +$var parameter 2 9 STATE_WAIT $end +$var reg 23 : mem_addr [22:0] $end +$var reg 1 ; mem_lb_n $end $var reg 1 % mem_req $end -$var reg 16 9 mem_wdata [15:0] $end +$var reg 1 < mem_ub_n $end +$var reg 16 = mem_wdata [15:0] $end $var reg 1 # mem_wr $end -$var reg 16 : rdata [15:0] $end +$var reg 16 > rdata [15:0] $end $var reg 1 ! ready $end -$var reg 2 ; state [1:0] $end +$var reg 2 ? state [1:0] $end $upscope $end $scope module memory $end -$var wire 22 < addr [21:0] $end +$var wire 23 @ addr [22:0] $end $var wire 1 , clk $end $var wire 1 % req $end $var wire 1 . rst $end -$var wire 16 = wdata [15:0] $end +$var wire 16 A wdata [15:0] $end $var wire 1 # wr $end -$var parameter 32 > ADDR_WIDTH $end -$var parameter 32 ? DATA_WIDTH $end -$var parameter 32 @ DEPTH $end -$var parameter 32 A READ_LATENCY $end -$var reg 1 B busy $end -$var reg 22 C pending_addr [21:0] $end -$var reg 16 D pending_wdata [15:0] $end -$var reg 1 E pending_wr $end -$var reg 16 F rdata [15:0] $end +$var parameter 32 B ADDR_WIDTH $end +$var parameter 32 C DATA_WIDTH $end +$var parameter 32 D DEPTH $end +$var parameter 32 E READ_LATENCY $end +$var reg 1 F busy $end +$var reg 23 G pending_addr [22:0] $end +$var reg 16 H pending_wdata [15:0] $end +$var reg 1 I pending_wr $end +$var reg 16 J rdata [15:0] $end $var reg 1 & ready $end -$var integer 32 G delay_count [31:0] $end -$var integer 32 H i [31:0] $end +$var integer 32 K delay_count [31:0] $end +$var integer 32 L i [31:0] $end $upscope $end $scope task read_mem $end -$var reg 22 I address [21:0] $end -$var reg 16 J expected [15:0] $end -$var reg 16 K received [15:0] $end +$var reg 23 M address [22:0] $end +$var reg 16 N expected [15:0] $end +$var reg 16 O received [15:0] $end $upscope $end $scope task write_mem $end -$var reg 22 L address [21:0] $end -$var reg 16 M data [15:0] $end +$var reg 23 P address [22:0] $end +$var reg 16 Q data [15:0] $end $upscope $end $upscope $end $enddefinitions $end $comment Show the parameter values. $end $dumpall -b10 A -b1000000000000 @ -b10000 ? -b10110 > -b1 7 -b0 6 -b10000 5 -b10110 4 +b10 E +b1000000000000 D +b10000 C +b10111 B +b1 9 +b0 8 +b10000 7 +b10111 6 b10000 * -b10110 ) +b10111 ) $end #0 $dumpvars +bx Q +bx P +bx O +bx N bx M bx L bx K bx J -bx I +xI bx H bx G -bx F -xE -bx D -bx C -xB +xF +bx A +bx @ +bx ? +bx > bx = -bx < -bx ; +x< +x; bx : -bx 9 -bx 8 -bx 3 -b0 2 +bx 5 +b0 4 +z3 +z2 b0 1 00 b0 / @@ -129,38 +137,40 @@ x! $end #5000 b0 $ -b0 9 b0 = +b0 A b0 ( -b0 8 -b0 < +b0 : +b0 @ 0# 0% +1< +1; 0! b0 " -b0 : -b0 ; +b0 > +b0 ? +b0 K +b0 H b0 G -b0 D -b0 C -0E -0B +0I +0F 0& b0 ' -b0 3 -b0 F -b1000000000000 H +b0 5 +b0 J +b1000000000000 L 1, #10000 0, #15000 -b1000000000000 H +b1000000000000 L 1, #20000 0, #25000 -b1001000110100 M -b1 L +b1001000110100 Q +b1 P 0. 1, #30000 @@ -169,7 +179,7 @@ b1 L 1- 10 b1001000110100 / -b1001000110100 2 +b1001000110100 4 b1 + b1 1 1, @@ -177,55 +187,57 @@ b1 1 0, #45000 0- -b1 ; +b1 ? 1% +z< +z; b1001000110100 $ -b1001000110100 9 b1001000110100 = +b1001000110100 A b1 ( -b1 8 -b1 < +b1 : +b1 @ 1# 1, #50000 0, #55000 -b10 G -b1001000110100 D -b1 C -1E -1B +b10 K +b1001000110100 H +b1 G +1I +1F 0% 1, #60000 0, #65000 -b1 G +b1 K 1, #70000 0, #75000 -b0 G +b0 K 1, #80000 0, #85000 -0B +0F 1& 1, #90000 0, #95000 0& -b0 ; +b0 ? 1! 1, #100000 0, #105000 0! -b1001000110100 J -b1 I +b1001000110100 N +b1 M 1, #110000 0, @@ -237,53 +249,53 @@ b1 I 0, #125000 0- -b1 ; +b1 ? 1% 0# 1, #130000 0, #135000 -b10 G -0E -1B +b10 K +0I +1F 0% 1, #140000 0, #145000 -b1 G +b1 K 1, #150000 0, #155000 -b0 G +b0 K 1, #160000 0, #165000 -0B +0F 1& b1001000110100 ' -b1001000110100 3 -b1001000110100 F +b1001000110100 5 +b1001000110100 J 1, #170000 0, #175000 -b1001000110100 K +b1001000110100 O 0& -b0 ; +b0 ? 1! b1001000110100 " -b1001000110100 : +b1001000110100 > 1, #180000 0, #185000 0! -b1010101111001101 M -b10000 L +b1010101111001101 Q +b10000 P 1, #190000 0, @@ -291,7 +303,7 @@ b10000 L 1- 10 b1010101111001101 / -b1010101111001101 2 +b1010101111001101 4 b10000 + b10000 1 1, @@ -299,55 +311,55 @@ b10000 1 0, #205000 0- -b1 ; +b1 ? 1% b1010101111001101 $ -b1010101111001101 9 b1010101111001101 = +b1010101111001101 A b10000 ( -b10000 8 -b10000 < +b10000 : +b10000 @ 1# 1, #210000 0, #215000 -b10 G -b1010101111001101 D -b10000 C -1E -1B +b10 K +b1010101111001101 H +b10000 G +1I +1F 0% 1, #220000 0, #225000 -b1 G +b1 K 1, #230000 0, #235000 -b0 G +b0 K 1, #240000 0, #245000 -0B +0F 1& 1, #250000 0, #255000 0& -b0 ; +b0 ? 1! 1, #260000 0, #265000 0! -b1010101111001101 J -b10000 I +b1010101111001101 N +b10000 M 1, #270000 0, @@ -359,53 +371,53 @@ b10000 I 0, #285000 0- -b1 ; +b1 ? 1% 0# 1, #290000 0, #295000 -b10 G -0E -1B +b10 K +0I +1F 0% 1, #300000 0, #305000 -b1 G +b1 K 1, #310000 0, #315000 -b0 G +b0 K 1, #320000 0, #325000 -0B +0F 1& b1010101111001101 ' -b1010101111001101 3 -b1010101111001101 F +b1010101111001101 5 +b1010101111001101 J 1, #330000 0, #335000 -b1010101111001101 K +b1010101111001101 O 0& -b0 ; +b0 ? 1! b1010101111001101 " -b1010101111001101 : +b1010101111001101 > 1, #340000 0, #345000 0! -b101010110101010 M -b100000000 L +b101010110101010 Q +b100000000 P 1, #350000 0, @@ -413,7 +425,7 @@ b100000000 L 1- 10 b101010110101010 / -b101010110101010 2 +b101010110101010 4 b100000000 + b100000000 1 1, @@ -421,55 +433,55 @@ b100000000 1 0, #365000 0- -b1 ; +b1 ? 1% b101010110101010 $ -b101010110101010 9 b101010110101010 = +b101010110101010 A b100000000 ( -b100000000 8 -b100000000 < +b100000000 : +b100000000 @ 1# 1, #370000 0, #375000 -b10 G -b101010110101010 D -b100000000 C -1E -1B +b10 K +b101010110101010 H +b100000000 G +1I +1F 0% 1, #380000 0, #385000 -b1 G +b1 K 1, #390000 0, #395000 -b0 G +b0 K 1, #400000 0, #405000 -0B +0F 1& 1, #410000 0, #415000 0& -b0 ; +b0 ? 1! 1, #420000 0, #425000 0! -b101010110101010 J -b100000000 I +b101010110101010 N +b100000000 M 1, #430000 0, @@ -481,53 +493,53 @@ b100000000 I 0, #445000 0- -b1 ; +b1 ? 1% 0# 1, #450000 0, #455000 -b10 G -0E -1B +b10 K +0I +1F 0% 1, #460000 0, #465000 -b1 G +b1 K 1, #470000 0, #475000 -b0 G +b0 K 1, #480000 0, #485000 -0B +0F 1& b101010110101010 ' -b101010110101010 3 -b101010110101010 F +b101010110101010 5 +b101010110101010 J 1, #490000 0, #495000 -b101010110101010 K +b101010110101010 O 0& -b0 ; +b0 ? 1! b101010110101010 " -b101010110101010 : +b101010110101010 > 1, #500000 0, #505000 0! -b1 M -b1000000000 L +b1 Q +b1000000000 P 1, #510000 0, @@ -535,7 +547,7 @@ b1000000000 L 1- 10 b1 / -b1 2 +b1 4 b1000000000 + b1000000000 1 1, @@ -543,62 +555,62 @@ b1000000000 1 0, #525000 0- -b1 ; +b1 ? 1% b1 $ -b1 9 b1 = +b1 A b1000000000 ( -b1000000000 8 -b1000000000 < +b1000000000 : +b1000000000 @ 1# 1, #530000 0, #535000 -b10 G -b1 D -b1000000000 C -1E -1B +b10 K +b1 H +b1000000000 G +1I +1F 0% 1, #540000 0, #545000 -b1 G +b1 K 1, #550000 0, #555000 -b0 G +b0 K 1, #560000 0, #565000 -0B +0F 1& 1, #570000 0, #575000 0& -b0 ; +b0 ? 1! 1, #580000 0, #585000 0! -b10 M -b1000000001 L +b10 Q +b1000000001 P 1, #590000 0, #595000 1- b10 / -b10 2 +b10 4 b1000000001 + b1000000001 1 1, @@ -606,60 +618,60 @@ b1000000001 1 0, #605000 0- -b1 ; +b1 ? 1% b10 $ -b10 9 b10 = +b10 A b1000000001 ( -b1000000001 8 -b1000000001 < +b1000000001 : +b1000000001 @ 1, #610000 0, #615000 -b10 G -b10 D -b1000000001 C -1B +b10 K +b10 H +b1000000001 G +1F 0% 1, #620000 0, #625000 -b1 G +b1 K 1, #630000 0, #635000 -b0 G +b0 K 1, #640000 0, #645000 -0B +0F 1& 1, #650000 0, #655000 0& -b0 ; +b0 ? 1! 1, #660000 0, #665000 0! -b11 M -b1000000010 L +b11 Q +b1000000010 P 1, #670000 0, #675000 1- b11 / -b11 2 +b11 4 b1000000010 + b1000000010 1 1, @@ -667,53 +679,53 @@ b1000000010 1 0, #685000 0- -b1 ; +b1 ? 1% b11 $ -b11 9 b11 = +b11 A b1000000010 ( -b1000000010 8 -b1000000010 < +b1000000010 : +b1000000010 @ 1, #690000 0, #695000 -b10 G -b11 D -b1000000010 C -1B +b10 K +b11 H +b1000000010 G +1F 0% 1, #700000 0, #705000 -b1 G +b1 K 1, #710000 0, #715000 -b0 G +b0 K 1, #720000 0, #725000 -0B +0F 1& 1, #730000 0, #735000 0& -b0 ; +b0 ? 1! 1, #740000 0, #745000 0! -b1 J -b1000000000 I +b1 N +b1000000000 M 1, #750000 0, @@ -727,57 +739,57 @@ b1000000000 1 0, #765000 0- -b1 ; +b1 ? 1% b1000000000 ( -b1000000000 8 -b1000000000 < +b1000000000 : +b1000000000 @ 0# 1, #770000 0, #775000 -b10 G -b1000000000 C -0E -1B +b10 K +b1000000000 G +0I +1F 0% 1, #780000 0, #785000 -b1 G +b1 K 1, #790000 0, #795000 -b0 G +b0 K 1, #800000 0, #805000 -0B +0F 1& b1 ' -b1 3 -b1 F +b1 5 +b1 J 1, #810000 0, #815000 -b1 K +b1 O 0& -b0 ; +b0 ? 1! b1 " -b1 : +b1 > 1, #820000 0, #825000 0! -b10 J -b1000000001 I +b10 N +b1000000001 M 1, #830000 0, @@ -790,55 +802,55 @@ b1000000001 1 0, #845000 0- -b1 ; +b1 ? 1% b1000000001 ( -b1000000001 8 -b1000000001 < +b1000000001 : +b1000000001 @ 1, #850000 0, #855000 -b10 G -b1000000001 C -1B +b10 K +b1000000001 G +1F 0% 1, #860000 0, #865000 -b1 G +b1 K 1, #870000 0, #875000 -b0 G +b0 K 1, #880000 0, #885000 -0B +0F 1& b10 ' -b10 3 -b10 F +b10 5 +b10 J 1, #890000 0, #895000 -b10 K +b10 O 0& -b0 ; +b0 ? 1! b10 " -b10 : +b10 > 1, #900000 0, #905000 0! -b11 J -b1000000010 I +b11 N +b1000000010 M 1, #910000 0, @@ -851,55 +863,55 @@ b1000000010 1 0, #925000 0- -b1 ; +b1 ? 1% b1000000010 ( -b1000000010 8 -b1000000010 < +b1000000010 : +b1000000010 @ 1, #930000 0, #935000 -b10 G -b1000000010 C -1B +b10 K +b1000000010 G +1F 0% 1, #940000 0, #945000 -b1 G +b1 K 1, #950000 0, #955000 -b0 G +b0 K 1, #960000 0, #965000 -0B +0F 1& b11 ' -b11 3 -b11 F +b11 5 +b11 J 1, #970000 0, #975000 -b11 K +b11 O 0& -b0 ; +b0 ? 1! b11 " -b11 : +b11 > 1, #980000 0, #985000 0! -b0 M -b1100000000 L +b0 Q +b1100000000 P 1, #990000 0, @@ -907,7 +919,7 @@ b1100000000 L 1- 10 b0 / -b0 2 +b0 4 b1100000000 + b1100000000 1 1, @@ -915,55 +927,55 @@ b1100000000 1 0, #1005000 0- -b1 ; +b1 ? 1% b0 $ -b0 9 b0 = +b0 A b1100000000 ( -b1100000000 8 -b1100000000 < +b1100000000 : +b1100000000 @ 1# 1, #1010000 0, #1015000 -b10 G -b0 D -b1100000000 C -1E -1B +b10 K +b0 H +b1100000000 G +1I +1F 0% 1, #1020000 0, #1025000 -b1 G +b1 K 1, #1030000 0, #1035000 -b0 G +b0 K 1, #1040000 0, #1045000 -0B +0F 1& 1, #1050000 0, #1055000 0& -b0 ; +b0 ? 1! 1, #1060000 0, #1065000 0! -b0 J -b1100000000 I +b0 N +b1100000000 M 1, #1070000 0, @@ -975,53 +987,53 @@ b1100000000 I 0, #1085000 0- -b1 ; +b1 ? 1% 0# 1, #1090000 0, #1095000 -b10 G -0E -1B +b10 K +0I +1F 0% 1, #1100000 0, #1105000 -b1 G +b1 K 1, #1110000 0, #1115000 -b0 G +b0 K 1, #1120000 0, #1125000 -0B +0F 1& b0 ' -b0 3 -b0 F +b0 5 +b0 J 1, #1130000 0, #1135000 -b0 K +b0 O 0& -b0 ; +b0 ? 1! b0 " -b0 : +b0 > 1, #1140000 0, #1145000 0! -b1111111111111111 M -b1100000001 L +b1111111111111111 Q +b1100000001 P 1, #1150000 0, @@ -1029,7 +1041,7 @@ b1100000001 L 1- 10 b1111111111111111 / -b1111111111111111 2 +b1111111111111111 4 b1100000001 + b1100000001 1 1, @@ -1037,55 +1049,55 @@ b1100000001 1 0, #1165000 0- -b1 ; +b1 ? 1% b1111111111111111 $ -b1111111111111111 9 b1111111111111111 = +b1111111111111111 A b1100000001 ( -b1100000001 8 -b1100000001 < +b1100000001 : +b1100000001 @ 1# 1, #1170000 0, #1175000 -b10 G -b1111111111111111 D -b1100000001 C -1E -1B +b10 K +b1111111111111111 H +b1100000001 G +1I +1F 0% 1, #1180000 0, #1185000 -b1 G +b1 K 1, #1190000 0, #1195000 -b0 G +b0 K 1, #1200000 0, #1205000 -0B +0F 1& 1, #1210000 0, #1215000 0& -b0 ; +b0 ? 1! 1, #1220000 0, #1225000 0! -b1111111111111111 J -b1100000001 I +b1111111111111111 N +b1100000001 M 1, #1230000 0, @@ -1097,46 +1109,46 @@ b1100000001 I 0, #1245000 0- -b1 ; +b1 ? 1% 0# 1, #1250000 0, #1255000 -b10 G -0E -1B +b10 K +0I +1F 0% 1, #1260000 0, #1265000 -b1 G +b1 K 1, #1270000 0, #1275000 -b0 G +b0 K 1, #1280000 0, #1285000 -0B +0F 1& b1111111111111111 ' -b1111111111111111 3 -b1111111111111111 F +b1111111111111111 5 +b1111111111111111 J 1, #1290000 0, #1295000 -b1111111111111111 K +b1111111111111111 O 0& -b0 ; +b0 ? 1! b1111111111111111 " -b1111111111111111 : +b1111111111111111 > 1, #1300000 0, diff --git a/sim/memory_interface_tb.v b/sim/memory_interface_tb.v index 8d767bd..0b08926 100644 --- a/sim/memory_interface_tb.v +++ b/sim/memory_interface_tb.v @@ -2,7 +2,7 @@ module memory_interface_tb; - parameter ADDR_WIDTH = 22; + parameter ADDR_WIDTH = 23; parameter DATA_WIDTH = 16; reg clk; diff --git a/sim/neuron_memory.vcd b/sim/neuron_memory.vcd index cb67cf7..118ad83 100644 --- a/sim/neuron_memory.vcd +++ b/sim/neuron_memory.vcd @@ -1,5 +1,5 @@ $date - Wed Sep 2 20:14:05 2026 + Wed Sep 2 20:58:09 2026 $end $version Icarus Verilog @@ -21,12 +21,12 @@ $var wire 1 * psram_mem_ready $end $var wire 16 + psram_mem_rdata [15:0] $end $var wire 1 , psram_lb_n $end $var wire 1 - psram_ce_n $end -$var wire 22 . psram_a [21:0] $end +$var wire 23 . psram_a [22:0] $end $var wire 1 / neuron_mem_wr $end $var wire 8 0 neuron_mem_wdata [7:0] $end $var wire 1 1 neuron_mem_req $end $var wire 8 2 neuron_mem_rdata [7:0] $end -$var wire 22 3 neuron_mem_addr [21:0] $end +$var wire 23 3 neuron_mem_addr [22:0] $end $var wire 1 4 memory_ready $end $var wire 16 5 memory_rdata [15:0] $end $var wire 1 6 memory_mem_wr $end @@ -34,38 +34,38 @@ $var wire 16 7 memory_mem_wdata [15:0] $end $var wire 1 8 memory_mem_ub_n $end $var wire 1 9 memory_mem_req $end $var wire 1 : memory_mem_lb_n $end -$var wire 22 ; memory_mem_addr [21:0] $end +$var wire 23 ; memory_mem_addr [22:0] $end $var wire 1 < master_wr $end $var wire 16 = master_wdata [15:0] $end $var wire 1 > master_ub_n $end $var wire 1 ? master_req $end $var wire 1 @ master_lb_n $end -$var wire 22 A master_addr [21:0] $end +$var wire 23 A master_addr [22:0] $end $var wire 1 B done $end $var wire 1 C busy $end $var parameter 32 D ADDR_WIDTH $end $var real 1 E CLK_PERIOD $end $var parameter 32 F DATA_WIDTH $end -$var reg 22 G bias_addr [21:0] $end +$var reg 23 G bias_addr [22:0] $end $var reg 1 H clk $end $var reg 16 I n_inputs_real [15:0] $end $var reg 1 J rst $end $var reg 1 K start $end -$var reg 22 L tb_mem_addr [21:0] $end +$var reg 23 L tb_mem_addr [22:0] $end $var reg 1 M tb_mem_lb_n $end $var reg 1 N tb_mem_req $end $var reg 1 O tb_mem_ub_n $end $var reg 16 P tb_mem_wdata [15:0] $end $var reg 1 Q tb_mem_wr $end $var reg 1 R use_neuron_master $end -$var reg 22 S w_base [21:0] $end -$var reg 22 T x_base [21:0] $end +$var reg 23 S w_base [22:0] $end +$var reg 23 T x_base [22:0] $end $var integer 32 U cycles_full_nm [31:0] $end $var integer 32 V cycles_reduced_nm [31:0] $end $var integer 32 W t_done_nm [31:0] $end $var integer 32 X t_start_nm [31:0] $end $scope module u_memory_if $end -$var wire 22 Y addr [21:0] $end +$var wire 23 Y addr [22:0] $end $var wire 1 H clk $end $var wire 1 @ lb_n $end $var wire 1 ? req $end @@ -79,7 +79,7 @@ $var parameter 32 \ ADDR_WIDTH $end $var parameter 32 ] DATA_WIDTH $end $var parameter 2 ^ STATE_IDLE $end $var parameter 2 _ STATE_WAIT $end -$var reg 22 ` mem_addr [21:0] $end +$var reg 23 ` mem_addr [22:0] $end $var reg 1 : mem_lb_n $end $var reg 1 9 mem_req $end $var reg 1 8 mem_ub_n $end @@ -91,9 +91,9 @@ $var reg 2 c state [1:0] $end $upscope $end $scope module u_neuron $end $var wire 2 d activation [1:0] $end -$var wire 22 e bias_addr [21:0] $end +$var wire 23 e bias_addr [22:0] $end $var wire 1 H clk $end -$var wire 22 f mem_addr [21:0] $end +$var wire 23 f mem_addr [22:0] $end $var wire 8 g mem_rdata [7:0] $end $var wire 1 ! mem_ready $end $var wire 1 1 mem_req $end @@ -103,8 +103,8 @@ $var wire 16 i n_inputs_real [15:0] $end $var wire 16 j n_neurons_real [15:0] $end $var wire 1 J rst $end $var wire 1 K start $end -$var wire 22 k w_base [21:0] $end -$var wire 22 l x_base [21:0] $end +$var wire 23 k w_base [22:0] $end +$var wire 23 l x_base [22:0] $end $var wire 8 m y_bus [7:0] $end $var wire 256 n x_bus [255:0] $end $var wire 256 o w_bus [255:0] $end @@ -119,7 +119,7 @@ $var wire 1 w access_mem_ub_n $end $var wire 1 x access_mem_req $end $var wire 16 y access_mem_rdata [15:0] $end $var wire 1 z access_mem_lb_n $end -$var wire 22 { access_mem_addr [21:0] $end +$var wire 23 { access_mem_addr [22:0] $end $var parameter 32 | ACC_WIDTH $end $var parameter 32 } ADDR_WIDTH $end $var parameter 32 ~ DATA_WIDTH $end @@ -133,11 +133,11 @@ $var parameter 4 '" STATE_READ_W $end $var parameter 4 (" STATE_READ_X $end $var parameter 4 )" STATE_START_N $end $var parameter 4 *" STATE_WAIT_N $end -$var reg 22 +" access_addr [21:0] $end +$var reg 23 +" access_addr [22:0] $end $var reg 1 ," access_req $end $var reg 8 -" access_wdata [7:0] $end $var reg 1 ." access_wr $end -$var reg 22 /" bias_group_addr [21:0] $end +$var reg 23 /" bias_group_addr [22:0] $end $var reg 8 0" bias_reg [7:0] $end $var reg 1 C busy $end $var reg 1 B done $end @@ -145,7 +145,7 @@ $var reg 6 1" index [5:0] $end $var reg 1 2" neuron_index $end $var reg 1 3" neuron_start $end $var reg 4 4" state [3:0] $end -$var reg 22 5" w_group_base [21:0] $end +$var reg 23 5" w_group_base [22:0] $end $var integer 32 6" rst_i [31:0] $end $scope begin GEN_BUS[0] $end $var parameter 2 7" i $end @@ -247,7 +247,7 @@ $scope begin GEN_Y_BUS[0] $end $var parameter 2 W" j $end $upscope $end $scope module u_mem $end -$var wire 22 X" addr [21:0] $end +$var wire 23 X" addr [22:0] $end $var wire 1 H clk $end $var wire 16 Y" mem_rdata [15:0] $end $var wire 1 ! mem_ready $end @@ -258,8 +258,8 @@ $var wire 1 ." wr $end $var parameter 32 [" ADDR_WIDTH $end $var parameter 2 \" STATE_IDLE $end $var parameter 2 ]" STATE_WAIT $end -$var reg 22 ^" addr_reg [21:0] $end -$var reg 22 _" mem_addr [21:0] $end +$var reg 23 ^" addr_reg [22:0] $end +$var reg 23 _" mem_addr [22:0] $end $var reg 1 z mem_lb_n $end $var reg 1 x mem_req $end $var reg 1 w mem_ub_n $end @@ -484,7 +484,7 @@ $var wire 1 ( ub_n $end $var wire 1 ) oe_n $end $var wire 1 , lb_n $end $var wire 1 - ce_n $end -$var wire 22 ($ a [21:0] $end +$var wire 23 ($ a [22:0] $end $var parameter 32 )$ ADDR_WIDTH $end $var parameter 32 *$ DATA_WIDTH $end $var parameter 32 +$ DEPTH $end @@ -503,7 +503,7 @@ $var real 1 7$ TWC_NS $end $var real 1 8$ TWPH_NS $end $var real 1 9$ TWP_NS $end $var real 1 :$ TWR_NS $end -$var reg 22 ;$ active_addr [21:0] $end +$var reg 23 ;$ active_addr [22:0] $end $var reg 16 <$ active_wdata [15:0] $end $var reg 1 =$ dq_oe $end $var reg 16 >$ dq_out [15:0] $end @@ -531,7 +531,7 @@ $upscope $end $upscope $end $scope module u_psram_ctrl $end $var wire 1 H clk $end -$var wire 22 P$ mem_addr [21:0] $end +$var wire 23 P$ mem_addr [22:0] $end $var wire 1 : mem_lb_n $end $var wire 1 9 mem_req $end $var wire 1 8 mem_ub_n $end @@ -550,14 +550,14 @@ $var parameter 3 Z$ STATE_INIT $end $var parameter 3 [$ STATE_READ $end $var parameter 3 \$ STATE_WRITE $end $var parameter 3 ]$ STATE_WRITE_WAIT $end -$var reg 22 ^$ address_reg [21:0] $end +$var reg 23 ^$ address_reg [22:0] $end $var reg 14 _$ counter [13:0] $end $var reg 1 `$ dq_oe $end $var reg 16 a$ dq_out [15:0] $end $var reg 1 b$ lb_reg $end $var reg 16 c$ mem_rdata [15:0] $end $var reg 1 * mem_ready $end -$var reg 22 d$ psram_a [21:0] $end +$var reg 23 d$ psram_a [22:0] $end $var reg 1 - psram_ce_n $end $var reg 1 , psram_lb_n $end $var reg 1 ) psram_oe_n $end @@ -570,27 +570,27 @@ $var reg 16 g$ wdata_reg [15:0] $end $var reg 1 h$ wr_reg $end $upscope $end $scope task preload_bias $end -$var reg 22 i$ addr_i [21:0] $end +$var reg 23 i$ addr_i [22:0] $end $var reg 8 j$ value [7:0] $end $upscope $end $scope task preload_vector $end -$var reg 22 k$ base [21:0] $end +$var reg 23 k$ base [22:0] $end $var reg 8 l$ value [7:0] $end $var integer 32 m$ k [31:0] $end $upscope $end $scope task preload_vector_n $end -$var reg 22 n$ base [21:0] $end +$var reg 23 n$ base [22:0] $end $var reg 8 o$ value [7:0] $end $var integer 32 p$ k [31:0] $end $var integer 32 q$ len [31:0] $end $upscope $end $scope task preload_weights $end -$var reg 22 r$ base [21:0] $end +$var reg 23 r$ base [22:0] $end $var reg 8 s$ value [7:0] $end $var integer 32 t$ k [31:0] $end $upscope $end $scope task preload_x_pattern $end -$var reg 22 u$ base [21:0] $end +$var reg 23 u$ base [22:0] $end $var reg 8 v$ v0 [7:0] $end $var reg 8 w$ v1 [7:0] $end $var integer 32 x$ k [31:0] $end @@ -605,7 +605,7 @@ $var reg 128 |$ test_name [127:0] $end $var integer 32 }$ elapsed_cycles [31:0] $end $upscope $end $scope task tb_write_word $end -$var reg 22 ~$ addr_i [21:0] $end +$var reg 23 ~$ addr_i [22:0] $end $var reg 16 !% data_i [15:0] $end $upscope $end $upscope $end @@ -621,7 +621,7 @@ b10111011100000 X$ b10000 W$ b1110 V$ b1010000 U$ -b10110 T$ +b10111 T$ b110 S$ r0 :$ r46 9$ @@ -640,7 +640,7 @@ r70 -$ r70 ,$ b100000000000000 +$ b10000 *$ -b10110 )$ +b10111 )$ b0 &$ b10 %$ b1 $$ @@ -705,7 +705,7 @@ b0 o" b100000 n" b1 ]" b0 \" -b10110 [" +b10111 [" b0 W" b11111 V" b11110 U" @@ -750,15 +750,15 @@ b1 #" b100000 "" b1 !" b1000 ~ -b10110 } +b10111 } b100000 | b1 _ b0 ^ b10000 ] -b10110 \ +b10111 \ b10000 F r12.5 E -b10110 D +b10111 D $end #0 $dumpvars diff --git a/sim/neuron_memory_multi.vcd b/sim/neuron_memory_multi.vcd index ba38de5..0f2f7ec 100644 --- a/sim/neuron_memory_multi.vcd +++ b/sim/neuron_memory_multi.vcd @@ -1,5 +1,5 @@ $date - Wed Sep 2 20:14:10 2026 + Wed Sep 2 20:58:13 2026 $end $version Icarus Verilog @@ -21,12 +21,12 @@ $var wire 1 * psram_mem_ready $end $var wire 16 + psram_mem_rdata [15:0] $end $var wire 1 , psram_lb_n $end $var wire 1 - psram_ce_n $end -$var wire 22 . psram_a [21:0] $end +$var wire 23 . psram_a [22:0] $end $var wire 1 / neuron_mem_wr $end $var wire 8 0 neuron_mem_wdata [7:0] $end $var wire 1 1 neuron_mem_req $end $var wire 8 2 neuron_mem_rdata [7:0] $end -$var wire 22 3 neuron_mem_addr [21:0] $end +$var wire 23 3 neuron_mem_addr [22:0] $end $var wire 1 4 memory_ready $end $var wire 16 5 memory_rdata [15:0] $end $var wire 1 6 memory_mem_wr $end @@ -34,13 +34,13 @@ $var wire 16 7 memory_mem_wdata [15:0] $end $var wire 1 8 memory_mem_ub_n $end $var wire 1 9 memory_mem_req $end $var wire 1 : memory_mem_lb_n $end -$var wire 22 ; memory_mem_addr [21:0] $end +$var wire 23 ; memory_mem_addr [22:0] $end $var wire 1 < master_wr $end $var wire 16 = master_wdata [15:0] $end $var wire 1 > master_ub_n $end $var wire 1 ? master_req $end $var wire 1 @ master_lb_n $end -$var wire 22 A master_addr [21:0] $end +$var wire 23 A master_addr [22:0] $end $var wire 1 B done $end $var wire 1 C busy $end $var parameter 32 D ADDR_WIDTH $end @@ -48,21 +48,21 @@ $var real 1 E CLK_PERIOD $end $var parameter 32 F DATA_WIDTH $end $var parameter 32 G N_INPUTS $end $var parameter 32 H N_NEURONS $end -$var reg 22 I bias_addr [21:0] $end +$var reg 23 I bias_addr [22:0] $end $var reg 1 J clk $end $var reg 1 K rst $end $var reg 1 L start $end -$var reg 22 M tb_mem_addr [21:0] $end +$var reg 23 M tb_mem_addr [22:0] $end $var reg 1 N tb_mem_lb_n $end $var reg 1 O tb_mem_req $end $var reg 1 P tb_mem_ub_n $end $var reg 16 Q tb_mem_wdata [15:0] $end $var reg 1 R tb_mem_wr $end $var reg 1 S use_neuron_master $end -$var reg 22 T w_base [21:0] $end -$var reg 22 U x_base [21:0] $end +$var reg 23 T w_base [22:0] $end +$var reg 23 U x_base [22:0] $end $scope module u_memory_if $end -$var wire 22 V addr [21:0] $end +$var wire 23 V addr [22:0] $end $var wire 1 J clk $end $var wire 1 @ lb_n $end $var wire 1 ? req $end @@ -76,7 +76,7 @@ $var parameter 32 Y ADDR_WIDTH $end $var parameter 32 Z DATA_WIDTH $end $var parameter 2 [ STATE_IDLE $end $var parameter 2 \ STATE_WAIT $end -$var reg 22 ] mem_addr [21:0] $end +$var reg 23 ] mem_addr [22:0] $end $var reg 1 : mem_lb_n $end $var reg 1 9 mem_req $end $var reg 1 8 mem_ub_n $end @@ -88,9 +88,9 @@ $var reg 2 ` state [1:0] $end $upscope $end $scope module u_neuron $end $var wire 2 a activation [1:0] $end -$var wire 22 b bias_addr [21:0] $end +$var wire 23 b bias_addr [22:0] $end $var wire 1 J clk $end -$var wire 22 c mem_addr [21:0] $end +$var wire 23 c mem_addr [22:0] $end $var wire 8 d mem_rdata [7:0] $end $var wire 1 ! mem_ready $end $var wire 1 1 mem_req $end @@ -100,8 +100,8 @@ $var wire 16 f n_inputs_real [15:0] $end $var wire 16 g n_neurons_real [15:0] $end $var wire 1 K rst $end $var wire 1 L start $end -$var wire 22 h w_base [21:0] $end -$var wire 22 i x_base [21:0] $end +$var wire 23 h w_base [22:0] $end +$var wire 23 i x_base [22:0] $end $var wire 24 j y_bus [23:0] $end $var wire 256 k x_bus [255:0] $end $var wire 256 l w_bus [255:0] $end @@ -116,7 +116,7 @@ $var wire 1 t access_mem_ub_n $end $var wire 1 u access_mem_req $end $var wire 16 v access_mem_rdata [15:0] $end $var wire 1 w access_mem_lb_n $end -$var wire 22 x access_mem_addr [21:0] $end +$var wire 23 x access_mem_addr [22:0] $end $var parameter 32 y ACC_WIDTH $end $var parameter 32 z ADDR_WIDTH $end $var parameter 32 { DATA_WIDTH $end @@ -130,11 +130,11 @@ $var parameter 4 $" STATE_READ_W $end $var parameter 4 %" STATE_READ_X $end $var parameter 4 &" STATE_START_N $end $var parameter 4 '" STATE_WAIT_N $end -$var reg 22 (" access_addr [21:0] $end +$var reg 23 (" access_addr [22:0] $end $var reg 1 )" access_req $end $var reg 8 *" access_wdata [7:0] $end $var reg 1 +" access_wr $end -$var reg 22 ," bias_group_addr [21:0] $end +$var reg 23 ," bias_group_addr [22:0] $end $var reg 8 -" bias_reg [7:0] $end $var reg 1 C busy $end $var reg 1 B done $end @@ -142,7 +142,7 @@ $var reg 6 ." index [5:0] $end $var reg 2 /" neuron_index [1:0] $end $var reg 1 0" neuron_start $end $var reg 4 1" state [3:0] $end -$var reg 22 2" w_group_base [21:0] $end +$var reg 23 2" w_group_base [22:0] $end $var integer 32 3" rst_i [31:0] $end $scope begin GEN_BUS[0] $end $var parameter 2 4" i $end @@ -250,7 +250,7 @@ $scope begin GEN_Y_BUS[2] $end $var parameter 3 V" j $end $upscope $end $scope module u_mem $end -$var wire 22 W" addr [21:0] $end +$var wire 23 W" addr [22:0] $end $var wire 1 J clk $end $var wire 16 X" mem_rdata [15:0] $end $var wire 1 ! mem_ready $end @@ -261,8 +261,8 @@ $var wire 1 +" wr $end $var parameter 32 Z" ADDR_WIDTH $end $var parameter 2 [" STATE_IDLE $end $var parameter 2 \" STATE_WAIT $end -$var reg 22 ]" addr_reg [21:0] $end -$var reg 22 ^" mem_addr [21:0] $end +$var reg 23 ]" addr_reg [22:0] $end +$var reg 23 ^" mem_addr [22:0] $end $var reg 1 w mem_lb_n $end $var reg 1 u mem_req $end $var reg 1 t mem_ub_n $end @@ -487,7 +487,7 @@ $var wire 1 ( ub_n $end $var wire 1 ) oe_n $end $var wire 1 , lb_n $end $var wire 1 - ce_n $end -$var wire 22 '$ a [21:0] $end +$var wire 23 '$ a [22:0] $end $var parameter 32 ($ ADDR_WIDTH $end $var parameter 32 )$ DATA_WIDTH $end $var parameter 32 *$ DEPTH $end @@ -506,7 +506,7 @@ $var real 1 6$ TWC_NS $end $var real 1 7$ TWPH_NS $end $var real 1 8$ TWP_NS $end $var real 1 9$ TWR_NS $end -$var reg 22 :$ active_addr [21:0] $end +$var reg 23 :$ active_addr [22:0] $end $var reg 16 ;$ active_wdata [15:0] $end $var reg 1 <$ dq_oe $end $var reg 16 =$ dq_out [15:0] $end @@ -534,7 +534,7 @@ $upscope $end $upscope $end $scope module u_psram_ctrl $end $var wire 1 J clk $end -$var wire 22 O$ mem_addr [21:0] $end +$var wire 23 O$ mem_addr [22:0] $end $var wire 1 : mem_lb_n $end $var wire 1 9 mem_req $end $var wire 1 8 mem_ub_n $end @@ -553,14 +553,14 @@ $var parameter 3 Y$ STATE_INIT $end $var parameter 3 Z$ STATE_READ $end $var parameter 3 [$ STATE_WRITE $end $var parameter 3 \$ STATE_WRITE_WAIT $end -$var reg 22 ]$ address_reg [21:0] $end +$var reg 23 ]$ address_reg [22:0] $end $var reg 14 ^$ counter [13:0] $end $var reg 1 _$ dq_oe $end $var reg 16 `$ dq_out [15:0] $end $var reg 1 a$ lb_reg $end $var reg 16 b$ mem_rdata [15:0] $end $var reg 1 * mem_ready $end -$var reg 22 c$ psram_a [21:0] $end +$var reg 23 c$ psram_a [22:0] $end $var reg 1 - psram_ce_n $end $var reg 1 , psram_lb_n $end $var reg 1 ) psram_oe_n $end @@ -576,17 +576,17 @@ $scope task preload_bias_3 $end $var reg 8 h$ b0 [7:0] $end $var reg 8 i$ b1 [7:0] $end $var reg 8 j$ b2 [7:0] $end -$var reg 22 k$ base [21:0] $end +$var reg 23 k$ base [22:0] $end $upscope $end $scope task preload_weights_n $end -$var reg 22 l$ base [21:0] $end -$var reg 22 m$ neuron_base [21:0] $end +$var reg 23 l$ base [22:0] $end +$var reg 23 m$ neuron_base [22:0] $end $var reg 8 n$ value [7:0] $end $var integer 32 o$ k [31:0] $end $var integer 32 p$ n [31:0] $end $upscope $end $scope task preload_x $end -$var reg 22 q$ base [21:0] $end +$var reg 23 q$ base [22:0] $end $var integer 32 r$ k [31:0] $end $upscope $end $scope task run_and_check $end @@ -596,7 +596,7 @@ $var reg 8 u$ expected2 [7:0] $end $var integer 32 v$ errors_local [31:0] $end $upscope $end $scope task tb_write_word $end -$var reg 22 w$ addr_i [21:0] $end +$var reg 23 w$ addr_i [22:0] $end $var reg 16 x$ data_i [15:0] $end $upscope $end $upscope $end @@ -612,7 +612,7 @@ b10111011100000 W$ b10000 V$ b1110 U$ b1010000 T$ -b10110 S$ +b10111 S$ b110 R$ r0 9$ r46 8$ @@ -631,7 +631,7 @@ r70 ,$ r70 +$ b100000000000000 *$ b10000 )$ -b10110 ($ +b10111 ($ b0 %$ b10 $$ b1 #$ @@ -696,7 +696,7 @@ b0 n" b100000 m" b1 \" b0 [" -b10110 Z" +b10111 Z" b10 V" b1 U" b0 T" @@ -743,17 +743,17 @@ b11 ~ b100000 } b10 | b1000 { -b10110 z +b10111 z b100000 y b1 \ b0 [ b10000 Z -b10110 Y +b10111 Y b11 H b100000 G b10000 F r12.5 E -b10110 D +b10111 D $end #0 $dumpvars diff --git a/sim/neuron_memory_multi_tb.v b/sim/neuron_memory_multi_tb.v index 5236720..28efb93 100644 --- a/sim/neuron_memory_multi_tb.v +++ b/sim/neuron_memory_multi_tb.v @@ -20,7 +20,7 @@ module tb; - localparam ADDR_WIDTH = 22; + localparam ADDR_WIDTH = 23; localparam DATA_WIDTH = 16; localparam CLK_PERIOD = 12.5; // 80 MHz diff --git a/sim/neuron_memory_tb.v b/sim/neuron_memory_tb.v index 04816c2..517391a 100644 --- a/sim/neuron_memory_tb.v +++ b/sim/neuron_memory_tb.v @@ -2,7 +2,7 @@ module tb; - localparam ADDR_WIDTH = 22; + localparam ADDR_WIDTH = 23; localparam DATA_WIDTH = 16; localparam CLK_PERIOD = 12.5; // 80 MHz diff --git a/sim/parameter_sweep.vcd b/sim/parameter_sweep.vcd index 717d3a7..fa9f70d 100644 --- a/sim/parameter_sweep.vcd +++ b/sim/parameter_sweep.vcd @@ -1,5 +1,5 @@ $date - Wed Sep 2 20:14:10 2026 + Wed Sep 2 20:58:26 2026 $end $version Icarus Verilog diff --git a/sim/psram_controller.vcd b/sim/psram_controller.vcd index d978160..78956d5 100644 --- a/sim/psram_controller.vcd +++ b/sim/psram_controller.vcd @@ -1,5 +1,5 @@ $date - Wed Sep 2 12:33:48 2026 + Wed Sep 2 20:58:44 2026 $end $version Icarus Verilog @@ -15,14 +15,14 @@ $var wire 1 $ psram_ub_n $end $var wire 1 % psram_oe_n $end $var wire 1 & psram_lb_n $end $var wire 1 ' psram_ce_n $end -$var wire 22 ( psram_a [21:0] $end +$var wire 23 ( psram_a [22:0] $end $var wire 1 ) mem_ready $end $var wire 16 * mem_rdata [15:0] $end $var parameter 32 + ADDR_WIDTH $end $var real 1 , CLK_PERIOD $end $var parameter 32 - DATA_WIDTH $end $var reg 1 . clk $end -$var reg 22 / mem_addr [21:0] $end +$var reg 23 / mem_addr [22:0] $end $var reg 1 0 mem_lb_n $end $var reg 1 1 mem_req $end $var reg 1 2 mem_ub_n $end @@ -34,7 +34,7 @@ $var integer 32 7 stress_addr [31:0] $end $var integer 32 8 stress_i [31:0] $end $scope module dut $end $var wire 1 . clk $end -$var wire 22 9 mem_addr [21:0] $end +$var wire 23 9 mem_addr [22:0] $end $var wire 1 0 mem_lb_n $end $var wire 1 1 mem_req $end $var wire 1 2 mem_ub_n $end @@ -53,14 +53,14 @@ $var parameter 3 C STATE_INIT $end $var parameter 3 D STATE_READ $end $var parameter 3 E STATE_WRITE $end $var parameter 3 F STATE_WRITE_WAIT $end -$var reg 22 G address_reg [21:0] $end +$var reg 23 G address_reg [22:0] $end $var reg 14 H counter [13:0] $end $var reg 1 I dq_oe $end $var reg 16 J dq_out [15:0] $end $var reg 1 K lb_reg $end $var reg 16 L mem_rdata [15:0] $end $var reg 1 ) mem_ready $end -$var reg 22 M psram_a [21:0] $end +$var reg 23 M psram_a [22:0] $end $var reg 1 ' psram_ce_n $end $var reg 1 & psram_lb_n $end $var reg 1 % psram_oe_n $end @@ -73,7 +73,7 @@ $var reg 16 P wdata_reg [15:0] $end $var reg 1 Q wr_reg $end $upscope $end $scope module memory $end -$var wire 22 R a [21:0] $end +$var wire 23 R a [22:0] $end $var wire 1 ' ce_n $end $var wire 1 . clk $end $var wire 16 S dq [15:0] $end @@ -100,7 +100,7 @@ $var real 1 b TWC_NS $end $var real 1 c TWPH_NS $end $var real 1 d TWP_NS $end $var real 1 e TWR_NS $end -$var reg 22 f active_addr [21:0] $end +$var reg 23 f active_addr [22:0] $end $var reg 16 g active_wdata [15:0] $end $var reg 1 h dq_oe $end $var reg 16 i dq_out [15:0] $end @@ -118,20 +118,20 @@ $var real 1 t oe_low_time $end $var real 1 u powerup_time $end $var real 1 v we_high_time $end $var real 1 w we_low_time $end -$scope begin $unm_blk_23 $end +$scope begin $unm_blk_41 $end $var real 1 x access_time $end $upscope $end -$scope begin $unm_blk_35 $end +$scope begin $unm_blk_53 $end $var real 1 y data_setup $end $var real 1 z write_width $end $upscope $end $upscope $end $scope task read_word $end -$var reg 22 { addr [21:0] $end +$var reg 23 { addr [22:0] $end $var reg 16 | expected [15:0] $end $upscope $end $scope task write_word $end -$var reg 22 } addr [21:0] $end +$var reg 23 } addr [22:0] $end $var reg 16 ~ data [15:0] $end $var reg 1 !" lb $end $var reg 1 "" ub $end @@ -157,7 +157,7 @@ r70 X r70 W b100000000000000 V b10000 U -b10110 T +b10111 T b100 F b11 E b10 D @@ -167,11 +167,11 @@ b10111011100000 A b10000 @ b1110 ? b1010000 > -b10110 = +b10111 = b110 < b10000 - r12.5 , -b10110 + +b10111 + $end #0 $dumpvars diff --git a/sim/psram_controller_tb.v b/sim/psram_controller_tb.v index b14b493..3610579 100644 --- a/sim/psram_controller_tb.v +++ b/sim/psram_controller_tb.v @@ -2,7 +2,7 @@ module tb; - localparam ADDR_WIDTH = 22; + localparam ADDR_WIDTH = 23; localparam DATA_WIDTH = 16; localparam CLK_PERIOD = 12.5; // 80 MHz diff --git a/sim/psram_model.v b/sim/psram_model.v index ec67711..20acc59 100644 --- a/sim/psram_model.v +++ b/sim/psram_model.v @@ -1,7 +1,7 @@ `timescale 1ns/1ps module psram_model #( - parameter ADDR_WIDTH = 22, + parameter ADDR_WIDTH = 23, parameter DATA_WIDTH = 16, parameter DEPTH = 16384 )( diff --git a/sim/spi_engine.vcd b/sim/spi_engine.vcd index a2942bc..490be84 100644 --- a/sim/spi_engine.vcd +++ b/sim/spi_engine.vcd @@ -1,5 +1,5 @@ $date - Wed Sep 2 20:13:54 2026 + Wed Sep 2 20:58:00 2026 $end $version Icarus Verilog @@ -8,11 +8,11 @@ $timescale 1ps $end $scope module tb $end -$var wire 22 ! x_base [21:0] $end -$var wire 22 " w_base [21:0] $end +$var wire 23 ! x_base [22:0] $end +$var wire 23 " w_base [22:0] $end $var wire 1 # tx_byte_req $end $var wire 8 $ tx_byte [7:0] $end -$var wire 22 % table_base [21:0] $end +$var wire 23 % table_base [22:0] $end $var wire 1 & rx_valid $end $var wire 8 ' rx_byte [7:0] $end $var wire 1 ( run_start $end @@ -20,7 +20,7 @@ $var wire 8 ) run_num_layers [7:0] $end $var wire 1 * ram_wr $end $var wire 8 + ram_wdata [7:0] $end $var wire 1 , ram_req $end -$var wire 22 - ram_addr [21:0] $end +$var wire 23 - ram_addr [22:0] $end $var wire 1 . nm_start $end $var wire 1 / nm_soft_rst $end $var wire 16 0 n_neurons_real [15:0] $end @@ -28,9 +28,9 @@ $var wire 16 1 n_inputs_real [15:0] $end $var wire 1 2 miso $end $var wire 1 3 cs_start $end $var wire 1 4 cs_end_w $end -$var wire 22 5 buf_b_base [21:0] $end -$var wire 22 6 buf_a_base [21:0] $end -$var wire 22 7 bias_addr [21:0] $end +$var wire 23 5 buf_b_base [22:0] $end +$var wire 23 6 buf_a_base [22:0] $end +$var wire 23 7 bias_addr [22:0] $end $var wire 2 8 activation [1:0] $end $var parameter 32 9 ADDR_WIDTH $end $var real 1 : CLK_PERIOD $end @@ -48,7 +48,7 @@ $var reg 1 E nm_busy $end $var reg 1 F nm_done $end $var reg 1 G nm_soft_rst_seen $end $var reg 1 H nm_start_seen $end -$var reg 22 I ram_addr_latched [21:0] $end +$var reg 23 I ram_addr_latched [22:0] $end $var reg 8 J ram_rdata [7:0] $end $var reg 1 K ram_ready $end $var reg 1 L ram_state $end @@ -122,11 +122,11 @@ $var parameter 4 %" ST_WRITE_ISSUE $end $var parameter 4 &" ST_WRITE_WAIT $end $var reg 2 '" activation [1:0] $end $var reg 24 (" addr_acc [23:0] $end -$var reg 22 )" bias_addr [21:0] $end -$var reg 22 *" buf_a_base [21:0] $end -$var reg 22 +" buf_b_base [21:0] $end +$var reg 23 )" bias_addr [22:0] $end +$var reg 23 *" buf_a_base [22:0] $end +$var reg 23 +" buf_b_base [22:0] $end $var reg 2 ," byte_pos [1:0] $end -$var reg 22 -" cur_addr [21:0] $end +$var reg 23 -" cur_addr [22:0] $end $var reg 8 ." cur_read_byte [7:0] $end $var reg 16 /" len_acc [15:0] $end $var reg 16 0" len_remaining [15:0] $end @@ -138,7 +138,7 @@ $var reg 1 . nm_start $end $var reg 8 4" opcode [7:0] $end $var reg 8 5" pending_wdata [7:0] $end $var reg 1 6" pending_write $end -$var reg 22 7" ram_addr [21:0] $end +$var reg 23 7" ram_addr [22:0] $end $var reg 1 , ram_req $end $var reg 8 8" ram_wdata [7:0] $end $var reg 1 * ram_wr $end @@ -149,10 +149,10 @@ $var reg 1 ( run_start $end $var reg 4 <" state [3:0] $end $var reg 1 =" status_done_sticky $end $var reg 8 >" status_snapshot [7:0] $end -$var reg 22 ?" table_base [21:0] $end +$var reg 23 ?" table_base [22:0] $end $var reg 8 @" tx_byte_comb [7:0] $end -$var reg 22 A" w_base [21:0] $end -$var reg 22 B" x_base [21:0] $end +$var reg 23 A" w_base [22:0] $end +$var reg 23 B" x_base [22:0] $end $upscope $end $scope module u_slave $end $var wire 1 B clk $end @@ -200,7 +200,7 @@ $scope task report $end $var reg 512 [" label [511:0] $end $upscope $end $scope task set_base $end -$var reg 22 \" addr [21:0] $end +$var reg 23 \" addr [22:0] $end $var reg 8 ]" sel [7:0] $end $upscope $end $scope task spi_begin $end @@ -256,7 +256,7 @@ b0 d b11 c b100000 b b1000 a -b10110 ` +b10111 ` 1A 0@ b1000 ? @@ -265,7 +265,7 @@ b100000 = b110 < b1000 ; r12.5 : -b10110 9 +b10111 9 $end #0 $dumpvars @@ -20902,7 +20902,7 @@ b101 U" 0B #41268750 xD -bx000000 b" +bx0000000 b" b111 d" b0 U" 1B @@ -21016,22 +21016,27 @@ b101 U" #41487500 0B #41493750 +0D b110 d" b0 U" 1B #41500000 0B #41506250 +bx0 O" b1 U" 1B #41512500 0B #41518750 +bx00 O" b10 U" 1B #41525000 0B #41531250 +0J" +b0 O" b11 U" 1B #41537500 @@ -21075,7 +21080,7 @@ b11 U" #41618750 0G" b10 L" -b0xx Q" +b0x0 Q" 1R" b100 U" 1B @@ -21125,27 +21130,22 @@ b101 U" #41712500 0B #41718750 -0D b101 d" b0 U" 1B #41725000 0B #41731250 -bx0 O" b1 U" 1B #41737500 0B #41743750 -bx00 O" b10 U" 1B #41750000 0B #41756250 -0J" -b0 O" b11 U" 1B #41762500 @@ -21189,7 +21189,7 @@ b11 U" #41843750 0G" b11 L" -b0xx0 Q" +b0x00 Q" 1R" b100 U" 1B @@ -21298,7 +21298,7 @@ b11 U" #42068750 0G" b100 L" -b0xx00 Q" +b0x000 Q" 1R" b100 U" 1B @@ -21407,7 +21407,7 @@ b11 U" #42293750 0G" b101 L" -b0xx000 Q" +b0x0000 Q" 1R" b100 U" 1B @@ -21516,7 +21516,7 @@ b11 U" #42518750 0G" b110 L" -b0xx0000 Q" +b0x00000 Q" 1R" b100 U" 1B @@ -21625,7 +21625,7 @@ b11 U" #42743750 0G" b111 L" -b0xx00000 Q" +b0x000000 Q" 1R" b100 U" 1B @@ -21734,11 +21734,11 @@ b11 U" #42968750 0G" 1& -bx000000 ' -bx000000 ^ -bx000000 P" +bx0000000 ' +bx0000000 ^ +bx0000000 P" b0 L" -bx000000 Q" +bx0000000 Q" 1R" b100 U" 1B @@ -21747,7 +21747,7 @@ b100 U" #42981250 0& b1 ," -b0xx000000 (" +b0x0000000 (" b101 U" 1B #42987500 @@ -21853,7 +21853,7 @@ b11 U" #43193750 0G" b1 L" -bx0000000 Q" +b0 Q" 1R" b100 U" 1B @@ -21962,7 +21962,6 @@ b11 U" #43418750 0G" b10 L" -b0 Q" 1R" b100 U" 1B @@ -22623,7 +22622,7 @@ b100 U" #44781250 0& b10 ," -b0xx00000000000000 (" +b0x000000000000000 (" b101 U" 1B #44787500 @@ -23506,7 +23505,7 @@ b1011 <" b1 ! b1 B" b0 ," -bx0000000000000000000001 (" +bx00000000000000000000001 (" b101 U" 1B #46587500 @@ -25604,7 +25603,7 @@ b101 U" 0B #50868750 xD -bx000000 b" +bx0000000 b" b111 d" b0 U" 1B @@ -25718,22 +25717,27 @@ b101 U" #51087500 0B #51093750 +0D b110 d" b0 U" 1B #51100000 0B #51106250 +bx0 O" b1 U" 1B #51112500 0B #51118750 +bx00 O" b10 U" 1B #51125000 0B #51131250 +0J" +b0 O" b11 U" 1B #51137500 @@ -25777,7 +25781,7 @@ b11 U" #51218750 0G" b10 L" -b1xx Q" +b1x0 Q" 1R" b100 U" 1B @@ -25827,27 +25831,22 @@ b101 U" #51312500 0B #51318750 -0D b101 d" b0 U" 1B #51325000 0B #51331250 -bx0 O" b1 U" 1B #51337500 0B #51343750 -bx00 O" b10 U" 1B #51350000 0B #51356250 -0J" -b0 O" b11 U" 1B #51362500 @@ -25891,7 +25890,7 @@ b11 U" #51443750 0G" b11 L" -b1xx0 Q" +b1x00 Q" 1R" b100 U" 1B @@ -26000,7 +25999,7 @@ b11 U" #51668750 0G" b100 L" -b1xx00 Q" +b1x000 Q" 1R" b100 U" 1B @@ -26109,7 +26108,7 @@ b11 U" #51893750 0G" b101 L" -b1xx000 Q" +b1x0000 Q" 1R" b100 U" 1B @@ -26218,7 +26217,7 @@ b11 U" #52118750 0G" b110 L" -b1xx0000 Q" +b1x00000 Q" 1R" b100 U" 1B @@ -26327,7 +26326,7 @@ b11 U" #52343750 0G" b111 L" -b1xx00000 Q" +b1x000000 Q" 1R" b100 U" 1B @@ -26436,11 +26435,11 @@ b11 U" #52568750 0G" 1& -bx000000 ' -bx000000 ^ -bx000000 P" +bx0000000 ' +bx0000000 ^ +bx0000000 P" b0 L" -bx000000 Q" +bx0000000 Q" 1R" b100 U" 1B @@ -26449,7 +26448,7 @@ b100 U" #52581250 0& b1 ," -b0xx000000 (" +b0x0000000 (" b101 U" 1B #52587500 @@ -26555,7 +26554,7 @@ b11 U" #52793750 0G" b1 L" -bx0000000 Q" +b0 Q" 1R" b100 U" 1B @@ -26664,7 +26663,6 @@ b11 U" #53018750 0G" b10 L" -b0 Q" 1R" b100 U" 1B @@ -27331,7 +27329,7 @@ b100 U" #54381250 0& b10 ," -b0xx00000000000001 (" +b0x000000000000001 (" b101 U" 1B #54387500 @@ -28222,7 +28220,7 @@ b1011 <" b100000001 " b100000001 A" b0 ," -bx0000000000000100000001 (" +bx00000000000000100000001 (" b101 U" 1B #56187500 @@ -30326,7 +30324,7 @@ b101 U" 0B #60468750 xD -bx000000 b" +bx0000000 b" b111 d" b0 U" 1B @@ -30440,22 +30438,27 @@ b101 U" #60687500 0B #60693750 +0D b110 d" b0 U" 1B #60700000 0B #60706250 +bx0 O" b1 U" 1B #60712500 0B #60718750 +bx00 O" b10 U" 1B #60725000 0B #60731250 +0J" +b0 O" b11 U" 1B #60737500 @@ -30499,7 +30502,7 @@ b11 U" #60818750 0G" b10 L" -b10xx Q" +b10x0 Q" 1R" b100 U" 1B @@ -30549,27 +30552,22 @@ b101 U" #60912500 0B #60918750 -0D b101 d" b0 U" 1B #60925000 0B #60931250 -bx0 O" b1 U" 1B #60937500 0B #60943750 -bx00 O" b10 U" 1B #60950000 0B #60956250 -0J" -b0 O" b11 U" 1B #60962500 @@ -30613,7 +30611,7 @@ b11 U" #61043750 0G" b11 L" -b10xx0 Q" +b10x00 Q" 1R" b100 U" 1B @@ -30722,7 +30720,7 @@ b11 U" #61268750 0G" b100 L" -b10xx00 Q" +b10x000 Q" 1R" b100 U" 1B @@ -30831,7 +30829,7 @@ b11 U" #61493750 0G" b101 L" -b10xx000 Q" +b10x0000 Q" 1R" b100 U" 1B @@ -30940,7 +30938,7 @@ b11 U" #61718750 0G" b110 L" -b10xx0000 Q" +b10x00000 Q" 1R" b100 U" 1B @@ -31049,7 +31047,7 @@ b11 U" #61943750 0G" b111 L" -b0xx00000 Q" +b0x000000 Q" 1R" b100 U" 1B @@ -31158,11 +31156,11 @@ b11 U" #62168750 0G" 1& -bx000000 ' -bx000000 ^ -bx000000 P" +bx0000000 ' +bx0000000 ^ +bx0000000 P" b0 L" -bx000000 Q" +bx0000000 Q" 1R" b100 U" 1B @@ -31171,7 +31169,7 @@ b100 U" #62181250 0& b1 ," -b0xx000000 (" +b0x0000000 (" b101 U" 1B #62187500 @@ -31277,7 +31275,7 @@ b11 U" #62393750 0G" b1 L" -bx0000000 Q" +b0 Q" 1R" b100 U" 1B @@ -31386,7 +31384,6 @@ b11 U" #62618750 0G" b10 L" -b0 Q" 1R" b100 U" 1B @@ -32059,7 +32056,7 @@ b100 U" #63981250 0& b10 ," -b0xx00000000000010 (" +b0x000000000000010 (" b101 U" 1B #63987500 @@ -32949,7 +32946,7 @@ b1011 <" b1000000001 7 b1000000001 )" b0 ," -bx0000000000001000000001 (" +bx00000000000001000000001 (" b101 U" 1B #65787500 @@ -49925,10 +49922,10 @@ b100 U" #100400000 0B #100406250 -b10110 $ -b10110 \ -b10110 H" -b10110 @" +b10111 $ +b10111 \ +b10111 H" +b10111 @" 0& b1010 <" b1000 :" @@ -49967,7 +49964,7 @@ b11 U" #100468750 0F" 1# -b10110 T" +b10111 T" 0R" b100 U" 1B @@ -50081,7 +50078,7 @@ b11 U" 0B #100693750 0F" -b101100 T" +b101110 T" 0R" b100 U" 1B @@ -50191,7 +50188,7 @@ b11 U" 0B #100918750 0F" -b1011000 T" +b1011100 T" 0R" b100 U" 1B @@ -50302,7 +50299,7 @@ b11 U" #101143750 0F" 12 -b10110000 T" +b10111000 T" 0R" b100 U" 1B @@ -50414,7 +50411,7 @@ b11 U" #101368750 0F" 02 -b1100000 T" +b1110000 T" 0R" b100 U" 1B @@ -50524,7 +50521,7 @@ b11 U" #101593750 0F" 12 -b11000000 T" +b11100000 T" 0R" b100 U" 1B @@ -50634,7 +50631,7 @@ b11 U" 0B #101818750 0F" -b10000000 T" +b11000000 T" 0R" b100 U" 1B @@ -50744,8 +50741,7 @@ b11 U" 0B #102043750 0F" -02 -b0 T" +b10000000 T" 0R" b100 U" 1B @@ -50788,6 +50784,7 @@ b101 U" #102137500 0B #102143750 +b10111 a" 1R b0 U" 1B @@ -50864,7 +50861,9 @@ b11 U" 0B #102268750 0F" +02 1# +b0 T" 0R" b100 U" 1B @@ -50879,10 +50878,10 @@ b101 U" #102293750 b0 a" b1000111001110100010000001000001010001000100010001010010010111110101011101001001010001000101010001001000 Y" -b10110 W" -b10110 X" -b10110 Q -b10110 `" +b10111 W" +b10111 X" +b10111 Q +b10111 `" b111 d" b0 U" 1B @@ -69539,7 +69538,7 @@ b101 U" 0B #140193750 xD -bx000000 b" +bx0000000 b" b111 d" b0 U" 1B @@ -69653,22 +69652,27 @@ b101 U" #140412500 0B #140418750 +0D b110 d" b0 U" 1B #140425000 0B #140431250 +bx0 O" b1 U" 1B #140437500 0B #140443750 +bx00 O" b10 U" 1B #140450000 0B #140456250 +0J" +b0 O" b11 U" 1B #140462500 @@ -69712,7 +69716,7 @@ b11 U" #140543750 0G" b10 L" -b0xx Q" +b0x0 Q" 1R" b100 U" 1B @@ -69762,27 +69766,22 @@ b101 U" #140637500 0B #140643750 -0D b101 d" b0 U" 1B #140650000 0B #140656250 -bx0 O" b1 U" 1B #140662500 0B #140668750 -bx00 O" b10 U" 1B #140675000 0B #140681250 -0J" -b0 O" b11 U" 1B #140687500 @@ -69826,7 +69825,7 @@ b11 U" #140768750 0G" b11 L" -b0xx0 Q" +b0x00 Q" 1R" b100 U" 1B @@ -69935,7 +69934,7 @@ b11 U" #140993750 0G" b100 L" -b0xx00 Q" +b0x000 Q" 1R" b100 U" 1B @@ -70044,7 +70043,7 @@ b11 U" #141218750 0G" b101 L" -b0xx000 Q" +b0x0000 Q" 1R" b100 U" 1B @@ -70153,7 +70152,7 @@ b11 U" #141443750 0G" b110 L" -b0xx0000 Q" +b0x00000 Q" 1R" b100 U" 1B @@ -70262,7 +70261,7 @@ b11 U" #141668750 0G" b111 L" -b0xx00000 Q" +b0x000000 Q" 1R" b100 U" 1B @@ -70371,11 +70370,11 @@ b11 U" #141893750 0G" 1& -bx000000 ' -bx000000 ^ -bx000000 P" +bx0000000 ' +bx0000000 ^ +bx0000000 P" b0 L" -bx000000 Q" +bx0000000 Q" 1R" b100 U" 1B @@ -70384,7 +70383,7 @@ b100 U" #141906250 0& b1 ," -b0xx000000 (" +b0x0000000 (" b101 U" 1B #141912500 @@ -70490,7 +70489,7 @@ b11 U" #142118750 0G" b1 L" -bx0000000 Q" +b0 Q" 1R" b100 U" 1B @@ -70599,7 +70598,6 @@ b11 U" #142343750 0G" b10 L" -b0 Q" 1R" b100 U" 1B @@ -71260,7 +71258,7 @@ b100 U" #143706250 0& b10 ," -b0xx00000000000000 (" +b0x000000000000000 (" b101 U" 1B #143712500 @@ -72155,7 +72153,7 @@ b1011 <" b101 ! b101 B" b0 ," -bx0000000000000000000101 (" +bx00000000000000000000101 (" b101 U" 1B #145512500 @@ -74253,7 +74251,7 @@ b101 U" 0B #149793750 xD -bx000000 b" +bx0000000 b" b111 d" b0 U" 1B @@ -74367,22 +74365,27 @@ b101 U" #150012500 0B #150018750 +0D b110 d" b0 U" 1B #150025000 0B #150031250 +bx0 O" b1 U" 1B #150037500 0B #150043750 +bx00 O" b10 U" 1B #150050000 0B #150056250 +0J" +b0 O" b11 U" 1B #150062500 @@ -74426,7 +74429,7 @@ b11 U" #150143750 0G" b10 L" -b1xx Q" +b1x0 Q" 1R" b100 U" 1B @@ -74476,27 +74479,22 @@ b101 U" #150237500 0B #150243750 -0D b101 d" b0 U" 1B #150250000 0B #150256250 -bx0 O" b1 U" 1B #150262500 0B #150268750 -bx00 O" b10 U" 1B #150275000 0B #150281250 -0J" -b0 O" b11 U" 1B #150287500 @@ -74540,7 +74538,7 @@ b11 U" #150368750 0G" b11 L" -b1xx0 Q" +b1x00 Q" 1R" b100 U" 1B @@ -74649,7 +74647,7 @@ b11 U" #150593750 0G" b100 L" -b1xx00 Q" +b1x000 Q" 1R" b100 U" 1B @@ -74758,7 +74756,7 @@ b11 U" #150818750 0G" b101 L" -b1xx000 Q" +b1x0000 Q" 1R" b100 U" 1B @@ -74867,7 +74865,7 @@ b11 U" #151043750 0G" b110 L" -b1xx0000 Q" +b1x00000 Q" 1R" b100 U" 1B @@ -74976,7 +74974,7 @@ b11 U" #151268750 0G" b111 L" -b1xx00000 Q" +b1x000000 Q" 1R" b100 U" 1B @@ -75085,11 +75083,11 @@ b11 U" #151493750 0G" 1& -bx000000 ' -bx000000 ^ -bx000000 P" +bx0000000 ' +bx0000000 ^ +bx0000000 P" b0 L" -bx000000 Q" +bx0000000 Q" 1R" b100 U" 1B @@ -75098,7 +75096,7 @@ b100 U" #151506250 0& b1 ," -b0xx000000 (" +b0x0000000 (" b101 U" 1B #151512500 @@ -75204,7 +75202,7 @@ b11 U" #151718750 0G" b1 L" -bx0000000 Q" +b0 Q" 1R" b100 U" 1B @@ -75313,7 +75311,6 @@ b11 U" #151943750 0G" b10 L" -b0 Q" 1R" b100 U" 1B @@ -75974,7 +75971,7 @@ b100 U" #153306250 0& b10 ," -b0xx00000000000000 (" +b0x000000000000000 (" b101 U" 1B #153312500 @@ -76864,7 +76861,7 @@ b1011 <" b110 " b110 A" b0 ," -bx0000000000000000000110 (" +bx00000000000000000000110 (" b101 U" 1B #155112500 @@ -78959,7 +78956,7 @@ b101 U" 0B #159393750 xD -bx000000 b" +bx0000000 b" b111 d" b0 U" 1B @@ -79073,22 +79070,27 @@ b101 U" #159612500 0B #159618750 +0D b110 d" b0 U" 1B #159625000 0B #159631250 +bx0 O" b1 U" 1B #159637500 0B #159643750 +bx00 O" b10 U" 1B #159650000 0B #159656250 +0J" +b0 O" b11 U" 1B #159662500 @@ -79132,7 +79134,7 @@ b11 U" #159743750 0G" b10 L" -b11xx Q" +b11x0 Q" 1R" b100 U" 1B @@ -79182,27 +79184,22 @@ b101 U" #159837500 0B #159843750 -0D b101 d" b0 U" 1B #159850000 0B #159856250 -bx0 O" b1 U" 1B #159862500 0B #159868750 -bx00 O" b10 U" 1B #159875000 0B #159881250 -0J" -b0 O" b11 U" 1B #159887500 @@ -79246,7 +79243,7 @@ b11 U" #159968750 0G" b11 L" -b11xx0 Q" +b11x00 Q" 1R" b100 U" 1B @@ -79355,7 +79352,7 @@ b11 U" #160193750 0G" b100 L" -b11xx00 Q" +b11x000 Q" 1R" b100 U" 1B @@ -79464,7 +79461,7 @@ b11 U" #160418750 0G" b101 L" -b11xx000 Q" +b11x0000 Q" 1R" b100 U" 1B @@ -79573,7 +79570,7 @@ b11 U" #160643750 0G" b110 L" -b11xx0000 Q" +b11x00000 Q" 1R" b100 U" 1B @@ -79682,7 +79679,7 @@ b11 U" #160868750 0G" b111 L" -b1xx00000 Q" +b1x000000 Q" 1R" b100 U" 1B @@ -79791,11 +79788,11 @@ b11 U" #161093750 0G" 1& -bx000000 ' -bx000000 ^ -bx000000 P" +bx0000000 ' +bx0000000 ^ +bx0000000 P" b0 L" -bx000000 Q" +bx0000000 Q" 1R" b100 U" 1B @@ -79804,7 +79801,7 @@ b100 U" #161106250 0& b1 ," -b0xx000000 (" +b0x0000000 (" b101 U" 1B #161112500 @@ -79910,7 +79907,7 @@ b11 U" #161318750 0G" b1 L" -bx0000000 Q" +b0 Q" 1R" b100 U" 1B @@ -80019,7 +80016,6 @@ b11 U" #161543750 0G" b10 L" -b0 Q" 1R" b100 U" 1B @@ -80687,7 +80683,7 @@ b100 U" #162906250 0& b10 ," -b0xx00000000000011 (" +b0x000000000000011 (" b101 U" 1B #162912500 @@ -81582,7 +81578,7 @@ b1011 <" b1100000001 % b1100000001 ?" b0 ," -bx0000000000001100000001 (" +bx00000000000001100000001 (" b101 U" 1B #164712500 @@ -83687,7 +83683,7 @@ b101 U" 0B #168993750 xD -bx000000 b" +bx0000000 b" b111 d" b0 U" 1B @@ -83801,22 +83797,27 @@ b101 U" #169212500 0B #169218750 +0D b110 d" b0 U" 1B #169225000 0B #169231250 +bx0 O" b1 U" 1B #169237500 0B #169243750 +bx00 O" b10 U" 1B #169250000 0B #169256250 +0J" +b0 O" b11 U" 1B #169262500 @@ -83860,7 +83861,7 @@ b11 U" #169343750 0G" b10 L" -b100xx Q" +b100x0 Q" 1R" b100 U" 1B @@ -83910,27 +83911,22 @@ b101 U" #169437500 0B #169443750 -0D b101 d" b0 U" 1B #169450000 0B #169456250 -bx0 O" b1 U" 1B #169462500 0B #169468750 -bx00 O" b10 U" 1B #169475000 0B #169481250 -0J" -b0 O" b11 U" 1B #169487500 @@ -83974,7 +83970,7 @@ b11 U" #169568750 0G" b11 L" -b100xx0 Q" +b100x00 Q" 1R" b100 U" 1B @@ -84083,7 +84079,7 @@ b11 U" #169793750 0G" b100 L" -b100xx00 Q" +b100x000 Q" 1R" b100 U" 1B @@ -84192,7 +84188,7 @@ b11 U" #170018750 0G" b101 L" -b100xx000 Q" +b100x0000 Q" 1R" b100 U" 1B @@ -84301,7 +84297,7 @@ b11 U" #170243750 0G" b110 L" -b0xx0000 Q" +b0x00000 Q" 1R" b100 U" 1B @@ -84410,7 +84406,7 @@ b11 U" #170468750 0G" b111 L" -b0xx00000 Q" +b0x000000 Q" 1R" b100 U" 1B @@ -84519,11 +84515,11 @@ b11 U" #170693750 0G" 1& -bx000000 ' -bx000000 ^ -bx000000 P" +bx0000000 ' +bx0000000 ^ +bx0000000 P" b0 L" -bx000000 Q" +bx0000000 Q" 1R" b100 U" 1B @@ -84532,7 +84528,7 @@ b100 U" #170706250 0& b1 ," -b0xx000000 (" +b0x0000000 (" b101 U" 1B #170712500 @@ -84638,7 +84634,7 @@ b11 U" #170918750 0G" b1 L" -bx0000000 Q" +b0 Q" 1R" b100 U" 1B @@ -84747,7 +84743,6 @@ b11 U" #171143750 0G" b10 L" -b0 Q" 1R" b100 U" 1B @@ -85421,7 +85416,7 @@ b100 U" #172506250 0& b10 ," -b0xx00000000000100 (" +b0x000000000000100 (" b101 U" 1B #172512500 @@ -86310,7 +86305,7 @@ b1011 <" b10000000001 6 b10000000001 *" b0 ," -bx0000000000010000000001 (" +bx00000000000010000000001 (" b101 U" 1B #174312500 @@ -88420,7 +88415,7 @@ b101 U" 0B #178593750 xD -bx000000 b" +bx0000000 b" b111 d" b0 U" 1B @@ -88534,22 +88529,27 @@ b101 U" #178812500 0B #178818750 +0D b110 d" b0 U" 1B #178825000 0B #178831250 +bx0 O" b1 U" 1B #178837500 0B #178843750 +bx00 O" b10 U" 1B #178850000 0B #178856250 +0J" +b0 O" b11 U" 1B #178862500 @@ -88593,7 +88593,7 @@ b11 U" #178943750 0G" b10 L" -b101xx Q" +b101x0 Q" 1R" b100 U" 1B @@ -88643,27 +88643,22 @@ b101 U" #179037500 0B #179043750 -0D b101 d" b0 U" 1B #179050000 0B #179056250 -bx0 O" b1 U" 1B #179062500 0B #179068750 -bx00 O" b10 U" 1B #179075000 0B #179081250 -0J" -b0 O" b11 U" 1B #179087500 @@ -88707,7 +88702,7 @@ b11 U" #179168750 0G" b11 L" -b101xx0 Q" +b101x00 Q" 1R" b100 U" 1B @@ -88816,7 +88811,7 @@ b11 U" #179393750 0G" b100 L" -b101xx00 Q" +b101x000 Q" 1R" b100 U" 1B @@ -88925,7 +88920,7 @@ b11 U" #179618750 0G" b101 L" -b101xx000 Q" +b101x0000 Q" 1R" b100 U" 1B @@ -89034,7 +89029,7 @@ b11 U" #179843750 0G" b110 L" -b1xx0000 Q" +b1x00000 Q" 1R" b100 U" 1B @@ -89143,7 +89138,7 @@ b11 U" #180068750 0G" b111 L" -b1xx00000 Q" +b1x000000 Q" 1R" b100 U" 1B @@ -89252,11 +89247,11 @@ b11 U" #180293750 0G" 1& -bx000000 ' -bx000000 ^ -bx000000 P" +bx0000000 ' +bx0000000 ^ +bx0000000 P" b0 L" -bx000000 Q" +bx0000000 Q" 1R" b100 U" 1B @@ -89265,7 +89260,7 @@ b100 U" #180306250 0& b1 ," -b0xx000000 (" +b0x0000000 (" b101 U" 1B #180312500 @@ -89371,7 +89366,7 @@ b11 U" #180518750 0G" b1 L" -bx0000000 Q" +b0 Q" 1R" b100 U" 1B @@ -89480,7 +89475,6 @@ b11 U" #180743750 0G" b10 L" -b0 Q" 1R" b100 U" 1B @@ -90159,7 +90153,7 @@ b100 U" #182106250 0& b10 ," -b0xx00000000000101 (" +b0x000000000000101 (" b101 U" 1B #182112500 @@ -91054,7 +91048,7 @@ b1011 <" b10100000001 5 b10100000001 +" b0 ," -bx0000000000010100000001 (" +bx00000000000010100000001 (" b101 U" 1B #183912500 @@ -103644,7 +103638,7 @@ b101 U" 0B #209443750 xD -bx000000 b" +bx0000000 b" b111 d" b0 U" 1B @@ -103758,22 +103752,27 @@ b101 U" #209662500 0B #209668750 +0D b110 d" b0 U" 1B #209675000 0B #209681250 +bx0 O" b1 U" 1B #209687500 0B #209693750 +bx00 O" b10 U" 1B #209700000 0B #209706250 +0J" +b0 O" b11 U" 1B #209712500 @@ -103817,7 +103816,7 @@ b11 U" #209793750 0G" b10 L" -b110xx Q" +b110x0 Q" 1R" b100 U" 1B @@ -103867,27 +103866,22 @@ b101 U" #209887500 0B #209893750 -0D b101 d" b0 U" 1B #209900000 0B #209906250 -bx0 O" b1 U" 1B #209912500 0B #209918750 -bx00 O" b10 U" 1B #209925000 0B #209931250 -0J" -b0 O" b11 U" 1B #209937500 @@ -103931,7 +103925,7 @@ b11 U" #210018750 0G" b11 L" -b110xx0 Q" +b110x00 Q" 1R" b100 U" 1B @@ -104040,7 +104034,7 @@ b11 U" #210243750 0G" b100 L" -b110xx00 Q" +b110x000 Q" 1R" b100 U" 1B @@ -104149,7 +104143,7 @@ b11 U" #210468750 0G" b101 L" -b110xx000 Q" +b110x0000 Q" 1R" b100 U" 1B @@ -104258,7 +104252,7 @@ b11 U" #210693750 0G" b110 L" -b10xx0000 Q" +b10x00000 Q" 1R" b100 U" 1B @@ -104367,7 +104361,7 @@ b11 U" #210918750 0G" b111 L" -b0xx00000 Q" +b0x000000 Q" 1R" b100 U" 1B @@ -104476,11 +104470,11 @@ b11 U" #211143750 0G" 1& -bx000000 ' -bx000000 ^ -bx000000 P" +bx0000000 ' +bx0000000 ^ +bx0000000 P" b0 L" -bx000000 Q" +bx0000000 Q" 1R" b100 U" 1B @@ -104489,7 +104483,7 @@ b100 U" #211156250 0& b1 ," -b0xx000000 (" +b0x0000000 (" b101 U" 1B #211162500 @@ -104595,7 +104589,7 @@ b11 U" #211368750 0G" b1 L" -bx0000000 Q" +b0 Q" 1R" b100 U" 1B @@ -104704,7 +104698,6 @@ b11 U" #211593750 0G" b10 L" -b0 Q" 1R" b100 U" 1B @@ -105365,7 +105358,7 @@ b100 U" #212956250 0& b10 ," -b0xx00000000000000 (" +b0x000000000000000 (" b101 U" 1B #212962500 @@ -106238,7 +106231,7 @@ b1011 <" b0 8 b0 '" b0 ," -bx0000000000000000000000 (" +bx00000000000000000000000 (" b101 U" 1B #214762500 @@ -108345,7 +108338,7 @@ b101 U" 0B #219068750 xD -bx000000 b" +bx0000000 b" b111 d" b0 U" 1B @@ -108459,22 +108452,27 @@ b101 U" #219287500 0B #219293750 +0D b110 d" b0 U" 1B #219300000 0B #219306250 +bx0 O" b1 U" 1B #219312500 0B #219318750 +bx00 O" b10 U" 1B #219325000 0B #219331250 +0J" +b0 O" b11 U" 1B #219337500 @@ -108518,7 +108516,7 @@ b11 U" #219418750 0G" b10 L" -b110xx Q" +b110x0 Q" 1R" b100 U" 1B @@ -108568,27 +108566,22 @@ b101 U" #219512500 0B #219518750 -0D b101 d" b0 U" 1B #219525000 0B #219531250 -bx0 O" b1 U" 1B #219537500 0B #219543750 -bx00 O" b10 U" 1B #219550000 0B #219556250 -0J" -b0 O" b11 U" 1B #219562500 @@ -108632,7 +108625,7 @@ b11 U" #219643750 0G" b11 L" -b110xx0 Q" +b110x00 Q" 1R" b100 U" 1B @@ -108741,7 +108734,7 @@ b11 U" #219868750 0G" b100 L" -b110xx00 Q" +b110x000 Q" 1R" b100 U" 1B @@ -108850,7 +108843,7 @@ b11 U" #220093750 0G" b101 L" -b110xx000 Q" +b110x0000 Q" 1R" b100 U" 1B @@ -108959,7 +108952,7 @@ b11 U" #220318750 0G" b110 L" -b10xx0000 Q" +b10x00000 Q" 1R" b100 U" 1B @@ -109068,7 +109061,7 @@ b11 U" #220543750 0G" b111 L" -b0xx00000 Q" +b0x000000 Q" 1R" b100 U" 1B @@ -109177,11 +109170,11 @@ b11 U" #220768750 0G" 1& -bx000000 ' -bx000000 ^ -bx000000 P" +bx0000000 ' +bx0000000 ^ +bx0000000 P" b0 L" -bx000000 Q" +bx0000000 Q" 1R" b100 U" 1B @@ -109190,7 +109183,7 @@ b100 U" #220781250 0& b1 ," -b0xx000000 (" +b0x0000000 (" b101 U" 1B #220787500 @@ -109296,7 +109289,7 @@ b11 U" #220993750 0G" b1 L" -bx0000000 Q" +b0 Q" 1R" b100 U" 1B @@ -109405,7 +109398,6 @@ b11 U" #221218750 0G" b10 L" -b0 Q" 1R" b100 U" 1B @@ -110066,7 +110058,7 @@ b100 U" #222581250 0& b10 ," -b0xx00000000000000 (" +b0x000000000000000 (" b101 U" 1B #222587500 @@ -110956,7 +110948,7 @@ b1011 <" b11 8 b11 '" b0 ," -bx0000000000000011111111 (" +bx00000000000000011111111 (" b101 U" 1B #224387500 @@ -113071,7 +113063,7 @@ b101 U" 0B #228693750 xD -bx000000 b" +bx0000000 b" b111 d" b0 U" 1B @@ -113185,22 +113177,27 @@ b101 U" #228912500 0B #228918750 +0D b110 d" b0 U" 1B #228925000 0B #228931250 +bx0 O" b1 U" 1B #228937500 0B #228943750 +bx00 O" b10 U" 1B #228950000 0B #228956250 +0J" +b0 O" b11 U" 1B #228962500 @@ -113244,7 +113241,7 @@ b11 U" #229043750 0G" b10 L" -b110xx Q" +b110x0 Q" 1R" b100 U" 1B @@ -113294,27 +113291,22 @@ b101 U" #229137500 0B #229143750 -0D b101 d" b0 U" 1B #229150000 0B #229156250 -bx0 O" b1 U" 1B #229162500 0B #229168750 -bx00 O" b10 U" 1B #229175000 0B #229181250 -0J" -b0 O" b11 U" 1B #229187500 @@ -113358,7 +113350,7 @@ b11 U" #229268750 0G" b11 L" -b110xx0 Q" +b110x00 Q" 1R" b100 U" 1B @@ -113467,7 +113459,7 @@ b11 U" #229493750 0G" b100 L" -b110xx00 Q" +b110x000 Q" 1R" b100 U" 1B @@ -113576,7 +113568,7 @@ b11 U" #229718750 0G" b101 L" -b110xx000 Q" +b110x0000 Q" 1R" b100 U" 1B @@ -113685,7 +113677,7 @@ b11 U" #229943750 0G" b110 L" -b10xx0000 Q" +b10x00000 Q" 1R" b100 U" 1B @@ -113794,7 +113786,7 @@ b11 U" #230168750 0G" b111 L" -b0xx00000 Q" +b0x000000 Q" 1R" b100 U" 1B @@ -113903,11 +113895,11 @@ b11 U" #230393750 0G" 1& -bx000000 ' -bx000000 ^ -bx000000 P" +bx0000000 ' +bx0000000 ^ +bx0000000 P" b0 L" -bx000000 Q" +bx0000000 Q" 1R" b100 U" 1B @@ -113916,7 +113908,7 @@ b100 U" #230406250 0& b1 ," -b0xx000000 (" +b0x0000000 (" b101 U" 1B #230412500 @@ -114022,7 +114014,7 @@ b11 U" #230618750 0G" b1 L" -bx0000000 Q" +b0 Q" 1R" b100 U" 1B @@ -114131,7 +114123,6 @@ b11 U" #230843750 0G" b10 L" -b0 Q" 1R" b100 U" 1B @@ -114792,7 +114783,7 @@ b100 U" #232206250 0& b10 ," -b0xx00000000000000 (" +b0x000000000000000 (" b101 U" 1B #232212500 @@ -115675,7 +115666,7 @@ b1011 <" b1 8 b1 '" b0 ," -bx0000000000000000000001 (" +bx00000000000000000000001 (" b101 U" 1B #234012500 @@ -117788,7 +117779,7 @@ b101 U" 0B #238318750 xD -bx000000 b" +bx0000000 b" b111 d" b0 U" 1B @@ -117902,22 +117893,27 @@ b101 U" #238537500 0B #238543750 +0D b110 d" b0 U" 1B #238550000 0B #238556250 +bx0 O" b1 U" 1B #238562500 0B #238568750 +bx00 O" b10 U" 1B #238575000 0B #238581250 +0J" +b0 O" b11 U" 1B #238587500 @@ -117961,7 +117957,7 @@ b11 U" #238668750 0G" b10 L" -b111xx Q" +b111x0 Q" 1R" b100 U" 1B @@ -118011,27 +118007,22 @@ b101 U" #238762500 0B #238768750 -0D b101 d" b0 U" 1B #238775000 0B #238781250 -bx0 O" b1 U" 1B #238787500 0B #238793750 -bx00 O" b10 U" 1B #238800000 0B #238806250 -0J" -b0 O" b11 U" 1B #238812500 @@ -118075,7 +118066,7 @@ b11 U" #238893750 0G" b11 L" -b111xx0 Q" +b111x00 Q" 1R" b100 U" 1B @@ -118184,7 +118175,7 @@ b11 U" #239118750 0G" b100 L" -b111xx00 Q" +b111x000 Q" 1R" b100 U" 1B @@ -118293,7 +118284,7 @@ b11 U" #239343750 0G" b101 L" -b111xx000 Q" +b111x0000 Q" 1R" b100 U" 1B @@ -118402,7 +118393,7 @@ b11 U" #239568750 0G" b110 L" -b11xx0000 Q" +b11x00000 Q" 1R" b100 U" 1B @@ -118511,7 +118502,7 @@ b11 U" #239793750 0G" b111 L" -b1xx00000 Q" +b1x000000 Q" 1R" b100 U" 1B @@ -118620,11 +118611,11 @@ b11 U" #240018750 0G" 1& -bx000000 ' -bx000000 ^ -bx000000 P" +bx0000000 ' +bx0000000 ^ +bx0000000 P" b0 L" -bx000000 Q" +bx0000000 Q" 1R" b100 U" 1B @@ -118633,7 +118624,7 @@ b100 U" #240031250 0& b1 ," -b0xx000000 (" +b0x0000000 (" b101 U" 1B #240037500 @@ -118739,7 +118730,7 @@ b11 U" #240243750 0G" b1 L" -bx0000000 Q" +b0 Q" 1R" b100 U" 1B @@ -118848,7 +118839,6 @@ b11 U" #240468750 0G" b10 L" -b0 Q" 1R" b100 U" 1B @@ -119509,7 +119499,7 @@ b100 U" #241831250 0& b10 ," -b0xx00000000000000 (" +b0x000000000000000 (" b101 U" 1B #241837500 @@ -120400,7 +120390,7 @@ b1011 <" b1000 1 b1000 1" b0 ," -bx0000000000000000001000 (" +bx00000000000000000001000 (" b101 U" 1B #243637500 @@ -122513,7 +122503,7 @@ b101 U" 0B #247943750 xD -bx000000 b" +bx0000000 b" b111 d" b0 U" 1B @@ -122627,22 +122617,27 @@ b101 U" #248162500 0B #248168750 +0D b110 d" b0 U" 1B #248175000 0B #248181250 +bx0 O" b1 U" 1B #248187500 0B #248193750 +bx00 O" b10 U" 1B #248200000 0B #248206250 +0J" +b0 O" b11 U" 1B #248212500 @@ -122686,7 +122681,7 @@ b11 U" #248293750 0G" b10 L" -b1000xx Q" +b1000x0 Q" 1R" b100 U" 1B @@ -122736,27 +122731,22 @@ b101 U" #248387500 0B #248393750 -0D b101 d" b0 U" 1B #248400000 0B #248406250 -bx0 O" b1 U" 1B #248412500 0B #248418750 -bx00 O" b10 U" 1B #248425000 0B #248431250 -0J" -b0 O" b11 U" 1B #248437500 @@ -122800,7 +122790,7 @@ b11 U" #248518750 0G" b11 L" -b1000xx0 Q" +b1000x00 Q" 1R" b100 U" 1B @@ -122909,7 +122899,7 @@ b11 U" #248743750 0G" b100 L" -b1000xx00 Q" +b1000x000 Q" 1R" b100 U" 1B @@ -123018,7 +123008,7 @@ b11 U" #248968750 0G" b101 L" -b0xx000 Q" +b0x0000 Q" 1R" b100 U" 1B @@ -123127,7 +123117,7 @@ b11 U" #249193750 0G" b110 L" -b0xx0000 Q" +b0x00000 Q" 1R" b100 U" 1B @@ -123236,7 +123226,7 @@ b11 U" #249418750 0G" b111 L" -b0xx00000 Q" +b0x000000 Q" 1R" b100 U" 1B @@ -123345,11 +123335,11 @@ b11 U" #249643750 0G" 1& -bx000000 ' -bx000000 ^ -bx000000 P" +bx0000000 ' +bx0000000 ^ +bx0000000 P" b0 L" -bx000000 Q" +bx0000000 Q" 1R" b100 U" 1B @@ -123358,7 +123348,7 @@ b100 U" #249656250 0& b1 ," -b0xx000000 (" +b0x0000000 (" b101 U" 1B #249662500 @@ -123464,7 +123454,7 @@ b11 U" #249868750 0G" b1 L" -bx0000000 Q" +b0 Q" 1R" b100 U" 1B @@ -123573,7 +123563,6 @@ b11 U" #250093750 0G" b10 L" -b0 Q" 1R" b100 U" 1B @@ -124234,7 +124223,7 @@ b100 U" #251456250 0& b10 ," -b0xx00000000000000 (" +b0x000000000000000 (" b101 U" 1B #251462500 @@ -125123,7 +125112,7 @@ b1011 <" b10 0 b10 2" b0 ," -bx0000000000000000000010 (" +bx00000000000000000000010 (" b101 U" 1B #253262500 @@ -127230,7 +127219,7 @@ b101 U" 0B #257568750 xD -bx000001 b" +bx0000001 b" b111 d" b0 U" 1B @@ -127344,22 +127333,27 @@ b101 U" #257787500 0B #257793750 +0D b110 d" b0 U" 1B #257800000 0B #257806250 +bx0 O" b1 U" 1B #257812500 0B #257818750 +bx00 O" b10 U" 1B #257825000 0B #257831250 +0J" +b0 O" b11 U" 1B #257837500 @@ -127403,7 +127397,7 @@ b11 U" #257918750 0G" b10 L" -b111xx Q" +b111x0 Q" 1R" b100 U" 1B @@ -127453,27 +127447,22 @@ b101 U" #258012500 0B #258018750 -0D b101 d" b0 U" 1B #258025000 0B #258031250 -bx0 O" b1 U" 1B #258037500 0B #258043750 -bx00 O" b10 U" 1B #258050000 0B #258056250 -0J" -b0 O" b11 U" 1B #258062500 @@ -127517,7 +127506,7 @@ b11 U" #258143750 0G" b11 L" -b111xx0 Q" +b111x00 Q" 1R" b100 U" 1B @@ -127626,7 +127615,7 @@ b11 U" #258368750 0G" b100 L" -b111xx00 Q" +b111x000 Q" 1R" b100 U" 1B @@ -127735,7 +127724,7 @@ b11 U" #258593750 0G" b101 L" -b111xx000 Q" +b111x0000 Q" 1R" b100 U" 1B @@ -127844,7 +127833,7 @@ b11 U" #258818750 0G" b110 L" -b11xx0000 Q" +b11x00000 Q" 1R" b100 U" 1B @@ -127953,7 +127942,7 @@ b11 U" #259043750 0G" b111 L" -b1xx00000 Q" +b1x000000 Q" 1R" b100 U" 1B @@ -128067,11 +128056,11 @@ b11 U" #259268750 0G" 1& -bx000001 ' -bx000001 ^ -bx000001 P" +bx0000001 ' +bx0000001 ^ +bx0000001 P" b0 L" -bx000001 Q" +bx0000001 Q" 1R" b100 U" 1B @@ -128080,7 +128069,7 @@ b100 U" #259281250 0& b1 ," -b0xx000001 (" +b0x0000001 (" b101 U" 1B #259287500 @@ -128191,7 +128180,7 @@ b11 U" #259493750 0G" b1 L" -bx0000010 Q" +b10 Q" 1R" b100 U" 1B @@ -128972,7 +128961,7 @@ b100 U" #261081250 0& b10 ," -b0xx00000100000001 (" +b0x000000100000001 (" b101 U" 1B #261087500 @@ -129872,7 +129861,7 @@ b1011 <" b100000010 1 b100000010 1" b0 ," -bx0000010000000100000010 (" +bx00000010000000100000010 (" b101 U" 1B #262887500 diff --git a/sim/spi_engine_tb.v b/sim/spi_engine_tb.v index 0f2b5f6..ad19d06 100644 --- a/sim/spi_engine_tb.v +++ b/sim/spi_engine_tb.v @@ -30,7 +30,7 @@ module tb; - localparam ADDR_WIDTH = 22; + localparam ADDR_WIDTH = 23; localparam DATA_WIDTH = 8; localparam N_INPUTS = 32; localparam N_NEURONS = 3; diff --git a/sim/spi_neuron_top.vcd b/sim/spi_neuron_top.vcd index 86572da..9964bb9 100644 --- a/sim/spi_neuron_top.vcd +++ b/sim/spi_neuron_top.vcd @@ -1,5 +1,5 @@ $date - Wed Sep 2 20:14:00 2026 + Wed Sep 2 20:58:04 2026 $end $version Icarus Verilog @@ -15,7 +15,7 @@ $var wire 1 $ psram_ub_n $end $var wire 1 % psram_oe_n $end $var wire 1 & psram_lb_n $end $var wire 1 ' psram_ce_n $end -$var wire 22 ( psram_a [21:0] $end +$var wire 23 ( psram_a [22:0] $end $var wire 1 ) miso $end $var parameter 32 * ACC_WIDTH $end $var parameter 32 + ADDR_WIDTH $end @@ -47,29 +47,29 @@ $var wire 16 @ psram_dq [15:0] $end $var wire 1 8 rst $end $var wire 1 : sclk $end $var wire 8 A y_bus [7:0] $end -$var wire 22 B x_base [21:0] $end -$var wire 22 C w_base [21:0] $end +$var wire 23 B x_base [22:0] $end +$var wire 23 C w_base [22:0] $end $var wire 1 D tx_byte_req $end $var wire 8 E tx_byte [7:0] $end -$var wire 22 F table_base [21:0] $end +$var wire 23 F table_base [22:0] $end $var wire 1 G spi_ram_wr $end $var wire 8 H spi_ram_wdata [7:0] $end $var wire 1 I spi_ram_req $end $var wire 1 J spi_ram_ready $end $var wire 8 K spi_ram_rdata [7:0] $end -$var wire 22 L spi_ram_addr [21:0] $end +$var wire 23 L spi_ram_addr [22:0] $end $var wire 1 M seq_ram_wr $end $var wire 8 N seq_ram_wdata [7:0] $end $var wire 1 O seq_ram_req $end $var wire 1 P seq_ram_ready $end $var wire 8 Q seq_ram_rdata [7:0] $end -$var wire 22 R seq_ram_addr [21:0] $end -$var wire 22 S seq_nm_x_base [21:0] $end -$var wire 22 T seq_nm_w_base [21:0] $end +$var wire 23 R seq_ram_addr [22:0] $end +$var wire 23 S seq_nm_x_base [22:0] $end +$var wire 23 T seq_nm_w_base [22:0] $end $var wire 1 U seq_nm_start $end $var wire 16 V seq_nm_n_neurons [15:0] $end $var wire 16 W seq_nm_n_inputs [15:0] $end -$var wire 22 X seq_nm_bias_addr [21:0] $end +$var wire 23 X seq_nm_bias_addr [22:0] $end $var wire 2 Y seq_nm_activation [1:0] $end $var wire 1 Z seq_done $end $var wire 1 [ seq_busy $end @@ -88,10 +88,10 @@ $var wire 1 c psram_mem_req $end $var wire 1 d psram_mem_ready $end $var wire 16 e psram_mem_rdata [15:0] $end $var wire 1 f psram_mem_lb_n $end -$var wire 22 g psram_mem_addr [21:0] $end +$var wire 23 g psram_mem_addr [22:0] $end $var wire 1 & psram_lb_n $end $var wire 1 ' psram_ce_n $end -$var wire 22 h psram_a [21:0] $end +$var wire 23 h psram_a [22:0] $end $var wire 1 i nm_start $end $var wire 1 j nm_soft_rst $end $var wire 1 k nm_ram_wr $end @@ -99,17 +99,17 @@ $var wire 8 l nm_ram_wdata [7:0] $end $var wire 1 m nm_ram_req $end $var wire 1 n nm_ram_ready $end $var wire 8 o nm_ram_rdata [7:0] $end -$var wire 22 p nm_ram_addr [21:0] $end +$var wire 23 p nm_ram_addr [22:0] $end $var wire 1 q nm_done $end $var wire 1 r nm_busy $end $var wire 16 s n_neurons_real [15:0] $end $var wire 16 t n_inputs_real [15:0] $end -$var wire 22 u mux_nm_x_base [21:0] $end -$var wire 22 v mux_nm_w_base [21:0] $end +$var wire 23 u mux_nm_x_base [22:0] $end +$var wire 23 v mux_nm_w_base [22:0] $end $var wire 1 w mux_nm_start $end $var wire 16 x mux_nm_n_neurons [15:0] $end $var wire 16 y mux_nm_n_inputs [15:0] $end -$var wire 22 z mux_nm_bias_addr [21:0] $end +$var wire 23 z mux_nm_bias_addr [22:0] $end $var wire 2 { mux_nm_activation [1:0] $end $var wire 1 ) miso $end $var wire 1 | i8_mem_wr $end @@ -119,18 +119,18 @@ $var wire 1 !" i8_mem_req $end $var wire 1 "" i8_mem_ready $end $var wire 16 #" i8_mem_rdata [15:0] $end $var wire 1 $" i8_mem_lb_n $end -$var wire 22 %" i8_mem_addr [21:0] $end +$var wire 23 %" i8_mem_addr [22:0] $end $var wire 1 &" cs_start $end $var wire 1 '" cs_end $end -$var wire 22 (" buf_b_base [21:0] $end -$var wire 22 )" buf_a_base [21:0] $end -$var wire 22 *" bias_addr [21:0] $end +$var wire 23 (" buf_b_base [22:0] $end +$var wire 23 )" buf_a_base [22:0] $end +$var wire 23 *" bias_addr [22:0] $end $var wire 1 +" arb_wr $end $var wire 8 ," arb_wdata [7:0] $end $var wire 1 -" arb_req $end $var wire 1 ." arb_ready $end $var wire 8 /" arb_rdata [7:0] $end -$var wire 22 0" arb_addr [21:0] $end +$var wire 23 0" arb_addr [22:0] $end $var wire 2 1" activation [1:0] $end $var parameter 32 2" ACC_WIDTH $end $var parameter 32 3" ADDR_WIDTH $end @@ -149,15 +149,15 @@ $var wire 8 ;" m_rdata [7:0] $end $var wire 1 M c_wr $end $var wire 8 <" c_wdata [7:0] $end $var wire 1 O c_req $end -$var wire 22 =" c_addr [21:0] $end +$var wire 23 =" c_addr [22:0] $end $var wire 1 k b_wr $end $var wire 8 >" b_wdata [7:0] $end $var wire 1 m b_req $end -$var wire 22 ?" b_addr [21:0] $end +$var wire 23 ?" b_addr [22:0] $end $var wire 1 G a_wr $end $var wire 8 @" a_wdata [7:0] $end $var wire 1 I a_req $end -$var wire 22 A" a_addr [21:0] $end +$var wire 23 A" a_addr [22:0] $end $var parameter 32 B" ADDR_WIDTH $end $var parameter 2 C" SEL_A $end $var parameter 2 D" SEL_B $end @@ -169,14 +169,14 @@ $var reg 8 H" b_rdata [7:0] $end $var reg 1 n b_ready $end $var reg 8 I" c_rdata [7:0] $end $var reg 1 P c_ready $end -$var reg 22 J" m_addr [21:0] $end +$var reg 23 J" m_addr [22:0] $end $var reg 1 -" m_req $end $var reg 8 K" m_wdata [7:0] $end $var reg 1 +" m_wr $end $var reg 2 L" owner [1:0] $end $upscope $end $scope module u_int8_access $end -$var wire 22 M" addr [21:0] $end +$var wire 23 M" addr [22:0] $end $var wire 1 5 clk $end $var wire 1 -" req $end $var wire 1 8 rst $end @@ -187,8 +187,8 @@ $var wire 16 O" mem_rdata [15:0] $end $var parameter 32 P" ADDR_WIDTH $end $var parameter 2 Q" STATE_IDLE $end $var parameter 2 R" STATE_WAIT $end -$var reg 22 S" addr_reg [21:0] $end -$var reg 22 T" mem_addr [21:0] $end +$var reg 23 S" addr_reg [22:0] $end +$var reg 23 T" mem_addr [22:0] $end $var reg 1 $" mem_lb_n $end $var reg 1 !" mem_req $end $var reg 1 ~ mem_ub_n $end @@ -204,14 +204,14 @@ $var wire 8 X" ram_rdata [7:0] $end $var wire 1 P ram_ready $end $var wire 1 8 rst $end $var wire 8 Y" y_bus [7:0] $end -$var wire 22 Z" x_base [21:0] $end -$var wire 22 [" table_base [21:0] $end +$var wire 23 Z" x_base [22:0] $end +$var wire 23 [" table_base [22:0] $end $var wire 1 ^ run_start $end $var wire 8 \" run_num_layers [7:0] $end $var wire 1 q nm_done $end $var wire 1 r nm_busy $end -$var wire 22 ]" buf_b_base [21:0] $end -$var wire 22 ^" buf_a_base [21:0] $end +$var wire 23 ]" buf_b_base [22:0] $end +$var wire 23 ^" buf_a_base [22:0] $end $var parameter 32 _" ADDR_WIDTH $end $var parameter 32 `" DATA_WIDTH $end $var parameter 32 a" N_LAYERS $end @@ -228,19 +228,19 @@ $var reg 24 k" bias_addr_acc [23:0] $end $var reg 1 l" copy_idx $end $var reg 1 m" cur_sel $end $var reg 4 n" desc_byte_idx [3:0] $end -$var reg 22 o" desc_table_addr [21:0] $end +$var reg 23 o" desc_table_addr [22:0] $end $var reg 8 p" layer_idx [7:0] $end $var reg 16 q" n_inputs_acc [15:0] $end $var reg 16 r" n_neurons_acc [15:0] $end $var reg 2 s" nm_activation [1:0] $end -$var reg 22 t" nm_bias_addr [21:0] $end +$var reg 23 t" nm_bias_addr [22:0] $end $var reg 16 u" nm_n_inputs [15:0] $end $var reg 16 v" nm_n_neurons [15:0] $end $var reg 1 U nm_start $end -$var reg 22 w" nm_w_base [21:0] $end -$var reg 22 x" nm_x_base [21:0] $end +$var reg 23 w" nm_w_base [22:0] $end +$var reg 23 x" nm_x_base [22:0] $end $var reg 8 y" num_layers_reg [7:0] $end -$var reg 22 z" ram_addr [21:0] $end +$var reg 23 z" ram_addr [22:0] $end $var reg 1 O ram_req $end $var reg 8 {" ram_wdata [7:0] $end $var reg 1 M ram_wr $end @@ -251,7 +251,7 @@ $var reg 24 }" w_base_acc [23:0] $end $var reg 1 ~" write_sel $end $upscope $end $scope module u_memory_if $end -$var wire 22 !# addr [21:0] $end +$var wire 23 !# addr [22:0] $end $var wire 1 5 clk $end $var wire 1 $" lb_n $end $var wire 1 !" req $end @@ -265,7 +265,7 @@ $var parameter 32 $# ADDR_WIDTH $end $var parameter 32 %# DATA_WIDTH $end $var parameter 2 &# STATE_IDLE $end $var parameter 2 '# STATE_WAIT $end -$var reg 22 (# mem_addr [21:0] $end +$var reg 23 (# mem_addr [22:0] $end $var reg 1 f mem_lb_n $end $var reg 1 c mem_req $end $var reg 1 b mem_ub_n $end @@ -277,9 +277,9 @@ $var reg 2 +# state [1:0] $end $upscope $end $scope module u_neuron_memory $end $var wire 2 ,# activation [1:0] $end -$var wire 22 -# bias_addr [21:0] $end +$var wire 23 -# bias_addr [22:0] $end $var wire 1 5 clk $end -$var wire 22 .# mem_addr [21:0] $end +$var wire 23 .# mem_addr [22:0] $end $var wire 8 /# mem_rdata [7:0] $end $var wire 1 n mem_ready $end $var wire 1 m mem_req $end @@ -289,8 +289,8 @@ $var wire 16 1# n_inputs_real [15:0] $end $var wire 16 2# n_neurons_real [15:0] $end $var wire 1 ? rst $end $var wire 1 w start $end -$var wire 22 3# w_base [21:0] $end -$var wire 22 4# x_base [21:0] $end +$var wire 23 3# w_base [22:0] $end +$var wire 23 4# x_base [22:0] $end $var wire 8 5# y_bus [7:0] $end $var wire 256 6# x_bus [255:0] $end $var wire 256 7# w_bus [255:0] $end @@ -305,7 +305,7 @@ $var wire 1 ?# access_mem_ub_n $end $var wire 1 @# access_mem_req $end $var wire 16 A# access_mem_rdata [15:0] $end $var wire 1 B# access_mem_lb_n $end -$var wire 22 C# access_mem_addr [21:0] $end +$var wire 23 C# access_mem_addr [22:0] $end $var parameter 32 D# ACC_WIDTH $end $var parameter 32 E# ADDR_WIDTH $end $var parameter 32 F# DATA_WIDTH $end @@ -319,11 +319,11 @@ $var parameter 4 M# STATE_READ_W $end $var parameter 4 N# STATE_READ_X $end $var parameter 4 O# STATE_START_N $end $var parameter 4 P# STATE_WAIT_N $end -$var reg 22 Q# access_addr [21:0] $end +$var reg 23 Q# access_addr [22:0] $end $var reg 1 R# access_req $end $var reg 8 S# access_wdata [7:0] $end $var reg 1 T# access_wr $end -$var reg 22 U# bias_group_addr [21:0] $end +$var reg 23 U# bias_group_addr [22:0] $end $var reg 8 V# bias_reg [7:0] $end $var reg 1 r busy $end $var reg 1 q done $end @@ -331,7 +331,7 @@ $var reg 6 W# index [5:0] $end $var reg 1 X# neuron_index $end $var reg 1 Y# neuron_start $end $var reg 4 Z# state [3:0] $end -$var reg 22 [# w_group_base [21:0] $end +$var reg 23 [# w_group_base [22:0] $end $var integer 32 \# rst_i [31:0] $end $scope begin GEN_BUS[0] $end $var parameter 2 ]# i $end @@ -433,7 +433,7 @@ $scope begin GEN_Y_BUS[0] $end $var parameter 2 }# j $end $upscope $end $scope module u_mem $end -$var wire 22 ~# addr [21:0] $end +$var wire 23 ~# addr [22:0] $end $var wire 1 5 clk $end $var wire 16 !$ mem_rdata [15:0] $end $var wire 1 n mem_ready $end @@ -444,8 +444,8 @@ $var wire 1 T# wr $end $var parameter 32 #$ ADDR_WIDTH $end $var parameter 2 $$ STATE_IDLE $end $var parameter 2 %$ STATE_WAIT $end -$var reg 22 &$ addr_reg [21:0] $end -$var reg 22 '$ mem_addr [21:0] $end +$var reg 23 &$ addr_reg [22:0] $end +$var reg 23 '$ mem_addr [22:0] $end $var reg 1 B# mem_lb_n $end $var reg 1 @# mem_req $end $var reg 1 ?# mem_ub_n $end @@ -663,7 +663,7 @@ $upscope $end $upscope $end $scope module u_psram_ctrl $end $var wire 1 5 clk $end -$var wire 22 M% mem_addr [21:0] $end +$var wire 23 M% mem_addr [22:0] $end $var wire 1 f mem_lb_n $end $var wire 1 c mem_req $end $var wire 1 b mem_ub_n $end @@ -682,14 +682,14 @@ $var parameter 3 W% STATE_INIT $end $var parameter 3 X% STATE_READ $end $var parameter 3 Y% STATE_WRITE $end $var parameter 3 Z% STATE_WRITE_WAIT $end -$var reg 22 [% address_reg [21:0] $end +$var reg 23 [% address_reg [22:0] $end $var reg 14 \% counter [13:0] $end $var reg 1 ]% dq_oe $end $var reg 16 ^% dq_out [15:0] $end $var reg 1 _% lb_reg $end $var reg 16 `% mem_rdata [15:0] $end $var reg 1 d mem_ready $end -$var reg 22 a% psram_a [21:0] $end +$var reg 23 a% psram_a [22:0] $end $var reg 1 ' psram_ce_n $end $var reg 1 & psram_lb_n $end $var reg 1 % psram_oe_n $end @@ -759,11 +759,11 @@ $var parameter 4 2& ST_WRITE_ISSUE $end $var parameter 4 3& ST_WRITE_WAIT $end $var reg 2 4& activation [1:0] $end $var reg 24 5& addr_acc [23:0] $end -$var reg 22 6& bias_addr [21:0] $end -$var reg 22 7& buf_a_base [21:0] $end -$var reg 22 8& buf_b_base [21:0] $end +$var reg 23 6& bias_addr [22:0] $end +$var reg 23 7& buf_a_base [22:0] $end +$var reg 23 8& buf_b_base [22:0] $end $var reg 2 9& byte_pos [1:0] $end -$var reg 22 :& cur_addr [21:0] $end +$var reg 23 :& cur_addr [22:0] $end $var reg 8 ;& cur_read_byte [7:0] $end $var reg 16 <& len_acc [15:0] $end $var reg 16 =& len_remaining [15:0] $end @@ -775,7 +775,7 @@ $var reg 1 i nm_start $end $var reg 8 A& opcode [7:0] $end $var reg 8 B& pending_wdata [7:0] $end $var reg 1 C& pending_write $end -$var reg 22 D& ram_addr [21:0] $end +$var reg 23 D& ram_addr [22:0] $end $var reg 1 I ram_req $end $var reg 8 E& ram_wdata [7:0] $end $var reg 1 G ram_wr $end @@ -786,10 +786,10 @@ $var reg 1 ^ run_start $end $var reg 4 I& state [3:0] $end $var reg 1 J& status_done_sticky $end $var reg 8 K& status_snapshot [7:0] $end -$var reg 22 L& table_base [21:0] $end +$var reg 23 L& table_base [22:0] $end $var reg 8 M& tx_byte_comb [7:0] $end -$var reg 22 N& w_base [21:0] $end -$var reg 22 O& x_base [21:0] $end +$var reg 23 N& w_base [22:0] $end +$var reg 23 O& x_base [22:0] $end $upscope $end $scope module u_spi_slave $end $var wire 1 5 clk $end @@ -823,7 +823,7 @@ $var reg 8 a& tx_shift [7:0] $end $upscope $end $upscope $end $scope module u_psram $end -$var wire 22 b& a [21:0] $end +$var wire 23 b& a [22:0] $end $var wire 1 ' ce_n $end $var wire 1 5 clk $end $var wire 16 c& dq [15:0] $end @@ -850,7 +850,7 @@ $var real 1 r& TWC_NS $end $var real 1 s& TWPH_NS $end $var real 1 t& TWP_NS $end $var real 1 u& TWR_NS $end -$var reg 22 v& active_addr [21:0] $end +$var reg 23 v& active_addr [22:0] $end $var reg 16 w& active_wdata [15:0] $end $var reg 1 x& dq_oe $end $var reg 16 y& dq_out [15:0] $end @@ -888,14 +888,14 @@ $scope task read_output_byte0 $end $var reg 8 /' y0 [7:0] $end $upscope $end $scope task read_ram_byte $end -$var reg 22 0' addr [21:0] $end +$var reg 23 0' addr [22:0] $end $var reg 8 1' data [7:0] $end $upscope $end $scope task read_status $end $var reg 8 2' status [7:0] $end $upscope $end $scope task set_base $end -$var reg 22 3' addr [21:0] $end +$var reg 23 3' addr [22:0] $end $var reg 8 4' sel [7:0] $end $upscope $end $scope task spi_begin $end @@ -915,7 +915,7 @@ $scope task wait_done $end $var reg 8 <' status [7:0] $end $upscope $end $scope task write_ram_const $end -$var reg 22 =' addr [21:0] $end +$var reg 23 =' addr [22:0] $end $var reg 8 >' value [7:0] $end $var integer 32 ?' k [31:0] $end $var integer 32 @' len [31:0] $end @@ -941,7 +941,7 @@ r70 h& r70 g& b100000000000000 f& b10000 e& -b10110 d& +b10111 d& b110 3& b101 2& b100 1& @@ -978,7 +978,7 @@ b0 q% b1 p% b100000 o% b1000 n% -b10110 m% +b10111 m% b100 Z% b11 Y% b10 X% @@ -988,7 +988,7 @@ b10111011100000 U% b10000 T% b1110 S% b1010000 R% -b10110 Q% +b10111 Q% b110 P% b0 L% b10 K% @@ -1054,7 +1054,7 @@ b0 7$ b100000 6$ b1 %$ b0 $$ -b10110 #$ +b10111 #$ b0 }# b11111 |# b11110 {# @@ -1099,12 +1099,12 @@ b1 I# b100000 H# b1 G# b1000 F# -b10110 E# +b10111 E# b100000 D# b1 '# b0 &# b10000 %# -b10110 $# +b10111 $# b100 i" b11 h" b10 g" @@ -1115,15 +1115,15 @@ b101 c" b1 b" b100 a" b1000 `" -b10110 _" +b10111 _" b1 R" b0 Q" -b10110 P" +b10111 P" b0 F" b11 E" b10 D" b1 C" -b10110 B" +b10111 B" b1000 :" b1 9" b100 8" @@ -1131,7 +1131,7 @@ b100000 7" b10000 6" b1000 5" b1010000 4" -b10110 3" +b10111 3" b100000 2" b1000 3 b1 2 @@ -1141,7 +1141,7 @@ b1000 / b101000 . b1000 - r12.5 , -b10110 + +b10111 + b100000 * $end #0 @@ -64539,10 +64539,10 @@ b100 -' #155900000 05 #155906250 -b10110 E -b10110 i% -b10110 U& -b10110 M& +b10111 E +b10111 i% +b10111 U& +b10111 M& 0\ b1010 I& b1000 G& @@ -64590,7 +64590,7 @@ b11 -' #155993750 0S& 1D -b10110 a& +b10111 a& 0_& b100 -' 15 @@ -64732,7 +64732,7 @@ b11 -' 05 #156293750 0S& -b101100 a& +b101110 a& 0_& b100 -' 15 @@ -64872,7 +64872,7 @@ b11 -' 05 #156593750 0S& -b1011000 a& +b1011100 a& 0_& b100 -' 15 @@ -65013,7 +65013,7 @@ b11 -' #156893750 0S& 1) -b10110000 a& +b10111000 a& 0_& b100 -' 15 @@ -65155,7 +65155,7 @@ b11 -' #157193750 0S& 0) -b1100000 a& +b1110000 a& 0_& b100 -' 15 @@ -65295,7 +65295,7 @@ b11 -' #157493750 0S& 1) -b11000000 a& +b11100000 a& 0_& b100 -' 15 @@ -65435,7 +65435,7 @@ b11 -' 05 #157793750 0S& -b10000000 a& +b11000000 a& 0_& b100 -' 15 @@ -65575,8 +65575,7 @@ b11 -' 05 #158093750 0S& -0) -b0 a& +b10000000 a& 0_& b100 -' 15 @@ -65639,6 +65638,7 @@ b111 -' #158237500 05 #158243750 +b10111 8' 1: b0 -' 15 @@ -65725,7 +65725,9 @@ b11 -' 05 #158393750 0S& +0) 1D +b0 a& 0_& b100 -' 15 @@ -65749,8 +65751,8 @@ b111 -' 05 #158443750 b0 8' -b10110 4 -b10110 7' +b10111 4 +b10111 7' b111 ;' b0 -' 15 @@ -77319,7 +77321,7 @@ b100111 -' 05 #184843750 x7 -bx000000 9' +bx0000000 9' b0 7' b111 ;' b0 -' @@ -77944,22 +77946,27 @@ b100111 -' #186337500 05 #186343750 +07 b110 ;' b0 -' 15 #186350000 05 #186356250 +bx0 \& b1 -' 15 #186362500 05 #186368750 +bx00 \& b10 -' 15 #186375000 05 #186381250 +0W& +b0 \& b11 -' 15 #186387500 @@ -78173,7 +78180,7 @@ b11 -' #186893750 0T& b10 Y& -b1xx ^& +b1x0 ^& 1_& b100 -' 15 @@ -78563,27 +78570,22 @@ b100111 -' #187837500 05 #187843750 -07 b101 ;' b0 -' 15 #187850000 05 #187856250 -bx0 \& b1 -' 15 #187862500 05 #187868750 -bx00 \& b10 -' 15 #187875000 05 #187881250 -0W& -b0 \& b11 -' 15 #187887500 @@ -78797,7 +78799,7 @@ b11 -' #188393750 0T& b11 Y& -b1xx0 ^& +b1x00 ^& 1_& b100 -' 15 @@ -79416,7 +79418,7 @@ b11 -' #189893750 0T& b100 Y& -b1xx00 ^& +b1x000 ^& 1_& b100 -' 15 @@ -80035,7 +80037,7 @@ b11 -' #191393750 0T& b101 Y& -b1xx000 ^& +b1x0000 ^& 1_& b100 -' 15 @@ -80654,7 +80656,7 @@ b11 -' #192893750 0T& b110 Y& -b1xx0000 ^& +b1x00000 ^& 1_& b100 -' 15 @@ -81273,7 +81275,7 @@ b11 -' #194393750 0T& b111 Y& -b1xx00000 ^& +b1x000000 ^& 1_& b100 -' 15 @@ -81892,11 +81894,11 @@ b11 -' #195893750 0T& 1\ -bx000000 ] -bx000000 k% -bx000000 ]& +bx0000000 ] +bx0000000 k% +bx0000000 ]& b0 Y& -bx000000 ^& +bx0000000 ^& 1_& b100 -' 15 @@ -81905,7 +81907,7 @@ b100 -' #195906250 0\ b1 9& -b0xx000000 5& +b0x0000000 5& b101 -' 15 #195912500 @@ -82521,7 +82523,7 @@ b11 -' #197393750 0T& b1 Y& -bx0000000 ^& +b0 ^& 1_& b100 -' 15 @@ -83140,7 +83142,6 @@ b11 -' #198893750 0T& b10 Y& -b0 ^& 1_& b100 -' 15 @@ -86861,7 +86862,7 @@ b100 -' #207906250 0\ b10 9& -b0xx00000000000000 5& +b0x000000000000000 5& b101 -' 15 #207912500 @@ -91812,7 +91813,7 @@ b100 -' 0\ b11 I& b0 9& -bx0000000000000000000000 5& +bx00000000000000000000000 5& b101 -' 15 #219912500 @@ -270467,7 +270468,7 @@ b100111 -' 05 #644843750 x7 -bx000000 9' +bx0000000 9' b111 ;' b0 -' 15 @@ -271091,22 +271092,27 @@ b100111 -' #646337500 05 #646343750 +07 b110 ;' b0 -' 15 #646350000 05 #646356250 +bx0 \& b1 -' 15 #646362500 05 #646368750 +bx00 \& b10 -' 15 #646375000 05 #646381250 +0W& +b0 \& b11 -' 15 #646387500 @@ -271320,7 +271326,7 @@ b11 -' #646893750 0T& b10 Y& -b1xx ^& +b1x0 ^& 1_& b100 -' 15 @@ -271710,27 +271716,22 @@ b100111 -' #647837500 05 #647843750 -07 b101 ;' b0 -' 15 #647850000 05 #647856250 -bx0 \& b1 -' 15 #647862500 05 #647868750 -bx00 \& b10 -' 15 #647875000 05 #647881250 -0W& -b0 \& b11 -' 15 #647887500 @@ -271944,7 +271945,7 @@ b11 -' #648393750 0T& b11 Y& -b1xx0 ^& +b1x00 ^& 1_& b100 -' 15 @@ -272563,7 +272564,7 @@ b11 -' #649893750 0T& b100 Y& -b1xx00 ^& +b1x000 ^& 1_& b100 -' 15 @@ -273182,7 +273183,7 @@ b11 -' #651393750 0T& b101 Y& -b1xx000 ^& +b1x0000 ^& 1_& b100 -' 15 @@ -273801,7 +273802,7 @@ b11 -' #652893750 0T& b110 Y& -b1xx0000 ^& +b1x00000 ^& 1_& b100 -' 15 @@ -274420,7 +274421,7 @@ b11 -' #654393750 0T& b111 Y& -b1xx00000 ^& +b1x000000 ^& 1_& b100 -' 15 @@ -275039,11 +275040,11 @@ b11 -' #655893750 0T& 1\ -bx000000 ] -bx000000 k% -bx000000 ]& +bx0000000 ] +bx0000000 k% +bx0000000 ]& b0 Y& -bx000000 ^& +bx0000000 ^& 1_& b100 -' 15 @@ -275052,7 +275053,7 @@ b100 -' #655906250 0\ b1 9& -b0xx000000 5& +b0x0000000 5& b101 -' 15 #655912500 @@ -275668,7 +275669,7 @@ b11 -' #657393750 0T& b1 Y& -bx0000000 ^& +b0 ^& 1_& b100 -' 15 @@ -276287,7 +276288,6 @@ b11 -' #658893750 0T& b10 Y& -b0 ^& 1_& b100 -' 15 @@ -280014,7 +280014,7 @@ b100 -' #667906250 0\ b10 9& -b0xx00000000000001 5& +b0x000000000000001 5& b101 -' 15 #667912500 @@ -284984,7 +284984,7 @@ b11 I& b0 <& b100000000 :& b0 9& -bx0000000000000100000000 5& +bx00000000000000100000000 5& b101 -' 15 #679912500 @@ -463647,7 +463647,7 @@ b100111 -' 05 #1104843750 x7 -bx000000 9' +bx0000000 9' b111 ;' b0 -' 15 @@ -464271,22 +464271,27 @@ b100111 -' #1106337500 05 #1106343750 +07 b110 ;' b0 -' 15 #1106350000 05 #1106356250 +bx0 \& b1 -' 15 #1106362500 05 #1106368750 +bx00 \& b10 -' 15 #1106375000 05 #1106381250 +0W& +b0 \& b11 -' 15 #1106387500 @@ -464500,7 +464505,7 @@ b11 -' #1106893750 0T& b10 Y& -b1xx ^& +b1x0 ^& 1_& b100 -' 15 @@ -464890,27 +464895,22 @@ b100111 -' #1107837500 05 #1107843750 -07 b101 ;' b0 -' 15 #1107850000 05 #1107856250 -bx0 \& b1 -' 15 #1107862500 05 #1107868750 -bx00 \& b10 -' 15 #1107875000 05 #1107881250 -0W& -b0 \& b11 -' 15 #1107887500 @@ -465124,7 +465124,7 @@ b11 -' #1108393750 0T& b11 Y& -b1xx0 ^& +b1x00 ^& 1_& b100 -' 15 @@ -465743,7 +465743,7 @@ b11 -' #1109893750 0T& b100 Y& -b1xx00 ^& +b1x000 ^& 1_& b100 -' 15 @@ -466362,7 +466362,7 @@ b11 -' #1111393750 0T& b101 Y& -b1xx000 ^& +b1x0000 ^& 1_& b100 -' 15 @@ -466981,7 +466981,7 @@ b11 -' #1112893750 0T& b110 Y& -b1xx0000 ^& +b1x00000 ^& 1_& b100 -' 15 @@ -467600,7 +467600,7 @@ b11 -' #1114393750 0T& b111 Y& -b1xx00000 ^& +b1x000000 ^& 1_& b100 -' 15 @@ -468219,11 +468219,11 @@ b11 -' #1115893750 0T& 1\ -bx000000 ] -bx000000 k% -bx000000 ]& +bx0000000 ] +bx0000000 k% +bx0000000 ]& b0 Y& -bx000000 ^& +bx0000000 ^& 1_& b100 -' 15 @@ -468232,7 +468232,7 @@ b100 -' #1115906250 0\ b1 9& -b0xx000000 5& +b0x0000000 5& b101 -' 15 #1115912500 @@ -468848,7 +468848,7 @@ b11 -' #1117393750 0T& b1 Y& -bx0000000 ^& +b0 ^& 1_& b100 -' 15 @@ -469467,7 +469467,6 @@ b11 -' #1118893750 0T& b10 Y& -b0 ^& 1_& b100 -' 15 @@ -473200,7 +473199,7 @@ b100 -' #1127906250 0\ b10 9& -b0xx00000000000010 5& +b0x000000000000010 5& b101 -' 15 #1127912500 @@ -478164,7 +478163,7 @@ b11 I& b0 <& b1000000000 :& b0 9& -bx0000000000001000000000 5& +bx00000000000001000000000 5& b101 -' 15 #1139912500 @@ -500126,7 +500125,7 @@ b100111 -' 05 #1192843750 x7 -bx000000 9' +bx0000000 9' b111 ;' b0 -' 15 @@ -500750,22 +500749,27 @@ b100111 -' #1194337500 05 #1194343750 +07 b110 ;' b0 -' 15 #1194350000 05 #1194356250 +bx0 \& b1 -' 15 #1194362500 05 #1194368750 +bx00 \& b10 -' 15 #1194375000 05 #1194381250 +0W& +b0 \& b11 -' 15 #1194387500 @@ -500979,7 +500983,7 @@ b11 -' #1194893750 0T& b10 Y& -b10xx ^& +b10x0 ^& 1_& b100 -' 15 @@ -501369,27 +501373,22 @@ b100111 -' #1195837500 05 #1195843750 -07 b101 ;' b0 -' 15 #1195850000 05 #1195856250 -bx0 \& b1 -' 15 #1195862500 05 #1195868750 -bx00 \& b10 -' 15 #1195875000 05 #1195881250 -0W& -b0 \& b11 -' 15 #1195887500 @@ -501603,7 +501602,7 @@ b11 -' #1196393750 0T& b11 Y& -b10xx0 ^& +b10x00 ^& 1_& b100 -' 15 @@ -502222,7 +502221,7 @@ b11 -' #1197893750 0T& b100 Y& -b10xx00 ^& +b10x000 ^& 1_& b100 -' 15 @@ -502841,7 +502840,7 @@ b11 -' #1199393750 0T& b101 Y& -b10xx000 ^& +b10x0000 ^& 1_& b100 -' 15 @@ -503460,7 +503459,7 @@ b11 -' #1200893750 0T& b110 Y& -b10xx0000 ^& +b10x00000 ^& 1_& b100 -' 15 @@ -504079,7 +504078,7 @@ b11 -' #1202393750 0T& b111 Y& -b0xx00000 ^& +b0x000000 ^& 1_& b100 -' 15 @@ -504698,11 +504697,11 @@ b11 -' #1203893750 0T& 1\ -bx000000 ] -bx000000 k% -bx000000 ]& +bx0000000 ] +bx0000000 k% +bx0000000 ]& b0 Y& -bx000000 ^& +bx0000000 ^& 1_& b100 -' 15 @@ -504711,7 +504710,7 @@ b100 -' #1203906250 0\ b1 9& -b0xx000000 5& +b0x0000000 5& b101 -' 15 #1203912500 @@ -505327,7 +505326,7 @@ b11 -' #1205393750 0T& b1 Y& -bx0000000 ^& +b0 ^& 1_& b100 -' 15 @@ -505946,7 +505945,6 @@ b11 -' #1206893750 0T& b10 Y& -b0 ^& 1_& b100 -' 15 @@ -509667,7 +509665,7 @@ b100 -' #1215906250 0\ b10 9& -b0xx00000000000000 5& +b0x000000000000000 5& b101 -' 15 #1215912500 @@ -514620,7 +514618,7 @@ b11 I& b0 <& b0 :& b0 9& -bx0000000000000000000000 5& +bx00000000000000000000000 5& b101 -' 15 #1227912500 @@ -533248,7 +533246,7 @@ b111 -' 05 #1272043750 x7 -bx000000 9' +bx0000000 9' b111 ;' b0 -' 15 @@ -533392,22 +533390,27 @@ b111 -' #1272337500 05 #1272343750 +07 b110 ;' b0 -' 15 #1272350000 05 #1272356250 +bx0 \& b1 -' 15 #1272362500 05 #1272368750 +bx00 \& b10 -' 15 #1272375000 05 #1272381250 +0W& +b0 \& b11 -' 15 #1272387500 @@ -533461,7 +533464,7 @@ b11 -' #1272493750 0T& b10 Y& -b0xx ^& +b0x0 ^& 1_& b100 -' 15 @@ -533531,27 +533534,22 @@ b111 -' #1272637500 05 #1272643750 -07 b101 ;' b0 -' 15 #1272650000 05 #1272656250 -bx0 \& b1 -' 15 #1272662500 05 #1272668750 -bx00 \& b10 -' 15 #1272675000 05 #1272681250 -0W& -b0 \& b11 -' 15 #1272687500 @@ -533605,7 +533603,7 @@ b11 -' #1272793750 0T& b11 Y& -b0xx0 ^& +b0x00 ^& 1_& b100 -' 15 @@ -533744,7 +533742,7 @@ b11 -' #1273093750 0T& b100 Y& -b0xx00 ^& +b0x000 ^& 1_& b100 -' 15 @@ -533883,7 +533881,7 @@ b11 -' #1273393750 0T& b101 Y& -b0xx000 ^& +b0x0000 ^& 1_& b100 -' 15 @@ -534022,7 +534020,7 @@ b11 -' #1273693750 0T& b110 Y& -b0xx0000 ^& +b0x00000 ^& 1_& b100 -' 15 @@ -534161,7 +534159,7 @@ b11 -' #1273993750 0T& b111 Y& -b0xx00000 ^& +b0x000000 ^& 1_& b100 -' 15 @@ -534300,11 +534298,11 @@ b11 -' #1274293750 0T& 1\ -bx000000 ] -bx000000 k% -bx000000 ]& +bx0000000 ] +bx0000000 k% +bx0000000 ]& b0 Y& -bx000000 ^& +bx0000000 ^& 1_& b100 -' 15 @@ -534313,7 +534311,7 @@ b100 -' #1274306250 0\ b1 9& -b0xx000000 5& +b0x0000000 5& b101 -' 15 #1274312500 @@ -534449,7 +534447,7 @@ b11 -' #1274593750 0T& b1 Y& -bx0000000 ^& +b0 ^& 1_& b100 -' 15 @@ -534588,7 +534586,6 @@ b11 -' #1274893750 0T& b10 Y& -b0 ^& 1_& b100 -' 15 @@ -535429,7 +535426,7 @@ b100 -' #1276706250 0\ b10 9& -b0xx00000000000000 5& +b0x000000000000000 5& b101 -' 15 #1276712500 @@ -536540,7 +536537,7 @@ b100 -' 0\ b1011 I& b0 9& -bx0000000000000000000000 5& +bx00000000000000000000000 5& b101 -' 15 #1279112500 @@ -539211,7 +539208,7 @@ b111 -' 05 #1284843750 x7 -bx000000 9' +bx0000000 9' b111 ;' b0 -' 15 @@ -539355,22 +539352,27 @@ b111 -' #1285137500 05 #1285143750 +07 b110 ;' b0 -' 15 #1285150000 05 #1285156250 +bx0 \& b1 -' 15 #1285162500 05 #1285168750 +bx00 \& b10 -' 15 #1285175000 05 #1285181250 +0W& +b0 \& b11 -' 15 #1285187500 @@ -539424,7 +539426,7 @@ b11 -' #1285293750 0T& b10 Y& -b1xx ^& +b1x0 ^& 1_& b100 -' 15 @@ -539494,27 +539496,22 @@ b111 -' #1285437500 05 #1285443750 -07 b101 ;' b0 -' 15 #1285450000 05 #1285456250 -bx0 \& b1 -' 15 #1285462500 05 #1285468750 -bx00 \& b10 -' 15 #1285475000 05 #1285481250 -0W& -b0 \& b11 -' 15 #1285487500 @@ -539568,7 +539565,7 @@ b11 -' #1285593750 0T& b11 Y& -b1xx0 ^& +b1x00 ^& 1_& b100 -' 15 @@ -539707,7 +539704,7 @@ b11 -' #1285893750 0T& b100 Y& -b1xx00 ^& +b1x000 ^& 1_& b100 -' 15 @@ -539846,7 +539843,7 @@ b11 -' #1286193750 0T& b101 Y& -b1xx000 ^& +b1x0000 ^& 1_& b100 -' 15 @@ -539985,7 +539982,7 @@ b11 -' #1286493750 0T& b110 Y& -b1xx0000 ^& +b1x00000 ^& 1_& b100 -' 15 @@ -540124,7 +540121,7 @@ b11 -' #1286793750 0T& b111 Y& -b1xx00000 ^& +b1x000000 ^& 1_& b100 -' 15 @@ -540263,11 +540260,11 @@ b11 -' #1287093750 0T& 1\ -bx000000 ] -bx000000 k% -bx000000 ]& +bx0000000 ] +bx0000000 k% +bx0000000 ]& b0 Y& -bx000000 ^& +bx0000000 ^& 1_& b100 -' 15 @@ -540276,7 +540273,7 @@ b100 -' #1287106250 0\ b1 9& -b0xx000000 5& +b0x0000000 5& b101 -' 15 #1287112500 @@ -540412,7 +540409,7 @@ b11 -' #1287393750 0T& b1 Y& -bx0000000 ^& +b0 ^& 1_& b100 -' 15 @@ -540551,7 +540548,6 @@ b11 -' #1287693750 0T& b10 Y& -b0 ^& 1_& b100 -' 15 @@ -541398,7 +541394,7 @@ b100 -' #1289506250 0\ b10 9& -b0xx00000000000001 5& +b0x000000000000001 5& b101 -' 15 #1289512500 @@ -542530,7 +542526,7 @@ b1011 I& b100000000 C b100000000 N& b0 9& -bx0000000000000100000000 5& +bx00000000000000100000000 5& b101 -' 15 #1291912500 @@ -545206,7 +545202,7 @@ b111 -' 05 #1297643750 x7 -bx000000 9' +bx0000000 9' b111 ;' b0 -' 15 @@ -545350,22 +545346,27 @@ b111 -' #1297937500 05 #1297943750 +07 b110 ;' b0 -' 15 #1297950000 05 #1297956250 +bx0 \& b1 -' 15 #1297962500 05 #1297968750 +bx00 \& b10 -' 15 #1297975000 05 #1297981250 +0W& +b0 \& b11 -' 15 #1297987500 @@ -545419,7 +545420,7 @@ b11 -' #1298093750 0T& b10 Y& -b10xx ^& +b10x0 ^& 1_& b100 -' 15 @@ -545489,27 +545490,22 @@ b111 -' #1298237500 05 #1298243750 -07 b101 ;' b0 -' 15 #1298250000 05 #1298256250 -bx0 \& b1 -' 15 #1298262500 05 #1298268750 -bx00 \& b10 -' 15 #1298275000 05 #1298281250 -0W& -b0 \& b11 -' 15 #1298287500 @@ -545563,7 +545559,7 @@ b11 -' #1298393750 0T& b11 Y& -b10xx0 ^& +b10x00 ^& 1_& b100 -' 15 @@ -545702,7 +545698,7 @@ b11 -' #1298693750 0T& b100 Y& -b10xx00 ^& +b10x000 ^& 1_& b100 -' 15 @@ -545841,7 +545837,7 @@ b11 -' #1298993750 0T& b101 Y& -b10xx000 ^& +b10x0000 ^& 1_& b100 -' 15 @@ -545980,7 +545976,7 @@ b11 -' #1299293750 0T& b110 Y& -b10xx0000 ^& +b10x00000 ^& 1_& b100 -' 15 @@ -546119,7 +546115,7 @@ b11 -' #1299593750 0T& b111 Y& -b0xx00000 ^& +b0x000000 ^& 1_& b100 -' 15 @@ -546258,11 +546254,11 @@ b11 -' #1299893750 0T& 1\ -bx000000 ] -bx000000 k% -bx000000 ]& +bx0000000 ] +bx0000000 k% +bx0000000 ]& b0 Y& -bx000000 ^& +bx0000000 ^& 1_& b100 -' 15 @@ -546271,7 +546267,7 @@ b100 -' #1299906250 0\ b1 9& -b0xx000000 5& +b0x0000000 5& b101 -' 15 #1299912500 @@ -546407,7 +546403,7 @@ b11 -' #1300193750 0T& b1 Y& -bx0000000 ^& +b0 ^& 1_& b100 -' 15 @@ -546546,7 +546542,6 @@ b11 -' #1300493750 0T& b10 Y& -b0 ^& 1_& b100 -' 15 @@ -547399,7 +547394,7 @@ b100 -' #1302306250 0\ b10 9& -b0xx00000000000010 5& +b0x000000000000010 5& b101 -' 15 #1302312500 @@ -548525,7 +548520,7 @@ b1011 I& b1000000000 *" b1000000000 6& b0 9& -bx0000000000001000000000 5& +bx00000000000001000000000 5& b101 -' 15 #1304712500 @@ -573483,7 +573478,7 @@ b100111 -' 05 #1345593750 x7 -bx000000 9' +bx0000000 9' b0 7' b111 ;' b0 -' @@ -574108,22 +574103,27 @@ b100111 -' #1347087500 05 #1347093750 +07 b110 ;' b0 -' 15 #1347100000 05 #1347106250 +bx0 \& b1 -' 15 #1347112500 05 #1347118750 +bx00 \& b10 -' 15 #1347125000 05 #1347131250 +0W& +b0 \& b11 -' 15 #1347137500 @@ -574337,7 +574337,7 @@ b11 -' #1347643750 0T& b10 Y& -b1xx ^& +b1x0 ^& 1_& b100 -' 15 @@ -574727,27 +574727,22 @@ b100111 -' #1348587500 05 #1348593750 -07 b101 ;' b0 -' 15 #1348600000 05 #1348606250 -bx0 \& b1 -' 15 #1348612500 05 #1348618750 -bx00 \& b10 -' 15 #1348625000 05 #1348631250 -0W& -b0 \& b11 -' 15 #1348637500 @@ -574961,7 +574956,7 @@ b11 -' #1349143750 0T& b11 Y& -b1xx0 ^& +b1x00 ^& 1_& b100 -' 15 @@ -575580,7 +575575,7 @@ b11 -' #1350643750 0T& b100 Y& -b1xx00 ^& +b1x000 ^& 1_& b100 -' 15 @@ -576199,7 +576194,7 @@ b11 -' #1352143750 0T& b101 Y& -b1xx000 ^& +b1x0000 ^& 1_& b100 -' 15 @@ -576818,7 +576813,7 @@ b11 -' #1353643750 0T& b110 Y& -b1xx0000 ^& +b1x00000 ^& 1_& b100 -' 15 @@ -577437,7 +577432,7 @@ b11 -' #1355143750 0T& b111 Y& -b1xx00000 ^& +b1x000000 ^& 1_& b100 -' 15 @@ -578056,11 +578051,11 @@ b11 -' #1356643750 0T& 1\ -bx000000 ] -bx000000 k% -bx000000 ]& +bx0000000 ] +bx0000000 k% +bx0000000 ]& b0 Y& -bx000000 ^& +bx0000000 ^& 1_& b100 -' 15 @@ -578069,7 +578064,7 @@ b100 -' #1356656250 0\ b1 9& -b0xx000000 5& +b0x0000000 5& b101 -' 15 #1356662500 @@ -578685,7 +578680,7 @@ b11 -' #1358143750 0T& b1 Y& -bx0000000 ^& +b0 ^& 1_& b100 -' 15 @@ -579304,7 +579299,6 @@ b11 -' #1359643750 0T& b10 Y& -b0 ^& 1_& b100 -' 15 @@ -583031,7 +583025,7 @@ b100 -' #1368656250 0\ b10 9& -b0xx00000000000001 5& +b0x000000000000001 5& b101 -' 15 #1368662500 @@ -588001,7 +587995,7 @@ b11 I& b0 <& b100000000 :& b0 9& -bx0000000000000100000000 5& +bx00000000000000100000000 5& b101 -' 15 #1380662500 @@ -785628,7 +785622,7 @@ b100111 -' 05 #1831943750 x7 -bx000000 9' +bx0000000 9' b0 7' b111 ;' b0 -' @@ -786253,22 +786247,27 @@ b100111 -' #1833437500 05 #1833443750 +07 b110 ;' b0 -' 15 #1833450000 05 #1833456250 +bx0 \& b1 -' 15 #1833462500 05 #1833468750 +bx00 \& b10 -' 15 #1833475000 05 #1833481250 +0W& +b0 \& b11 -' 15 #1833487500 @@ -786482,7 +786481,7 @@ b11 -' #1833993750 0T& b10 Y& -b1xx ^& +b1x0 ^& 1_& b100 -' 15 @@ -786872,27 +786871,22 @@ b100111 -' #1834937500 05 #1834943750 -07 b101 ;' b0 -' 15 #1834950000 05 #1834956250 -bx0 \& b1 -' 15 #1834962500 05 #1834968750 -bx00 \& b10 -' 15 #1834975000 05 #1834981250 -0W& -b0 \& b11 -' 15 #1834987500 @@ -787106,7 +787100,7 @@ b11 -' #1835493750 0T& b11 Y& -b1xx0 ^& +b1x00 ^& 1_& b100 -' 15 @@ -787725,7 +787719,7 @@ b11 -' #1836993750 0T& b100 Y& -b1xx00 ^& +b1x000 ^& 1_& b100 -' 15 @@ -788344,7 +788338,7 @@ b11 -' #1838493750 0T& b101 Y& -b1xx000 ^& +b1x0000 ^& 1_& b100 -' 15 @@ -788963,7 +788957,7 @@ b11 -' #1839993750 0T& b110 Y& -b1xx0000 ^& +b1x00000 ^& 1_& b100 -' 15 @@ -789582,7 +789576,7 @@ b11 -' #1841493750 0T& b111 Y& -b1xx00000 ^& +b1x000000 ^& 1_& b100 -' 15 @@ -790201,11 +790195,11 @@ b11 -' #1842993750 0T& 1\ -bx000000 ] -bx000000 k% -bx000000 ]& +bx0000000 ] +bx0000000 k% +bx0000000 ]& b0 Y& -bx000000 ^& +bx0000000 ^& 1_& b100 -' 15 @@ -790214,7 +790208,7 @@ b100 -' #1843006250 0\ b1 9& -b0xx000000 5& +b0x0000000 5& b101 -' 15 #1843012500 @@ -790830,7 +790824,7 @@ b11 -' #1844493750 0T& b1 Y& -bx0000000 ^& +b0 ^& 1_& b100 -' 15 @@ -791449,7 +791443,6 @@ b11 -' #1845993750 0T& b10 Y& -b0 ^& 1_& b100 -' 15 @@ -795176,7 +795169,7 @@ b100 -' #1855006250 0\ b10 9& -b0xx00000000000001 5& +b0x000000000000001 5& b101 -' 15 #1855012500 @@ -800146,7 +800139,7 @@ b11 I& b0 <& b100000000 :& b0 9& -bx0000000000000100000000 5& +bx00000000000000100000000 5& b101 -' 15 #1867012500 diff --git a/sim/spi_neuron_top_runnetwork.vcd b/sim/spi_neuron_top_runnetwork.vcd index 51c1c67..1e15177 100644 --- a/sim/spi_neuron_top_runnetwork.vcd +++ b/sim/spi_neuron_top_runnetwork.vcd @@ -1,5 +1,5 @@ $date - Wed Sep 2 20:13:40 2026 + Wed Sep 2 20:58:18 2026 $end $version Icarus Verilog @@ -15,14 +15,14 @@ $var wire 1 $ psram_ub_n $end $var wire 1 % psram_oe_n $end $var wire 1 & psram_lb_n $end $var wire 1 ' psram_ce_n $end -$var wire 22 ( psram_a [21:0] $end +$var wire 23 ( psram_a [22:0] $end $var wire 1 ) miso $end $var parameter 32 * ACC_WIDTH $end $var parameter 32 + ADDR_WIDTH $end -$var parameter 22 , BIAS0_ADDR $end -$var parameter 22 - BIAS1_ADDR $end -$var parameter 22 . BUF_A_BASE $end -$var parameter 22 / BUF_B_BASE $end +$var parameter 23 , BIAS0_ADDR $end +$var parameter 23 - BIAS1_ADDR $end +$var parameter 23 . BUF_A_BASE $end +$var parameter 23 / BUF_B_BASE $end $var real 1 0 CLK_PERIOD $end $var parameter 32 1 DATA_WIDTH $end $var parameter 32 2 HB_RAM $end @@ -32,10 +32,10 @@ $var parameter 32 5 N_INPUTS $end $var parameter 32 6 N_LAYERS $end $var parameter 32 7 N_NEURONS $end $var parameter 32 8 PARALLEL $end -$var parameter 22 9 TABLE_BASE $end -$var parameter 22 : W0_BASE $end -$var parameter 22 ; W1_BASE $end -$var parameter 22 < X_BASE $end +$var parameter 23 9 TABLE_BASE $end +$var parameter 23 : W0_BASE $end +$var parameter 23 ; W1_BASE $end +$var parameter 23 < X_BASE $end $var reg 1 = clk $end $var reg 1 > cs_n $end $var reg 1 ? mosi $end @@ -54,29 +54,29 @@ $var wire 16 G psram_dq [15:0] $end $var wire 1 @ rst $end $var wire 1 B sclk $end $var wire 32 H y_bus [31:0] $end -$var wire 22 I x_base [21:0] $end -$var wire 22 J w_base [21:0] $end +$var wire 23 I x_base [22:0] $end +$var wire 23 J w_base [22:0] $end $var wire 1 K tx_byte_req $end $var wire 8 L tx_byte [7:0] $end -$var wire 22 M table_base [21:0] $end +$var wire 23 M table_base [22:0] $end $var wire 1 N spi_ram_wr $end $var wire 8 O spi_ram_wdata [7:0] $end $var wire 1 P spi_ram_req $end $var wire 1 Q spi_ram_ready $end $var wire 8 R spi_ram_rdata [7:0] $end -$var wire 22 S spi_ram_addr [21:0] $end +$var wire 23 S spi_ram_addr [22:0] $end $var wire 1 T seq_ram_wr $end $var wire 8 U seq_ram_wdata [7:0] $end $var wire 1 V seq_ram_req $end $var wire 1 W seq_ram_ready $end $var wire 8 X seq_ram_rdata [7:0] $end -$var wire 22 Y seq_ram_addr [21:0] $end -$var wire 22 Z seq_nm_x_base [21:0] $end -$var wire 22 [ seq_nm_w_base [21:0] $end +$var wire 23 Y seq_ram_addr [22:0] $end +$var wire 23 Z seq_nm_x_base [22:0] $end +$var wire 23 [ seq_nm_w_base [22:0] $end $var wire 1 \ seq_nm_start $end $var wire 16 ] seq_nm_n_neurons [15:0] $end $var wire 16 ^ seq_nm_n_inputs [15:0] $end -$var wire 22 _ seq_nm_bias_addr [21:0] $end +$var wire 23 _ seq_nm_bias_addr [22:0] $end $var wire 2 ` seq_nm_activation [1:0] $end $var wire 1 a seq_done $end $var wire 1 b seq_busy $end @@ -95,10 +95,10 @@ $var wire 1 j psram_mem_req $end $var wire 1 k psram_mem_ready $end $var wire 16 l psram_mem_rdata [15:0] $end $var wire 1 m psram_mem_lb_n $end -$var wire 22 n psram_mem_addr [21:0] $end +$var wire 23 n psram_mem_addr [22:0] $end $var wire 1 & psram_lb_n $end $var wire 1 ' psram_ce_n $end -$var wire 22 o psram_a [21:0] $end +$var wire 23 o psram_a [22:0] $end $var wire 1 p nm_start $end $var wire 1 q nm_soft_rst $end $var wire 1 r nm_ram_wr $end @@ -106,17 +106,17 @@ $var wire 8 s nm_ram_wdata [7:0] $end $var wire 1 t nm_ram_req $end $var wire 1 u nm_ram_ready $end $var wire 8 v nm_ram_rdata [7:0] $end -$var wire 22 w nm_ram_addr [21:0] $end +$var wire 23 w nm_ram_addr [22:0] $end $var wire 1 x nm_done $end $var wire 1 y nm_busy $end $var wire 16 z n_neurons_real [15:0] $end $var wire 16 { n_inputs_real [15:0] $end -$var wire 22 | mux_nm_x_base [21:0] $end -$var wire 22 } mux_nm_w_base [21:0] $end +$var wire 23 | mux_nm_x_base [22:0] $end +$var wire 23 } mux_nm_w_base [22:0] $end $var wire 1 ~ mux_nm_start $end $var wire 16 !" mux_nm_n_neurons [15:0] $end $var wire 16 "" mux_nm_n_inputs [15:0] $end -$var wire 22 #" mux_nm_bias_addr [21:0] $end +$var wire 23 #" mux_nm_bias_addr [22:0] $end $var wire 2 $" mux_nm_activation [1:0] $end $var wire 1 ) miso $end $var wire 1 %" i8_mem_wr $end @@ -126,18 +126,18 @@ $var wire 1 (" i8_mem_req $end $var wire 1 )" i8_mem_ready $end $var wire 16 *" i8_mem_rdata [15:0] $end $var wire 1 +" i8_mem_lb_n $end -$var wire 22 ," i8_mem_addr [21:0] $end +$var wire 23 ," i8_mem_addr [22:0] $end $var wire 1 -" cs_start $end $var wire 1 ." cs_end $end -$var wire 22 /" buf_b_base [21:0] $end -$var wire 22 0" buf_a_base [21:0] $end -$var wire 22 1" bias_addr [21:0] $end +$var wire 23 /" buf_b_base [22:0] $end +$var wire 23 0" buf_a_base [22:0] $end +$var wire 23 1" bias_addr [22:0] $end $var wire 1 2" arb_wr $end $var wire 8 3" arb_wdata [7:0] $end $var wire 1 4" arb_req $end $var wire 1 5" arb_ready $end $var wire 8 6" arb_rdata [7:0] $end -$var wire 22 7" arb_addr [21:0] $end +$var wire 23 7" arb_addr [22:0] $end $var wire 2 8" activation [1:0] $end $var parameter 32 9" ACC_WIDTH $end $var parameter 32 :" ADDR_WIDTH $end @@ -156,15 +156,15 @@ $var wire 8 B" m_rdata [7:0] $end $var wire 1 T c_wr $end $var wire 8 C" c_wdata [7:0] $end $var wire 1 V c_req $end -$var wire 22 D" c_addr [21:0] $end +$var wire 23 D" c_addr [22:0] $end $var wire 1 r b_wr $end $var wire 8 E" b_wdata [7:0] $end $var wire 1 t b_req $end -$var wire 22 F" b_addr [21:0] $end +$var wire 23 F" b_addr [22:0] $end $var wire 1 N a_wr $end $var wire 8 G" a_wdata [7:0] $end $var wire 1 P a_req $end -$var wire 22 H" a_addr [21:0] $end +$var wire 23 H" a_addr [22:0] $end $var parameter 32 I" ADDR_WIDTH $end $var parameter 2 J" SEL_A $end $var parameter 2 K" SEL_B $end @@ -176,14 +176,14 @@ $var reg 8 O" b_rdata [7:0] $end $var reg 1 u b_ready $end $var reg 8 P" c_rdata [7:0] $end $var reg 1 W c_ready $end -$var reg 22 Q" m_addr [21:0] $end +$var reg 23 Q" m_addr [22:0] $end $var reg 1 4" m_req $end $var reg 8 R" m_wdata [7:0] $end $var reg 1 2" m_wr $end $var reg 2 S" owner [1:0] $end $upscope $end $scope module u_int8_access $end -$var wire 22 T" addr [21:0] $end +$var wire 23 T" addr [22:0] $end $var wire 1 = clk $end $var wire 1 4" req $end $var wire 1 @ rst $end @@ -194,8 +194,8 @@ $var wire 16 V" mem_rdata [15:0] $end $var parameter 32 W" ADDR_WIDTH $end $var parameter 2 X" STATE_IDLE $end $var parameter 2 Y" STATE_WAIT $end -$var reg 22 Z" addr_reg [21:0] $end -$var reg 22 [" mem_addr [21:0] $end +$var reg 23 Z" addr_reg [22:0] $end +$var reg 23 [" mem_addr [22:0] $end $var reg 1 +" mem_lb_n $end $var reg 1 (" mem_req $end $var reg 1 '" mem_ub_n $end @@ -211,14 +211,14 @@ $var wire 8 _" ram_rdata [7:0] $end $var wire 1 W ram_ready $end $var wire 1 @ rst $end $var wire 32 `" y_bus [31:0] $end -$var wire 22 a" x_base [21:0] $end -$var wire 22 b" table_base [21:0] $end +$var wire 23 a" x_base [22:0] $end +$var wire 23 b" table_base [22:0] $end $var wire 1 e run_start $end $var wire 8 c" run_num_layers [7:0] $end $var wire 1 x nm_done $end $var wire 1 y nm_busy $end -$var wire 22 d" buf_b_base [21:0] $end -$var wire 22 e" buf_a_base [21:0] $end +$var wire 23 d" buf_b_base [22:0] $end +$var wire 23 e" buf_a_base [22:0] $end $var parameter 32 f" ADDR_WIDTH $end $var parameter 32 g" DATA_WIDTH $end $var parameter 32 h" N_LAYERS $end @@ -235,19 +235,19 @@ $var reg 24 r" bias_addr_acc [23:0] $end $var reg 3 s" copy_idx [2:0] $end $var reg 1 t" cur_sel $end $var reg 4 u" desc_byte_idx [3:0] $end -$var reg 22 v" desc_table_addr [21:0] $end +$var reg 23 v" desc_table_addr [22:0] $end $var reg 8 w" layer_idx [7:0] $end $var reg 16 x" n_inputs_acc [15:0] $end $var reg 16 y" n_neurons_acc [15:0] $end $var reg 2 z" nm_activation [1:0] $end -$var reg 22 {" nm_bias_addr [21:0] $end +$var reg 23 {" nm_bias_addr [22:0] $end $var reg 16 |" nm_n_inputs [15:0] $end $var reg 16 }" nm_n_neurons [15:0] $end $var reg 1 \ nm_start $end -$var reg 22 ~" nm_w_base [21:0] $end -$var reg 22 !# nm_x_base [21:0] $end +$var reg 23 ~" nm_w_base [22:0] $end +$var reg 23 !# nm_x_base [22:0] $end $var reg 8 "# num_layers_reg [7:0] $end -$var reg 22 ## ram_addr [21:0] $end +$var reg 23 ## ram_addr [22:0] $end $var reg 1 V ram_req $end $var reg 8 $# ram_wdata [7:0] $end $var reg 1 T ram_wr $end @@ -258,7 +258,7 @@ $var reg 24 &# w_base_acc [23:0] $end $var reg 1 '# write_sel $end $upscope $end $scope module u_memory_if $end -$var wire 22 (# addr [21:0] $end +$var wire 23 (# addr [22:0] $end $var wire 1 = clk $end $var wire 1 +" lb_n $end $var wire 1 (" req $end @@ -272,7 +272,7 @@ $var parameter 32 +# ADDR_WIDTH $end $var parameter 32 ,# DATA_WIDTH $end $var parameter 2 -# STATE_IDLE $end $var parameter 2 .# STATE_WAIT $end -$var reg 22 /# mem_addr [21:0] $end +$var reg 23 /# mem_addr [22:0] $end $var reg 1 m mem_lb_n $end $var reg 1 j mem_req $end $var reg 1 i mem_ub_n $end @@ -284,9 +284,9 @@ $var reg 2 2# state [1:0] $end $upscope $end $scope module u_neuron_memory $end $var wire 2 3# activation [1:0] $end -$var wire 22 4# bias_addr [21:0] $end +$var wire 23 4# bias_addr [22:0] $end $var wire 1 = clk $end -$var wire 22 5# mem_addr [21:0] $end +$var wire 23 5# mem_addr [22:0] $end $var wire 8 6# mem_rdata [7:0] $end $var wire 1 u mem_ready $end $var wire 1 t mem_req $end @@ -296,8 +296,8 @@ $var wire 16 8# n_inputs_real [15:0] $end $var wire 16 9# n_neurons_real [15:0] $end $var wire 1 F rst $end $var wire 1 ~ start $end -$var wire 22 :# w_base [21:0] $end -$var wire 22 ;# x_base [21:0] $end +$var wire 23 :# w_base [22:0] $end +$var wire 23 ;# x_base [22:0] $end $var wire 32 <# y_bus [31:0] $end $var wire 32 =# x_bus [31:0] $end $var wire 32 ># w_bus [31:0] $end @@ -312,7 +312,7 @@ $var wire 1 F# access_mem_ub_n $end $var wire 1 G# access_mem_req $end $var wire 16 H# access_mem_rdata [15:0] $end $var wire 1 I# access_mem_lb_n $end -$var wire 22 J# access_mem_addr [21:0] $end +$var wire 23 J# access_mem_addr [22:0] $end $var parameter 32 K# ACC_WIDTH $end $var parameter 32 L# ADDR_WIDTH $end $var parameter 32 M# DATA_WIDTH $end @@ -326,11 +326,11 @@ $var parameter 4 T# STATE_READ_W $end $var parameter 4 U# STATE_READ_X $end $var parameter 4 V# STATE_START_N $end $var parameter 4 W# STATE_WAIT_N $end -$var reg 22 X# access_addr [21:0] $end +$var reg 23 X# access_addr [22:0] $end $var reg 1 Y# access_req $end $var reg 8 Z# access_wdata [7:0] $end $var reg 1 [# access_wr $end -$var reg 22 \# bias_group_addr [21:0] $end +$var reg 23 \# bias_group_addr [22:0] $end $var reg 8 ]# bias_reg [7:0] $end $var reg 1 y busy $end $var reg 1 x done $end @@ -338,7 +338,7 @@ $var reg 3 ^# index [2:0] $end $var reg 2 _# neuron_index [1:0] $end $var reg 1 `# neuron_start $end $var reg 4 a# state [3:0] $end -$var reg 22 b# w_group_base [21:0] $end +$var reg 23 b# w_group_base [22:0] $end $var integer 32 c# rst_i [31:0] $end $scope begin GEN_BUS[0] $end $var parameter 2 d# i $end @@ -365,7 +365,7 @@ $scope begin GEN_Y_BUS[3] $end $var parameter 3 k# j $end $upscope $end $scope module u_mem $end -$var wire 22 l# addr [21:0] $end +$var wire 23 l# addr [22:0] $end $var wire 1 = clk $end $var wire 16 m# mem_rdata [15:0] $end $var wire 1 u mem_ready $end @@ -376,8 +376,8 @@ $var wire 1 [# wr $end $var parameter 32 o# ADDR_WIDTH $end $var parameter 2 p# STATE_IDLE $end $var parameter 2 q# STATE_WAIT $end -$var reg 22 r# addr_reg [21:0] $end -$var reg 22 s# mem_addr [21:0] $end +$var reg 23 r# addr_reg [22:0] $end +$var reg 23 s# mem_addr [22:0] $end $var reg 1 I# mem_lb_n $end $var reg 1 G# mem_req $end $var reg 1 F# mem_ub_n $end @@ -469,7 +469,7 @@ $upscope $end $upscope $end $scope module u_psram_ctrl $end $var wire 1 = clk $end -$var wire 22 O$ mem_addr [21:0] $end +$var wire 23 O$ mem_addr [22:0] $end $var wire 1 m mem_lb_n $end $var wire 1 j mem_req $end $var wire 1 i mem_ub_n $end @@ -488,14 +488,14 @@ $var parameter 3 Y$ STATE_INIT $end $var parameter 3 Z$ STATE_READ $end $var parameter 3 [$ STATE_WRITE $end $var parameter 3 \$ STATE_WRITE_WAIT $end -$var reg 22 ]$ address_reg [21:0] $end +$var reg 23 ]$ address_reg [22:0] $end $var reg 14 ^$ counter [13:0] $end $var reg 1 _$ dq_oe $end $var reg 16 `$ dq_out [15:0] $end $var reg 1 a$ lb_reg $end $var reg 16 b$ mem_rdata [15:0] $end $var reg 1 k mem_ready $end -$var reg 22 c$ psram_a [21:0] $end +$var reg 23 c$ psram_a [22:0] $end $var reg 1 ' psram_ce_n $end $var reg 1 & psram_lb_n $end $var reg 1 % psram_oe_n $end @@ -565,11 +565,11 @@ $var parameter 4 4% ST_WRITE_ISSUE $end $var parameter 4 5% ST_WRITE_WAIT $end $var reg 2 6% activation [1:0] $end $var reg 24 7% addr_acc [23:0] $end -$var reg 22 8% bias_addr [21:0] $end -$var reg 22 9% buf_a_base [21:0] $end -$var reg 22 :% buf_b_base [21:0] $end +$var reg 23 8% bias_addr [22:0] $end +$var reg 23 9% buf_a_base [22:0] $end +$var reg 23 :% buf_b_base [22:0] $end $var reg 2 ;% byte_pos [1:0] $end -$var reg 22 <% cur_addr [21:0] $end +$var reg 23 <% cur_addr [22:0] $end $var reg 8 =% cur_read_byte [7:0] $end $var reg 16 >% len_acc [15:0] $end $var reg 16 ?% len_remaining [15:0] $end @@ -581,7 +581,7 @@ $var reg 1 p nm_start $end $var reg 8 C% opcode [7:0] $end $var reg 8 D% pending_wdata [7:0] $end $var reg 1 E% pending_write $end -$var reg 22 F% ram_addr [21:0] $end +$var reg 23 F% ram_addr [22:0] $end $var reg 1 P ram_req $end $var reg 8 G% ram_wdata [7:0] $end $var reg 1 N ram_wr $end @@ -592,10 +592,10 @@ $var reg 1 e run_start $end $var reg 4 K% state [3:0] $end $var reg 1 L% status_done_sticky $end $var reg 8 M% status_snapshot [7:0] $end -$var reg 22 N% table_base [21:0] $end +$var reg 23 N% table_base [22:0] $end $var reg 8 O% tx_byte_comb [7:0] $end -$var reg 22 P% w_base [21:0] $end -$var reg 22 Q% x_base [21:0] $end +$var reg 23 P% w_base [22:0] $end +$var reg 23 Q% x_base [22:0] $end $upscope $end $scope module u_spi_slave $end $var wire 1 = clk $end @@ -629,7 +629,7 @@ $var reg 8 c% tx_shift [7:0] $end $upscope $end $upscope $end $scope module u_psram $end -$var wire 22 d% a [21:0] $end +$var wire 23 d% a [22:0] $end $var wire 1 ' ce_n $end $var wire 1 = clk $end $var wire 16 e% dq [15:0] $end @@ -656,7 +656,7 @@ $var real 1 t% TWC_NS $end $var real 1 u% TWPH_NS $end $var real 1 v% TWP_NS $end $var real 1 w% TWR_NS $end -$var reg 22 x% active_addr [21:0] $end +$var reg 23 x% active_addr [22:0] $end $var reg 16 y% active_wdata [15:0] $end $var reg 1 z% dq_oe $end $var reg 16 {% dq_out [15:0] $end @@ -702,7 +702,7 @@ $var integer 32 6& k [31:0] $end $var integer 32 7& n [31:0] $end $upscope $end $scope task read_ram_bytes $end -$var reg 22 8& addr [21:0] $end +$var reg 23 8& addr [22:0] $end $var integer 32 9& k [31:0] $end $var integer 32 :& len [31:0] $end $upscope $end @@ -716,7 +716,7 @@ $scope task run_network $end $var reg 8 =& num_layers [7:0] $end $upscope $end $scope task set_base $end -$var reg 22 >& addr [21:0] $end +$var reg 23 >& addr [22:0] $end $var reg 8 ?& sel [7:0] $end $upscope $end $scope task spi_begin $end @@ -736,7 +736,7 @@ $scope task wait_done $end $var reg 8 G& status [7:0] $end $upscope $end $scope task write_ram_bytes $end -$var reg 22 H& addr [21:0] $end +$var reg 23 H& addr [22:0] $end $var integer 32 I& k [31:0] $end $var integer 32 J& len [31:0] $end $upscope $end @@ -761,7 +761,7 @@ r70 j% r70 i% b100000000000000 h% b10000 g% -b10110 f% +b10111 f% b110 5% b101 4% b100 3% @@ -798,7 +798,7 @@ b0 s$ b100 r$ b100 q$ b1000 p$ -b10110 o$ +b10111 o$ b100 \$ b11 [$ b10 Z$ @@ -808,7 +808,7 @@ b10111011100000 W$ b10000 V$ b1110 U$ b1010000 T$ -b10110 S$ +b10111 S$ b110 R$ b0 N$ b0 M$ @@ -836,7 +836,7 @@ b0 %$ b100000 $$ b1 q# b0 p# -b10110 o# +b10111 o# b11 k# b10 j# b1 i# @@ -856,12 +856,12 @@ b100 P# b100 O# b10 N# b1000 M# -b10110 L# +b10111 L# b100000 K# b1 .# b0 -# b10000 ,# -b10110 +# +b10111 +# b100 p" b11 o" b10 n" @@ -872,15 +872,15 @@ b101 j" b100 i" b100 h" b1000 g" -b10110 f" +b10111 f" b1 Y" b0 X" -b10110 W" +b10111 W" b0 M" b11 L" b10 K" b1 J" -b10110 I" +b10111 I" b10 A" b100 @" b100 ?" @@ -888,7 +888,7 @@ b100 >" b10000 =" b1000 <" b1010000 ;" -b10110 :" +b10111 :" b100000 9" b0 < b1000000000 ; @@ -907,7 +907,7 @@ b1100010000 / b1100000000 . b1000100000 - b100100000 , -b10110 + +b10111 + b100000 * $end #0 @@ -68825,7 +68825,7 @@ b100111 4& 0= #167243750 x? -bx000000 D& +bx0000000 D& b111 F& b0 4& 1= @@ -69449,22 +69449,27 @@ b100111 4& #168737500 0= #168743750 +0? b110 F& b0 4& 1= #168750000 0= #168756250 +bx0 ^% b1 4& 1= #168762500 0= #168768750 +bx00 ^% b10 4& 1= #168775000 0= #168781250 +0Y% +b0 ^% b11 4& 1= #168787500 @@ -69678,7 +69683,7 @@ b11 4& #169293750 0V% b10 [% -b1xx `% +b1x0 `% 1a% b100 4& 1= @@ -70068,27 +70073,22 @@ b100111 4& #170237500 0= #170243750 -0? b101 F& b0 4& 1= #170250000 0= #170256250 -bx0 ^% b1 4& 1= #170262500 0= #170268750 -bx00 ^% b10 4& 1= #170275000 0= #170281250 -0Y% -b0 ^% b11 4& 1= #170287500 @@ -70302,7 +70302,7 @@ b11 4& #170793750 0V% b11 [% -b1xx0 `% +b1x00 `% 1a% b100 4& 1= @@ -70921,7 +70921,7 @@ b11 4& #172293750 0V% b100 [% -b1xx00 `% +b1x000 `% 1a% b100 4& 1= @@ -71540,7 +71540,7 @@ b11 4& #173793750 0V% b101 [% -b1xx000 `% +b1x0000 `% 1a% b100 4& 1= @@ -72159,7 +72159,7 @@ b11 4& #175293750 0V% b110 [% -b1xx0000 `% +b1x00000 `% 1a% b100 4& 1= @@ -72778,7 +72778,7 @@ b11 4& #176793750 0V% b111 [% -b1xx00000 `% +b1x000000 `% 1a% b100 4& 1= @@ -73397,11 +73397,11 @@ b11 4& #178293750 0V% 1c -bx000000 d -bx000000 m$ -bx000000 _% +bx0000000 d +bx0000000 m$ +bx0000000 _% b0 [% -bx000000 `% +bx0000000 `% 1a% b100 4& 1= @@ -73410,7 +73410,7 @@ b100 4& #178306250 0c b1 ;% -b0xx000000 7% +b0x0000000 7% b101 4& 1= #178312500 @@ -74026,7 +74026,7 @@ b11 4& #179793750 0V% b1 [% -bx0000000 `% +b0 `% 1a% b100 4& 1= @@ -74645,7 +74645,6 @@ b11 4& #181293750 0V% b10 [% -b0 `% 1a% b100 4& 1= @@ -78366,7 +78365,7 @@ b100 4& #190306250 0c b10 ;% -b0xx00000000000000 7% +b0x000000000000000 7% b101 4& 1= #190312500 @@ -83317,7 +83316,7 @@ b100 4& 0c b11 K% b0 ;% -bx0000000000000000000000 7% +bx00000000000000000000000 7% b101 4& 1= #202312500 @@ -120469,7 +120468,7 @@ b100111 4& 0= #291243750 x? -bx000000 D& +bx0000000 D& b111 F& b0 4& 1= @@ -121093,22 +121092,27 @@ b100111 4& #292737500 0= #292743750 +0? b110 F& b0 4& 1= #292750000 0= #292756250 +bx0 ^% b1 4& 1= #292762500 0= #292768750 +bx00 ^% b10 4& 1= #292775000 0= #292781250 +0Y% +b0 ^% b11 4& 1= #292787500 @@ -121322,7 +121326,7 @@ b11 4& #293293750 0V% b10 [% -b1xx `% +b1x0 `% 1a% b100 4& 1= @@ -121712,27 +121716,22 @@ b100111 4& #294237500 0= #294243750 -0? b101 F& b0 4& 1= #294250000 0= #294256250 -bx0 ^% b1 4& 1= #294262500 0= #294268750 -bx00 ^% b10 4& 1= #294275000 0= #294281250 -0Y% -b0 ^% b11 4& 1= #294287500 @@ -121946,7 +121945,7 @@ b11 4& #294793750 0V% b11 [% -b1xx0 `% +b1x00 `% 1a% b100 4& 1= @@ -122565,7 +122564,7 @@ b11 4& #296293750 0V% b100 [% -b1xx00 `% +b1x000 `% 1a% b100 4& 1= @@ -123184,7 +123183,7 @@ b11 4& #297793750 0V% b101 [% -b1xx000 `% +b1x0000 `% 1a% b100 4& 1= @@ -123803,7 +123802,7 @@ b11 4& #299293750 0V% b110 [% -b1xx0000 `% +b1x00000 `% 1a% b100 4& 1= @@ -124422,7 +124421,7 @@ b11 4& #300793750 0V% b111 [% -b1xx00000 `% +b1x000000 `% 1a% b100 4& 1= @@ -125041,11 +125040,11 @@ b11 4& #302293750 0V% 1c -bx000000 d -bx000000 m$ -bx000000 _% +bx0000000 d +bx0000000 m$ +bx0000000 _% b0 [% -bx000000 `% +bx0000000 `% 1a% b100 4& 1= @@ -125054,7 +125053,7 @@ b100 4& #302306250 0c b1 ;% -b0xx000000 7% +b0x0000000 7% b101 4& 1= #302312500 @@ -125670,7 +125669,7 @@ b11 4& #303793750 0V% b1 [% -bx0000000 `% +b0 `% 1a% b100 4& 1= @@ -126289,7 +126288,6 @@ b11 4& #305293750 0V% b10 [% -b0 `% 1a% b100 4& 1= @@ -130010,7 +130008,7 @@ b100 4& #314306250 0c b10 ;% -b0xx00000000000000 7% +b0x000000000000000 7% b101 4& 1= #314312500 @@ -134982,7 +134980,7 @@ b11 K% b0 >% b10000 <% b0 ;% -bx0000000000000000010000 7% +bx00000000000000000010000 7% b101 4& 1= #326312500 @@ -145307,7 +145305,7 @@ b100111 4& 0= #351243750 x? -bx000000 D& +bx0000000 D& b0 I& b111 F& b0 4& @@ -145932,22 +145930,27 @@ b100111 4& #352737500 0= #352743750 +0? b110 F& b0 4& 1= #352750000 0= #352756250 +bx0 ^% b1 4& 1= #352762500 0= #352768750 +bx00 ^% b10 4& 1= #352775000 0= #352781250 +0Y% +b0 ^% b11 4& 1= #352787500 @@ -146161,7 +146164,7 @@ b11 4& #353293750 0V% b10 [% -b10110xx `% +b10110x0 `% 1a% b100 4& 1= @@ -146551,27 +146554,22 @@ b100111 4& #354237500 0= #354243750 -0? b101 F& b0 4& 1= #354250000 0= #354256250 -bx0 ^% b1 4& 1= #354262500 0= #354268750 -bx00 ^% b10 4& 1= #354275000 0= #354281250 -0Y% -b0 ^% b11 4& 1= #354287500 @@ -146785,7 +146783,7 @@ b11 4& #354793750 0V% b11 [% -b10110xx0 `% +b10110x00 `% 1a% b100 4& 1= @@ -147404,7 +147402,7 @@ b11 4& #356293750 0V% b100 [% -b110xx00 `% +b110x000 `% 1a% b100 4& 1= @@ -148023,7 +148021,7 @@ b11 4& #357793750 0V% b101 [% -b110xx000 `% +b110x0000 `% 1a% b100 4& 1= @@ -148642,7 +148640,7 @@ b11 4& #359293750 0V% b110 [% -b10xx0000 `% +b10x00000 `% 1a% b100 4& 1= @@ -149261,7 +149259,7 @@ b11 4& #360793750 0V% b111 [% -b0xx00000 `% +b0x000000 `% 1a% b100 4& 1= @@ -149880,11 +149878,11 @@ b11 4& #362293750 0V% 1c -bx000000 d -bx000000 m$ -bx000000 _% +bx0000000 d +bx0000000 m$ +bx0000000 _% b0 [% -bx000000 `% +bx0000000 `% 1a% b100 4& 1= @@ -149893,16 +149891,16 @@ b100 4& #362306250 0c b101 K% -bx000000 D% +bx0000000 D% b101 4& 1= #362312500 0= #362318750 b110 K% -bx000000 O -bx000000 G" -bx000000 G% +bx0000000 O +bx0000000 G" +bx0000000 G% b10000 S b10000 H" b10000 F% @@ -149913,9 +149911,9 @@ b110 4& 0= #362331250 0P -bx000000 3" -bx000000 R" -bx000000 U" +bx0000000 3" +bx0000000 R" +bx0000000 U" b10000 7" b10000 Q" b10000 T" @@ -149927,9 +149925,9 @@ b111 4& 0= #362343750 b1 ^" -b0xx000000 &" -b0xx000000 \" -b0xx000000 )# +b0x0000000 &" +b0x0000000 \" +b0x0000000 )# 1'" 0+" b1000 ," @@ -149948,9 +149946,9 @@ b1 2# 1j 1i 0m -b0xx000000 h -b0xx000000 0# -b0xx000000 P$ +b0x0000000 h +b0x0000000 0# +b0x0000000 P$ b1000 n b1000 /# b1000 O$ @@ -149959,12 +149957,12 @@ b1001 4& #362362500 0= #362368750 -b0xx000000 y% +b0x0000000 y% r362368.75 +& -b0xx000000 ! -b0xx000000 G -b0xx000000 Q$ -b0xx000000 e% +b0x0000000 ! +b0x0000000 G +b0x0000000 Q$ +b0x0000000 e% 1}% r362368.75 && b1000 x% @@ -149973,7 +149971,7 @@ r362368.75 "& b11 d$ 0# 1_$ -b0xx000000 `$ +b0x0000000 `$ 0' 0& b1000 ( @@ -149982,7 +149980,7 @@ b1000 c$ b1000 d% 1e$ 0a$ -b0xx000000 f$ +b0x0000000 f$ b1000 ]$ 0j b1010 4& @@ -150609,7 +150607,7 @@ b11 4& #363793750 0V% b1 [% -bx0000000 `% +b0 `% 1a% b100 4& 1= @@ -151228,7 +151226,6 @@ b11 4& #365293750 0V% b10 [% -b0 `% 1a% b100 4& 1= @@ -160496,7 +160493,7 @@ b100111 4& 0= #387243750 x? -bx000000 D& +bx0000000 D& b11 I& b111 F& b0 4& @@ -161121,22 +161118,27 @@ b100111 4& #388737500 0= #388743750 +0? b110 F& b0 4& 1= #388750000 0= #388756250 +bx0 ^% b1 4& 1= #388762500 0= #388768750 +bx00 ^% b10 4& 1= #388775000 0= #388781250 +0Y% +b0 ^% b11 4& 1= #388787500 @@ -161350,7 +161352,7 @@ b11 4& #389293750 0V% b10 [% -b0xx `% +b0x0 `% 1a% b100 4& 1= @@ -161740,27 +161742,22 @@ b100111 4& #390237500 0= #390243750 -0? b101 F& b0 4& 1= #390250000 0= #390256250 -bx0 ^% b1 4& 1= #390262500 0= #390268750 -bx00 ^% b10 4& 1= #390275000 0= #390281250 -0Y% -b0 ^% b11 4& 1= #390287500 @@ -161974,7 +161971,7 @@ b11 4& #390793750 0V% b11 [% -b0xx0 `% +b0x00 `% 1a% b100 4& 1= @@ -162593,7 +162590,7 @@ b11 4& #392293750 0V% b100 [% -b0xx00 `% +b0x000 `% 1a% b100 4& 1= @@ -163212,7 +163209,7 @@ b11 4& #393793750 0V% b101 [% -b0xx000 `% +b0x0000 `% 1a% b100 4& 1= @@ -163831,7 +163828,7 @@ b11 4& #395293750 0V% b110 [% -b0xx0000 `% +b0x00000 `% 1a% b100 4& 1= @@ -164450,7 +164447,7 @@ b11 4& #396793750 0V% b111 [% -b0xx00000 `% +b0x000000 `% 1a% b100 4& 1= @@ -165069,11 +165066,11 @@ b11 4& #398293750 0V% 1c -bx000000 d -bx000000 m$ -bx000000 _% +bx0000000 d +bx0000000 m$ +bx0000000 _% b0 [% -bx000000 `% +bx0000000 `% 1a% b100 4& 1= @@ -165082,16 +165079,16 @@ b100 4& #398306250 0c b101 K% -bx000000 D% +bx0000000 D% b101 4& 1= #398312500 0= #398318750 b110 K% -bx000000 O -bx000000 G" -bx000000 G% +bx0000000 O +bx0000000 G" +bx0000000 G% b10011 S b10011 H" b10011 F% @@ -165102,9 +165099,9 @@ b110 4& 0= #398331250 0P -bx000000 3" -bx000000 R" -bx000000 U" +bx0000000 3" +bx0000000 R" +bx0000000 U" b10011 7" b10011 Q" b10011 T" @@ -165116,9 +165113,9 @@ b111 4& 0= #398343750 b1 ^" -bx00000000000000 &" -bx00000000000000 \" -bx00000000000000 )# +bx000000000000000 &" +bx000000000000000 \" +bx000000000000000 )# 0'" 1+" 1(" @@ -165134,20 +165131,20 @@ b1 2# 1j 0i 1m -bx00000000000000 h -bx00000000000000 0# -bx00000000000000 P$ +bx000000000000000 h +bx000000000000000 0# +bx000000000000000 P$ b1001 4& 1= #398362500 0= #398368750 -bx00000000000000 y% +bx000000000000000 y% r398368.75 +& -bx00000000000000 ! -bx00000000000000 G -bx00000000000000 Q$ -bx00000000000000 e% +bx000000000000000 ! +bx000000000000000 G +bx000000000000000 Q$ +bx000000000000000 e% 1}% r398368.75 && r398368.75 ~% @@ -165155,12 +165152,12 @@ r398368.75 "& b11 d$ 0# 1_$ -bx00000000000000 `$ +bx000000000000000 `$ 0' 0$ 0e$ 1a$ -bx00000000000000 f$ +bx000000000000000 f$ 0j b1010 4& 1= @@ -165786,7 +165783,7 @@ b11 4& #399793750 0V% b1 [% -bx0000000 `% +b0 `% 1a% b100 4& 1= @@ -166405,7 +166402,6 @@ b11 4& #401293750 0V% b10 [% -b0 `% 1a% b100 4& 1= @@ -200983,7 +200979,7 @@ b100111 4& 0= #483243750 x? -bx000000 D& +bx0000000 D& b1011 I& b111 F& b0 4& @@ -201608,22 +201604,27 @@ b100111 4& #484737500 0= #484743750 +0? b110 F& b0 4& 1= #484750000 0= #484756250 +bx0 ^% b1 4& 1= #484762500 0= #484768750 +bx00 ^% b10 4& 1= #484775000 0= #484781250 +0Y% +b0 ^% b11 4& 1= #484787500 @@ -201837,7 +201838,7 @@ b11 4& #485293750 0V% b10 [% -b100xx `% +b100x0 `% 1a% b100 4& 1= @@ -202227,27 +202228,22 @@ b100111 4& #486237500 0= #486243750 -0? b101 F& b0 4& 1= #486250000 0= #486256250 -bx0 ^% b1 4& 1= #486262500 0= #486268750 -bx00 ^% b10 4& 1= #486275000 0= #486281250 -0Y% -b0 ^% b11 4& 1= #486287500 @@ -202461,7 +202457,7 @@ b11 4& #486793750 0V% b11 [% -b100xx0 `% +b100x00 `% 1a% b100 4& 1= @@ -203080,7 +203076,7 @@ b11 4& #488293750 0V% b100 [% -b100xx00 `% +b100x000 `% 1a% b100 4& 1= @@ -203699,7 +203695,7 @@ b11 4& #489793750 0V% b101 [% -b100xx000 `% +b100x0000 `% 1a% b100 4& 1= @@ -204318,7 +204314,7 @@ b11 4& #491293750 0V% b110 [% -b0xx0000 `% +b0x00000 `% 1a% b100 4& 1= @@ -204937,7 +204933,7 @@ b11 4& #492793750 0V% b111 [% -b0xx00000 `% +b0x000000 `% 1a% b100 4& 1= @@ -205556,11 +205552,11 @@ b11 4& #494293750 0V% 1c -bx000000 d -bx000000 m$ -bx000000 _% +bx0000000 d +bx0000000 m$ +bx0000000 _% b0 [% -bx000000 `% +bx0000000 `% 1a% b100 4& 1= @@ -205569,16 +205565,16 @@ b100 4& #494306250 0c b101 K% -bx000000 D% +bx0000000 D% b101 4& 1= #494312500 0= #494318750 b110 K% -bx000000 O -bx000000 G" -bx000000 G% +bx0000000 O +bx0000000 G" +bx0000000 G% b11011 S b11011 H" b11011 F% @@ -205589,9 +205585,9 @@ b110 4& 0= #494331250 0P -bx000000 3" -bx000000 R" -bx000000 U" +bx0000000 3" +bx0000000 R" +bx0000000 U" b11011 7" b11011 Q" b11011 T" @@ -205603,9 +205599,9 @@ b111 4& 0= #494343750 b1 ^" -bx00000000000000 &" -bx00000000000000 \" -bx00000000000000 )# +bx000000000000000 &" +bx000000000000000 \" +bx000000000000000 )# 0'" 1+" 1(" @@ -205621,20 +205617,20 @@ b1 2# 1j 0i 1m -bx00000000000000 h -bx00000000000000 0# -bx00000000000000 P$ +bx000000000000000 h +bx000000000000000 0# +bx000000000000000 P$ b1001 4& 1= #494362500 0= #494368750 -bx00000000000000 y% +bx000000000000000 y% r494368.75 +& -bx00000000000000 ! -bx00000000000000 G -bx00000000000000 Q$ -bx00000000000000 e% +bx000000000000000 ! +bx000000000000000 G +bx000000000000000 Q$ +bx000000000000000 e% 1}% r494368.75 && r494368.75 ~% @@ -205642,12 +205638,12 @@ r494368.75 "& b11 d$ 0# 1_$ -bx00000000000000 `$ +bx000000000000000 `$ 0' 0$ 0e$ 1a$ -bx00000000000000 f$ +bx000000000000000 f$ 0j b1010 4& 1= @@ -206273,7 +206269,7 @@ b11 4& #495793750 0V% b1 [% -bx0000000 `% +b0 `% 1a% b100 4& 1= @@ -206892,7 +206888,6 @@ b11 4& #497293750 0V% b10 [% -b0 `% 1a% b100 4& 1= @@ -216160,7 +216155,7 @@ b100111 4& 0= #519243750 x? -bx000000 D& +bx0000000 D& b1110 I& b111 F& b0 4& @@ -216785,22 +216780,27 @@ b100111 4& #520737500 0= #520743750 +0? b110 F& b0 4& 1= #520750000 0= #520756250 +bx0 ^% b1 4& 1= #520762500 0= #520768750 +bx00 ^% b10 4& 1= #520775000 0= #520781250 +0Y% +b0 ^% b11 4& 1= #520787500 @@ -217014,7 +217014,7 @@ b11 4& #521293750 0V% b10 [% -b0xx `% +b0x0 `% 1a% b100 4& 1= @@ -217404,27 +217404,22 @@ b100111 4& #522237500 0= #522243750 -0? b101 F& b0 4& 1= #522250000 0= #522256250 -bx0 ^% b1 4& 1= #522262500 0= #522268750 -bx00 ^% b10 4& 1= #522275000 0= #522281250 -0Y% -b0 ^% b11 4& 1= #522287500 @@ -217638,7 +217633,7 @@ b11 4& #522793750 0V% b11 [% -b0xx0 `% +b0x00 `% 1a% b100 4& 1= @@ -218257,7 +218252,7 @@ b11 4& #524293750 0V% b100 [% -b0xx00 `% +b0x000 `% 1a% b100 4& 1= @@ -218876,7 +218871,7 @@ b11 4& #525793750 0V% b101 [% -b0xx000 `% +b0x0000 `% 1a% b100 4& 1= @@ -219495,7 +219490,7 @@ b11 4& #527293750 0V% b110 [% -b0xx0000 `% +b0x00000 `% 1a% b100 4& 1= @@ -220114,7 +220109,7 @@ b11 4& #528793750 0V% b111 [% -b0xx00000 `% +b0x000000 `% 1a% b100 4& 1= @@ -220733,11 +220728,11 @@ b11 4& #530293750 0V% 1c -bx000000 d -bx000000 m$ -bx000000 _% +bx0000000 d +bx0000000 m$ +bx0000000 _% b0 [% -bx000000 `% +bx0000000 `% 1a% b100 4& 1= @@ -220746,16 +220741,16 @@ b100 4& #530306250 0c b101 K% -bx000000 D% +bx0000000 D% b101 4& 1= #530312500 0= #530318750 b110 K% -bx000000 O -bx000000 G" -bx000000 G% +bx0000000 O +bx0000000 G" +bx0000000 G% b11110 S b11110 H" b11110 F% @@ -220766,9 +220761,9 @@ b110 4& 0= #530331250 0P -bx000000 3" -bx000000 R" -bx000000 U" +bx0000000 3" +bx0000000 R" +bx0000000 U" b11110 7" b11110 Q" b11110 T" @@ -220780,9 +220775,9 @@ b111 4& 0= #530343750 b1 ^" -b0xx000000 &" -b0xx000000 \" -b0xx000000 )# +b0x0000000 &" +b0x0000000 \" +b0x0000000 )# 1'" 0+" b1111 ," @@ -220801,9 +220796,9 @@ b1 2# 1j 1i 0m -b0xx000000 h -b0xx000000 0# -b0xx000000 P$ +b0x0000000 h +b0x0000000 0# +b0x0000000 P$ b1111 n b1111 /# b1111 O$ @@ -220812,12 +220807,12 @@ b1001 4& #530362500 0= #530368750 -b0xx000000 y% +b0x0000000 y% r530368.75 +& -b0xx000000 ! -b0xx000000 G -b0xx000000 Q$ -b0xx000000 e% +b0x0000000 ! +b0x0000000 G +b0x0000000 Q$ +b0x0000000 e% 1}% r530368.75 && b1111 x% @@ -220826,7 +220821,7 @@ r530368.75 "& b11 d$ 0# 1_$ -b0xx000000 `$ +b0x0000000 `$ 0' 0& b1111 ( @@ -220835,7 +220830,7 @@ b1111 c$ b1111 d% 1e$ 0a$ -b0xx000000 f$ +b0x0000000 f$ b1111 ]$ 0j b1010 4& @@ -221462,7 +221457,7 @@ b11 4& #531793750 0V% b1 [% -bx0000000 `% +b0 `% 1a% b100 4& 1= @@ -222081,7 +222076,6 @@ b11 4& #533293750 0V% b10 [% -b0 `% 1a% b100 4& 1= @@ -263206,7 +263200,7 @@ b100111 4& 0= #631243750 x? -bx000000 D& +bx0000000 D& b111 F& b0 4& 1= @@ -263830,22 +263824,27 @@ b100111 4& #632737500 0= #632743750 +0? b110 F& b0 4& 1= #632750000 0= #632756250 +bx0 ^% b1 4& 1= #632762500 0= #632768750 +bx00 ^% b10 4& 1= #632775000 0= #632781250 +0Y% +b0 ^% b11 4& 1= #632787500 @@ -264059,7 +264058,7 @@ b11 4& #633293750 0V% b10 [% -b1xx `% +b1x0 `% 1a% b100 4& 1= @@ -264449,27 +264448,22 @@ b100111 4& #634237500 0= #634243750 -0? b101 F& b0 4& 1= #634250000 0= #634256250 -bx0 ^% b1 4& 1= #634262500 0= #634268750 -bx00 ^% b10 4& 1= #634275000 0= #634281250 -0Y% -b0 ^% b11 4& 1= #634287500 @@ -264683,7 +264677,7 @@ b11 4& #634793750 0V% b11 [% -b1xx0 `% +b1x00 `% 1a% b100 4& 1= @@ -265302,7 +265296,7 @@ b11 4& #636293750 0V% b100 [% -b1xx00 `% +b1x000 `% 1a% b100 4& 1= @@ -265921,7 +265915,7 @@ b11 4& #637793750 0V% b101 [% -b1xx000 `% +b1x0000 `% 1a% b100 4& 1= @@ -266540,7 +266534,7 @@ b11 4& #639293750 0V% b110 [% -b1xx0000 `% +b1x00000 `% 1a% b100 4& 1= @@ -267159,7 +267153,7 @@ b11 4& #640793750 0V% b111 [% -b1xx00000 `% +b1x000000 `% 1a% b100 4& 1= @@ -267778,11 +267772,11 @@ b11 4& #642293750 0V% 1c -bx000000 d -bx000000 m$ -bx000000 _% +bx0000000 d +bx0000000 m$ +bx0000000 _% b0 [% -bx000000 `% +bx0000000 `% 1a% b100 4& 1= @@ -267791,7 +267785,7 @@ b100 4& #642306250 0c b1 ;% -b0xx000000 7% +b0x0000000 7% b101 4& 1= #642312500 @@ -268407,7 +268401,7 @@ b11 4& #643793750 0V% b1 [% -bx0000000 `% +b0 `% 1a% b100 4& 1= @@ -269026,7 +269020,6 @@ b11 4& #645293750 0V% b10 [% -b0 `% 1a% b100 4& 1= @@ -272753,7 +272746,7 @@ b100 4& #654306250 0c b10 ;% -b0xx00000000000001 7% +b0x000000000000001 7% b101 4& 1= #654312500 @@ -277723,7 +277716,7 @@ b11 K% b0 >% b100000000 <% b0 ;% -bx0000000000000100000000 7% +bx00000000000000100000000 7% b101 4& 1= #666312500 @@ -375360,7 +375353,7 @@ b100111 4& 0= #899243750 x? -bx000000 D& +bx0000000 D& b111 F& b0 4& 1= @@ -375984,22 +375977,27 @@ b100111 4& #900737500 0= #900743750 +0? b110 F& b0 4& 1= #900750000 0= #900756250 +bx0 ^% b1 4& 1= #900762500 0= #900768750 +bx00 ^% b10 4& 1= #900775000 0= #900781250 +0Y% +b0 ^% b11 4& 1= #900787500 @@ -376213,7 +376211,7 @@ b11 4& #901293750 0V% b10 [% -b1xx `% +b1x0 `% 1a% b100 4& 1= @@ -376603,27 +376601,22 @@ b100111 4& #902237500 0= #902243750 -0? b101 F& b0 4& 1= #902250000 0= #902256250 -bx0 ^% b1 4& 1= #902262500 0= #902268750 -bx00 ^% b10 4& 1= #902275000 0= #902281250 -0Y% -b0 ^% b11 4& 1= #902287500 @@ -376837,7 +376830,7 @@ b11 4& #902793750 0V% b11 [% -b1xx0 `% +b1x00 `% 1a% b100 4& 1= @@ -377456,7 +377449,7 @@ b11 4& #904293750 0V% b100 [% -b1xx00 `% +b1x000 `% 1a% b100 4& 1= @@ -378075,7 +378068,7 @@ b11 4& #905793750 0V% b101 [% -b1xx000 `% +b1x0000 `% 1a% b100 4& 1= @@ -378694,7 +378687,7 @@ b11 4& #907293750 0V% b110 [% -b1xx0000 `% +b1x00000 `% 1a% b100 4& 1= @@ -379313,7 +379306,7 @@ b11 4& #908793750 0V% b111 [% -b1xx00000 `% +b1x000000 `% 1a% b100 4& 1= @@ -379932,11 +379925,11 @@ b11 4& #910293750 0V% 1c -bx000000 d -bx000000 m$ -bx000000 _% +bx0000000 d +bx0000000 m$ +bx0000000 _% b0 [% -bx000000 `% +bx0000000 `% 1a% b100 4& 1= @@ -379945,7 +379938,7 @@ b100 4& #910306250 0c b1 ;% -b0xx000000 7% +b0x0000000 7% b101 4& 1= #910312500 @@ -380561,7 +380554,7 @@ b11 4& #911793750 0V% b1 [% -bx0000000 `% +b0 `% 1a% b100 4& 1= @@ -381180,7 +381173,6 @@ b11 4& #913293750 0V% b10 [% -b0 `% 1a% b100 4& 1= @@ -384907,7 +384899,7 @@ b100 4& #922306250 0c b10 ;% -b0xx00000000000001 7% +b0x000000000000001 7% b101 4& 1= #922312500 @@ -389887,7 +389879,7 @@ b11 K% b0 >% b100100000 <% b0 ;% -bx0000000000000100100000 7% +bx00000000000000100100000 7% b101 4& 1= #934312500 @@ -427052,7 +427044,7 @@ b100111 4& 0= #1023243750 x? -bx000000 D& +bx0000000 D& b111 F& b0 4& 1= @@ -427676,22 +427668,27 @@ b100111 4& #1024737500 0= #1024743750 +0? b110 F& b0 4& 1= #1024750000 0= #1024756250 +bx0 ^% b1 4& 1= #1024762500 0= #1024768750 +bx00 ^% b10 4& 1= #1024775000 0= #1024781250 +0Y% +b0 ^% b11 4& 1= #1024787500 @@ -427905,7 +427902,7 @@ b11 4& #1025293750 0V% b10 [% -b1xx `% +b1x0 `% 1a% b100 4& 1= @@ -428295,27 +428292,22 @@ b100111 4& #1026237500 0= #1026243750 -0? b101 F& b0 4& 1= #1026250000 0= #1026256250 -bx0 ^% b1 4& 1= #1026262500 0= #1026268750 -bx00 ^% b10 4& 1= #1026275000 0= #1026281250 -0Y% -b0 ^% b11 4& 1= #1026287500 @@ -428529,7 +428521,7 @@ b11 4& #1026793750 0V% b11 [% -b1xx0 `% +b1x00 `% 1a% b100 4& 1= @@ -429148,7 +429140,7 @@ b11 4& #1028293750 0V% b100 [% -b1xx00 `% +b1x000 `% 1a% b100 4& 1= @@ -429767,7 +429759,7 @@ b11 4& #1029793750 0V% b101 [% -b1xx000 `% +b1x0000 `% 1a% b100 4& 1= @@ -430386,7 +430378,7 @@ b11 4& #1031293750 0V% b110 [% -b1xx0000 `% +b1x00000 `% 1a% b100 4& 1= @@ -431005,7 +430997,7 @@ b11 4& #1032793750 0V% b111 [% -b1xx00000 `% +b1x000000 `% 1a% b100 4& 1= @@ -431624,11 +431616,11 @@ b11 4& #1034293750 0V% 1c -bx000000 d -bx000000 m$ -bx000000 _% +bx0000000 d +bx0000000 m$ +bx0000000 _% b0 [% -bx000000 `% +bx0000000 `% 1a% b100 4& 1= @@ -431637,7 +431629,7 @@ b100 4& #1034306250 0c b1 ;% -b0xx000000 7% +b0x0000000 7% b101 4& 1= #1034312500 @@ -432253,7 +432245,7 @@ b11 4& #1035793750 0V% b1 [% -bx0000000 `% +b0 `% 1a% b100 4& 1= @@ -432872,7 +432864,6 @@ b11 4& #1037293750 0V% b10 [% -b0 `% 1a% b100 4& 1= @@ -436605,7 +436596,7 @@ b100 4& #1046306250 0c b10 ;% -b0xx00000000000010 7% +b0x000000000000010 7% b101 4& 1= #1046312500 @@ -441569,7 +441560,7 @@ b11 K% b0 >% b1000000000 <% b0 ;% -bx0000000000001000000000 7% +bx00000000000001000000000 7% b101 4& 1= #1058312500 @@ -539179,7 +539170,7 @@ b100111 4& 0= #1291243750 x? -bx000000 D& +bx0000000 D& b111 F& b0 4& 1= @@ -539803,22 +539794,27 @@ b100111 4& #1292737500 0= #1292743750 +0? b110 F& b0 4& 1= #1292750000 0= #1292756250 +bx0 ^% b1 4& 1= #1292762500 0= #1292768750 +bx00 ^% b10 4& 1= #1292775000 0= #1292781250 +0Y% +b0 ^% b11 4& 1= #1292787500 @@ -540032,7 +540028,7 @@ b11 4& #1293293750 0V% b10 [% -b1xx `% +b1x0 `% 1a% b100 4& 1= @@ -540422,27 +540418,22 @@ b100111 4& #1294237500 0= #1294243750 -0? b101 F& b0 4& 1= #1294250000 0= #1294256250 -bx0 ^% b1 4& 1= #1294262500 0= #1294268750 -bx00 ^% b10 4& 1= #1294275000 0= #1294281250 -0Y% -b0 ^% b11 4& 1= #1294287500 @@ -540656,7 +540647,7 @@ b11 4& #1294793750 0V% b11 [% -b1xx0 `% +b1x00 `% 1a% b100 4& 1= @@ -541275,7 +541266,7 @@ b11 4& #1296293750 0V% b100 [% -b1xx00 `% +b1x000 `% 1a% b100 4& 1= @@ -541894,7 +541885,7 @@ b11 4& #1297793750 0V% b101 [% -b1xx000 `% +b1x0000 `% 1a% b100 4& 1= @@ -542513,7 +542504,7 @@ b11 4& #1299293750 0V% b110 [% -b1xx0000 `% +b1x00000 `% 1a% b100 4& 1= @@ -543132,7 +543123,7 @@ b11 4& #1300793750 0V% b111 [% -b1xx00000 `% +b1x000000 `% 1a% b100 4& 1= @@ -543751,11 +543742,11 @@ b11 4& #1302293750 0V% 1c -bx000000 d -bx000000 m$ -bx000000 _% +bx0000000 d +bx0000000 m$ +bx0000000 _% b0 [% -bx000000 `% +bx0000000 `% 1a% b100 4& 1= @@ -543764,7 +543755,7 @@ b100 4& #1302306250 0c b1 ;% -b0xx000000 7% +b0x0000000 7% b101 4& 1= #1302312500 @@ -544380,7 +544371,7 @@ b11 4& #1303793750 0V% b1 [% -bx0000000 `% +b0 `% 1a% b100 4& 1= @@ -544999,7 +544990,6 @@ b11 4& #1305293750 0V% b10 [% -b0 `% 1a% b100 4& 1= @@ -548732,7 +548722,7 @@ b100 4& #1314306250 0c b10 ;% -b0xx00000000000010 7% +b0x000000000000010 7% b101 4& 1= #1314312500 @@ -553707,7 +553697,7 @@ b11 K% b0 >% b1000100000 <% b0 ;% -bx0000000000001000100000 7% +bx00000000000001000100000 7% b101 4& 1= #1326312500 @@ -587523,7 +587513,7 @@ b111 4& 0= #1406443750 x? -bx000000 D& +bx0000000 D& b111 F& b0 4& 1= @@ -587667,22 +587657,27 @@ b111 4& #1406737500 0= #1406743750 +0? b110 F& b0 4& 1= #1406750000 0= #1406756250 +bx0 ^% b1 4& 1= #1406762500 0= #1406768750 +bx00 ^% b10 4& 1= #1406775000 0= #1406781250 +0Y% +b0 ^% b11 4& 1= #1406787500 @@ -587736,7 +587731,7 @@ b11 4& #1406893750 0V% b10 [% -b0xx `% +b0x0 `% 1a% b100 4& 1= @@ -587806,27 +587801,22 @@ b111 4& #1407037500 0= #1407043750 -0? b101 F& b0 4& 1= #1407050000 0= #1407056250 -bx0 ^% b1 4& 1= #1407062500 0= #1407068750 -bx00 ^% b10 4& 1= #1407075000 0= #1407081250 -0Y% -b0 ^% b11 4& 1= #1407087500 @@ -587880,7 +587870,7 @@ b11 4& #1407193750 0V% b11 [% -b0xx0 `% +b0x00 `% 1a% b100 4& 1= @@ -588019,7 +588009,7 @@ b11 4& #1407493750 0V% b100 [% -b0xx00 `% +b0x000 `% 1a% b100 4& 1= @@ -588158,7 +588148,7 @@ b11 4& #1407793750 0V% b101 [% -b0xx000 `% +b0x0000 `% 1a% b100 4& 1= @@ -588297,7 +588287,7 @@ b11 4& #1408093750 0V% b110 [% -b0xx0000 `% +b0x00000 `% 1a% b100 4& 1= @@ -588436,7 +588426,7 @@ b11 4& #1408393750 0V% b111 [% -b0xx00000 `% +b0x000000 `% 1a% b100 4& 1= @@ -588575,11 +588565,11 @@ b11 4& #1408693750 0V% 1c -bx000000 d -bx000000 m$ -bx000000 _% +bx0000000 d +bx0000000 m$ +bx0000000 _% b0 [% -bx000000 `% +bx0000000 `% 1a% b100 4& 1= @@ -588588,7 +588578,7 @@ b100 4& #1408706250 0c b1 ;% -b0xx000000 7% +b0x0000000 7% b101 4& 1= #1408712500 @@ -588724,7 +588714,7 @@ b11 4& #1408993750 0V% b1 [% -bx0000000 `% +b0 `% 1a% b100 4& 1= @@ -588863,7 +588853,6 @@ b11 4& #1409293750 0V% b10 [% -b0 `% 1a% b100 4& 1= @@ -589704,7 +589693,7 @@ b100 4& #1411106250 0c b10 ;% -b0xx00000000000000 7% +b0x000000000000000 7% b101 4& 1= #1411112500 @@ -590815,7 +590804,7 @@ b100 4& 0c b1011 K% b0 ;% -bx0000000000000000000000 7% +bx00000000000000000000000 7% b101 4& 1= #1413512500 @@ -593487,7 +593476,7 @@ b111 4& 0= #1419243750 x? -bx000000 D& +bx0000000 D& b111 F& b0 4& 1= @@ -593631,22 +593620,27 @@ b111 4& #1419537500 0= #1419543750 +0? b110 F& b0 4& 1= #1419550000 0= #1419556250 +bx0 ^% b1 4& 1= #1419562500 0= #1419568750 +bx00 ^% b10 4& 1= #1419575000 0= #1419581250 +0Y% +b0 ^% b11 4& 1= #1419587500 @@ -593700,7 +593694,7 @@ b11 4& #1419693750 0V% b10 [% -b11xx `% +b11x0 `% 1a% b100 4& 1= @@ -593770,27 +593764,22 @@ b111 4& #1419837500 0= #1419843750 -0? b101 F& b0 4& 1= #1419850000 0= #1419856250 -bx0 ^% b1 4& 1= #1419862500 0= #1419868750 -bx00 ^% b10 4& 1= #1419875000 0= #1419881250 -0Y% -b0 ^% b11 4& 1= #1419887500 @@ -593844,7 +593833,7 @@ b11 4& #1419993750 0V% b11 [% -b11xx0 `% +b11x00 `% 1a% b100 4& 1= @@ -593983,7 +593972,7 @@ b11 4& #1420293750 0V% b100 [% -b11xx00 `% +b11x000 `% 1a% b100 4& 1= @@ -594122,7 +594111,7 @@ b11 4& #1420593750 0V% b101 [% -b11xx000 `% +b11x0000 `% 1a% b100 4& 1= @@ -594261,7 +594250,7 @@ b11 4& #1420893750 0V% b110 [% -b11xx0000 `% +b11x00000 `% 1a% b100 4& 1= @@ -594400,7 +594389,7 @@ b11 4& #1421193750 0V% b111 [% -b1xx00000 `% +b1x000000 `% 1a% b100 4& 1= @@ -594539,11 +594528,11 @@ b11 4& #1421493750 0V% 1c -bx000000 d -bx000000 m$ -bx000000 _% +bx0000000 d +bx0000000 m$ +bx0000000 _% b0 [% -bx000000 `% +bx0000000 `% 1a% b100 4& 1= @@ -594552,7 +594541,7 @@ b100 4& #1421506250 0c b1 ;% -b0xx000000 7% +b0x0000000 7% b101 4& 1= #1421512500 @@ -594688,7 +594677,7 @@ b11 4& #1421793750 0V% b1 [% -bx0000000 `% +b0 `% 1a% b100 4& 1= @@ -594827,7 +594816,6 @@ b11 4& #1422093750 0V% b10 [% -b0 `% 1a% b100 4& 1= @@ -595668,7 +595656,7 @@ b100 4& #1423906250 0c b10 ;% -b0xx00000000000000 7% +b0x000000000000000 7% b101 4& 1= #1423912500 @@ -596801,7 +596789,7 @@ b10000 M b10000 b" b10000 N% b0 ;% -bx0000000000000000010000 7% +bx00000000000000000010000 7% b101 4& 1= #1426312500 @@ -599477,7 +599465,7 @@ b111 4& 0= #1432043750 x? -bx000000 D& +bx0000000 D& b111 F& b0 4& 1= @@ -599621,22 +599609,27 @@ b111 4& #1432337500 0= #1432343750 +0? b110 F& b0 4& 1= #1432350000 0= #1432356250 +bx0 ^% b1 4& 1= #1432362500 0= #1432368750 +bx00 ^% b10 4& 1= #1432375000 0= #1432381250 +0Y% +b0 ^% b11 4& 1= #1432387500 @@ -599690,7 +599683,7 @@ b11 4& #1432493750 0V% b10 [% -b100xx `% +b100x0 `% 1a% b100 4& 1= @@ -599760,27 +599753,22 @@ b111 4& #1432637500 0= #1432643750 -0? b101 F& b0 4& 1= #1432650000 0= #1432656250 -bx0 ^% b1 4& 1= #1432662500 0= #1432668750 -bx00 ^% b10 4& 1= #1432675000 0= #1432681250 -0Y% -b0 ^% b11 4& 1= #1432687500 @@ -599834,7 +599822,7 @@ b11 4& #1432793750 0V% b11 [% -b100xx0 `% +b100x00 `% 1a% b100 4& 1= @@ -599973,7 +599961,7 @@ b11 4& #1433093750 0V% b100 [% -b100xx00 `% +b100x000 `% 1a% b100 4& 1= @@ -600112,7 +600100,7 @@ b11 4& #1433393750 0V% b101 [% -b100xx000 `% +b100x0000 `% 1a% b100 4& 1= @@ -600251,7 +600239,7 @@ b11 4& #1433693750 0V% b110 [% -b0xx0000 `% +b0x00000 `% 1a% b100 4& 1= @@ -600390,7 +600378,7 @@ b11 4& #1433993750 0V% b111 [% -b0xx00000 `% +b0x000000 `% 1a% b100 4& 1= @@ -600529,11 +600517,11 @@ b11 4& #1434293750 0V% 1c -bx000000 d -bx000000 m$ -bx000000 _% +bx0000000 d +bx0000000 m$ +bx0000000 _% b0 [% -bx000000 `% +bx0000000 `% 1a% b100 4& 1= @@ -600542,7 +600530,7 @@ b100 4& #1434306250 0c b1 ;% -b0xx000000 7% +b0x0000000 7% b101 4& 1= #1434312500 @@ -600678,7 +600666,7 @@ b11 4& #1434593750 0V% b1 [% -bx0000000 `% +b0 `% 1a% b100 4& 1= @@ -600817,7 +600805,6 @@ b11 4& #1434893750 0V% b10 [% -b0 `% 1a% b100 4& 1= @@ -601665,7 +601652,7 @@ b100 4& #1436706250 0c b10 ;% -b0xx00000000000011 7% +b0x000000000000011 7% b101 4& 1= #1436712500 @@ -602796,7 +602783,7 @@ b1100000000 0" b1100000000 e" b1100000000 9% b0 ;% -bx0000000000001100000000 7% +bx00000000000001100000000 7% b101 4& 1= #1439112500 @@ -605478,7 +605465,7 @@ b111 4& 0= #1444843750 x? -bx000000 D& +bx0000000 D& b111 F& b0 4& 1= @@ -605622,22 +605609,27 @@ b111 4& #1445137500 0= #1445143750 +0? b110 F& b0 4& 1= #1445150000 0= #1445156250 +bx0 ^% b1 4& 1= #1445162500 0= #1445168750 +bx00 ^% b10 4& 1= #1445175000 0= #1445181250 +0Y% +b0 ^% b11 4& 1= #1445187500 @@ -605691,7 +605683,7 @@ b11 4& #1445293750 0V% b10 [% -b101xx `% +b101x0 `% 1a% b100 4& 1= @@ -605761,27 +605753,22 @@ b111 4& #1445437500 0= #1445443750 -0? b101 F& b0 4& 1= #1445450000 0= #1445456250 -bx0 ^% b1 4& 1= #1445462500 0= #1445468750 -bx00 ^% b10 4& 1= #1445475000 0= #1445481250 -0Y% -b0 ^% b11 4& 1= #1445487500 @@ -605835,7 +605822,7 @@ b11 4& #1445593750 0V% b11 [% -b101xx0 `% +b101x00 `% 1a% b100 4& 1= @@ -605974,7 +605961,7 @@ b11 4& #1445893750 0V% b100 [% -b101xx00 `% +b101x000 `% 1a% b100 4& 1= @@ -606113,7 +606100,7 @@ b11 4& #1446193750 0V% b101 [% -b101xx000 `% +b101x0000 `% 1a% b100 4& 1= @@ -606252,7 +606239,7 @@ b11 4& #1446493750 0V% b110 [% -b1xx0000 `% +b1x00000 `% 1a% b100 4& 1= @@ -606391,7 +606378,7 @@ b11 4& #1446793750 0V% b111 [% -b1xx00000 `% +b1x000000 `% 1a% b100 4& 1= @@ -606530,11 +606517,11 @@ b11 4& #1447093750 0V% 1c -bx000000 d -bx000000 m$ -bx000000 _% +bx0000000 d +bx0000000 m$ +bx0000000 _% b0 [% -bx000000 `% +bx0000000 `% 1a% b100 4& 1= @@ -606543,7 +606530,7 @@ b100 4& #1447106250 0c b1 ;% -b0xx000000 7% +b0x0000000 7% b101 4& 1= #1447112500 @@ -606679,7 +606666,7 @@ b11 4& #1447393750 0V% b1 [% -bx0000000 `% +b0 `% 1a% b100 4& 1= @@ -606818,7 +606805,6 @@ b11 4& #1447693750 0V% b10 [% -b0 `% 1a% b100 4& 1= @@ -607666,7 +607652,7 @@ b100 4& #1449506250 0c b10 ;% -b0xx00000000000011 7% +b0x000000000000011 7% b101 4& 1= #1449512500 @@ -608807,7 +608793,7 @@ b1100010000 /" b1100010000 d" b1100010000 :% b0 ;% -bx0000000000001100010000 7% +bx00000000000001100010000 7% b101 4& 1= #1451912500 @@ -611512,10 +611498,10 @@ b10 4& 0= #1457581250 1U% -b0xx000000 ! -b0xx000000 G -b0xx000000 Q$ -b0xx000000 e% +b0x0000000 ! +b0x0000000 G +b0x0000000 Q$ +b0x0000000 e% 0X% r1457581.25 (& 1|% @@ -611523,7 +611509,7 @@ r1457581.25 %& b1000 x% r1457581.25 ~% r1457581.25 "& -b0xx000000 {% +b0x0000000 {% 1z% b0 b% 0j @@ -611596,9 +611582,9 @@ b0 ^$ 1% 1' 1k -b0xx000000 l -b0xx000000 *# -b0xx000000 b$ +b0x0000000 l +b0x0000000 *# +b0x0000000 b$ b1 4& 1= #1457662500 @@ -611607,9 +611593,9 @@ b1 4& 0k b0 2# 1)" -b0xx000000 *" -b0xx000000 V" -b0xx000000 1# +b0x0000000 *" +b0x0000000 V" +b0x0000000 1# b10 4& 1= #1457675000 @@ -611617,9 +611603,9 @@ b10 4& #1457681250 b0 ^" 15" -bx000000 6" -bx000000 B" -bx000000 ]" +bx0000000 6" +bx0000000 B" +bx0000000 ]" 0)" b11 4& 1= @@ -611629,9 +611615,9 @@ b11 4& 05" b0 S" 1W -bx000000 X -bx000000 P" -bx000000 _" +bx0000000 X +bx0000000 P" +bx0000000 _" b100 4& 1= #1457700000 @@ -611639,7 +611625,7 @@ b100 4& #1457706250 b1 %# b1 u" -bx0000000000000000000000 &# +bx00000000000000000000000 &# 0W b101 4& 1= @@ -611808,7 +611794,7 @@ b11 4& 0W b1 %# b10 u" -bx0000000000000100000000 &# +bx00000000000000100000000 &# 1." 1\% b100 4& @@ -612031,16 +612017,16 @@ b11 4& #1458137500 0= #1458143750 -bx00000000000000 ! -bx00000000000000 G -bx00000000000000 Q$ -bx00000000000000 e% +bx000000000000000 ! +bx000000000000000 G +bx000000000000000 Q$ +bx000000000000000 e% r1458143.75 (& 1|% r1458143.75 %& r1458143.75 ~% r1458143.75 "& -bx00000000000000 {% +bx000000000000000 {% 1z% b10 d$ 0% @@ -612099,9 +612085,9 @@ b0 ^$ 1% 1' 1k -bx00000000000000 l -bx00000000000000 *# -bx00000000000000 b$ +bx000000000000000 l +bx000000000000000 *# +bx000000000000000 b$ b1010 4& 1= #1458225000 @@ -612109,9 +612095,9 @@ b1010 4& #1458231250 b0 2# 1)" -bx00000000000000 *" -bx00000000000000 V" -bx00000000000000 1# +bx000000000000000 *" +bx000000000000000 V" +bx000000000000000 1# 0k b1011 4& 1= @@ -612121,9 +612107,9 @@ b1011 4& 0)" b0 ^" 15" -bx000000 6" -bx000000 B" -bx000000 ]" +bx0000000 6" +bx0000000 B" +bx0000000 ]" b1100 4& 1= #1458250000 @@ -612131,9 +612117,9 @@ b1100 4& #1458256250 b0 S" 1W -bx000000 X -bx000000 P" -bx000000 _" +bx0000000 X +bx0000000 P" +bx0000000 _" 05" b1101 4& 1= @@ -612143,7 +612129,7 @@ b1101 4& 0W b1 %# b100 u" -bx0000000000000000000000 r" +bx00000000000000000000000 r" b1110 4& 1= #1458275000 @@ -612327,7 +612313,7 @@ b1100 4& #1458456250 b1 %# b101 u" -bx0000000000000100000000 r" +bx00000000000000100000000 r" 0W b1101 4& 1= @@ -612498,7 +612484,7 @@ b11 4& 0W b1 %# b110 u" -bx0000000000000100100000 r" +bx00000000000000100100000 r" b1 [% b100 `% 1a% @@ -619331,17 +619317,17 @@ b110 4& #1465525000 0= #1465531250 -bx00000000000000 ! -bx00000000000000 G -bx00000000000000 Q$ -bx00000000000000 e% +bx000000000000000 ! +bx000000000000000 G +bx000000000000000 Q$ +bx000000000000000 e% r1465531.25 (& 1|% r1465531.25 %& b1101 x% r1465531.25 ~% r1465531.25 "& -bx00000000000000 {% +bx000000000000000 {% 1z% 0j b10 d$ @@ -619406,9 +619392,9 @@ b0 ^$ 1% 1' 1k -bx00000000000000 l -bx00000000000000 *# -bx00000000000000 b$ +bx000000000000000 l +bx000000000000000 *# +bx000000000000000 b$ b101 4& 1= #1465612500 @@ -619417,9 +619403,9 @@ b101 4& 0k b0 2# 1)" -bx00000000000000 *" -bx00000000000000 V" -bx00000000000000 1# +bx000000000000000 *" +bx000000000000000 V" +bx000000000000000 1# b110 4& 1= #1465625000 @@ -619427,9 +619413,9 @@ b110 4& #1465631250 b0 ^" 15" -bx000000 6" -bx000000 B" -bx000000 ]" +bx0000000 6" +bx0000000 B" +bx0000000 ]" 0)" b111 4& 1= @@ -619439,9 +619425,9 @@ b111 4& 05" b0 S" 1W -bx000000 X -bx000000 P" -bx000000 _" +bx0000000 X +bx0000000 P" +bx0000000 _" 1B b0 4& 1= @@ -619646,7 +619632,7 @@ b111 4& 0W b1 %# b10 u" -bx0000000000001000000000 &# +bx00000000000001000000000 &# b10 F& b0 4& 1= @@ -619887,17 +619873,17 @@ b11 4& #1466087500 0= #1466093750 -b0xx000000 ! -b0xx000000 G -b0xx000000 Q$ -b0xx000000 e% +b0x0000000 ! +b0x0000000 G +b0x0000000 Q$ +b0x0000000 e% r1466093.75 (& 1|% r1466093.75 %& b1111 x% r1466093.75 ~% r1466093.75 "& -b0xx000000 {% +b0x0000000 {% 1z% 0U% b10 d$ @@ -619965,9 +619951,9 @@ b0 ^$ 1% 1' 1k -b0xx000000 l -b0xx000000 *# -b0xx000000 b$ +b0x0000000 l +b0x0000000 *# +b0x0000000 b$ b10 4& 1= #1466175000 @@ -619975,9 +619961,9 @@ b10 4& #1466181250 b0 2# 1)" -b0xx000000 *" -b0xx000000 V" -b0xx000000 1# +b0x0000000 *" +b0x0000000 V" +b0x0000000 1# 0k b11 4& 1= @@ -619987,9 +619973,9 @@ b11 4& 0)" b0 ^" 15" -bx000000 6" -bx000000 B" -bx000000 ]" +bx0000000 6" +bx0000000 B" +bx0000000 ]" b100 4& 1= #1466200000 @@ -619997,9 +619983,9 @@ b100 4& #1466206250 b0 S" 1W -bx000000 X -bx000000 P" -bx000000 _" +bx0000000 X +bx0000000 P" +bx0000000 _" 05" b101 4& 1= @@ -620192,7 +620178,7 @@ b100 4& #1466406250 b1 %# b101 u" -bx0000000000001000100000 r" +bx00000000000001000100000 r" 0W b101 4& 1= @@ -642692,7 +642678,7 @@ b100111 4& 0= #1508043750 x? -bx000000 D& +bx0000000 D& b0 B& b111 F& b0 4& @@ -643317,22 +643303,27 @@ b100111 4& #1509537500 0= #1509543750 +0? b110 F& b0 4& 1= #1509550000 0= #1509556250 +bx0 ^% b1 4& 1= #1509562500 0= #1509568750 +bx00 ^% b10 4& 1= #1509575000 0= #1509581250 +0Y% +b0 ^% b11 4& 1= #1509587500 @@ -643546,7 +643537,7 @@ b11 4& #1510093750 0V% b10 [% -b10xx `% +b10x0 `% 1a% b100 4& 1= @@ -643936,27 +643927,22 @@ b100111 4& #1511037500 0= #1511043750 -0? b101 F& b0 4& 1= #1511050000 0= #1511056250 -bx0 ^% b1 4& 1= #1511062500 0= #1511068750 -bx00 ^% b10 4& 1= #1511075000 0= #1511081250 -0Y% -b0 ^% b11 4& 1= #1511087500 @@ -644170,7 +644156,7 @@ b11 4& #1511593750 0V% b11 [% -b10xx0 `% +b10x00 `% 1a% b100 4& 1= @@ -644789,7 +644775,7 @@ b11 4& #1513093750 0V% b100 [% -b10xx00 `% +b10x000 `% 1a% b100 4& 1= @@ -645408,7 +645394,7 @@ b11 4& #1514593750 0V% b101 [% -b10xx000 `% +b10x0000 `% 1a% b100 4& 1= @@ -646027,7 +646013,7 @@ b11 4& #1516093750 0V% b110 [% -b10xx0000 `% +b10x00000 `% 1a% b100 4& 1= @@ -646646,7 +646632,7 @@ b11 4& #1517593750 0V% b111 [% -b0xx00000 `% +b0x000000 `% 1a% b100 4& 1= @@ -647265,11 +647251,11 @@ b11 4& #1519093750 0V% 1c -bx000000 d -bx000000 m$ -bx000000 _% +bx0000000 d +bx0000000 m$ +bx0000000 _% b0 [% -bx000000 `% +bx0000000 `% 1a% b100 4& 1= @@ -647278,7 +647264,7 @@ b100 4& #1519106250 0c b1 ;% -b0xx000000 7% +b0x0000000 7% b101 4& 1= #1519112500 @@ -647894,7 +647880,7 @@ b11 4& #1520593750 0V% b1 [% -bx0000000 `% +b0 `% 1a% b100 4& 1= @@ -648513,7 +648499,6 @@ b11 4& #1522093750 0V% b10 [% -b0 `% 1a% b100 4& 1= @@ -652241,7 +652226,7 @@ b100 4& #1531106250 0c b10 ;% -b0xx00000000000011 7% +b0x000000000000011 7% b101 4& 1= #1531112500 @@ -657221,7 +657206,7 @@ b11 K% b0 >% b1100010000 <% b0 ;% -bx0000000000001100010000 7% +bx00000000000001100010000 7% b101 4& 1= #1543112500 @@ -694432,7 +694417,7 @@ b100111 4& 0= #1632043750 x? -bx000000 D& +bx0000000 D& b0 B& b111 F& b0 4& @@ -695057,22 +695042,27 @@ b100111 4& #1633537500 0= #1633543750 +0? b110 F& b0 4& 1= #1633550000 0= #1633556250 +bx0 ^% b1 4& 1= #1633562500 0= #1633568750 +bx00 ^% b10 4& 1= #1633575000 0= #1633581250 +0Y% +b0 ^% b11 4& 1= #1633587500 @@ -695286,7 +695276,7 @@ b11 4& #1634093750 0V% b10 [% -b10xx `% +b10x0 `% 1a% b100 4& 1= @@ -695676,27 +695666,22 @@ b100111 4& #1635037500 0= #1635043750 -0? b101 F& b0 4& 1= #1635050000 0= #1635056250 -bx0 ^% b1 4& 1= #1635062500 0= #1635068750 -bx00 ^% b10 4& 1= #1635075000 0= #1635081250 -0Y% -b0 ^% b11 4& 1= #1635087500 @@ -695910,7 +695895,7 @@ b11 4& #1635593750 0V% b11 [% -b10xx0 `% +b10x00 `% 1a% b100 4& 1= @@ -696529,7 +696514,7 @@ b11 4& #1637093750 0V% b100 [% -b10xx00 `% +b10x000 `% 1a% b100 4& 1= @@ -697148,7 +697133,7 @@ b11 4& #1638593750 0V% b101 [% -b10xx000 `% +b10x0000 `% 1a% b100 4& 1= @@ -697767,7 +697752,7 @@ b11 4& #1640093750 0V% b110 [% -b10xx0000 `% +b10x00000 `% 1a% b100 4& 1= @@ -698386,7 +698371,7 @@ b11 4& #1641593750 0V% b111 [% -b0xx00000 `% +b0x000000 `% 1a% b100 4& 1= @@ -699005,11 +698990,11 @@ b11 4& #1643093750 0V% 1c -bx000000 d -bx000000 m$ -bx000000 _% +bx0000000 d +bx0000000 m$ +bx0000000 _% b0 [% -bx000000 `% +bx0000000 `% 1a% b100 4& 1= @@ -699018,7 +699003,7 @@ b100 4& #1643106250 0c b1 ;% -b0xx000000 7% +b0x0000000 7% b101 4& 1= #1643112500 @@ -699634,7 +699619,7 @@ b11 4& #1644593750 0V% b1 [% -bx0000000 `% +b0 `% 1a% b100 4& 1= @@ -700253,7 +700238,6 @@ b11 4& #1646093750 0V% b10 [% -b0 `% 1a% b100 4& 1= @@ -703981,7 +703965,7 @@ b100 4& #1655106250 0c b10 ;% -b0xx00000000000011 7% +b0x000000000000011 7% b101 4& 1= #1655112500 @@ -708951,7 +708935,7 @@ b11 K% b0 >% b1100000000 <% b0 ;% -bx0000000000001100000000 7% +bx00000000000001100000000 7% b101 4& 1= #1667112500 @@ -742755,7 +742739,7 @@ b111 4& 0= #1747243750 x? -bx000000 D& +bx0000000 D& b111 F& b0 4& 1= @@ -742899,22 +742883,27 @@ b111 4& #1747537500 0= #1747543750 +0? b110 F& b0 4& 1= #1747550000 0= #1747556250 +bx0 ^% b1 4& 1= #1747562500 0= #1747568750 +bx00 ^% b10 4& 1= #1747575000 0= #1747581250 +0Y% +b0 ^% b11 4& 1= #1747587500 @@ -742968,7 +742957,7 @@ b11 4& #1747693750 0V% b10 [% -b0xx `% +b0x0 `% 1a% b100 4& 1= @@ -743038,27 +743027,22 @@ b111 4& #1747837500 0= #1747843750 -0? b101 F& b0 4& 1= #1747850000 0= #1747856250 -bx0 ^% b1 4& 1= #1747862500 0= #1747868750 -bx00 ^% b10 4& 1= #1747875000 0= #1747881250 -0Y% -b0 ^% b11 4& 1= #1747887500 @@ -743112,7 +743096,7 @@ b11 4& #1747993750 0V% b11 [% -b0xx0 `% +b0x00 `% 1a% b100 4& 1= @@ -743251,7 +743235,7 @@ b11 4& #1748293750 0V% b100 [% -b0xx00 `% +b0x000 `% 1a% b100 4& 1= @@ -743390,7 +743374,7 @@ b11 4& #1748593750 0V% b101 [% -b0xx000 `% +b0x0000 `% 1a% b100 4& 1= @@ -743529,7 +743513,7 @@ b11 4& #1748893750 0V% b110 [% -b0xx0000 `% +b0x00000 `% 1a% b100 4& 1= @@ -743668,7 +743652,7 @@ b11 4& #1749193750 0V% b111 [% -b0xx00000 `% +b0x000000 `% 1a% b100 4& 1= @@ -743807,11 +743791,11 @@ b11 4& #1749493750 0V% 1c -bx000000 d -bx000000 m$ -bx000000 _% +bx0000000 d +bx0000000 m$ +bx0000000 _% b0 [% -bx000000 `% +bx0000000 `% 1a% b100 4& 1= @@ -743820,7 +743804,7 @@ b100 4& #1749506250 0c b1 ;% -b0xx000000 7% +b0x0000000 7% b101 4& 1= #1749512500 @@ -743956,7 +743940,7 @@ b11 4& #1749793750 0V% b1 [% -bx0000000 `% +b0 `% 1a% b100 4& 1= @@ -744095,7 +744079,6 @@ b11 4& #1750093750 0V% b10 [% -b0 `% 1a% b100 4& 1= @@ -744936,7 +744919,7 @@ b100 4& #1751906250 0c b10 ;% -b0xx00000000000000 7% +b0x000000000000000 7% b101 4& 1= #1751912500 @@ -746047,7 +746030,7 @@ b100 4& 0c b1011 K% b0 ;% -bx0000000000000000000000 7% +bx00000000000000000000000 7% b101 4& 1= #1754312500 @@ -748718,7 +748701,7 @@ b111 4& 0= #1760043750 x? -bx000000 D& +bx0000000 D& b111 F& b0 4& 1= @@ -748862,22 +748845,27 @@ b111 4& #1760337500 0= #1760343750 +0? b110 F& b0 4& 1= #1760350000 0= #1760356250 +bx0 ^% b1 4& 1= #1760362500 0= #1760368750 +bx00 ^% b10 4& 1= #1760375000 0= #1760381250 +0Y% +b0 ^% b11 4& 1= #1760387500 @@ -748931,7 +748919,7 @@ b11 4& #1760493750 0V% b10 [% -b1xx `% +b1x0 `% 1a% b100 4& 1= @@ -749001,27 +748989,22 @@ b111 4& #1760637500 0= #1760643750 -0? b101 F& b0 4& 1= #1760650000 0= #1760656250 -bx0 ^% b1 4& 1= #1760662500 0= #1760668750 -bx00 ^% b10 4& 1= #1760675000 0= #1760681250 -0Y% -b0 ^% b11 4& 1= #1760687500 @@ -749075,7 +749058,7 @@ b11 4& #1760793750 0V% b11 [% -b1xx0 `% +b1x00 `% 1a% b100 4& 1= @@ -749214,7 +749197,7 @@ b11 4& #1761093750 0V% b100 [% -b1xx00 `% +b1x000 `% 1a% b100 4& 1= @@ -749353,7 +749336,7 @@ b11 4& #1761393750 0V% b101 [% -b1xx000 `% +b1x0000 `% 1a% b100 4& 1= @@ -749492,7 +749475,7 @@ b11 4& #1761693750 0V% b110 [% -b1xx0000 `% +b1x00000 `% 1a% b100 4& 1= @@ -749631,7 +749614,7 @@ b11 4& #1761993750 0V% b111 [% -b1xx00000 `% +b1x000000 `% 1a% b100 4& 1= @@ -749770,11 +749753,11 @@ b11 4& #1762293750 0V% 1c -bx000000 d -bx000000 m$ -bx000000 _% +bx0000000 d +bx0000000 m$ +bx0000000 _% b0 [% -bx000000 `% +bx0000000 `% 1a% b100 4& 1= @@ -749783,7 +749766,7 @@ b100 4& #1762306250 0c b1 ;% -b0xx000000 7% +b0x0000000 7% b101 4& 1= #1762312500 @@ -749919,7 +749902,7 @@ b11 4& #1762593750 0V% b1 [% -bx0000000 `% +b0 `% 1a% b100 4& 1= @@ -750058,7 +750041,6 @@ b11 4& #1762893750 0V% b10 [% -b0 `% 1a% b100 4& 1= @@ -750905,7 +750887,7 @@ b100 4& #1764706250 0c b10 ;% -b0xx00000000000001 7% +b0x000000000000001 7% b101 4& 1= #1764712500 @@ -752037,7 +752019,7 @@ b1011 K% b100000000 J b100000000 P% b0 ;% -bx0000000000000100000000 7% +bx00000000000000100000000 7% b101 4& 1= #1767112500 @@ -754713,7 +754695,7 @@ b111 4& 0= #1772843750 x? -bx000000 D& +bx0000000 D& b111 F& b0 4& 1= @@ -754857,22 +754839,27 @@ b111 4& #1773137500 0= #1773143750 +0? b110 F& b0 4& 1= #1773150000 0= #1773156250 +bx0 ^% b1 4& 1= #1773162500 0= #1773168750 +bx00 ^% b10 4& 1= #1773175000 0= #1773181250 +0Y% +b0 ^% b11 4& 1= #1773187500 @@ -754926,7 +754913,7 @@ b11 4& #1773293750 0V% b10 [% -b10xx `% +b10x0 `% 1a% b100 4& 1= @@ -754996,27 +754983,22 @@ b111 4& #1773437500 0= #1773443750 -0? b101 F& b0 4& 1= #1773450000 0= #1773456250 -bx0 ^% b1 4& 1= #1773462500 0= #1773468750 -bx00 ^% b10 4& 1= #1773475000 0= #1773481250 -0Y% -b0 ^% b11 4& 1= #1773487500 @@ -755070,7 +755052,7 @@ b11 4& #1773593750 0V% b11 [% -b10xx0 `% +b10x00 `% 1a% b100 4& 1= @@ -755209,7 +755191,7 @@ b11 4& #1773893750 0V% b100 [% -b10xx00 `% +b10x000 `% 1a% b100 4& 1= @@ -755348,7 +755330,7 @@ b11 4& #1774193750 0V% b101 [% -b10xx000 `% +b10x0000 `% 1a% b100 4& 1= @@ -755487,7 +755469,7 @@ b11 4& #1774493750 0V% b110 [% -b10xx0000 `% +b10x00000 `% 1a% b100 4& 1= @@ -755626,7 +755608,7 @@ b11 4& #1774793750 0V% b111 [% -b0xx00000 `% +b0x000000 `% 1a% b100 4& 1= @@ -755765,11 +755747,11 @@ b11 4& #1775093750 0V% 1c -bx000000 d -bx000000 m$ -bx000000 _% +bx0000000 d +bx0000000 m$ +bx0000000 _% b0 [% -bx000000 `% +bx0000000 `% 1a% b100 4& 1= @@ -755778,7 +755760,7 @@ b100 4& #1775106250 0c b1 ;% -b0xx000000 7% +b0x0000000 7% b101 4& 1= #1775112500 @@ -755914,7 +755896,7 @@ b11 4& #1775393750 0V% b1 [% -bx0000000 `% +b0 `% 1a% b100 4& 1= @@ -756053,7 +756035,6 @@ b11 4& #1775693750 0V% b10 [% -b0 `% 1a% b100 4& 1= @@ -756900,7 +756881,7 @@ b100 4& #1777506250 0c b10 ;% -b0xx00000000000001 7% +b0x000000000000001 7% b101 4& 1= #1777512500 @@ -758042,7 +758023,7 @@ b1011 K% b100100000 1" b100100000 8% b0 ;% -bx0000000000000100100000 7% +bx00000000000000100100000 7% b101 4& 1= #1779912500 diff --git a/sim/spi_neuron_top_runnetwork_tb.v b/sim/spi_neuron_top_runnetwork_tb.v index d12fd94..b843fd7 100644 --- a/sim/spi_neuron_top_runnetwork_tb.v +++ b/sim/spi_neuron_top_runnetwork_tb.v @@ -38,7 +38,7 @@ module tb; - localparam ADDR_WIDTH = 22; + localparam ADDR_WIDTH = 23; localparam DATA_WIDTH = 8; localparam N_INPUTS = 4; localparam N_NEURONS = 4; diff --git a/sim/spi_neuron_top_tb.v b/sim/spi_neuron_top_tb.v index 18433be..52fd80e 100644 --- a/sim/spi_neuron_top_tb.v +++ b/sim/spi_neuron_top_tb.v @@ -23,7 +23,7 @@ module tb; - localparam ADDR_WIDTH = 22; + localparam ADDR_WIDTH = 23; localparam DATA_WIDTH = 8; localparam N_INPUTS = 32; localparam N_NEURONS = 1; diff --git a/sim/spi_slave.vcd b/sim/spi_slave.vcd index 5c427a8..9474656 100644 --- a/sim/spi_slave.vcd +++ b/sim/spi_slave.vcd @@ -1,5 +1,5 @@ $date - Wed Sep 2 20:13:54 2026 + Wed Sep 2 20:58:00 2026 $end $version Icarus Verilog