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feat(v2): M2 Neural Processor Array, N_PROCESSORS resource sweep

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Implements M2 of the V2 roadmap: neural_processor_array.v instantiates
N_PROCESSORS independent neural_processor (M1) units, each with its
own dedicated point-to-point job/operand/result interface -- no shared
bus or mux at this level (arbitration is explicitly the Neural
Director's job, M5).

Verified with Verilator (tb_neural_processor_array.v, N_PROCESSORS=4):
7/7 tests pass, including a same-cycle 4-way concurrent launch with
different tile counts and a staggered-start test where a
later-launched, shorter job completes before an earlier-launched,
longer one -- confirming genuine independent concurrent execution
(§18/§34: a blocked/busy processor must not block the others).

Real resource/timing sweep for N_PROCESSORS in {1,2,4,8} (Yosys +
nextpnr-ecp5, real place&route): Fmax stays above the 80MHz target
throughout (159.11 -> 134.70 MHz), but MULT18X18D usage scales
linearly and reaches 88% of the LFE5U-45F's 72 DSPs at N=8 while
LUT/FF stay under 6% -- DSP, not LUT/FF/routing, is the first hard
ceiling on N_PROCESSORS at P_IN=8 (decisions.log DEC-0005). Measured
via a dedicated synthesis-only timing harness after the array's wide
per-processor buses were found to exhaust the device's TRELLIS_IO pin
budget as a bare top-level module beyond N=1 (errors.log ERR-0005) --
not a logic limit, an artifact of testing the array in isolation
before the Memory Manager/Director (M4/M5) exist to consume those
ports on-chip.

Full log trail (development/experiments/errors/decisions/simulation/
synthesis/timing/benchmark.log) in hardware/v2/logs/ per the project's
logging mandate.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
This commit is contained in:
michele
2026-09-05 14:15:11 +02:00
co-authored by Claude Sonnet 5
parent dc0b331d3e
commit 3026dcd997
41 changed files with 1076183 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files
hardware/v2/docs/ROADMAP.md
+5 -2
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@@ -13,8 +13,11 @@ reali, non solo scritto).
problemi CHECK, Fmax 183.12 MHz (ACC_WIDTH=32) — vedi problemi CHECK, Fmax 183.12 MHz (ACC_WIDTH=32) — vedi
`logs/experiments.log` EXP-0001/EXP-0002, `logs/errors.log` per 3 `logs/experiments.log` EXP-0001/EXP-0002, `logs/errors.log` per 3
bug reali trovati e risolti (2 del toolchain Icarus, 1 RTL). bug reali trovati e risolti (2 del toolchain Icarus, 1 RTL).
- [ ] **M2 — Processor Array** (`neural_processor_array.v`). Test 1/2/4/8 - [x] **M2 — Processor Array** (`neural_processor_array.v`). 1/2/4/8
processor, misurare timing/risorse/throughput/utilization. processor testati (sim concorrenza reale + sintesi/P&R reali).
Fmax sempre PASS a 80MHz (159.11→134.70 MHz). Scoperta: il DSP
(MULT18X18D), non LUT/FF, satura per primo (88% a N=8) — vedi
`logs/decisions.log` DEC-0005.
- [ ] **M3 — Buffers** (`activation_buffer.v`, `weight_buffer.v`, - [ ] **M3 — Buffers** (`activation_buffer.v`, `weight_buffer.v`,
`result_buffer.v`). `result_buffer.v`).
- [ ] **M4 — Memory Manager** (`memory_manager.v`, `prefetch_engine.v`), - [ ] **M4 — Memory Manager** (`memory_manager.v`, `prefetch_engine.v`),
hardware/v2/logs/benchmark.log
+22
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@@ -18,3 +18,25 @@ stall %, effective MAC/s: not yet meaningful at this milestone (single
isolated processor, no streaming benchmark harness yet -- deferred to isolated processor, no streaming benchmark harness yet -- deferred to
M2 once neural_processor_array.v exists and a real workload can be M2 once neural_processor_array.v exists and a real workload can be
timed end-to-end). timed end-to-end).
[2026-09-05] M2 Neural Processor Array, N_PROCESSORS sweep (P_IN=8,
ACC_WIDTH=32 each; synthesized via the timing harness, see errors.log
ERR-0005 for why)
| N_PROCESSORS | Fmax (POST-P&R) | LUT | FF | DSP (MULT18X18D) | DSP % of 72 |
|--------------|------------------|-----|------|-------------------|-------------|
| 1 | 159.11 MHz | 59 | 409 | 8 | 11% |
| 2 | 149.59 MHz | 106 | 786 | 16 | 22% |
| 4 | 151.01 MHz | 207 | 1540 | 32 | 44% |
| 8 | 134.70 MHz | 374 | 3048 | 64 | 88% |
All figures POST-P&R (real nextpnr-ecp5), all PASS at the 80MHz
target. LUT4 utilization stays under 6% of the device even at N=8;
DSP is the binding resource (see decisions.log DEC-0005), reaching 88%
at N=8 -- N_PROCESSORS=9 would already exceed the LFE5U-45F's 72
MULT18X18D budget at P_IN=8. Theoretical MAC/cycle (THEORETICAL, not
yet measured end-to-end -- no real workload/benchmark harness exists
until M9): N_PROCESSORS * P_IN MACs/cycle when all processors are
simultaneously streaming tiles (8, 16, 32, 64 for N=1/2/4/8 -- verified
achievable in principle by EXP-0003's concurrent/staggered simulation,
not yet measured as a sustained throughput number).
hardware/v2/logs/decisions.log
+47
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@@ -201,3 +201,50 @@ resolved by picking whichever answer looks more convenient.
STATUS: STATUS:
ACCEPTED ACCEPTED
---
DEC-0005
DATE: 2026-09-05
DECISION:
Treat DSP (MULT18X18D) budget, not LUT/FF/routing, as the primary
constraint when exploring the N_PROCESSORS x P_IN trade-off space
(§16) going forward.
WHY:
Real place&route measurement (EXP-0003) shows MULT18X18D usage
scaling linearly and reaching 88% of the LFE5U-45F-8BG381's 72 total
DSPs at N_PROCESSORS=8, P_IN=8 -- while LUT4/FF usage stays under 6%
at the SAME configuration and Fmax is still comfortably above the
80MHz target (134.70 MHz). This means the naive "just add more
processors" scaling (§8/§16) hits a hard DSP ceiling around
N_PROCESSORS=9 at P_IN=8, long before LUT/FF/routing/timing become
relevant -- the opposite of what LUT/FF utilization alone would
suggest if read in isolation.
EVIDENCE:
experiments.log EXP-0003 -- MULT18X18D 8/16/32/64 (11%/22%/44%/88% of
72) at N_PROCESSORS 1/2/4/8, LUT4 under 6% throughout, Fmax PASS at
80MHz throughout (159.11/149.59/151.01/134.70 MHz).
ALTERNATIVES:
Assume LUT/FF/routing congestion would be the limiting factor (the
naive expectation for "more parallel copies of a datapath"). Rejected
by direct measurement, not assumed -- §16 explicitly requires
choosing the final configuration "sulla base del throughput effettivo
... non dell'utilizzo massimo delle risorse", and knowing WHICH
resource binds first is a prerequisite for that.
RESULT:
Future N_PROCESSORS x P_IN sweeps (§16, deferred to a dedicated
scripts/sweep/ run per §31) should budget MULT18X18D count explicitly
(N_PROCESSORS * P_IN <= ~72, minus whatever the rest of the real
system needs once M4/PSRAM integration lands) rather than only
tracking LUT/FF. A smaller P_IN with more N_PROCESSORS (or vice versa)
is a live trade-off worth exploring precisely because of this ceiling,
not merely a stylistic choice.
STATUS:
ACCEPTED
hardware/v2/logs/development.log
+29
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@@ -59,3 +59,32 @@ errors: vedi errors.log ERR-0001, ERR-0002, ERR-0003, ERR-0004.
decision: vedi decisions.log DEC-0002, DEC-0003, DEC-0004. decision: vedi decisions.log DEC-0002, DEC-0003, DEC-0004.
next_action: M2 -- neural_processor_array.v, sweep N_PROCESSORS next_action: M2 -- neural_processor_array.v, sweep N_PROCESSORS
(1,2,4,8), misura timing/risorse/throughput/utilization reali. (1,2,4,8), misura timing/risorse/throughput/utilization reali.
[2026-09-05T14:30:00Z] commit=dc0b331 session=v2-M2-processor-array
module: hardware/v2/rtl/neural_processor_array.v + hardware/v2/sim/
tb_neural_processor_array.v + hardware/v2/synthesis/
harness_neural_processor_array.v
action: implementato M2 -- Neural Processor Array, N_PROCESSORS
parametrico, ogni processore con interfaccia job/operand/result
dedicata (nessun bus condiviso/mux a questo livello, §7). Testato
N_PROCESSORS=4 con esecuzione concorrente reale (lancio simultaneo
di 4 job diversi, più un test a partenza sfalsata) e con lo sweep
reale N_PROCESSORS={1,2,4,8} per sintesi/place&route.
reason: roadmap M2.
result: 7/7 test PASS (Verilator), confermata esecuzione concorrente e
indipendente (un job più corto lanciato dopo completa prima di uno
più lungo lanciato prima -- non c'e' serializzazione nascosta).
Sintesi/P&R reali per N=1/2/4/8: 0 problemi CHECK, scaling lineare
delle risorse, Fmax sempre PASS a 80MHz (159.11/149.59/151.01/134.70
MHz). Scoperta reale non assunta: il DSP (MULT18X18D) e' la prima
risorsa a saturare (88% a N=8), non LUT/FF (sotto il 6% anche a
N=8) -- vedi decisions.log DEC-0005.
errors: ERR-0005 (artefatto di sintesi da pin-count, non un bug RTL --
workaround con un harness dedicato, vedi errors.log). Un primo
tentativo di harness alimentava dati identici a ogni processore/lane
MAC, e Yosys deduplicava silenziosamente tutto a 1x indipendentemente
da N -- scoperto verificando che lo scaling fosse davvero lineare
prima di fidarsi dei numeri.
decision: vedi decisions.log DEC-0005.
next_action: M3 -- activation_buffer.v / weight_buffer.v /
result_buffer.v (profondita' parametrica, valutare BRAM mapping).
hardware/v2/logs/errors.log
+26
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@@ -98,3 +98,29 @@ NOTE: this session's V1 certification campaign (docs/validation/,
this V2-kickoff session (V1 is frozen, not to be touched) and was this V2-kickoff session (V1 is frozen, not to be touched) and was
not performed. See decisions.log DEC-0004. not performed. See decisions.log DEC-0004.
STATUS: OPEN CAVEAT, not actioned in this session by design. STATUS: OPEN CAVEAT, not actioned in this session by design.
ERR-0005 (synthesis measurement artifact, WORKED AROUND, not an RTL bug)
DATE: 2026-09-05
MODULE: hardware/v2/rtl/neural_processor_array.v
SYMPTOM: synthesizing neural_processor_array as a bare top-level
module (every per-processor job/operand/result field exposed as a
real TRELLIS_IO pin) works at N_PROCESSORS=1 but fails place&route
at N_PROCESSORS=2 with "Unable to place cell ...$tr_io, no BELs
remaining to implement cell type 'TRELLIS_IO'".
ROOT CAUSE: not a logic/timing limit -- the LFE5U-45F-8BG381 package
has 245 TRELLIS_IO pins total; the array's wide per-processor buses
(input_data/weight_data alone are DATA_WIDTH*P_IN*N_PROCESSORS bits)
exceed that budget once N_PROCESSORS>=2, purely because these ports
have no on-chip consumer yet (the Memory Manager/M4 and Neural
Director/M5 that will drive them in the real system don't exist
yet).
WORKAROUND: hardware/v2/synthesis/harness_neural_processor_array.v --
a synthesis-only wrapper (NOT part of rtl/, not a functional
deliverable) that drives all wide buses from an internal free-
running LFSR and reduces outputs to a small checksum, keeping only
clk/rst/seed/checksum as real top-level pins. See its own header
comment and experiments.log EXP-0003 for the resulting real
resource/Fmax numbers.
STATUS: WORKED AROUND. Will become moot once M4/M5 exist and the array
is synthesized as part of a larger design with on-chip ports instead
of a bare top-level module.
hardware/v2/logs/experiments.log
+61
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@@ -98,3 +98,64 @@ decision: ACC_WIDTH=32 remains the M1 default (matches V1 exactly for
comparison run). comparison run).
next_action: revisit ACC_WIDTH choice during M10 (Optimization) with a next_action: revisit ACC_WIDTH choice during M10 (Optimization) with a
real seed sweep, not before. real seed sweep, not before.
EXP-0003
timestamp: 2026-09-05T14:30:00Z
git_commit: dc0b331 (+ uncommitted M2 work)
session: v2-M2-processor-array
module: hardware/v2/rtl/neural_processor_array.v
configuration: N_PROCESSORS in {1,2,4,8}, P_IN=8, ACC_WIDTH=32 each
action: M2 -- functional array + real N_PROCESSORS resource/timing sweep
command (sim, Verilator): verilator --binary --timing -j 0 -Wno-fatal
--top-module tb -o /tmp/vtb_array hardware/v2/rtl/neural_processor.v
hardware/v2/rtl/neural_processor_array.v
hardware/v2/sim/tb_neural_processor_array.v && /tmp/vtb_array
command (synth/timing): see hardware/v2/synthesis/harness_n{1,2,4,8}/
(yosys.log, nextpnr.log) -- synthesized via
hardware/v2/synthesis/harness_neural_processor_array.v, a
synthesis-only timing harness (see its own header comment and
errors.log ERR-0005 for why the array cannot be synthesized as a
bare top-level module beyond N_PROCESSORS=1 without it).
result:
SIMULATED (N_PROCESSORS=4, tb_neural_processor_array.v): 7/7 tests
PASS -- single-processor sanity, 4 processors launched the SAME
cycle with different tile counts (finish at different times,
proving true concurrency), and a staggered-start test (processor 1
launched mid-way through processor 0's 6-tile job, both complete
correctly and independently, confirming §18/§34's "un processor
bloccato non deve bloccare gli altri").
SYNTHESIZED (resource scaling, harness): perfectly linear in
N_PROCESSORS, confirming no unintended resource sharing:
N=1: LUT=59 FF=409 MULT18X18D=8 CCU2C=96
N=2: LUT=106 FF=786 MULT18X18D=16 CCU2C=192
N=4: LUT=207 FF=1540 MULT18X18D=32 CCU2C=384
N=8: LUT=374 FF=3048 MULT18X18D=64 CCU2C=768
0 CHECK problems in every configuration.
POST-P&R (real nextpnr-ecp5, --45k --package CABGA381 --speed 8
--freq 80): Fmax PASS at 80MHz in every configuration:
N=1: 159.11 MHz N=2: 149.59 MHz
N=4: 151.01 MHz N=8: 134.70 MHz
Fmax decreases gently with N (routing congestion), never close to
failing the 80MHz target up to N=8.
REAL RESOURCE CEILING FOUND (not assumed, measured via nextpnr's own
device utilisation report): MULT18X18D usage is 22%/44%/88% of the
LFE5U-45F's 72 total DSPs at N=2/4/8 respectively, while LUT4/FF
usage stays under 6% even at N=8. **DSP (not LUT/FF/routing) is
the first hard ceiling as N_PROCESSORS grows at P_IN=8** --
N_PROCESSORS=9 would already exceed the device's 72 MULT18X18D
budget at P_IN=8, before accounting for any multipliers the rest
of a real system (Memory Manager, PSRAM path, etc.) might need.
See decisions.log DEC-0005 and benchmark.log.
errors: ERR-0005 (toplevel-pin-count synthesis artifact, worked around
with the timing harness -- see errors.log); a first harness attempt
fed every processor and every MAC lane identical LFSR-derived data,
which Yosys correctly (from pure logic-equivalence) collapsed via
CSE down to 1 processor's worth of multipliers regardless of N --
fixed by giving each processor AND each of its P_IN MAC lanes a
distinct bit-rotated data source, confirmed by the corrected,
properly-linear MULT18X18D counts above.
decision: see decisions.log DEC-0005 (DSP is the binding constraint,
not LUT/FF -- informs how the N_PROCESSORS x P_IN trade-off should
be explored going forward).
next_action: M3 -- activation_buffer.v / weight_buffer.v /
result_buffer.v.
hardware/v2/logs/simulation.log
+13
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@@ -15,3 +15,16 @@ PASS/FAIL: 7/7 PASS (ACC_WIDTH=32); 7/7 PASS (ACC_WIDTH=24, EXP-0002)
bit-exact result: V1.y === V2.result_data for every case, both widths bit-exact result: V1.y === V2.result_data for every case, both widths
stall cycles / memory wait / utilization: N/A (no Memory Manager yet, stall cycles / memory wait / utilization: N/A (no Memory Manager yet,
M1 operands fed directly by testbench per the roadmap) M1 operands fed directly by testbench per the roadmap)
[2026-09-05] EXP-0003 -- hardware/v2/sim/tb_neural_processor_array.v
(N_PROCESSORS=4)
test: 7 cases (single-processor sanity; 4-way same-cycle concurrent
launch with different tile counts; staggered-start 2-processor test)
simulator: Verilator 5.050 (--binary --timing)
PASS/FAIL: 7/7 PASS
bit-exact result: N/A at this milestone (hand-computed expected
values, arithmetic itself already bit-exact-certified vs V1 at M1)
concurrency: confirmed genuine -- in the staggered test, the
later-launched, shorter job (processor 1) completes BEFORE the
earlier-launched, longer job (processor 0), proving independent
progress rather than serialization.
hardware/v2/logs/synthesis.log
+13
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@@ -14,3 +14,16 @@ CHECK: 0 problems. 36 warnings, all "multiple conflicting drivers for
LUT: 49 FF: 509 DSP(MULT18X18D): 8 BRAM: 0 CCU2C: 88 LUT: 49 FF: 509 DSP(MULT18X18D): 8 BRAM: 0 CCU2C: 88
CHECK: 0 problems, same 36 benign warnings as EXP-0001. CHECK: 0 problems, same 36 benign warnings as EXP-0001.
Log: hardware/v2/synthesis/neural_processor_p8_acc24/yosys.log Log: hardware/v2/synthesis/neural_processor_p8_acc24/yosys.log
[2026-09-05] EXP-0003 -- neural_processor_array via
harness_neural_processor_array.v (synthesis-only wrapper, see
errors.log ERR-0005), N_PROCESSORS in {1,2,4,8}, P_IN=8
N=1: LUT=59 FF=409 MULT18X18D=8 CCU2C=96
N=2: LUT=106 FF=786 MULT18X18D=16 CCU2C=192
N=4: LUT=207 FF=1540 MULT18X18D=32 CCU2C=384
N=8: LUT=374 FF=3048 MULT18X18D=64 CCU2C=768
CHECK: 0 problems in all 4 configurations. Perfectly linear scaling in
N confirms no unintended cross-processor resource sharing (a first,
flawed harness attempt fed identical data to every processor/lane
and Yosys silently deduplicated down to 1x regardless of N -- caught
by checking for exactly this linearity before trusting the numbers).
hardware/v2/logs/timing.log
+11
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@@ -20,3 +20,14 @@ Delta vs ACC_WIDTH=32: -6.91 MHz (-3.8%) despite FEWER resources --
(no seed sweep run to confirm either way -- see experiments.log (no seed sweep run to confirm either way -- see experiments.log
EXP-0002 and benchmark.log). Log: hardware/v2/synthesis/ EXP-0002 and benchmark.log). Log: hardware/v2/synthesis/
neural_processor_p8_acc24/nextpnr.log neural_processor_p8_acc24/nextpnr.log
[2026-09-05] EXP-0003 -- N_PROCESSORS sweep (P_IN=8), real nextpnr-ecp5
--45k --package CABGA381 --speed 8 --freq 80 --lpf-allow-unconstrained
N=1: Fmax=159.11 MHz PASS MULT18X18D 8/72 (11%)
N=2: Fmax=149.59 MHz PASS MULT18X18D 16/72 (22%)
N=4: Fmax=151.01 MHz PASS MULT18X18D 32/72 (44%)
N=8: Fmax=134.70 MHz PASS MULT18X18D 64/72 (88%)
TRELLIS_IO stays at 18/245 (7%) throughout (harness has only
clk/rst/seed/checksum as real pins, by design -- see ERR-0005).
See decisions.log DEC-0005: DSP, not Fmax or LUT/FF, is the resource
that will first prevent scaling N_PROCESSORS further at P_IN=8.
hardware/v2/rtl/neural_processor_array.v
+90
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@@ -0,0 +1,90 @@
// ============================================================
// FPGA-Neural V2 -- Neural Processor Array (M2, docs/v2-description.md §8)
//
// Instantiates N_PROCESSORS independent neural_processor units (M1),
// each with its OWN dedicated point-to-point job/operand/result
// interface -- no shared bus, no arbitration, no mux at this level
// (§7: "evitare grandi mux dinamici come quelli dell'architettura
// V1"). Arbitrating which processor gets which job is explicitly the
// Neural Director's job (M5) and the Memory Manager's job (M4), not
// this array's -- at M2 the array is purely a resource/scaling
// vehicle: does the design synthesize, route, and run correctly with
// N independent copies, and how do LUT/FF/DSP/Fmax scale with N.
//
// Per-processor ports are flattened buses (port[i] occupies bits
// [i*WIDTH +: WIDTH]), the same convention used throughout V1's own
// multi-lane interfaces (e.g. x_bus/weights_bus).
//
// A blocked/errored processor (NP_ERROR, M1) never affects any other
// processor's ports -- each is wired independently, confirmed in
// tb_neural_processor_array.v by running N_PROCESSORS concurrently
// with staggered start times and one deliberately-slower job.
// ============================================================
module neural_processor_array #(
parameter DATA_WIDTH = 8,
parameter P_IN = 8,
parameter ACC_WIDTH = 32,
parameter N_PROCESSORS = 4
)(
input clk,
input rst,
input [N_PROCESSORS-1:0] job_valid,
output [N_PROCESSORS-1:0] job_ready,
input [16*N_PROCESSORS-1:0] job_node_id,
input signed [DATA_WIDTH*N_PROCESSORS-1:0] job_bias,
input [2*N_PROCESSORS-1:0] job_activation,
input [N_PROCESSORS-1:0] operand_valid,
output [N_PROCESSORS-1:0] operand_ready,
input signed [DATA_WIDTH*P_IN*N_PROCESSORS-1:0] input_data,
input signed [DATA_WIDTH*P_IN*N_PROCESSORS-1:0] weight_data,
input [N_PROCESSORS-1:0] tile_last,
output [N_PROCESSORS-1:0] result_valid,
input [N_PROCESSORS-1:0] result_ready,
output signed [DATA_WIDTH*N_PROCESSORS-1:0] result_data,
output [16*N_PROCESSORS-1:0] result_node_id,
output [4*N_PROCESSORS-1:0] np_state,
output [N_PROCESSORS-1:0] np_error
);
genvar p;
generate
for (p = 0; p < N_PROCESSORS; p = p + 1) begin : GEN_NP
neural_processor #(
.DATA_WIDTH(DATA_WIDTH),
.P_IN(P_IN),
.ACC_WIDTH(ACC_WIDTH)
) u_np (
.clk(clk),
.rst(rst),
.job_valid (job_valid[p]),
.job_ready (job_ready[p]),
.job_node_id (job_node_id[p*16 +: 16]),
.job_bias (job_bias[p*DATA_WIDTH +: DATA_WIDTH]),
.job_activation (job_activation[p*2 +: 2]),
.operand_valid (operand_valid[p]),
.operand_ready (operand_ready[p]),
.input_data (input_data[p*DATA_WIDTH*P_IN +: DATA_WIDTH*P_IN]),
.weight_data (weight_data[p*DATA_WIDTH*P_IN +: DATA_WIDTH*P_IN]),
.tile_last (tile_last[p]),
.result_valid (result_valid[p]),
.result_ready (result_ready[p]),
.result_data (result_data[p*DATA_WIDTH +: DATA_WIDTH]),
.result_node_id (result_node_id[p*16 +: 16]),
.np_state (np_state[p*4 +: 4]),
.np_error (np_error[p])
);
end
endgenerate
endmodule
hardware/v2/sim/tb_neural_processor_array.v
+210
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@@ -0,0 +1,210 @@
`timescale 1ns/1ps
// ============================================================
// M2 testbench (docs/v2-description.md §8/§18/§34): neural_processor_array.v
// with N_PROCESSORS=4. Verified with Verilator (see hardware/v2/logs/
// decisions.log DEC-0004 -- Icarus Verilog v13.0 is not trusted for
// hardware/v2 testbenches).
//
// Coverage:
// - TEST 1: single processor (index 0), sanity check that the
// array's per-processor bus flattening/slicing is wired correctly
// (arithmetic itself already bit-exact-certified at M1).
// - TEST 2: all 4 processors launched on the SAME cycle with
// DIFFERENT jobs (different tile counts, so they finish at
// different times) -- proves genuine concurrent, independent
// execution, not a hidden shared resource serializing them.
// - TEST 3: staggered start (processor 1 launched while processor 0
// is still mid-job) -- proves a busy processor does not block a
// job being accepted by another (§18/§34: "un processor bloccato
// non deve bloccare gli altri").
// ============================================================
module tb;
localparam DATA_WIDTH = 8;
localparam P_IN = 8;
localparam ACC_WIDTH = 32;
localparam N_PROCESSORS = 4;
reg clk, rst;
initial begin clk = 0; forever #5 clk = ~clk; end
reg [N_PROCESSORS-1:0] job_valid;
wire [N_PROCESSORS-1:0] job_ready;
reg [16*N_PROCESSORS-1:0] job_node_id;
reg signed [DATA_WIDTH*N_PROCESSORS-1:0] job_bias;
reg [2*N_PROCESSORS-1:0] job_activation;
reg [N_PROCESSORS-1:0] operand_valid;
wire [N_PROCESSORS-1:0] operand_ready;
reg signed [DATA_WIDTH*P_IN*N_PROCESSORS-1:0] input_data;
reg signed [DATA_WIDTH*P_IN*N_PROCESSORS-1:0] weight_data;
reg [N_PROCESSORS-1:0] tile_last;
wire [N_PROCESSORS-1:0] result_valid;
reg [N_PROCESSORS-1:0] result_ready;
wire signed [DATA_WIDTH*N_PROCESSORS-1:0] result_data;
wire [16*N_PROCESSORS-1:0] result_node_id;
wire [4*N_PROCESSORS-1:0] np_state;
wire [N_PROCESSORS-1:0] np_error;
neural_processor_array #(
.DATA_WIDTH(DATA_WIDTH), .P_IN(P_IN), .ACC_WIDTH(ACC_WIDTH),
.N_PROCESSORS(N_PROCESSORS)
) dut (
.clk(clk), .rst(rst),
.job_valid(job_valid), .job_ready(job_ready),
.job_node_id(job_node_id), .job_bias(job_bias), .job_activation(job_activation),
.operand_valid(operand_valid), .operand_ready(operand_ready),
.input_data(input_data), .weight_data(weight_data), .tile_last(tile_last),
.result_valid(result_valid), .result_ready(result_ready),
.result_data(result_data), .result_node_id(result_node_id),
.np_state(np_state), .np_error(np_error)
);
integer errors, tests;
// ---- per-processor job launch task: fires the job handshake and
// every tile for processor `idx`, WITHOUT waiting for
// completion (so the caller can launch several processors
// back-to-back / interleaved and observe true concurrency). ----
task automatic launch_job(
input integer idx,
input integer n_tiles,
input signed [DATA_WIDTH-1:0] lane_x,
input signed [DATA_WIDTH-1:0] lane_w,
input signed [DATA_WIDTH-1:0] bias,
input [1:0] activation,
input [15:0] node_id
);
integer t, k;
reg signed [DATA_WIDTH*P_IN-1:0] tile_data;
begin
@(posedge clk);
job_node_id[idx*16 +: 16] = node_id;
job_bias[idx*DATA_WIDTH +: DATA_WIDTH] = bias;
job_activation[idx*2 +: 2] = activation;
job_valid[idx] = 1'b1;
while (!job_ready[idx]) @(posedge clk);
@(posedge clk);
job_valid[idx] = 1'b0;
tile_data = {DATA_WIDTH*P_IN{1'b0}};
for (k = 0; k < P_IN; k = k + 1)
tile_data[k*DATA_WIDTH +: DATA_WIDTH] = lane_x;
for (t = 0; t < n_tiles; t = t + 1) begin
input_data[idx*DATA_WIDTH*P_IN +: DATA_WIDTH*P_IN] = tile_data;
for (k = 0; k < P_IN; k = k + 1)
weight_data[idx*DATA_WIDTH*P_IN + k*DATA_WIDTH +: DATA_WIDTH] = lane_w;
tile_last[idx] = (t == n_tiles - 1);
operand_valid[idx] = 1'b1;
while (!operand_ready[idx]) @(posedge clk);
@(posedge clk);
end
operand_valid[idx] = 1'b0;
tile_last[idx] = 1'b0;
end
endtask
// ---- wait for processor `idx` to produce a result, check it,
// then let it fully return to idle. ----
task automatic collect_result(
input integer idx,
input signed [DATA_WIDTH-1:0] expect_y,
input [15:0] expect_node_id
);
integer wd;
reg signed [DATA_WIDTH-1:0] got_y;
reg [15:0] got_node;
begin
tests = tests + 1;
result_ready[idx] = 1'b1;
wd = 0;
while (!result_valid[idx] && wd < 300) begin
@(posedge clk);
wd = wd + 1;
end
if (!result_valid[idx]) begin
$display("FAIL proc=%0d: no result_valid within watchdog", idx);
errors = errors + 1;
end else begin
got_y = result_data[idx*DATA_WIDTH +: DATA_WIDTH];
got_node = result_node_id[idx*16 +: 16];
@(posedge clk);
if (got_y !== expect_y || got_node !== expect_node_id) begin
$display("FAIL proc=%0d: got y=%0d node=%0d, expected y=%0d node=%0d",
idx, got_y, got_node, expect_y, expect_node_id);
errors = errors + 1;
end else begin
$display("PASS proc=%0d: y=%0d node=%0d", idx, got_y, got_node);
end
end
while (!job_ready[idx]) @(posedge clk);
end
endtask
integer i;
initial begin
errors = 0;
tests = 0;
rst = 1;
job_valid = 0; job_node_id = 0; job_bias = 0; job_activation = 0;
operand_valid = 0; input_data = 0; weight_data = 0; tile_last = 0;
result_ready = 0;
repeat(4) @(posedge clk);
rst = 0;
@(posedge clk);
// ---- TEST 1: single processor (idx 0), 2 tiles, ACT_RELU ----
// 16 inputs of x=3,w=2 -> acc=96, bias=0, relu(96)=96
launch_job(0, 2, 8'sd3, 8'sd2, 8'sd0, 2'd1, 16'd101);
collect_result(0, 8'sd96, 16'd101);
// ---- TEST 2: all 4 processors launched the SAME cycle,
// different tile counts (1,2,3,4) so they finish at different
// times -- proves genuine independent concurrent execution. ----
fork
launch_job(0, 1, 8'sd1, 8'sd1, 8'sd0, 2'd1, 16'd200); // sum=8
launch_job(1, 2, 8'sd1, 8'sd1, 8'sd0, 2'd1, 16'd201); // sum=16
launch_job(2, 3, 8'sd1, 8'sd1, 8'sd0, 2'd1, 16'd202); // sum=24
launch_job(3, 4, 8'sd1, 8'sd1, 8'sd0, 2'd1, 16'd203); // sum=32
join
fork
collect_result(0, 8'sd8, 16'd200);
collect_result(1, 8'sd16, 16'd201);
collect_result(2, 8'sd24, 16'd202);
collect_result(3, 8'sd32, 16'd203);
join
// ---- TEST 3: staggered start -- processor 0 launched first
// with a long (6-tile) job, processor 1 launched a few cycles
// later while processor 0 is still mid-job. Both must
// complete correctly and independently. ----
fork
begin
launch_job(0, 6, 8'sd2, 8'sd2, 8'sd0, 2'd1, 16'd300); // sum=8*6*... wait per-tile sum=8*4=32*6=192->sat 127
end
begin
repeat(3) @(posedge clk); // let processor 0 get well underway first
launch_job(1, 1, 8'sd5, 8'sd5, 8'sd0, 2'd0, 16'd301); // sum=8*25=200, ACT_NONE saturates to 127
end
join
fork
collect_result(0, 8'sd127, 16'd300); // 8 lanes * 2*2=4 -> 32/tile *6 tiles=192, ACT_RELU saturate +127
collect_result(1, 8'sd127, 16'd301); // 8 lanes * 5*5=25 -> 200, ACT_NONE saturate +127
join
$display("========================================");
if (errors == 0)
$display("ALL %0d TESTS PASSED (N_PROCESSORS=%0d array, concurrent/staggered/independent)", tests, N_PROCESSORS);
else
$display("FAILED: %0d/%0d test(s) had errors -- see messages above", errors, tests);
$display("========================================");
$finish;
end
endmodule
hardware/v2/synthesis/harness_n1/nextpnr.log
+196
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@@ -0,0 +1,196 @@
Info: Logic utilisation before packing:
Info: Total LUT4s: 251/43848 0%
Info: logic LUTs: 59/43848 0%
Info: carry LUTs: 192/43848 0%
Info: RAM LUTs: 0/ 5481 0%
Info: RAMW LUTs: 0/10962 0%
Info: Total DFFs: 409/43848 0%
Info: Packing IOs..
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 196 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info: promoting clock net clk$TRELLIS_IO_IN to global network
Info: Checksum: 0x181a2c1f
Info: Device utilisation:
Info: TRELLIS_IO: 18/ 245 7%
Info: DCCA: 1/ 56 1%
Info: DP16KD: 0/ 108 0%
Info: MULT18X18D: 8/ 72 11%
Info: ALU54B: 0/ 36 0%
Info: EHXPLLL: 0/ 4 0%
Info: EXTREFB: 0/ 2 0%
Info: DCUA: 0/ 2 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 0/ 160 0%
Info: SIOLOGIC: 0/ 85 0%
Info: GSR: 0/ 1 0%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 0/ 1 0%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 409/ 43848 0%
Info: TRELLIS_COMB: 289/ 43848 0%
Info: TRELLIS_RAMW: 0/ 5481 0%
Info: Placed 0 cells based on constraints.
Info: Creating initial analytic placement for 279 cells, random placement wirelen = 31995.
Info: at initial placer iter 0, wirelen = 1151
Info: at initial placer iter 1, wirelen = 1128
Info: at initial placer iter 2, wirelen = 989
Info: at initial placer iter 3, wirelen = 975
Info: Running main analytical placer, max placement attempts per cell = 65703.
Info: at iteration #1, type ALL: wirelen solved = 965, spread = 6362, legal = 6299; time = 0.01s
Info: at iteration #2, type ALL: wirelen solved = 1001, spread = 6347, legal = 6570; time = 0.00s
Info: at iteration #3, type ALL: wirelen solved = 1047, spread = 6112, legal = 6089; time = 0.00s
Info: at iteration #4, type ALL: wirelen solved = 1111, spread = 6479, legal = 6502; time = 0.00s
Info: at iteration #5, type ALL: wirelen solved = 1125, spread = 6467, legal = 6611; time = 0.00s
Info: at iteration #6, type ALL: wirelen solved = 1231, spread = 6741, legal = 6845; time = 0.00s
Info: at iteration #7, type ALL: wirelen solved = 1289, spread = 6529, legal = 6566; time = 0.00s
Info: at iteration #8, type ALL: wirelen solved = 1241, spread = 6711, legal = 6886; time = 0.00s
Info: HeAP Placer Time: 0.06s
Info: of which solving equations: 0.03s
Info: of which spreading cells: 0.01s
Info: of which strict legalisation: 0.00s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 322, wirelen = 6089
Info: at iteration #5: temp = 0.000000, timing cost = 122, wirelen = 4437
Info: at iteration #10: temp = 0.000000, timing cost = 143, wirelen = 3970
Info: at iteration #15: temp = 0.000000, timing cost = 136, wirelen = 3894
Info: at iteration #16: temp = 0.000000, timing cost = 120, wirelen = 3909
Info: SA placement time 0.09s
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 141.70 MHz (PASS at 80.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 5.80 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 1.39 ns
Info: Slack histogram:
Info: legend: * represents 1 endpoint(s)
Info: + represents [1,1) endpoint(s)
Info: [ 5443, 5758) |*************************+
Info: [ 5758, 6073) |*****************************************+
Info: [ 6073, 6388) |*****************+
Info: [ 6388, 6703) |****************+
Info: [ 6703, 7018) |*+
Info: [ 7018, 7333) |**+
Info: [ 7333, 7648) |*+
Info: [ 7648, 7963) |******+
Info: [ 7963, 8278) |*******+
Info: [ 8278, 8593) |
Info: [ 8593, 8908) |**************+
Info: [ 8908, 9223) |********+
Info: [ 9223, 9538) |***************
Info: [ 9538, 9853) |**********************************+
Info: [ 9853, 10168) |************************************************************
Info: [ 10168, 10483) |*****************************************+
Info: [ 10483, 10798) |********************************************+
Info: [ 10798, 11113) |*********************+
Info: [ 11113, 11428) |**************+
Info: [ 11428, 11743) |******************************
Info: Checksum: 0x82e6001e
Info: Routing globals...
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 1745 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 166 833 | 166 833 | 919| 0.30 0.30|
Info: 1953 | 200 1630 | 34 797 | 0| 0.11 0.41|
Info: Routing complete.
Info: Router1 time 0.41s
Info: Checksum: 0xd0a27c89
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source dut.GEN_NP[0].u_np.x0[1]_TRELLIS_FF_Q.Q
Info: routing 1.92 2.32 Net dut.GEN_NP[0].u_np.x0[0][7] (74,43) -> (65,22)
Info: Sink dut.GEN_NP[0].u_np.product_comb[7]_MULT18X18D_P9.A0
Info: Defined in:
Info: hardware/v2/rtl/neural_processor.v:99.44-99.46
Info: logic 3.07 5.38 Source dut.GEN_NP[0].u_np.product_comb[7]_MULT18X18D_P9.P1
Info: routing 0.90 6.28 Net dut.GEN_NP[0].u_np.product_comb[7][1] (65,22) -> (65,23)
Info: Sink dut.GEN_NP[0].u_np.prod1[7]_TRELLIS_FF_Q_1.M
Info: Defined in:
Info: hardware/v2/rtl/neural_processor.v:135.34-135.46
Info: setup 0.00 6.28 Source dut.GEN_NP[0].u_np.prod1[7]_TRELLIS_FF_Q_1.M
Info: 3.46 ns logic, 2.82 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info: type curr total name
Info: source 0.00 0.00 Source rst$tr_io.O
Info: routing 2.56 2.56 Net rst$TRELLIS_IO_IN (67,0) -> (74,32)
Info: Sink dut.GEN_NP[0].u_np.valid0_TRELLIS_FF_Q_DI_LUT4_D.C
Info: Defined in:
Info: hardware/v2/synthesis/harness_neural_processor_array.v:30.12-30.15
Info: logic 0.18 2.74 Source dut.GEN_NP[0].u_np.valid0_TRELLIS_FF_Q_DI_LUT4_D.F
Info: routing 0.83 3.57 Net dut.GEN_NP[0].u_np.valid0_TRELLIS_FF_Q_DI_LUT4_D_Z (74,32) -> (83,33)
Info: Sink dut.GEN_NP[0].u_np.last0_TRELLIS_FF_Q_LSR_LUT4_Z.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 3.75 Source dut.GEN_NP[0].u_np.last0_TRELLIS_FF_Q_LSR_LUT4_Z.F
Info: routing 0.22 3.98 Net dut.GEN_NP[0].u_np.last0_TRELLIS_FF_Q_LSR (83,33) -> (83,33)
Info: Sink dut.GEN_NP[0].u_np.last0_TRELLIS_FF_Q.LSR
Info: setup 0.29 4.26 Source dut.GEN_NP[0].u_np.last0_TRELLIS_FF_Q.LSR
Info: 0.65 ns logic, 3.62 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source chk_TRELLIS_FF_Q.Q
Info: routing 1.00 1.39 Net checksum[0]$TRELLIS_IO_OUT (86,33) -> (90,32)
Info: Sink checksum[0]$tr_io.I
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: 0.40 ns logic, 1.00 ns routing
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 159.11 MHz (PASS at 80.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 4.26 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 1.39 ns
Info: Slack histogram:
Info: legend: * represents 1 endpoint(s)
Info: + represents [1,1) endpoint(s)
Info: [ 6215, 6495) |*********************************************************+
Info: [ 6495, 6775) |*******************************************+
Info: [ 6775, 7055) |***********+
Info: [ 7055, 7335) |+
Info: [ 7335, 7615) |
Info: [ 7615, 7895) |
Info: [ 7895, 8175) |+
Info: [ 8175, 8455) |****+
Info: [ 8455, 8735) |************+
Info: [ 8735, 9015) |**************+
Info: [ 9015, 9295) |***********+
Info: [ 9295, 9575) |****************************+
Info: [ 9575, 9855) |*****************************************************+
Info: [ 9855, 10135) |************************************************************
Info: [ 10135, 10415) |************************************+
Info: [ 10415, 10695) |***************+
Info: [ 10695, 10975) |******************************
Info: [ 10975, 11255) |*********************+
Info: [ 11255, 11535) |**********************+
Info: [ 11535, 11815) |****************************+
Info: Program finished normally.
hardware/v2/synthesis/harness_n1/top.config
+12423
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hardware/v2/synthesis/harness_n1/top.json
+43016
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File diff suppressed because it is too large Load Diff
hardware/v2/synthesis/harness_n1/yosys.log
+2091
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File diff suppressed because it is too large Load Diff
hardware/v2/synthesis/harness_n2/nextpnr.log
+195
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@@ -0,0 +1,195 @@
Info: Logic utilisation before packing:
Info: Total LUT4s: 490/43848 1%
Info: logic LUTs: 106/43848 0%
Info: carry LUTs: 384/43848 0%
Info: RAM LUTs: 0/ 5481 0%
Info: RAMW LUTs: 0/10962 0%
Info: Total DFFs: 786/43848 1%
Info: Packing IOs..
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 382 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info: promoting clock net clk$TRELLIS_IO_IN to global network
Info: Checksum: 0x1109bfb2
Info: Device utilisation:
Info: TRELLIS_IO: 18/ 245 7%
Info: DCCA: 1/ 56 1%
Info: DP16KD: 0/ 108 0%
Info: MULT18X18D: 16/ 72 22%
Info: ALU54B: 0/ 36 0%
Info: EHXPLLL: 0/ 4 0%
Info: EXTREFB: 0/ 2 0%
Info: DCUA: 0/ 2 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 0/ 160 0%
Info: SIOLOGIC: 0/ 85 0%
Info: GSR: 0/ 1 0%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 0/ 1 0%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 786/ 43848 1%
Info: TRELLIS_COMB: 564/ 43848 1%
Info: TRELLIS_RAMW: 0/ 5481 0%
Info: Placed 0 cells based on constraints.
Info: Creating initial analytic placement for 525 cells, random placement wirelen = 59923.
Info: at initial placer iter 0, wirelen = 1274
Info: at initial placer iter 1, wirelen = 1127
Info: at initial placer iter 2, wirelen = 1106
Info: at initial placer iter 3, wirelen = 1157
Info: Running main analytical placer, max placement attempts per cell = 239778.
Info: at iteration #1, type ALL: wirelen solved = 1094, spread = 11216, legal = 11682; time = 0.01s
Info: at iteration #2, type ALL: wirelen solved = 1169, spread = 11144, legal = 12395; time = 0.01s
Info: at iteration #3, type ALL: wirelen solved = 1247, spread = 10165, legal = 10861; time = 0.01s
Info: at iteration #4, type ALL: wirelen solved = 1364, spread = 10421, legal = 11693; time = 0.01s
Info: at iteration #5, type ALL: wirelen solved = 1543, spread = 12396, legal = 12770; time = 0.01s
Info: at iteration #6, type ALL: wirelen solved = 1695, spread = 13413, legal = 14136; time = 0.01s
Info: at iteration #7, type ALL: wirelen solved = 1690, spread = 14255, legal = 14878; time = 0.01s
Info: at iteration #8, type ALL: wirelen solved = 1897, spread = 15038, legal = 15799; time = 0.01s
Info: HeAP Placer Time: 0.09s
Info: of which solving equations: 0.04s
Info: of which spreading cells: 0.01s
Info: of which strict legalisation: 0.01s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 463, wirelen = 10861
Info: at iteration #5: temp = 0.000000, timing cost = 252, wirelen = 7927
Info: at iteration #10: temp = 0.000000, timing cost = 89, wirelen = 7375
Info: at iteration #15: temp = 0.000000, timing cost = 125, wirelen = 6924
Info: at iteration #20: temp = 0.000000, timing cost = 130, wirelen = 6701
Info: at iteration #23: temp = 0.000000, timing cost = 134, wirelen = 6655
Info: SA placement time 0.25s
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 134.61 MHz (PASS at 80.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 5.64 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 6.10 ns
Info: Slack histogram:
Info: legend: * represents 2 endpoint(s)
Info: + represents [1,2) endpoint(s)
Info: [ 5071, 5405) |********+
Info: [ 5405, 5739) |*****+
Info: [ 5739, 6073) |**********************+
Info: [ 6073, 6407) |***********************+
Info: [ 6407, 6741) |********************
Info: [ 6741, 7075) |***********************+
Info: [ 7075, 7409) |**+
Info: [ 7409, 7743) |+
Info: [ 7743, 8077) |*+
Info: [ 8077, 8411) |****+
Info: [ 8411, 8745) |******+
Info: [ 8745, 9079) |********************+
Info: [ 9079, 9413) |********************+
Info: [ 9413, 9747) |***************************+
Info: [ 9747, 10081) |************************************************************
Info: [ 10081, 10415) |*********************************************************+
Info: [ 10415, 10749) |***************************+
Info: [ 10749, 11083) |************************+
Info: [ 11083, 11417) |***************************+
Info: [ 11417, 11751) |**********************+
Info: Checksum: 0x68ae7406
Info: Routing globals...
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 3376 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 181 818 | 181 818 | 2615| 0.44 0.44|
Info: 2000 | 482 1517 | 301 699 | 1944| 0.21 0.65|
Info: 3000 | 541 2284 | 59 767 | 1009| 0.06 0.70|
Info: 4000 | 590 3173 | 49 889 | 66| 0.10 0.81|
Info: 4067 | 592 3229 | 2 56 | 0| 0.01 0.82|
Info: Routing complete.
Info: Router1 time 0.82s
Info: Checksum: 0xe0f5407a
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source dut.GEN_NP[1].u_np.x0[5]_TRELLIS_FF_Q.Q
Info: routing 2.11 2.51 Net dut.GEN_NP[1].u_np.w0[0][3] (79,23) -> (82,46)
Info: Sink dut.GEN_NP[1].u_np.product_comb[1]_MULT18X18D_P9.B2
Info: Defined in:
Info: hardware/v2/rtl/neural_processor.v:99.44-99.46
Info: logic 3.07 5.57 Source dut.GEN_NP[1].u_np.product_comb[1]_MULT18X18D_P9.P3
Info: routing 1.11 6.68 Net dut.GEN_NP[1].u_np.product_comb[1][3] (82,46) -> (82,33)
Info: Sink dut.GEN_NP[1].u_np.prod1[1]_TRELLIS_FF_Q.M
Info: Defined in:
Info: hardware/v2/rtl/neural_processor.v:135.34-135.46
Info: setup 0.00 6.68 Source dut.GEN_NP[1].u_np.prod1[1]_TRELLIS_FF_Q.M
Info: 3.46 ns logic, 3.22 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info: type curr total name
Info: source 0.00 0.00 Source seed[2]$tr_io.O
Info: routing 3.64 3.64 Net seed[2]$TRELLIS_IO_IN (0,26) -> (77,26)
Info: Sink seed_LUT4_B_Z_LUT4_Z_1.B
Info: Defined in:
Info: hardware/v2/synthesis/harness_neural_processor_array.v:31.18-31.22
Info: logic 0.18 3.82 Source seed_LUT4_B_Z_LUT4_Z_1.F
Info: routing 0.12 3.94 Net seed_LUT4_B_Z[2] (77,26) -> (77,26)
Info: Sink dut.GEN_NP[1].u_np.job_valid_TRELLIS_FF_Q.DI
Info: setup 0.00 3.94 Source dut.GEN_NP[1].u_np.job_valid_TRELLIS_FF_Q.DI
Info: 0.18 ns logic, 3.76 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source chk_TRELLIS_FF_Q.Q
Info: routing 3.68 4.07 Net checksum[0]$TRELLIS_IO_OUT (79,28) -> (0,29)
Info: Sink checksum[0]$tr_io.I
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: 0.40 ns logic, 3.68 ns routing
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 149.59 MHz (PASS at 80.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 3.94 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 4.07 ns
Info: Slack histogram:
Info: legend: * represents 2 endpoint(s)
Info: + represents [1,2) endpoint(s)
Info: [ 5815, 6115) |*********+
Info: [ 6115, 6415) |**********+
Info: [ 6415, 6715) |*************************+
Info: [ 6715, 7015) |************************************+
Info: [ 7015, 7315) |***************+
Info: [ 7315, 7615) |+
Info: [ 7615, 7915) |
Info: [ 7915, 8215) |+
Info: [ 8215, 8515) |*+
Info: [ 8515, 8815) |*******+
Info: [ 8815, 9115) |**********************+
Info: [ 9115, 9415) |*************+
Info: [ 9415, 9715) |**********************************+
Info: [ 9715, 10015) |************************************************************
Info: [ 10015, 10315) |************************************************+
Info: [ 10315, 10615) |***********+
Info: [ 10615, 10915) |********+
Info: [ 10915, 11215) |********************************+
Info: [ 11215, 11515) |********************+
Info: [ 11515, 11815) |******************+
Info: Program finished normally.
hardware/v2/synthesis/harness_n2/top.config
+21879
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hardware/v2/synthesis/harness_n2/top.json
+62763
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hardware/v2/synthesis/harness_n2/yosys.log
+2261
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hardware/v2/synthesis/harness_n4/nextpnr.log
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Info: Logic utilisation before packing:
Info: Total LUT4s: 975/43848 2%
Info: logic LUTs: 207/43848 0%
Info: carry LUTs: 768/43848 1%
Info: RAM LUTs: 0/ 5481 0%
Info: RAMW LUTs: 0/10962 0%
Info: Total DFFs: 1540/43848 3%
Info: Packing IOs..
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 755 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info: promoting clock net clk$TRELLIS_IO_IN to global network
Info: Checksum: 0x560267d7
Info: Device utilisation:
Info: TRELLIS_IO: 18/ 245 7%
Info: DCCA: 1/ 56 1%
Info: DP16KD: 0/ 108 0%
Info: MULT18X18D: 32/ 72 44%
Info: ALU54B: 0/ 36 0%
Info: EHXPLLL: 0/ 4 0%
Info: EXTREFB: 0/ 2 0%
Info: DCUA: 0/ 2 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 0/ 160 0%
Info: SIOLOGIC: 0/ 85 0%
Info: GSR: 0/ 1 0%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 0/ 1 0%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 1540/ 43848 3%
Info: TRELLIS_COMB: 1121/ 43848 2%
Info: TRELLIS_RAMW: 0/ 5481 0%
Info: Placed 0 cells based on constraints.
Info: Creating initial analytic placement for 1018 cells, random placement wirelen = 120985.
Info: at initial placer iter 0, wirelen = 1796
Info: at initial placer iter 1, wirelen = 1649
Info: at initial placer iter 2, wirelen = 1698
Info: at initial placer iter 3, wirelen = 1586
Info: Running main analytical placer, max placement attempts per cell = 919368.
Info: at iteration #1, type ALL: wirelen solved = 1546, spread = 31023, legal = 34537; time = 0.02s
Info: at iteration #2, type ALL: wirelen solved = 1873, spread = 27635, legal = 31318; time = 0.02s
Info: at iteration #3, type ALL: wirelen solved = 2361, spread = 26175, legal = 29501; time = 0.02s
Info: at iteration #4, type ALL: wirelen solved = 2432, spread = 27276, legal = 30779; time = 0.02s
Info: at iteration #5, type ALL: wirelen solved = 2485, spread = 28458, legal = 30586; time = 0.01s
Info: at iteration #6, type ALL: wirelen solved = 2680, spread = 29235, legal = 32295; time = 0.02s
Info: at iteration #7, type ALL: wirelen solved = 2809, spread = 29926, legal = 32990; time = 0.02s
Info: at iteration #8, type ALL: wirelen solved = 2999, spread = 30221, legal = 32095; time = 0.01s
Info: HeAP Placer Time: 0.22s
Info: of which solving equations: 0.10s
Info: of which spreading cells: 0.01s
Info: of which strict legalisation: 0.06s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 1110, wirelen = 29501
Info: at iteration #5: temp = 0.000000, timing cost = 598, wirelen = 23863
Info: at iteration #10: temp = 0.000000, timing cost = 442, wirelen = 20435
Info: at iteration #15: temp = 0.000000, timing cost = 314, wirelen = 19582
Info: at iteration #20: temp = 0.000000, timing cost = 211, wirelen = 18791
Info: at iteration #25: temp = 0.000000, timing cost = 225, wirelen = 18367
Info: at iteration #26: temp = 0.000000, timing cost = 244, wirelen = 18366
Info: SA placement time 0.61s
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 120.63 MHz (PASS at 80.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 11.00 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 7.53 ns
Info: Slack histogram:
Info: legend: * represents 4 endpoint(s)
Info: + represents [1,4) endpoint(s)
Info: [ 4210, 4587) |+
Info: [ 4587, 4964) |+
Info: [ 4964, 5341) |***+
Info: [ 5341, 5718) |***************************+
Info: [ 5718, 6095) |*************************************+
Info: [ 6095, 6472) |********************************+
Info: [ 6472, 6849) |************+
Info: [ 6849, 7226) |*****+
Info: [ 7226, 7603) |****+
Info: [ 7603, 7980) |********+
Info: [ 7980, 8357) |***************+
Info: [ 8357, 8734) |************+
Info: [ 8734, 9111) |*******************+
Info: [ 9111, 9488) |******************+
Info: [ 9488, 9865) |*****************+
Info: [ 9865, 10242) |**************************************************+
Info: [ 10242, 10619) |************************************************************
Info: [ 10619, 10996) |***************************+
Info: [ 10996, 11373) |***************************+
Info: [ 11373, 11750) |******************+
Info: Checksum: 0xa617f308
Info: Routing globals...
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 6674 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 373 626 | 373 626 | 6229| 0.41 0.41|
Info: 2000 | 577 1422 | 204 796 | 5542| 0.68 1.09|
Info: 3000 | 761 2238 | 184 816 | 4800| 0.34 1.43|
Info: 4000 | 1201 2798 | 440 560 | 4327| 0.28 1.71|
Info: 5000 | 1272 3658 | 71 860 | 3465| 0.14 1.85|
Info: 6000 | 1354 4460 | 82 802 | 2552| 0.09 1.93|
Info: 7000 | 1432 5185 | 78 725 | 1634| 0.09 2.02|
Info: 8000 | 1489 6074 | 57 889 | 700| 0.10 2.12|
Info: 8706 | 1496 6719 | 7 645 | 0| 0.07 2.19|
Info: Routing complete.
Info: Router1 time 2.19s
Info: Checksum: 0x9b8ba237
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source dut.GEN_NP[0].u_np.w0[7]_TRELLIS_FF_Q.Q
Info: routing 2.11 2.50 Net dut.GEN_NP[0].u_np.w0[6][7] (63,23) -> (27,22)
Info: Sink dut.GEN_NP[0].u_np.product_comb[7]_MULT18X18D_P9.B6
Info: Defined in:
Info: hardware/v2/rtl/neural_processor.v:100.44-100.46
Info: logic 3.07 5.57 Source dut.GEN_NP[0].u_np.product_comb[7]_MULT18X18D_P9.P9
Info: routing 1.06 6.62 Net dut.GEN_NP[0].u_np.product_comb[7][9] (27,22) -> (27,21)
Info: Sink dut.GEN_NP[0].u_np.prod1[7]_TRELLIS_FF_Q_9.M
Info: Defined in:
Info: hardware/v2/rtl/neural_processor.v:135.34-135.46
Info: setup 0.00 6.62 Source dut.GEN_NP[0].u_np.prod1[7]_TRELLIS_FF_Q_9.M
Info: 3.46 ns logic, 3.16 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info: type curr total name
Info: source 0.00 0.00 Source rst$tr_io.O
Info: routing 6.36 6.36 Net rst$TRELLIS_IO_IN (15,71) -> (85,14)
Info: Sink dut.GEN_NP[1].u_np.acc_reg_TRELLIS_FF_Q_LSR_LUT4_Z.A
Info: Defined in:
Info: hardware/v2/synthesis/harness_neural_processor_array.v:30.12-30.15
Info: logic 0.18 6.54 Source dut.GEN_NP[1].u_np.acc_reg_TRELLIS_FF_Q_LSR_LUT4_Z.F
Info: routing 0.68 7.22 Net dut.GEN_NP[1].u_np.acc_reg_TRELLIS_FF_Q_LSR (85,14) -> (87,15)
Info: Sink dut.GEN_NP[1].u_np.acc_reg_TRELLIS_FF_Q_4.LSR
Info: setup 0.29 7.50 Source dut.GEN_NP[1].u_np.acc_reg_TRELLIS_FF_Q_4.LSR
Info: 0.47 ns logic, 7.04 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source chk_TRELLIS_FF_Q_2.Q
Info: routing 4.69 5.09 Net checksum[2]$TRELLIS_IO_OUT (75,29) -> (18,71)
Info: Sink checksum[2]$tr_io.I
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: 0.40 ns logic, 4.69 ns routing
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 151.01 MHz (PASS at 80.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 7.50 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 5.09 ns
Info: Slack histogram:
Info: legend: * represents 4 endpoint(s)
Info: + represents [1,4) endpoint(s)
Info: [ 5878, 6174) |***************+
Info: [ 6174, 6470) |**************************************+
Info: [ 6470, 6766) |************************************+
Info: [ 6766, 7062) |**********+
Info: [ 7062, 7358) |*****+
Info: [ 7358, 7654) |+
Info: [ 7654, 7950) |+
Info: [ 7950, 8246) |***************+
Info: [ 8246, 8542) |**************+
Info: [ 8542, 8838) |****************+
Info: [ 8838, 9134) |*********************+
Info: [ 9134, 9430) |*********************+
Info: [ 9430, 9726) |*********************+
Info: [ 9726, 10022) |************************************************************
Info: [ 10022, 10318) |*********************************************+
Info: [ 10318, 10614) |***************+
Info: [ 10614, 10910) |***********+
Info: [ 10910, 11206) |************************+
Info: [ 11206, 11502) |********************+
Info: [ 11502, 11798) |*************+
Info: Program finished normally.
hardware/v2/synthesis/harness_n4/top.config
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hardware/v2/synthesis/harness_n4/top.json
+102696
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hardware/v2/synthesis/harness_n4/yosys.log
+2600
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hardware/v2/synthesis/harness_n8/nextpnr.log
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Info: Logic utilisation before packing:
Info: Total LUT4s: 1910/43848 4%
Info: logic LUTs: 374/43848 0%
Info: carry LUTs: 1536/43848 3%
Info: RAM LUTs: 0/ 5481 0%
Info: RAMW LUTs: 0/10962 0%
Info: Total DFFs: 3048/43848 6%
Info: Packing IOs..
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 1505 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info: promoting clock net clk$TRELLIS_IO_IN to global network
Info: Checksum: 0xc54ffca4
Info: Device utilisation:
Info: TRELLIS_IO: 18/ 245 7%
Info: DCCA: 1/ 56 1%
Info: DP16KD: 0/ 108 0%
Info: MULT18X18D: 64/ 72 88%
Info: ALU54B: 0/ 36 0%
Info: EHXPLLL: 0/ 4 0%
Info: EXTREFB: 0/ 2 0%
Info: DCUA: 0/ 2 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 0/ 160 0%
Info: SIOLOGIC: 0/ 85 0%
Info: GSR: 0/ 1 0%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 0/ 1 0%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 3048/ 43848 6%
Info: TRELLIS_COMB: 2200/ 43848 5%
Info: TRELLIS_RAMW: 0/ 5481 0%
Info: Placed 0 cells based on constraints.
Info: Creating initial analytic placement for 2000 cells, random placement wirelen = 237944.
Info: at initial placer iter 0, wirelen = 2833
Info: at initial placer iter 1, wirelen = 2361
Info: at initial placer iter 2, wirelen = 2391
Info: at initial placer iter 3, wirelen = 2328
Info: Running main analytical placer, max placement attempts per cell = 3552445.
Info: at iteration #1, type ALL: wirelen solved = 2347, spread = 88719, legal = 96946; time = 0.13s
Info: at iteration #2, type ALL: wirelen solved = 2990, spread = 77005, legal = 88952; time = 0.12s
Info: at iteration #3, type ALL: wirelen solved = 3774, spread = 74483, legal = 85580; time = 0.12s
Info: at iteration #4, type ALL: wirelen solved = 4347, spread = 77909, legal = 88520; time = 0.12s
Info: at iteration #5, type ALL: wirelen solved = 4517, spread = 75128, legal = 86754; time = 0.12s
Info: at iteration #6, type ALL: wirelen solved = 5126, spread = 74185, legal = 82449; time = 0.12s
Info: at iteration #7, type ALL: wirelen solved = 5229, spread = 73739, legal = 84387; time = 0.12s
Info: at iteration #8, type ALL: wirelen solved = 5827, spread = 72928, legal = 82109; time = 0.12s
Info: at iteration #9, type ALL: wirelen solved = 5739, spread = 72243, legal = 83492; time = 0.12s
Info: at iteration #10, type ALL: wirelen solved = 6366, spread = 71190, legal = 82622; time = 0.12s
Info: at iteration #11, type ALL: wirelen solved = 6226, spread = 71845, legal = 82524; time = 0.12s
Info: at iteration #12, type ALL: wirelen solved = 6126, spread = 72093, legal = 79506; time = 0.12s
Info: at iteration #13, type ALL: wirelen solved = 6327, spread = 70392, legal = 80435; time = 0.12s
Info: at iteration #14, type ALL: wirelen solved = 6688, spread = 68808, legal = 78516; time = 0.12s
Info: at iteration #15, type ALL: wirelen solved = 7246, spread = 69205, legal = 79422; time = 0.12s
Info: at iteration #16, type ALL: wirelen solved = 7128, spread = 69848, legal = 81864; time = 0.12s
Info: at iteration #17, type ALL: wirelen solved = 6913, spread = 68240, legal = 77295; time = 0.12s
Info: at iteration #18, type ALL: wirelen solved = 7495, spread = 69919, legal = 79795; time = 0.12s
Info: at iteration #19, type ALL: wirelen solved = 7433, spread = 70131, legal = 80425; time = 0.12s
Info: at iteration #20, type ALL: wirelen solved = 7332, spread = 70955, legal = 78731; time = 0.12s
Info: at iteration #21, type ALL: wirelen solved = 7815, spread = 70691, legal = 82570; time = 0.12s
Info: at iteration #22, type ALL: wirelen solved = 7907, spread = 66858, legal = 80330; time = 0.12s
Info: HeAP Placer Time: 2.96s
Info: of which solving equations: 0.44s
Info: of which spreading cells: 0.08s
Info: of which strict legalisation: 2.21s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 2470, wirelen = 77295
Info: at iteration #5: temp = 0.000000, timing cost = 958, wirelen = 63401
Info: at iteration #10: temp = 0.000000, timing cost = 347, wirelen = 54640
Info: at iteration #15: temp = 0.000000, timing cost = 217, wirelen = 51562
Info: at iteration #20: temp = 0.000000, timing cost = 399, wirelen = 49406
Info: at iteration #25: temp = 0.000000, timing cost = 344, wirelen = 48261
Info: at iteration #30: temp = 0.000000, timing cost = 416, wirelen = 47947
Info: at iteration #30: temp = 0.000000, timing cost = 414, wirelen = 47960
Info: SA placement time 1.60s
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 106.38 MHz (PASS at 80.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 8.46 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 5.29 ns
Info: Slack histogram:
Info: legend: * represents 7 endpoint(s)
Info: + represents [1,7) endpoint(s)
Info: [ 3100, 3532) |+
Info: [ 3532, 3964) |**+
Info: [ 3964, 4396) |****+
Info: [ 4396, 4828) |**************+
Info: [ 4828, 5260) |***************************+
Info: [ 5260, 5692) |**********************+
Info: [ 5692, 6124) |****************+
Info: [ 6124, 6556) |************************************+
Info: [ 6556, 6988) |*********************************+
Info: [ 6988, 7420) |***********************+
Info: [ 7420, 7852) |**************+
Info: [ 7852, 8284) |*************+
Info: [ 8284, 8716) |*******************+
Info: [ 8716, 9148) |***************************+
Info: [ 9148, 9580) |******************************************+
Info: [ 9580, 10012) |**********************************************************+
Info: [ 10012, 10444) |************************************************************
Info: [ 10444, 10876) |*********************************************+
Info: [ 10876, 11308) |*****************+
Info: [ 11308, 11740) |*******************+
Info: Checksum: 0xffbac1a4
Info: Routing globals...
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 13199 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 504 495 | 504 495 | 12908| 0.52 0.52|
Info: 2000 | 963 1036 | 459 541 | 12547| 0.52 1.04|
Info: 3000 | 1240 1759 | 277 723 | 12118| 0.84 1.88|
Info: 4000 | 1522 2477 | 282 718 | 11659| 0.83 2.71|
Info: 5000 | 1767 3232 | 245 755 | 11069| 1.01 3.72|
Info: 6000 | 1942 4057 | 175 825 | 10312| 0.65 4.37|
Info: 7000 | 2145 4854 | 203 797 | 9554| 0.33 4.69|
Info: 8000 | 2501 5498 | 356 644 | 8951| 0.26 4.96|
Info: 9000 | 2850 6149 | 349 651 | 8376| 0.35 5.30|
Info: 10000 | 3183 6815 | 333 666 | 7803| 0.37 5.67|
Info: 11000 | 3224 7639 | 41 824 | 6849| 0.11 5.78|
Info: 12000 | 3292 8462 | 68 823 | 5921| 0.08 5.86|
Info: 13000 | 3371 9233 | 79 771 | 5002| 0.10 5.96|
Info: 14000 | 3444 9947 | 73 714 | 4085| 0.11 6.07|
Info: 15000 | 3513 10733 | 69 786 | 3163| 0.10 6.17|
Info: 16000 | 3575 11653 | 62 920 | 2242| 0.07 6.24|
Info: 17000 | 3663 12489 | 88 836 | 1390| 0.24 6.49|
Info: 18000 | 3752 13322 | 89 833 | 510| 0.23 6.72|
Info: 18584 | 3797 13825 | 45 503 | 0| 0.31 7.02|
Info: Routing complete.
Info: Router1 time 7.02s
Info: Checksum: 0x69cac44f
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source dut.GEN_NP[5].u_np.w0[5]_TRELLIS_FF_Q.Q
Info: routing 3.07 3.46 Net dut.GEN_NP[5].u_np.w0[4][7] (73,21) -> (8,22)
Info: Sink dut.GEN_NP[5].u_np.product_comb[5]_MULT18X18D_P9.B6
Info: Defined in:
Info: hardware/v2/rtl/neural_processor.v:100.44-100.46
Info: logic 3.07 6.53 Source dut.GEN_NP[5].u_np.product_comb[5]_MULT18X18D_P9.P13
Info: routing 0.89 7.42 Net dut.GEN_NP[5].u_np.product_comb[5][13] (8,22) -> (8,23)
Info: Sink dut.GEN_NP[5].u_np.prod1[5]_TRELLIS_FF_Q_13.M
Info: Defined in:
Info: hardware/v2/rtl/neural_processor.v:135.34-135.46
Info: setup 0.00 7.42 Source dut.GEN_NP[5].u_np.prod1[5]_TRELLIS_FF_Q_13.M
Info: 3.46 ns logic, 3.96 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info: type curr total name
Info: source 0.00 0.00 Source rst$tr_io.O
Info: routing 2.85 2.85 Net rst$TRELLIS_IO_IN (90,47) -> (42,45)
Info: Sink dut.GEN_NP[0].u_np.valid0_TRELLIS_FF_Q_DI_LUT4_D.C
Info: Defined in:
Info: hardware/v2/synthesis/harness_neural_processor_array.v:30.12-30.15
Info: logic 0.18 3.03 Source dut.GEN_NP[0].u_np.valid0_TRELLIS_FF_Q_DI_LUT4_D.F
Info: routing 2.27 5.30 Net dut.GEN_NP[0].u_np.valid0_TRELLIS_FF_Q_DI_LUT4_D_Z (42,45) -> (55,17)
Info: Sink dut.GEN_NP[0].u_np.last0_TRELLIS_FF_Q_LSR_LUT4_Z.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 5.47 Source dut.GEN_NP[0].u_np.last0_TRELLIS_FF_Q_LSR_LUT4_Z.F
Info: routing 0.22 5.70 Net dut.GEN_NP[0].u_np.last0_TRELLIS_FF_Q_LSR (55,17) -> (55,17)
Info: Sink dut.GEN_NP[0].u_np.last0_TRELLIS_FF_Q.LSR
Info: setup 0.29 5.99 Source dut.GEN_NP[0].u_np.last0_TRELLIS_FF_Q.LSR
Info: 0.65 ns logic, 5.34 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source chk_TRELLIS_FF_Q_6.Q
Info: routing 3.77 4.16 Net checksum[6]$TRELLIS_IO_OUT (68,23) -> (0,23)
Info: Sink checksum[6]$tr_io.I
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: 0.40 ns logic, 3.77 ns routing
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 134.70 MHz (PASS at 80.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 5.99 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 4.16 ns
Info: Slack histogram:
Info: legend: * represents 8 endpoint(s)
Info: + represents [1,8) endpoint(s)
Info: [ 5076, 5412) |**+
Info: [ 5412, 5748) |*****************+
Info: [ 5748, 6084) |********************************+
Info: [ 6084, 6420) |****************+
Info: [ 6420, 6756) |*********************+
Info: [ 6756, 7092) |**********************************+
Info: [ 7092, 7428) |**************+
Info: [ 7428, 7764) |***********+
Info: [ 7764, 8100) |***************+
Info: [ 8100, 8436) |******************+
Info: [ 8436, 8772) |*****************+
Info: [ 8772, 9108) |**************************+
Info: [ 9108, 9444) |***************************+
Info: [ 9444, 9780) |**************************************************+
Info: [ 9780, 10116) |************************************************************
Info: [ 10116, 10452) |**********************************+
Info: [ 10452, 10788) |**********************+
Info: [ 10788, 11124) |*************************+
Info: [ 11124, 11460) |*****************+
Info: [ 11460, 11796) |**************+
Info: Program finished normally.
hardware/v2/synthesis/harness_n8/top.config
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hardware/v2/synthesis/harness_n8/top.json
+180389
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hardware/v2/synthesis/harness_n8/yosys.log
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hardware/v2/synthesis/harness_neural_processor_array.v
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// ============================================================
// SYNTHESIS-ONLY TIMING HARNESS -- NOT a functional deliverable.
//
// neural_processor_array.v's real ports (per-processor wide
// input_data/weight_data buses, per-processor job/result fields) are
// meant to be driven on-chip by the Memory Manager (M4) and Neural
// Director (M5), which do not exist yet. Synthesizing the array
// standalone with every one of those bits exposed as a real
// TRELLIS_IO pin exhausts the ECP5's ~245 available I/O well before
// N_PROCESSORS=2 (see hardware/v2/logs/errors.log ERR-0005) -- a
// packaging artifact of this specific isolated measurement, NOT a
// logic/timing limit of the array itself.
//
// This harness replaces the wide external buses with an internal
// free-running LFSR (so the data ports are not synthesized away as
// constants) and reduces the outputs to a small XOR-reduced checksum,
// keeping only clk/rst/seed/checksum as real top-level pins. This
// gives a representative Fmax for the array's OWN logic/routing
// congestion, uninflated and unconstrained by an artificial pin
// budget that will not exist once M4/M5 land.
// ============================================================
module harness_neural_processor_array #(
parameter DATA_WIDTH = 8,
parameter P_IN = 8,
parameter ACC_WIDTH = 32,
parameter N_PROCESSORS = 4
)(
input clk,
input rst,
input [7:0] seed,
output [7:0] checksum
);
reg [31:0] lfsr;
always @(posedge clk) begin
if (rst) lfsr <= {24'h0, seed} | 32'h1;
else lfsr <= {lfsr[30:0], lfsr[31] ^ lfsr[21] ^ lfsr[1] ^ lfsr[0]};
end
// Each processor gets a DISTINCT data slice (LFSR rotated by its
// own index) so Yosys cannot common-subexpression-eliminate
// N_PROCESSORS identical instances down to one -- that would
// silently defeat the point of the N_PROCESSORS sweep.
genvar hgi;
wire [N_PROCESSORS-1:0] job_valid;
wire [16*N_PROCESSORS-1:0] job_node_id;
wire signed [DATA_WIDTH*N_PROCESSORS-1:0] job_bias;
wire [2*N_PROCESSORS-1:0] job_activation;
wire [N_PROCESSORS-1:0] operand_valid;
wire signed [DATA_WIDTH*P_IN*N_PROCESSORS-1:0] input_data;
wire signed [DATA_WIDTH*P_IN*N_PROCESSORS-1:0] weight_data;
wire [N_PROCESSORS-1:0] tile_last;
wire [N_PROCESSORS-1:0] result_ready;
genvar hgk;
generate
for (hgi = 0; hgi < N_PROCESSORS; hgi = hgi + 1) begin : GEN_HARNESS_LANE
wire [31:0] rot = {lfsr[hgi:0], lfsr[31:hgi+1]};
assign job_valid[hgi] = rot[0];
assign job_node_id[hgi*16 +: 16] = rot[15:0];
assign job_bias[hgi*DATA_WIDTH +: DATA_WIDTH] = rot[7:0];
assign job_activation[hgi*2 +: 2] = rot[1:0];
assign operand_valid[hgi] = rot[2];
assign tile_last[hgi] = rot[3];
assign result_ready[hgi] = rot[4];
// Each of the P_IN MAC lanes WITHIN this processor also
// needs a distinct value -- otherwise all P_IN
// multiplications are identical and Yosys collapses them
// to a single shared MULT18X18D (observed: N=1 synthesized
// to just 1 multiplier instead of P_IN=8).
for (hgk = 0; hgk < P_IN; hgk = hgk + 1) begin : GEN_HARNESS_MAC_LANE
wire [31:0] lane_rot = {rot[hgk:0], rot[31:hgk+1]};
assign input_data[hgi*DATA_WIDTH*P_IN + hgk*DATA_WIDTH +: DATA_WIDTH] = lane_rot[7:0];
assign weight_data[hgi*DATA_WIDTH*P_IN + hgk*DATA_WIDTH +: DATA_WIDTH] = lane_rot[15:8];
end
end
endgenerate
wire [N_PROCESSORS-1:0] job_ready;
wire [N_PROCESSORS-1:0] operand_ready;
wire [N_PROCESSORS-1:0] result_valid;
wire signed [DATA_WIDTH*N_PROCESSORS-1:0] result_data;
wire [16*N_PROCESSORS-1:0] result_node_id;
wire [4*N_PROCESSORS-1:0] np_state;
wire [N_PROCESSORS-1:0] np_error;
neural_processor_array #(
.DATA_WIDTH(DATA_WIDTH), .P_IN(P_IN), .ACC_WIDTH(ACC_WIDTH),
.N_PROCESSORS(N_PROCESSORS)
) dut (
.clk(clk), .rst(rst),
.job_valid(job_valid), .job_ready(job_ready),
.job_node_id(job_node_id), .job_bias(job_bias), .job_activation(job_activation),
.operand_valid(operand_valid), .operand_ready(operand_ready),
.input_data(input_data), .weight_data(weight_data), .tile_last(tile_last),
.result_valid(result_valid), .result_ready(result_ready),
.result_data(result_data), .result_node_id(result_node_id),
.np_state(np_state), .np_error(np_error)
);
// Fold in a real bit from EVERY processor's wide outputs
// (result_data/result_node_id/np_state), not just processor 0's
// slice -- otherwise the arithmetic datapath of every processor
// but one has no observable path to any output at all, and Yosys
// correctly (from a pure logic-equivalence standpoint) strips it
// out as dead logic, silently defeating the N_PROCESSORS sweep.
wire [N_PROCESSORS-1:0] result_data_lsb;
wire [N_PROCESSORS-1:0] result_node_id_lsb;
wire [N_PROCESSORS-1:0] np_state_lsb;
generate
for (hgi = 0; hgi < N_PROCESSORS; hgi = hgi + 1) begin : GEN_CHK_LANE
assign result_data_lsb[hgi] = result_data[hgi*DATA_WIDTH];
assign result_node_id_lsb[hgi] = result_node_id[hgi*16];
assign np_state_lsb[hgi] = np_state[hgi*4];
end
endgenerate
reg [7:0] chk;
always @(posedge clk) begin
if (rst) chk <= 8'h0;
else chk <= chk ^ job_ready ^ operand_ready ^ result_valid ^ np_error
^ result_data_lsb ^ result_node_id_lsb ^ np_state_lsb;
end
assign checksum = chk;
endmodule
hardware/v2/synthesis/neural_processor_array_n1/nextpnr.log
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Info: Logic utilisation before packing:
Info: Total LUT4s: 281/43848 0%
Info: logic LUTs: 77/43848 0%
Info: carry LUTs: 204/43848 0%
Info: RAM LUTs: 0/ 5481 0%
Info: RAMW LUTs: 0/10962 0%
Info: Total DFFs: 561/43848 1%
Info: Packing IOs..
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 212 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info: promoting clock net clk$TRELLIS_IO_IN to global network
Info: Checksum: 0xe4bf0be0
Info: Device utilisation:
Info: TRELLIS_IO: 192/ 245 78%
Info: DCCA: 1/ 56 1%
Info: DP16KD: 0/ 108 0%
Info: MULT18X18D: 8/ 72 11%
Info: ALU54B: 0/ 36 0%
Info: EHXPLLL: 0/ 4 0%
Info: EXTREFB: 0/ 2 0%
Info: DCUA: 0/ 2 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 0/ 160 0%
Info: SIOLOGIC: 0/ 85 0%
Info: GSR: 0/ 1 0%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 0/ 1 0%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 561/ 43848 1%
Info: TRELLIS_COMB: 319/ 43848 0%
Info: TRELLIS_RAMW: 0/ 5481 0%
Info: Placed 0 cells based on constraints.
Info: Creating initial analytic placement for 424 cells, random placement wirelen = 50455.
Info: at initial placer iter 0, wirelen = 12005
Info: at initial placer iter 1, wirelen = 11180
Info: at initial placer iter 2, wirelen = 11007
Info: at initial placer iter 3, wirelen = 11030
Info: Running main analytical placer, max placement attempts per cell = 146070.
Info: at iteration #1, type ALL: wirelen solved = 11022, spread = 14876, legal = 16032; time = 0.01s
Info: at iteration #2, type ALL: wirelen solved = 11185, spread = 13525, legal = 14773; time = 0.01s
Info: at iteration #3, type ALL: wirelen solved = 11171, spread = 14157, legal = 15687; time = 0.01s
Info: at iteration #4, type ALL: wirelen solved = 11247, spread = 13660, legal = 15080; time = 0.01s
Info: at iteration #5, type ALL: wirelen solved = 11256, spread = 14501, legal = 16195; time = 0.01s
Info: at iteration #6, type ALL: wirelen solved = 11281, spread = 14413, legal = 15627; time = 0.01s
Info: at iteration #7, type ALL: wirelen solved = 11322, spread = 14088, legal = 15088; time = 0.01s
Info: HeAP Placer Time: 0.07s
Info: of which solving equations: 0.04s
Info: of which spreading cells: 0.01s
Info: of which strict legalisation: 0.00s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 131, wirelen = 14773
Info: at iteration #5: temp = 0.000000, timing cost = 106, wirelen = 11964
Info: at iteration #9: temp = 0.000000, timing cost = 77, wirelen = 12024
Info: SA placement time 0.09s
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 158.73 MHz (PASS at 80.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 7.92 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 8.14 ns
Info: Slack histogram:
Info: legend: * represents 1 endpoint(s)
Info: + represents [1,1) endpoint(s)
Info: [ 6200, 6477) |*+
Info: [ 6477, 6754) |***+
Info: [ 6754, 7031) |********+
Info: [ 7031, 7308) |*******************************************+
Info: [ 7308, 7585) |******************************************+
Info: [ 7585, 7862) |************************************************************
Info: [ 7862, 8139) |*************************+
Info: [ 8139, 8416) |*******+
Info: [ 8416, 8693) |******+
Info: [ 8693, 8970) |**************+
Info: [ 8970, 9247) |*******************+
Info: [ 9247, 9524) |******************+
Info: [ 9524, 9801) |**********************+
Info: [ 9801, 10078) |**************************************+
Info: [ 10078, 10355) |***************************************************+
Info: [ 10355, 10632) |**********************+
Info: [ 10632, 10909) |********+
Info: [ 10909, 11186) |*****+
Info: [ 11186, 11463) |***+
Info: [ 11463, 11740) |************+
Info: Checksum: 0x34ea3833
Info: Routing globals...
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 2137 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 108 891 | 108 891 | 1309| 0.20 0.20|
Info: 2000 | 230 1654 | 122 763 | 437| 0.15 0.35|
Info: 2450 | 244 2069 | 14 415 | 0| 0.12 0.47|
Info: Routing complete.
Info: Router1 time 0.47s
Info: Checksum: 0xf8fda93b
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source GEN_NP[0].u_np.w0[4]_TRELLIS_FF_Q_3.Q
Info: routing 1.15 1.55 Net GEN_NP[0].u_np.w0[4][3] (25,20) -> (27,22)
Info: Sink GEN_NP[0].u_np.product_comb[4]_MULT18X18D_P9.B3
Info: Defined in:
Info: hardware/v2/rtl/neural_processor.v:100.44-100.46
Info: logic 3.07 4.62 Source GEN_NP[0].u_np.product_comb[4]_MULT18X18D_P9.P9
Info: routing 0.97 5.58 Net GEN_NP[0].u_np.product_comb[4][9] (27,22) -> (27,27)
Info: Sink GEN_NP[0].u_np.prod1[4]_TRELLIS_FF_Q_9.M
Info: Defined in:
Info: hardware/v2/rtl/neural_processor.v:135.34-135.46
Info: setup 0.00 5.58 Source GEN_NP[0].u_np.prod1[4]_TRELLIS_FF_Q_9.M
Info: 3.46 ns logic, 2.12 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info: type curr total name
Info: source 0.00 0.00 Source tile_last$tr_io.O
Info: routing 4.08 4.08 Net tile_last$TRELLIS_IO_IN (90,50) -> (19,31)
Info: Sink job_valid_LUT4_C_Z_LUT4_Z.C
Info: Defined in:
Info: hardware/v2/rtl/neural_processor_array.v:43.57-43.66
Info: logic 0.18 4.26 Source job_valid_LUT4_C_Z_LUT4_Z.F
Info: routing 0.64 4.90 Net job_valid_LUT4_C_Z[2] (19,31) -> (18,31)
Info: Sink result_ready_LUT4_A_Z_LUT4_B.C
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 5.08 Source result_ready_LUT4_A_Z_LUT4_B.F
Info: routing 0.49 5.57 Net result_ready_LUT4_A_Z_LUT4_B_Z (18,31) -> (18,32)
Info: Sink GEN_NP[0].u_np.np_state_TRELLIS_FF_Q_2.CE
Info: setup 0.00 5.57 Source GEN_NP[0].u_np.np_state_TRELLIS_FF_Q_2.CE
Info: 0.36 ns logic, 5.21 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source GEN_NP[0].u_np.np_state_TRELLIS_FF_Q_1.Q
Info: routing 0.64 1.03 Net np_state[2]$TRELLIS_IO_OUT (18,32) -> (18,32)
Info: Sink operand_ready_LUT4_Z.B
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 1.21 Source operand_ready_LUT4_Z.F
Info: routing 4.40 5.61 Net operand_ready$TRELLIS_IO_OUT (18,32) -> (90,56)
Info: Sink operand_ready$tr_io.I
Info: Defined in:
Info: hardware/v2/rtl/neural_processor_array.v:40.58-40.71
Info: 0.57 ns logic, 5.03 ns routing
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 179.08 MHz (PASS at 80.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 5.57 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 5.61 ns
Info: Slack histogram:
Info: legend: * represents 1 endpoint(s)
Info: + represents [1,1) endpoint(s)
Info: [ 6916, 7160) |**********************+
Info: [ 7160, 7404) |************************************************************
Info: [ 7404, 7648) |********+
Info: [ 7648, 7892) |********+
Info: [ 7892, 8136) |***+
Info: [ 8136, 8380) |******+
Info: [ 8380, 8624) |*********************+
Info: [ 8624, 8868) |**************************************+
Info: [ 8868, 9112) |***************************************+
Info: [ 9112, 9356) |**********+
Info: [ 9356, 9600) |*****************************************+
Info: [ 9600, 9844) |*************************************+
Info: [ 9844, 10088) |****************************************************+
Info: [ 10088, 10332) |******************************+
Info: [ 10332, 10576) |********+
Info: [ 10576, 10820) |***************+
Info: [ 10820, 11064) |***************+
Info: [ 11064, 11308) |******+
Info: [ 11308, 11552) |*****+
Info: [ 11552, 11796) |**********+
Info: Program finished normally.
hardware/v2/synthesis/neural_processor_array_n1/top.config
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hardware/v2/synthesis/neural_processor_array_n1/top.json
+48343
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hardware/v2/synthesis/neural_processor_array_n1/yosys.log
+2008
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hardware/v2/synthesis/neural_processor_array_n2/nextpnr.log
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Info: Logic utilisation before packing:
Info: Total LUT4s: 527/43848 1%
Info: logic LUTs: 119/43848 0%
Info: carry LUTs: 408/43848 0%
Info: RAM LUTs: 0/ 5481 0%
Info: RAMW LUTs: 0/10962 0%
Info: Total DFFs: 1122/43848 2%
Info: Packing IOs..
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 424 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info: promoting clock net clk$TRELLIS_IO_IN to global network
Info: Checksum: 0x8a2b0eea
Info: Device utilisation:
Info: TRELLIS_IO: 382/ 245 155%
Info: DCCA: 1/ 56 1%
Info: DP16KD: 0/ 108 0%
Info: MULT18X18D: 16/ 72 22%
Info: ALU54B: 0/ 36 0%
Info: EHXPLLL: 0/ 4 0%
Info: EXTREFB: 0/ 2 0%
Info: DCUA: 0/ 2 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 0/ 160 0%
Info: SIOLOGIC: 0/ 85 0%
Info: GSR: 0/ 1 0%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 0/ 1 0%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 1122/ 43848 2%
Info: TRELLIS_COMB: 601/ 43848 1%
Info: TRELLIS_RAMW: 0/ 5481 0%
Info: Placed 0 cells based on constraints.
ERROR: Unable to place cell 'weight_data[36]$tr_io', no BELs remaining to implement cell type 'TRELLIS_IO'
0 warnings, 1 error
hardware/v2/synthesis/neural_processor_array_n2/top.json
+73380
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hardware/v2/synthesis/neural_processor_array_n2/yosys.log
+2160
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hardware/v2/synthesis/neural_processor_array_n4/nextpnr.log
+56
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Info: Logic utilisation before packing:
Info: Total LUT4s: 1067/43848 2%
Info: logic LUTs: 251/43848 0%
Info: carry LUTs: 816/43848 1%
Info: RAM LUTs: 0/ 5481 0%
Info: RAMW LUTs: 0/10962 0%
Info: Total DFFs: 2244/43848 5%
Info: Packing IOs..
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 849 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info: promoting clock net clk$TRELLIS_IO_IN to global network
Info: Checksum: 0x97aa63c3
Info: Device utilisation:
Info: TRELLIS_IO: 762/ 245 311%
Info: DCCA: 1/ 56 1%
Info: DP16KD: 0/ 108 0%
Info: MULT18X18D: 32/ 72 44%
Info: ALU54B: 0/ 36 0%
Info: EHXPLLL: 0/ 4 0%
Info: EXTREFB: 0/ 2 0%
Info: DCUA: 0/ 2 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 0/ 160 0%
Info: SIOLOGIC: 0/ 85 0%
Info: GSR: 0/ 1 0%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 0/ 1 0%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 2244/ 43848 5%
Info: TRELLIS_COMB: 1213/ 43848 2%
Info: TRELLIS_RAMW: 0/ 5481 0%
Info: Placed 0 cells based on constraints.
ERROR: Unable to place cell 'np_state[7]$tr_io', no BELs remaining to implement cell type 'TRELLIS_IO'
0 warnings, 1 error
hardware/v2/synthesis/neural_processor_array_n4/top.json
+125234
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hardware/v2/synthesis/neural_processor_array_n4/yosys.log
+2472
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hardware/v2/synthesis/neural_processor_array_n8/nextpnr.log
+56
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@@ -0,0 +1,56 @@
Info: Logic utilisation before packing:
Info: Total LUT4s: 2161/43848 4%
Info: logic LUTs: 529/43848 1%
Info: carry LUTs: 1632/43848 3%
Info: RAM LUTs: 0/ 5481 0%
Info: RAMW LUTs: 0/10962 0%
Info: Total DFFs: 4488/43848 10%
Info: Packing IOs..
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 1702 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info: promoting clock net clk$TRELLIS_IO_IN to global network
Info: Checksum: 0x48984257
Info: Device utilisation:
Info: TRELLIS_IO: 1522/ 245 621%
Info: DCCA: 1/ 56 1%
Info: DP16KD: 0/ 108 0%
Info: MULT18X18D: 64/ 72 88%
Info: ALU54B: 0/ 36 0%
Info: EHXPLLL: 0/ 4 0%
Info: EXTREFB: 0/ 2 0%
Info: DCUA: 0/ 2 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 0/ 160 0%
Info: SIOLOGIC: 0/ 85 0%
Info: GSR: 0/ 1 0%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 0/ 1 0%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 4488/ 43848 10%
Info: TRELLIS_COMB: 2451/ 43848 5%
Info: TRELLIS_RAMW: 0/ 5481 0%
Info: Placed 0 cells based on constraints.
ERROR: Unable to place cell 'job_node_id[3]$tr_io', no BELs remaining to implement cell type 'TRELLIS_IO'
0 warnings, 1 error
hardware/v2/synthesis/neural_processor_array_n8/top.json
+230098
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File diff suppressed because it is too large Load Diff
hardware/v2/synthesis/neural_processor_array_n8/yosys.log
+3109
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File diff suppressed because it is too large Load Diff