micheleandClaude Sonnet 5
3026dcd997
Implements M2 of the V2 roadmap: neural_processor_array.v instantiates
N_PROCESSORS independent neural_processor (M1) units, each with its
own dedicated point-to-point job/operand/result interface -- no shared
bus or mux at this level (arbitration is explicitly the Neural
Director's job, M5).
Verified with Verilator (tb_neural_processor_array.v, N_PROCESSORS=4):
7/7 tests pass, including a same-cycle 4-way concurrent launch with
different tile counts and a staggered-start test where a
later-launched, shorter job completes before an earlier-launched,
longer one -- confirming genuine independent concurrent execution
(§18/§34: a blocked/busy processor must not block the others).
Real resource/timing sweep for N_PROCESSORS in {1,2,4,8} (Yosys +
nextpnr-ecp5, real place&route): Fmax stays above the 80MHz target
throughout (159.11 -> 134.70 MHz), but MULT18X18D usage scales
linearly and reaches 88% of the LFE5U-45F's 72 DSPs at N=8 while
LUT/FF stay under 6% -- DSP, not LUT/FF/routing, is the first hard
ceiling on N_PROCESSORS at P_IN=8 (decisions.log DEC-0005). Measured
via a dedicated synthesis-only timing harness after the array's wide
per-processor buses were found to exhaust the device's TRELLIS_IO pin
budget as a bare top-level module beyond N=1 (errors.log ERR-0005) --
not a logic limit, an artifact of testing the array in isolation
before the Memory Manager/Director (M4/M5) exist to consume those
ports on-chip.
Full log trail (development/experiments/errors/decisions/simulation/
synthesis/timing/benchmark.log) in hardware/v2/logs/ per the project's
logging mandate.
Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
2.4 KiB
2.4 KiB
FPGA-Neural V2 — stato roadmap
Fonte del mandato: docs/v2-description.md (root del repository). Baseline
funzionale/numerica/bit-exact: hardware/v1/ (frozen, sola lettura — vedi
hardware/v1/README.md).
Legenda: [ ] non iniziato · [~] in corso · [x] completo (sim+synth+timing
reali, non solo scritto).
- M1 — Neural Processor (
hardware/v2/rtl/neural_processor.v, P8). Bit-exact vs V1 (7/7 test, Verilator), pipeline a 8 stadi funzionante, throughput reale (1 tile/ciclo). Sintesi reale: 0 problemi CHECK, Fmax 183.12 MHz (ACC_WIDTH=32) — vedilogs/experiments.logEXP-0001/EXP-0002,logs/errors.logper 3 bug reali trovati e risolti (2 del toolchain Icarus, 1 RTL). - M2 — Processor Array (
neural_processor_array.v). 1/2/4/8 processor testati (sim concorrenza reale + sintesi/P&R reali). Fmax sempre PASS a 80MHz (159.11→134.70 MHz). Scoperta: il DSP (MULT18X18D), non LUT/FF, satura per primo (88% a N=8) — vedilogs/decisions.logDEC-0005. - M3 — Buffers (
activation_buffer.v,weight_buffer.v,result_buffer.v). - M4 — Memory Manager (
memory_manager.v,prefetch_engine.v), backend PSRAM V1 riusato senza modifiche. - M5 — Neural Director (
neural_director.v), scheduling first-free. - M6 — Dependency Manager (
dependency_manager.v), ready/waiting queue, dependency counters, wake-up, producer tracking. - M7 — Dataflow Core (
dataflow_core.v), integrazione completa. - M8 — PSRAM integration, controller V1 non modificato, misura reale.
- M9 — Full benchmark, tabella V1 vs V2 (§32 del mandato).
- M10 — Optimization, solo sulla base dei dati raccolti in M1-M9.
Log
Vedi hardware/v2/logs/ (development.log per la cronologia di sessione,
decisions.log per le decisioni architetturali con motivazione,
experiments.log per ogni EXP-XXXX end-to-end).
Regole non negoziabili attive (§34 del mandato, per riferimento rapido)
- V1 (
hardware/v1/) rimane intatta — mai modificata. - V2 vive esclusivamente sotto
hardware/v2/. - Nessun risultato inventato: THEORETICAL vs SIMULATED vs SYNTHESIZED vs POST-P&R sempre etichettati esplicitamente.
- Ogni modifica/esperimento/decisione registrata nei log, mai persa.
- Ogni esperimento ha un ID univoco, mai riutilizzato — anche i FAIL restano.