micheleandClaude Sonnet 5
3026dcd997
Implements M2 of the V2 roadmap: neural_processor_array.v instantiates
N_PROCESSORS independent neural_processor (M1) units, each with its
own dedicated point-to-point job/operand/result interface -- no shared
bus or mux at this level (arbitration is explicitly the Neural
Director's job, M5).
Verified with Verilator (tb_neural_processor_array.v, N_PROCESSORS=4):
7/7 tests pass, including a same-cycle 4-way concurrent launch with
different tile counts and a staggered-start test where a
later-launched, shorter job completes before an earlier-launched,
longer one -- confirming genuine independent concurrent execution
(§18/§34: a blocked/busy processor must not block the others).
Real resource/timing sweep for N_PROCESSORS in {1,2,4,8} (Yosys +
nextpnr-ecp5, real place&route): Fmax stays above the 80MHz target
throughout (159.11 -> 134.70 MHz), but MULT18X18D usage scales
linearly and reaches 88% of the LFE5U-45F's 72 DSPs at N=8 while
LUT/FF stay under 6% -- DSP, not LUT/FF/routing, is the first hard
ceiling on N_PROCESSORS at P_IN=8 (decisions.log DEC-0005). Measured
via a dedicated synthesis-only timing harness after the array's wide
per-processor buses were found to exhaust the device's TRELLIS_IO pin
budget as a bare top-level module beyond N=1 (errors.log ERR-0005) --
not a logic limit, an artifact of testing the array in isolation
before the Memory Manager/Director (M4/M5) exist to consume those
ports on-chip.
Full log trail (development/experiments/errors/decisions/simulation/
synthesis/timing/benchmark.log) in hardware/v2/logs/ per the project's
logging mandate.
Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
12424 lines
279 KiB
Plaintext
12424 lines
279 KiB
Plaintext
.device LFE5U-45F
|
|
|
|
.comment Part: LFE5U-45F-8CABGA381
|
|
|
|
.tile CIB_R10C39:CIB_EBR
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile CIB_R10C3:PVT_COUNT2
|
|
unknown: F2B0
|
|
unknown: F3B0
|
|
unknown: F5B0
|
|
unknown: F11B0
|
|
unknown: F13B0
|
|
|
|
.tile CIB_R1C38:CIB
|
|
arc: E3_H06E0003 JQ0
|
|
|
|
.tile CIB_R1C39:CIB
|
|
arc: E1_H02E0301 V06N0003
|
|
arc: E3_H06E0003 JQ0
|
|
|
|
.tile CIB_R1C41:CIB
|
|
arc: E3_H06E0003 W1_H02E0301
|
|
|
|
.tile CIB_R1C44:CIB
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile CIB_R1C45:CIB
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile CIB_R1C47:CIB
|
|
arc: E1_H02E0001 W3_H06E0003
|
|
arc: JA0 H02W0701
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R1C48:CIB
|
|
arc: JD7 H02E0001
|
|
arc: W1_H02W0701 V02N0701
|
|
|
|
.tile CIB_R1C50:CIB
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile CIB_R1C51:CIB
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile CIB_R1C56:CIB
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile CIB_R1C57:CIB
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile CIB_R1C62:CIB
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile CIB_R1C63:CIB
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: JA0 V02N0501
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R1C65:CIB
|
|
arc: S3_V06S0003 H06W0003
|
|
|
|
.tile CIB_R1C66:CIB
|
|
arc: JA0 V02N0501
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R1C68:CIB
|
|
arc: E3_H06E0003 JQ0
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: W3_H06W0003 JQ0
|
|
|
|
.tile CIB_R1C69:CIB
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile CIB_R1C74:CIB
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: S3_V06S0003 W3_H06E0003
|
|
arc: S3_V06S0103 W3_H06E0103
|
|
|
|
.tile CIB_R1C75:CIB
|
|
arc: S3_V06S0303 W3_H06E0303
|
|
|
|
.tile CIB_R1C77:CIB
|
|
arc: S3_V06S0103 H06E0103
|
|
|
|
.tile CIB_R1C78:CIB
|
|
arc: S3_V06S0003 JQ0
|
|
|
|
.tile CIB_R1C80:CIB
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: S3_V06S0103 W3_H06E0103
|
|
|
|
.tile CIB_R1C83:CIB
|
|
arc: S3_V06S0103 H06E0103
|
|
|
|
.tile CIB_R1C86:CIB
|
|
arc: S3_V06S0103 W3_H06E0103
|
|
|
|
.tile CIB_R20C89:CIB_LR
|
|
arc: S1_V02S0701 W1_H02E0701
|
|
|
|
.tile CIB_R22C39:CIB_DSP
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
|
|
.tile CIB_R22C64:CIB_DSP
|
|
arc: E1_H01E0001 JQ7
|
|
arc: S1_V02S0401 JQ6
|
|
arc: S1_V02S0501 JQ5
|
|
arc: S1_V02S0601 JQ4
|
|
|
|
.tile CIB_R22C65:CIB_DSP
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: N1_V02N0001 JQ2
|
|
arc: N1_V02N0301 JQ1
|
|
arc: N1_V02N0401 JQ6
|
|
arc: N1_V02N0501 JQ7
|
|
arc: N1_V02N0601 JQ4
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: S1_V02S0001 JQ0
|
|
arc: S1_V02S0101 JQ3
|
|
arc: S1_V02S0401 E1_H01W0000
|
|
arc: S1_V02S0601 H01E0001
|
|
arc: S1_V02S0701 JQ5
|
|
enum: CIB.JC1MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JC7MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
enum: CIB.JA2MUX 0
|
|
enum: CIB.JC3MUX 0
|
|
enum: CIB.JA0MUX 0
|
|
|
|
.tile CIB_R22C66:CIB_DSP
|
|
arc: E1_H02E0001 V06N0003
|
|
arc: E1_H02E0101 V01N0101
|
|
arc: E1_H02E0201 V01N0001
|
|
arc: E1_H02E0301 V06N0003
|
|
arc: E1_H02E0701 V01N0101
|
|
arc: H01W0000 JQ3
|
|
arc: H01W0100 JQ1
|
|
arc: JB6 S1_V02N0701
|
|
arc: JB7 E1_H02W0301
|
|
arc: JD6 E1_H02W0201
|
|
arc: JD7 V02N0401
|
|
arc: N1_V01N0001 JQ0
|
|
arc: S1_V02S0201 JQ2
|
|
enum: CIB.JC1MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JC7MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
|
|
.tile CIB_R22C67:CIB_DSP
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: JB0 V02N0301
|
|
arc: JB1 H00R0100
|
|
arc: JB2 E1_H02W0101
|
|
arc: JB3 V02N0101
|
|
arc: JB4 H02E0101
|
|
arc: JB5 H02E0301
|
|
arc: JB6 H02E0101
|
|
arc: JB7 H02E0301
|
|
arc: JD0 V02N0001
|
|
arc: JD1 H02W0001
|
|
arc: JD2 S1_V02N0001
|
|
arc: JD3 W1_H02E0001
|
|
arc: JD4 W1_H02E0201
|
|
arc: JD5 E1_H02W0201
|
|
arc: JD6 H02E0001
|
|
arc: JD7 H02E0201
|
|
arc: JLSR1 E1_H02W0501
|
|
|
|
.tile CIB_R22C68:CIB_DSP
|
|
arc: H00R0100 H02W0501
|
|
arc: JB0 W1_H02E0101
|
|
arc: JB1 W1_H02E0301
|
|
arc: JB2 W1_H02E0101
|
|
arc: JB3 W1_H02E0301
|
|
arc: JB4 W1_H02E0101
|
|
arc: JB5 W1_H02E0301
|
|
arc: JB6 W1_H02E0101
|
|
arc: JB7 W1_H02E0301
|
|
arc: JCE3 H00R0100
|
|
arc: JD0 W1_H02E0001
|
|
arc: JD1 V00B0100
|
|
arc: JD2 W1_H02E0001
|
|
arc: JD3 V00B0100
|
|
arc: JD4 W1_H02E0001
|
|
arc: JD5 W1_H02E0201
|
|
arc: JD6 W1_H02E0001
|
|
arc: JD7 W1_H02E0201
|
|
arc: JLSR0 V00B0000
|
|
arc: JLSR1 V00B0000
|
|
arc: V00B0000 H02W0401
|
|
arc: V00B0100 W1_H02E0701
|
|
arc: W1_H02W0001 V06N0003
|
|
arc: W1_H02W0201 V06N0103
|
|
arc: W1_H02W0301 S3_V06N0003
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
|
|
.tile CIB_R22C69:CIB_DSP
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0201 E1_H02W0701
|
|
arc: W1_H02W0401 S3_V06N0203
|
|
arc: W1_H02W0501 V02N0501
|
|
|
|
.tile CIB_R22C71:CIB_DSP
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: W1_H02W0701 V02N0701
|
|
|
|
.tile CIB_R22C72:CIB_DSP
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: S1_V02S0101 E1_H02W0101
|
|
arc: S1_V02S0201 H06W0103
|
|
arc: S1_V02S0401 E1_H01W0000
|
|
arc: S1_V02S0501 E1_H01W0100
|
|
|
|
.tile CIB_R22C73:CIB_DSP
|
|
arc: E1_H01E0001 JF4
|
|
arc: E1_H02E0001 V06N0003
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0501 V06N0303
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
arc: H00L0100 E1_H02W0301
|
|
arc: H01W0000 JQ5
|
|
arc: H01W0100 JF7
|
|
arc: JB4 H02E0301
|
|
arc: JB5 N1_V01S0000
|
|
arc: JB6 H02W0301
|
|
arc: JB7 N1_V02S0501
|
|
arc: JCE2 H00L0100
|
|
arc: JCE3 H00L0100
|
|
arc: JD4 H02W0201
|
|
arc: JD5 W1_H02E0001
|
|
arc: JD6 H02W0001
|
|
arc: JD7 H02E0201
|
|
arc: N1_V01N0001 JQ6
|
|
arc: S1_V02S0001 E1_H01W0000
|
|
arc: S1_V02S0101 E1_H02W0101
|
|
arc: S1_V02S0201 E1_H02W0201
|
|
arc: S1_V02S0301 E1_H01W0100
|
|
arc: S1_V02S0401 JQ4
|
|
arc: S1_V02S0501 JF5
|
|
arc: S1_V02S0601 JF6
|
|
arc: S1_V02S0701 H02W0701
|
|
arc: V01S0000 JQ7
|
|
|
|
.tile CIB_R22C74:CIB_DSP
|
|
arc: E1_H01E0001 JF3
|
|
arc: E1_H01E0101 JQ2
|
|
arc: E1_H02E0001 V06N0003
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: E1_H02E0201 S3_V06N0103
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0501 N1_V01S0100
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: E1_H02E0701 JQ7
|
|
arc: H01W0000 JF4
|
|
arc: H01W0100 JF6
|
|
arc: JB0 V00T0000
|
|
arc: JB1 N1_V02S0101
|
|
arc: JB2 V02N0301
|
|
arc: JB3 H02E0101
|
|
arc: JB4 V02N0701
|
|
arc: JB5 H02E0101
|
|
arc: JB6 V02N0701
|
|
arc: JB7 H02E0101
|
|
arc: JD0 H02E0001
|
|
arc: JD1 V02N0201
|
|
arc: JD2 S1_V02N0201
|
|
arc: JD3 S1_V02N0001
|
|
arc: JD4 H02E0201
|
|
arc: JD5 V02N0401
|
|
arc: JD6 H02E0201
|
|
arc: JD7 V02N0401
|
|
arc: N1_V01N0001 JF2
|
|
arc: N1_V02N0401 JQ6
|
|
arc: N1_V02N0601 JQ4
|
|
arc: S1_V02S0001 JQ0
|
|
arc: S1_V02S0101 JQ1
|
|
arc: S1_V02S0201 JF0
|
|
arc: S1_V02S0301 JQ3
|
|
arc: S1_V02S0401 E1_H01W0000
|
|
arc: S1_V02S0501 E1_H01W0100
|
|
arc: S1_V02S0601 H01E0001
|
|
arc: S1_V02S0701 JF5
|
|
arc: V00T0000 S1_V02N0601
|
|
arc: V01S0000 JQ5
|
|
arc: W1_H02W0001 V06N0003
|
|
arc: W1_H02W0101 JF1
|
|
arc: W1_H02W0201 V01N0001
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0701 JF7
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC1MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JC7MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
enum: CIB.JA2MUX 0
|
|
enum: CIB.JC3MUX 0
|
|
enum: CIB.JA0MUX 0
|
|
|
|
.tile CIB_R22C75:CIB_DSP
|
|
arc: E1_H02E0001 W1_H02E0501
|
|
arc: E1_H02E0201 W1_H02E0701
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: H01W0000 JF0
|
|
arc: H01W0100 JQ2
|
|
arc: JB0 V02N0101
|
|
arc: JB1 W1_H02E0101
|
|
arc: JB2 V02N0101
|
|
arc: JB3 W1_H02E0101
|
|
arc: JB4 V00B0100
|
|
arc: JB5 W1_H02E0101
|
|
arc: JB6 W1_H02E0101
|
|
arc: JB7 N1_V01S0000
|
|
arc: JD0 W1_H02E0201
|
|
arc: JD1 V00B0100
|
|
arc: JD2 W1_H02E0201
|
|
arc: JD3 V00B0100
|
|
arc: JD4 W1_H02E0201
|
|
arc: JD5 V01N0001
|
|
arc: JD6 H02E0201
|
|
arc: JD7 V00B0000
|
|
arc: JLSR0 V00T0100
|
|
arc: JLSR1 V00T0100
|
|
arc: N1_V01N0001 JQ0
|
|
arc: S1_V02S0001 H01E0001
|
|
arc: S1_V02S0101 H01E0101
|
|
arc: S1_V02S0301 JQ1
|
|
arc: S1_V02S0701 H02E0701
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00B0100 V02N0101
|
|
arc: V00T0100 S1_V02N0701
|
|
arc: V01S0000 JQ3
|
|
arc: W1_H02W0101 JF3
|
|
arc: W1_H02W0201 JF2
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W3_H06W0103 JF1
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JC1MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JC7MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
|
|
.tile CIB_R22C76:CIB_DSP
|
|
arc: E1_H02E0001 W1_H02E0501
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: JB0 E1_H02W0301
|
|
arc: JB1 W1_H02E0101
|
|
arc: JB2 W1_H02E0301
|
|
arc: JB3 N1_V02S0301
|
|
arc: JB4 H00R0000
|
|
arc: JB5 S1_V02N0501
|
|
arc: JB6 V00B0000
|
|
arc: JB7 S1_V02N0501
|
|
arc: JD0 V02N0001
|
|
arc: JD1 S1_V02N0001
|
|
arc: JD2 W1_H02E0001
|
|
arc: JD3 E1_H02W0201
|
|
arc: JD4 H02E0001
|
|
arc: JD5 V02N0401
|
|
arc: JD6 S1_V02N0401
|
|
arc: JD7 V00B0000
|
|
arc: JLSR1 H02E0301
|
|
arc: V00B0000 W1_H02E0601
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
|
|
.tile CIB_R22C77:CIB_DSP
|
|
arc: E1_H02E0001 S3_V06N0003
|
|
arc: E1_H02E0101 V06N0103
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0501 V06N0303
|
|
arc: E1_H02E0601 S3_V06N0303
|
|
arc: E1_H02E0701 V01N0101
|
|
arc: E3_H06E0003 W1_H02E0301
|
|
arc: H00L0100 W1_H02E0301
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: JB0 S1_V02N0101
|
|
arc: JB1 H00R0100
|
|
arc: JB2 S1_V02N0101
|
|
arc: JB3 H00R0100
|
|
arc: JB4 H00R0000
|
|
arc: JB5 S1_V02N0501
|
|
arc: JB6 V00B0000
|
|
arc: JB7 S1_V02N0501
|
|
arc: JCE3 H00L0100
|
|
arc: JD0 W1_H02E0201
|
|
arc: JD1 S1_V02N0001
|
|
arc: JD2 W1_H02E0201
|
|
arc: JD3 S1_V02N0001
|
|
arc: JD4 W1_H02E0201
|
|
arc: JD5 S1_V02N0601
|
|
arc: JD6 W1_H02E0201
|
|
arc: JD7 S1_V02N0601
|
|
arc: JLSR0 H02W0501
|
|
arc: JLSR1 H02W0501
|
|
arc: S1_V02S0601 E1_H01W0000
|
|
arc: V00B0000 S1_V02N0001
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
|
|
.tile CIB_R22C78:CIB_DSP
|
|
arc: E1_H01E0001 JF6
|
|
arc: E1_H01E0101 JF7
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: H00R0000 H02W0601
|
|
arc: H00R0100 H02E0501
|
|
arc: H01W0000 JF3
|
|
arc: JB0 V02N0101
|
|
arc: JB1 H02E0101
|
|
arc: JB2 H00R0100
|
|
arc: JB3 H02W0301
|
|
arc: JB4 H02E0301
|
|
arc: JB5 H02W0101
|
|
arc: JB6 V02N0501
|
|
arc: JB7 S1_V02N0701
|
|
arc: JCE0 H00R0000
|
|
arc: JD0 W1_H02E0001
|
|
arc: JD1 V02N0001
|
|
arc: JD2 N1_V02S0001
|
|
arc: JD3 H02E0201
|
|
arc: JD4 N1_V02S0401
|
|
arc: JD5 E1_H02W0001
|
|
arc: JD6 H02W0201
|
|
arc: JD7 S1_V02N0601
|
|
arc: JLSR0 V00B0000
|
|
arc: JLSR1 V00B0000
|
|
arc: N1_V02N0001 JF2
|
|
arc: N1_V02N0301 JF1
|
|
arc: S1_V02S0001 JF0
|
|
arc: S1_V02S0101 V01N0101
|
|
arc: S1_V02S0201 E1_H01W0000
|
|
arc: S1_V02S0401 V01N0001
|
|
arc: S1_V02S0501 JF5
|
|
arc: S1_V02S0601 JF4
|
|
arc: S1_V02S0701 E1_H01W0100
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
|
|
.tile CIB_R22C79:CIB_DSP
|
|
arc: E1_H01E0001 JF1
|
|
arc: E1_H01E0101 JF7
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: H00R0100 V02N0501
|
|
arc: H01W0000 JF0
|
|
arc: H01W0100 JF6
|
|
arc: JB0 H00R0100
|
|
arc: JB1 S1_V02N0301
|
|
arc: JB2 H00R0100
|
|
arc: JB3 S1_V02N0301
|
|
arc: JB4 V02N0501
|
|
arc: JB5 H00R0000
|
|
arc: JB6 V02N0501
|
|
arc: JB7 H02E0101
|
|
arc: JD0 S1_V02N0201
|
|
arc: JD1 V00B0100
|
|
arc: JD2 S1_V02N0201
|
|
arc: JD3 V00B0100
|
|
arc: JD4 W1_H02E0001
|
|
arc: JD5 H00R0100
|
|
arc: JD6 W1_H02E0001
|
|
arc: JD7 H00R0100
|
|
arc: JLSR1 E1_H02W0301
|
|
arc: N1_V01N0001 JF4
|
|
arc: S1_V02S0001 JF2
|
|
arc: S1_V02S0101 V01N0101
|
|
arc: S1_V02S0201 H01E0001
|
|
arc: S1_V02S0501 JF5
|
|
arc: S1_V02S0701 H01E0101
|
|
arc: V00B0100 W1_H02E0701
|
|
arc: V01S0000 JF3
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0301 V06N0003
|
|
arc: W1_H02W0601 E1_H02W0301
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
|
|
.tile CIB_R22C80:CIB_DSP
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 V02N0701
|
|
arc: JB0 H00R0100
|
|
arc: JB1 S1_V02N0101
|
|
arc: JD0 S1_V02N0201
|
|
arc: JD1 H00R0000
|
|
arc: S1_V02S0101 H01E0101
|
|
arc: S1_V02S0201 H01E0001
|
|
arc: W1_H02W0001 S1_V02N0001
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
|
|
.tile CIB_R22C81:CIB_DSP
|
|
arc: W1_H02W0301 E1_H02W0301
|
|
|
|
.tile CIB_R22C83:CIB_DSP
|
|
arc: W1_H02W0301 W3_H06E0003
|
|
|
|
.tile CIB_R22C89:CIB_LR_S
|
|
arc: JA3 N1_V02S0701
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R31C89:CIB_LR
|
|
arc: JA3 V02N0701
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R32C89:CIB_LR
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
arc: W3_H06W0303 JQ5
|
|
|
|
.tile CIB_R34C39:CIB_EBR
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
|
|
.tile CIB_R34C69:CIB_EBR
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
|
|
.tile CIB_R34C73:CIB_EBR
|
|
arc: E1_H02E0101 V06N0103
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
|
|
.tile CIB_R34C74:CIB_EBR
|
|
arc: N3_V06N0003 V01N0001
|
|
arc: S1_V02S0401 N1_V02S0101
|
|
|
|
.tile CIB_R34C75:CIB_EBR
|
|
arc: N1_V02N0101 W1_H02E0101
|
|
arc: N1_V02N0301 W1_H02E0301
|
|
|
|
.tile CIB_R34C78:CIB_EBR
|
|
arc: N1_V01N0101 S3_V06N0203
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0301 N1_V01S0100
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: S3_V06S0003 N1_V02S0301
|
|
|
|
.tile CIB_R34C79:CIB_EBR
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0401 N1_V01S0000
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
|
|
.tile CIB_R34C80:CIB_EBR
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
|
|
.tile CIB_R34C86:CIB_EBR
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
|
|
.tile CIB_R34C88:CIB_EBR
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
|
|
.tile CIB_R34C89:CIB_LR_S
|
|
arc: JA3 H02E0501
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R37C1:CIB_LR
|
|
arc: E3_H06E0303 JQ5
|
|
|
|
.tile CIB_R41C89:CIB_LR
|
|
arc: W1_H02W0701 JF5
|
|
|
|
.tile CIB_R46C39:CIB_DSP
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile CIB_R46C64:CIB_DSP
|
|
arc: E1_H01E0101 JQ6
|
|
arc: N1_V01N0001 JQ5
|
|
arc: N1_V02N0401 JQ4
|
|
arc: N1_V02N0501 JQ7
|
|
arc: S1_V02S0601 E1_H01W0000
|
|
|
|
.tile CIB_R46C65:CIB_DSP
|
|
arc: E1_H02E0001 N1_V02S0001
|
|
arc: E1_H02E0101 N1_V02S0101
|
|
arc: E1_H02E0401 N1_V02S0401
|
|
arc: H01W0000 JQ1
|
|
arc: N1_V01N0001 JQ5
|
|
arc: N1_V02N0001 JQ0
|
|
arc: N1_V02N0201 JQ2
|
|
arc: N1_V02N0401 JQ4
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0601 JQ6
|
|
arc: S1_V02S0001 E1_H01W0000
|
|
arc: S1_V02S0101 JQ3
|
|
arc: S1_V02S0501 E1_H01W0100
|
|
arc: S1_V02S0701 JQ7
|
|
enum: CIB.JC1MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JC7MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
enum: CIB.JA2MUX 0
|
|
enum: CIB.JC3MUX 0
|
|
enum: CIB.JA0MUX 0
|
|
|
|
.tile CIB_R46C66:CIB_DSP
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: H01W0000 JQ2
|
|
arc: H01W0100 JQ1
|
|
arc: JB6 V00B0000
|
|
arc: JB7 N1_V02S0501
|
|
arc: JD6 V02S0401
|
|
arc: JD7 V02N0401
|
|
arc: N1_V01N0001 JQ3
|
|
arc: S1_V02S0201 JQ0
|
|
arc: V00B0000 H02E0401
|
|
enum: CIB.JC1MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JC7MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
|
|
.tile CIB_R46C67:CIB_DSP
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0301 N1_V02S0301
|
|
arc: H00L0100 W1_H02E0101
|
|
arc: H00R0000 N1_V02S0601
|
|
arc: JB0 H02E0101
|
|
arc: JB1 E1_H01W0100
|
|
arc: JB2 V02S0301
|
|
arc: JB3 N1_V02S0101
|
|
arc: JB4 W1_H02E0101
|
|
arc: JB5 H00R0000
|
|
arc: JB6 W1_H02E0101
|
|
arc: JB7 V00B0100
|
|
arc: JD0 H02W0201
|
|
arc: JD1 H02E0001
|
|
arc: JD2 W1_H02E0001
|
|
arc: JD3 N1_V02S0001
|
|
arc: JD4 N1_V02S0401
|
|
arc: JD5 V00B0000
|
|
arc: JD6 N1_V02S0601
|
|
arc: JD7 H00L0100
|
|
arc: JLSR1 E1_H02W0501
|
|
arc: V00B0000 H02W0401
|
|
arc: V00B0100 N1_V02S0301
|
|
|
|
.tile CIB_R46C68:CIB_DSP
|
|
arc: H00R0100 H02W0501
|
|
arc: H01W0100 E3_H06W0303
|
|
arc: JB0 N1_V02S0101
|
|
arc: JB1 H02E0301
|
|
arc: JB2 N1_V02S0101
|
|
arc: JB3 H02E0301
|
|
arc: JB4 V00B0100
|
|
arc: JB5 H02E0301
|
|
arc: JB6 V00B0000
|
|
arc: JB7 H02E0301
|
|
arc: JCE3 H00R0100
|
|
arc: JD0 H02E0201
|
|
arc: JD1 V00B0100
|
|
arc: JD2 H02E0201
|
|
arc: JD3 V00B0100
|
|
arc: JD4 H02E0201
|
|
arc: JD5 V00B0000
|
|
arc: JD6 H02E0201
|
|
arc: JD7 V00B0000
|
|
arc: JLSR0 H02W0301
|
|
arc: JLSR1 H02W0301
|
|
arc: V00B0000 N1_V02S0201
|
|
arc: V00B0100 N1_V02S0101
|
|
arc: W1_H02W0201 N1_V01S0000
|
|
arc: W1_H02W0401 N1_V02S0401
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
|
|
.tile CIB_R46C69:CIB_DSP
|
|
arc: E1_H02E0501 V06S0303
|
|
arc: N3_V06N0003 S1_V02N0301
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0501 V06S0303
|
|
|
|
.tile CIB_R46C71:CIB_DSP
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
|
|
.tile CIB_R46C72:CIB_DSP
|
|
arc: E1_H02E0201 V06S0103
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
|
|
.tile CIB_R46C73:CIB_DSP
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: E1_H02E0301 V06S0003
|
|
arc: E1_H02E0401 JQ6
|
|
arc: H00L0000 N1_V02S0001
|
|
arc: H00R0000 E1_H02W0601
|
|
arc: H00R0100 W1_H02E0501
|
|
arc: H01W0000 JQ5
|
|
arc: JB4 H00L0000
|
|
arc: JB5 H02W0101
|
|
arc: JB6 V00B0100
|
|
arc: JB7 N1_V02S0501
|
|
arc: JCE2 H00R0000
|
|
arc: JCE3 H00R0100
|
|
arc: JD4 N1_V02S0401
|
|
arc: JD5 N1_V02S0601
|
|
arc: JD6 H02W0201
|
|
arc: JD7 V02N0401
|
|
arc: N1_V01N0001 JQ7
|
|
arc: N1_V01N0101 JQ4
|
|
arc: N1_V02N0401 JF4
|
|
arc: N1_V02N0501 JF7
|
|
arc: N1_V02N0601 JF6
|
|
arc: N1_V02N0701 JF5
|
|
arc: S1_V02S0001 E1_H01W0000
|
|
arc: S1_V02S0301 H02W0301
|
|
arc: S1_V02S0501 E1_H01W0100
|
|
arc: V00B0100 N1_V02S0101
|
|
|
|
.tile CIB_R46C74:CIB_DSP
|
|
arc: E1_H01E0001 JF6
|
|
arc: E1_H01E0101 JF0
|
|
arc: E1_H02E0101 N3_V06S0103
|
|
arc: E1_H02E0201 V01N0001
|
|
arc: E1_H02E0301 N3_V06S0003
|
|
arc: E1_H02E0401 V06S0203
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
arc: E1_H02E0701 V06S0203
|
|
arc: E3_H06E0303 V06S0303
|
|
arc: H00R0100 V02S0501
|
|
arc: H01W0000 JF7
|
|
arc: H01W0100 JF3
|
|
arc: JB0 V02N0301
|
|
arc: JB1 N1_V02S0301
|
|
arc: JB2 H00R0100
|
|
arc: JB3 H02E0301
|
|
arc: JB4 V02S0501
|
|
arc: JB5 H02E0301
|
|
arc: JB6 V02S0501
|
|
arc: JB7 H02E0301
|
|
arc: JD0 N1_V01S0000
|
|
arc: JD1 W1_H02E0201
|
|
arc: JD2 V00T0100
|
|
arc: JD3 N1_V02S0201
|
|
arc: JD4 H02E0001
|
|
arc: JD5 V02S0401
|
|
arc: JD6 H02E0001
|
|
arc: JD7 V02S0401
|
|
arc: N1_V01N0001 JQ3
|
|
arc: N1_V01N0101 JF2
|
|
arc: N1_V02N0001 JQ0
|
|
arc: N1_V02N0101 JQ1
|
|
arc: N1_V02N0201 JQ2
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: N1_V02N0401 JQ6
|
|
arc: N1_V02N0601 JF4
|
|
arc: N1_V02N0701 JQ5
|
|
arc: S1_V02S0401 JQ4
|
|
arc: S1_V02S0701 JF5
|
|
arc: V00T0100 N1_V02S0501
|
|
arc: V01S0000 JQ7
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0201 N3_V06S0103
|
|
arc: W1_H02W0301 JF1
|
|
arc: W3_H06W0303 V06S0303
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC1MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JC7MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
enum: CIB.JA2MUX 0
|
|
enum: CIB.JC3MUX 0
|
|
enum: CIB.JA0MUX 0
|
|
|
|
.tile CIB_R46C75:CIB_DSP
|
|
arc: E1_H01E0001 JF1
|
|
arc: E1_H02E0101 V06S0103
|
|
arc: E1_H02E0501 V06S0303
|
|
arc: E3_H06E0303 V06S0303
|
|
arc: H00R0000 H02E0401
|
|
arc: H00R0100 H02E0701
|
|
arc: H01W0100 JQ3
|
|
arc: JB0 H00R0100
|
|
arc: JB1 W1_H02E0301
|
|
arc: JB2 H00R0000
|
|
arc: JB3 W1_H02E0301
|
|
arc: JB4 H00R0000
|
|
arc: JB5 W1_H02E0301
|
|
arc: JB6 N1_V02S0501
|
|
arc: JB7 N1_V02S0701
|
|
arc: JD0 W1_H02E0001
|
|
arc: JD1 H00R0000
|
|
arc: JD2 W1_H02E0001
|
|
arc: JD3 H00R0000
|
|
arc: JD4 W1_H02E0001
|
|
arc: JD5 H00R0100
|
|
arc: JD6 N1_V02S0601
|
|
arc: JD7 W1_H02E0001
|
|
arc: JLSR0 V00B0100
|
|
arc: JLSR1 V00B0100
|
|
arc: N1_V01N0001 JF0
|
|
arc: N1_V01N0101 JF2
|
|
arc: N1_V02N0001 JQ0
|
|
arc: N1_V02N0101 JQ1
|
|
arc: N1_V02N0201 JQ2
|
|
arc: N1_V02N0301 JF3
|
|
arc: N1_V02N0401 W1_H02E0401
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: V00B0100 N1_V02S0301
|
|
arc: W1_H02W0601 V06S0303
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JC1MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JC7MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
|
|
.tile CIB_R46C76:CIB_DSP
|
|
arc: E1_H02E0001 W1_H02E0501
|
|
arc: H00L0100 N1_V02S0101
|
|
arc: H00R0100 V02N0501
|
|
arc: JB0 H00R0100
|
|
arc: JB1 W1_H02E0101
|
|
arc: JB2 H02E0101
|
|
arc: JB3 W1_H02E0301
|
|
arc: JB4 V00B0100
|
|
arc: JB5 N1_V02S0501
|
|
arc: JB6 V00B0100
|
|
arc: JB7 N1_V02S0501
|
|
arc: JD0 N1_V02S0201
|
|
arc: JD1 S1_V02N0201
|
|
arc: JD2 W1_H02E0201
|
|
arc: JD3 H02W0001
|
|
arc: JD4 N1_V02S0401
|
|
arc: JD5 E1_H02W0001
|
|
arc: JD6 N1_V02S0601
|
|
arc: JD7 H00L0100
|
|
arc: JLSR1 H02E0501
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: V00B0100 N1_V02S0101
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
|
|
.tile CIB_R46C77:CIB_DSP
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: E1_H02E0201 N3_V06S0103
|
|
arc: E1_H02E0301 N1_V02S0301
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
arc: H00R0000 N1_V02S0601
|
|
arc: H00R0100 W1_H02E0501
|
|
arc: JB0 V00B0000
|
|
arc: JB1 V00T0000
|
|
arc: JB2 N1_V02S0101
|
|
arc: JB3 H00R0000
|
|
arc: JB4 V00B0100
|
|
arc: JB5 H00R0000
|
|
arc: JB6 V00B0100
|
|
arc: JB7 V00T0000
|
|
arc: JCE3 H00R0100
|
|
arc: JD0 H02E0001
|
|
arc: JD1 V00B0100
|
|
arc: JD2 H02E0001
|
|
arc: JD3 N1_V02S0201
|
|
arc: JD4 N1_V02S0601
|
|
arc: JD5 V00B0000
|
|
arc: JD6 N1_V02S0601
|
|
arc: JD7 V00B0000
|
|
arc: JLSR0 H02W0501
|
|
arc: JLSR1 H02W0501
|
|
arc: N1_V02N0501 H02W0501
|
|
arc: V00B0000 N1_V02S0201
|
|
arc: V00B0100 N1_V02S0101
|
|
arc: V00T0000 N1_V02S0601
|
|
arc: W1_H02W0001 N1_V02S0001
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
|
|
.tile CIB_R46C78:CIB_DSP
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: H00R0000 H02W0401
|
|
arc: H00R0100 H02W0501
|
|
arc: JB0 H00R0100
|
|
arc: JB1 N1_V02S0101
|
|
arc: JB2 H02W0301
|
|
arc: JB3 N1_V02S0301
|
|
arc: JB4 H02E0301
|
|
arc: JB5 N1_V02S0501
|
|
arc: JB6 V00B0000
|
|
arc: JB7 N1_V02S0701
|
|
arc: JCE0 E1_H02W0101
|
|
arc: JD0 N1_V02S0001
|
|
arc: JD1 V00B0100
|
|
arc: JD2 N1_V02S0201
|
|
arc: JD3 H00R0000
|
|
arc: JD4 H02E0201
|
|
arc: JD5 V02N0401
|
|
arc: JD6 H02E0001
|
|
arc: JD7 V02S0601
|
|
arc: JLSR0 V00T0000
|
|
arc: JLSR1 V00T0000
|
|
arc: N1_V02N0101 N1_V01S0100
|
|
arc: N1_V02N0201 V01N0001
|
|
arc: N1_V02N0301 JF3
|
|
arc: N1_V02N0401 JF6
|
|
arc: N1_V02N0501 V01N0101
|
|
arc: N1_V02N0601 JF4
|
|
arc: N1_V02N0701 JF5
|
|
arc: N3_V06N0203 S1_V02N0401
|
|
arc: S1_V02S0001 JF2
|
|
arc: S1_V02S0101 JF1
|
|
arc: S1_V02S0201 JF0
|
|
arc: S1_V02S0401 E1_H01W0000
|
|
arc: S1_V02S0501 E1_H01W0100
|
|
arc: S1_V02S0601 H02W0601
|
|
arc: S1_V02S0701 JF7
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 H02E0501
|
|
arc: V00T0000 S1_V02N0401
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
|
|
.tile CIB_R46C79:CIB_DSP
|
|
arc: E1_H01E0001 JF2
|
|
arc: E1_H01E0101 JF3
|
|
arc: H01W0000 JF1
|
|
arc: H01W0100 JF4
|
|
arc: JB0 H02E0301
|
|
arc: JB1 E1_H01W0100
|
|
arc: JB2 H02E0301
|
|
arc: JB3 E1_H01W0100
|
|
arc: JB4 H02E0301
|
|
arc: JB5 N1_V02S0701
|
|
arc: JB6 H02E0301
|
|
arc: JB7 N1_V02S0701
|
|
arc: JD0 N1_V02S0001
|
|
arc: JD1 H02E0001
|
|
arc: JD2 N1_V02S0001
|
|
arc: JD3 H02E0001
|
|
arc: JD4 E1_H01W0100
|
|
arc: JD5 H02E0001
|
|
arc: JD6 E1_H01W0100
|
|
arc: JD7 H02E0001
|
|
arc: JLSR1 E1_H02W0501
|
|
arc: N1_V01N0001 JF6
|
|
arc: N1_V01N0101 JF5
|
|
arc: N1_V02N0001 JF0
|
|
arc: N1_V02N0701 JF7
|
|
arc: W1_H02W0301 N1_V02S0301
|
|
arc: W1_H02W0401 N1_V02S0401
|
|
arc: W1_H02W0501 V06S0303
|
|
arc: W1_H02W0601 V02N0601
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
|
|
.tile CIB_R46C80:CIB_DSP
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: JB0 W1_H02E0301
|
|
arc: JB1 H01W0100
|
|
arc: JD0 V02S0001
|
|
arc: JD1 W1_H02E0001
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: W1_H02W0101 E1_H01W0100
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
|
|
.tile CIB_R46C81:CIB_DSP
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: W1_H02W0501 W3_H06E0303
|
|
|
|
.tile CIB_R46C85:CIB_DSP
|
|
arc: N1_V02N0101 H06W0103
|
|
|
|
.tile CIB_R46C88:CIB_DSP
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
|
|
.tile CIB_R46C89:CIB_LR_S
|
|
arc: H01W0100 JQ5
|
|
|
|
.tile CIB_R58C39:CIB_EBR
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile CIB_R5C1:CIB_PLL1
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R5C89:CIB_PLL1
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R62C89:CIB_LR
|
|
arc: S1_V02S0501 H06E0303
|
|
|
|
.tile CIB_R64C89:CIB_LR
|
|
arc: JA3 N1_V02S0501
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R70C16:CIB
|
|
arc: JA0 N1_V02S0701
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R70C18:CIB
|
|
arc: E3_H06E0003 JQ0
|
|
|
|
.tile CIB_R70C24:CIB
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile CIB_R70C30:CIB
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile CIB_R70C36:CIB
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile CIB_R70C39:CIB
|
|
arc: N3_V06N0103 H06E0103
|
|
|
|
.tile CIB_R70C3:CIB_PLL3
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile CIB_R70C42:VCIB_DCU0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C43:VCIB_DCUA
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C44:VCIB_DCUB
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C45:VCIB_DCUC
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C46:VCIB_DCUD
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C47:VCIB_DCUF
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C48:VCIB_DCU3
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C49:VCIB_DCU2
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C50:VCIB_DCUG
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C51:VCIB_DCUH
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C52:VCIB_DCUI
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C53:VCIB_DCU1
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
|
|
.tile CIB_R70C69:VCIB_DCU0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C6:CIB_EFB0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C70:VCIB_DCUA
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C71:VCIB_DCUB
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C72:VCIB_DCUC
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C73:VCIB_DCUD
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C74:VCIB_DCUF
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C75:VCIB_DCU3
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C76:VCIB_DCU2
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C77:VCIB_DCUG
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C78:VCIB_DCUH
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C79:VCIB_DCUI
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C7:CIB_EFB1
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB4MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB6MUX 0
|
|
enum: CIB.JC3MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
enum: CIB.JD3MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD5MUX 0
|
|
|
|
.tile CIB_R70C80:VCIB_DCU1
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
|
|
.tile CIB_R70C87:CIB_PLL3
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile MIB_R0C38:PIOT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C39:PIOT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C40:TMID_0
|
|
arc: G_TDCC0CLKI G_JTRQPCLKCIB1
|
|
|
|
.tile MIB_R0C47:PIOT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C63:PIOT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C66:PIOT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R0C68:PIOT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C78:PIOT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C87:BANKREF1
|
|
enum: BANK.VCCIO 3V3
|
|
|
|
.tile MIB_R10C40:CMUX_UL_0
|
|
arc: G_DCS0CLK0 G_VPFN0000
|
|
arc: G_ULPCLK0 G_VPFS0000
|
|
|
|
.tile MIB_R10C41:CMUX_UR_0
|
|
arc: G_DCS0CLK1 G_VPFN0000
|
|
arc: G_URPCLK0 G_VPFS0000
|
|
|
|
.tile MIB_R10C77:EBR_SPINE_UR1
|
|
arc: G_VPTX0000 G_HPRX0000
|
|
|
|
.tile MIB_R10C90:BANKREF2
|
|
enum: BANK.VCCIO 3V3
|
|
|
|
.tile MIB_R1C38:PICT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C39:PICT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C47:PICT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C63:PICT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C66:PICT1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C68:PICT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C78:PICT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R21C90:PICR1
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R22C78:MIB_DSP0
|
|
arc: JMULTA0 JMUIA0
|
|
arc: JMULTA1 JMUIA1
|
|
arc: JMULTA10 JMUIA10
|
|
arc: JMULTA11 JMUIA11
|
|
arc: JMULTA12 JMUIA12
|
|
arc: JMULTA13 JMUIA13
|
|
arc: JMULTA14 JMUIA14
|
|
arc: JMULTA15 JMUIA15
|
|
arc: JMULTA16 JMUIA16
|
|
arc: JMULTA17 JMUIA17
|
|
arc: JMULTA2 JMUIA2
|
|
arc: JMULTA3 JMUIA3
|
|
arc: JMULTA4 JMUIA4
|
|
arc: JMULTA5 JMUIA5
|
|
arc: JMULTA6 JMUIA6
|
|
arc: JMULTA7 JMUIA7
|
|
arc: JMULTA8 JMUIA8
|
|
arc: JMULTA9 JMUIA9
|
|
|
|
.tile MIB_R22C90:MIB_CIB_LR_A
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R30C90:PICR1_DQS3
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R31C90:PICR2
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R32C90:PICR0
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R33C90:PICR1
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R34C90:MIB_CIB_LR_A
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R36C0:PICL1
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
|
|
.tile MIB_R37C0:PICL2
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R41C90:PICR0_DQS2
|
|
arc: JDIA JPADDIA_PIO
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R42C90:PICR1_DQS3
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R45C90:PICR1
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
|
|
.tile MIB_R46C78:MIB_DSP0
|
|
arc: JMULTA0 JMUIA0
|
|
arc: JMULTA1 JMUIA1
|
|
arc: JMULTA10 JMUIA10
|
|
arc: JMULTA11 JMUIA11
|
|
arc: JMULTA12 JMUIA12
|
|
arc: JMULTA13 JMUIA13
|
|
arc: JMULTA14 JMUIA14
|
|
arc: JMULTA15 JMUIA15
|
|
arc: JMULTA16 JMUIA16
|
|
arc: JMULTA17 JMUIA17
|
|
arc: JMULTA2 JMUIA2
|
|
arc: JMULTA3 JMUIA3
|
|
arc: JMULTA4 JMUIA4
|
|
arc: JMULTA5 JMUIA5
|
|
arc: JMULTA6 JMUIA6
|
|
arc: JMULTA7 JMUIA7
|
|
arc: JMULTA8 JMUIA8
|
|
arc: JMULTA9 JMUIA9
|
|
|
|
.tile MIB_R46C90:MIB_CIB_LR_A
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R58C40:CMUX_LL_0
|
|
arc: G_DCS1CLK0 G_VPFN0000
|
|
arc: G_LLPCLK0 G_VPFS0000
|
|
|
|
.tile MIB_R58C41:CMUX_LR_0
|
|
arc: G_DCS1CLK1 G_VPFN0000
|
|
arc: G_LRPCLK0 G_VPFS0000
|
|
|
|
.tile MIB_R58C77:EBR_SPINE_LR1
|
|
arc: G_VPTX0000 G_HPRX0000
|
|
|
|
.tile MIB_R63C90:PICR1_DQS0
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R64C90:PICR2_DQS1
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R66C90:PICR1_DQS3
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
|
|
.tile MIB_R67C90:PICR2
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R71C16:PICB1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R71C18:SPICB0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R71C3:BANKREF8
|
|
enum: BANK.VCCIO 3V3
|
|
|
|
.tile MIB_R71C4:EFB0_PICB0
|
|
unknown: F54B1
|
|
unknown: F56B1
|
|
unknown: F82B1
|
|
unknown: F94B1
|
|
|
|
.tile MIB_R71C89:BANKREF3
|
|
enum: BANK.VCCIO 3V3
|
|
|
|
.tile R13C65:PLC2
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
|
|
.tile R13C74:PLC2
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile R13C75:PLC2
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
|
|
.tile R13C77:PLC2
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile R13C78:PLC2
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
|
|
.tile R13C80:PLC2
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
|
|
.tile R13C83:PLC2
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile R13C86:PLC2
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile R14C48:PLC2
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile R14C63:PLC2
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
|
|
.tile R14C66:PLC2
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile R16C39:PLC2
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile R19C65:PLC2
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: V01S0000 N3_V06S0103
|
|
|
|
.tile R19C74:PLC2
|
|
arc: S1_V02S0201 N3_V06S0103
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
|
|
.tile R19C75:PLC2
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
|
|
.tile R19C77:PLC2
|
|
arc: S1_V02S0701 N3_V06S0203
|
|
|
|
.tile R19C78:PLC2
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile R19C80:PLC2
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile R19C83:PLC2
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
|
|
.tile R19C86:PLC2
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
|
|
.tile R20C48:PLC2
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
|
|
.tile R20C63:PLC2
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
|
|
.tile R20C65:PLC2
|
|
arc: S1_V02S0601 N1_V01S0000
|
|
|
|
.tile R20C66:PLC2
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
|
|
.tile R20C73:PLC2
|
|
arc: S1_V02S0501 H02W0501
|
|
|
|
.tile R20C74:PLC2
|
|
arc: E1_H02E0301 S3_V06N0003
|
|
arc: E1_H02E0501 S3_V06N0303
|
|
arc: S1_V02S0101 S3_V06N0103
|
|
arc: W1_H02W0501 S3_V06N0303
|
|
|
|
.tile R20C76:PLC2
|
|
arc: E1_H02E0001 W1_H02E0501
|
|
arc: E1_H02E0401 S3_V06N0203
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
|
|
.tile R20C78:PLC2
|
|
arc: S1_V02S0001 W1_H02E0001
|
|
arc: S1_V02S0401 W1_H02E0401
|
|
|
|
.tile R20C87:PLC2
|
|
arc: E1_H02E0701 S3_V06N0203
|
|
|
|
.tile R21C65:PLC2
|
|
arc: H00L0000 V02N0001
|
|
arc: H00L0100 V02N0301
|
|
arc: H00R0000 V02N0601
|
|
arc: H00R0100 V02N0701
|
|
arc: V00T0000 V02N0401
|
|
arc: V00T0100 V02N0501
|
|
arc: CE0 S1_V02N0201
|
|
arc: CE1 S1_V02N0201
|
|
arc: CE2 V02S0601
|
|
arc: CE3 V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0103 Q1
|
|
arc: E3_H06E0203 Q7
|
|
arc: E3_H06E0303 Q5
|
|
arc: M0 V00T0000
|
|
arc: M1 H00R0000
|
|
arc: M2 H02W0601
|
|
arc: M3 H00R0100
|
|
arc: M4 V00T0100
|
|
arc: M5 H00L0000
|
|
arc: M7 H00L0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S3_V06S0003 Q3
|
|
arc: S3_V06S0103 Q2
|
|
arc: S3_V06S0203 Q4
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C66:PLC2
|
|
arc: W1_H02W0601 V01N0001
|
|
|
|
.tile R21C71:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: S3_V06S0003 W3_H06E0003
|
|
|
|
.tile R21C73:PLC2
|
|
arc: S1_V02S0201 V01N0001
|
|
arc: V01S0000 S3_V06N0103
|
|
|
|
.tile R21C74:PLC2
|
|
arc: H00L0000 N1_V02S0201
|
|
arc: H00R0000 V02N0601
|
|
arc: S1_V02S0301 N1_V02S0201
|
|
arc: S1_V02S0601 V01N0001
|
|
arc: V00T0000 V02N0401
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: CE1 N1_V02S0201
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M3 H00R0000
|
|
arc: M4 V00T0000
|
|
arc: M6 H02W0401
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S3_V06S0003 Q3
|
|
arc: S3_V06S0203 Q4
|
|
arc: S3_V06S0303 Q6
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C75:PLC2
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: W1_H02W0401 V01N0001
|
|
|
|
.tile R21C77:PLC2
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E1_H02E0701 N1_V02S0701
|
|
arc: S1_V02S0201 N1_V02S0701
|
|
arc: S1_V02S0701 N1_V02S0701
|
|
arc: S3_V06S0003 W3_H06E0003
|
|
arc: S3_V06S0303 W3_H06E0303
|
|
|
|
.tile R21C78:PLC2
|
|
arc: H00R0100 H02E0701
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 V02N0301
|
|
arc: CE1 H00R0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M2 V00B0100
|
|
arc: M6 V00B0000
|
|
arc: M7 H02W0201
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0201 Q2
|
|
arc: S1_V02S0501 Q7
|
|
arc: S1_V02S0601 Q6
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R21C79:PLC2
|
|
arc: S1_V02S0101 W1_H02E0101
|
|
arc: S1_V02S0701 W1_H02E0701
|
|
arc: W1_H02W0201 V01N0001
|
|
|
|
.tile R23C64:PLC2
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: E1_H02E0501 V02S0501
|
|
arc: E1_H02E0601 V02S0601
|
|
|
|
.tile R23C65:PLC2
|
|
arc: H00L0000 V02S0001
|
|
arc: H00L0100 V02S0101
|
|
arc: H00R0000 V02S0601
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: V00B0000 H02E0601
|
|
arc: V00B0100 H02E0501
|
|
arc: V00T0100 V02S0701
|
|
arc: CE0 S1_V02N0201
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q2
|
|
arc: E1_H01E0101 Q4
|
|
arc: E1_H02E0701 Q5
|
|
arc: E3_H06E0003 Q3
|
|
arc: E3_H06E0103 Q1
|
|
arc: E3_H06E0203 Q7
|
|
arc: E3_H06E0303 Q6
|
|
arc: M0 V00B0100
|
|
arc: M1 H00R0000
|
|
arc: M2 V00T0100
|
|
arc: M3 H00L0100
|
|
arc: M4 V00B0000
|
|
arc: M5 H00L0000
|
|
arc: M6 H02E0401
|
|
arc: M7 H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: V01S0100 Q0
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C66:PLC2
|
|
arc: E3_H06E0203 H01E0001
|
|
arc: E3_H06E0303 H01E0101
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: V00B0000 V02N0001
|
|
arc: W1_H02W0201 V02S0201
|
|
arc: CE0 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M0 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: N1_V01N0001 Q0
|
|
arc: N1_V01N0101 Q0
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C67:PLC2
|
|
arc: E3_H06E0203 W1_H02E0701
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0301 H02W0301
|
|
|
|
.tile R23C68:PLC2
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0301 V06N0003
|
|
|
|
.tile R23C69:PLC2
|
|
arc: N1_V02N0101 E3_H06W0103
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
|
|
.tile R23C71:PLC2
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: N1_V02N0701 E3_H06W0203
|
|
|
|
.tile R23C72:PLC2
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
arc: H00L0000 V02S0201
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: S3_V06S0003 E1_H01W0000
|
|
arc: CE0 E1_H02W0101
|
|
arc: CE2 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M1 H00R0100
|
|
arc: M5 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: S1_V02S0101 Q1
|
|
arc: S3_V06S0303 Q5
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C73:PLC2
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: E1_H02E0201 N1_V02S0201
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: E3_H06E0303 W1_H02E0501
|
|
arc: H00L0000 V02S0201
|
|
arc: H00L0100 V02S0101
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: V00B0000 V02S0001
|
|
arc: V00B0100 H02W0701
|
|
arc: V00T0100 V02S0501
|
|
arc: CE0 H02W0101
|
|
arc: CE1 H02W0101
|
|
arc: CE2 H02W0101
|
|
arc: CE3 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: H01W0000 Q0
|
|
arc: M0 H02W0601
|
|
arc: M1 E1_H02W0001
|
|
arc: M2 V00B0000
|
|
arc: M3 H00L0100
|
|
arc: M4 V00B0100
|
|
arc: M5 H00L0000
|
|
arc: M6 V00T0100
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0301 Q1
|
|
arc: S1_V02S0501 Q7
|
|
arc: S3_V06S0003 Q3
|
|
arc: S3_V06S0103 Q2
|
|
arc: S3_V06S0203 Q4
|
|
arc: S3_V06S0303 Q6
|
|
arc: V01S0000 Q5
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C74:PLC2
|
|
arc: E1_H02E0001 S3_V06N0003
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0201 N1_V01S0000
|
|
arc: H00L0000 S1_V02N0201
|
|
arc: H00L0100 V02S0301
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: S1_V02S0601 N1_V02S0301
|
|
arc: V00B0100 V02S0101
|
|
arc: V00T0100 H02W0301
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: W1_H02W0601 N1_V02S0601
|
|
arc: W1_H02W0701 V02S0701
|
|
arc: CE0 S1_V02N0201
|
|
arc: CE1 S1_V02N0201
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q6
|
|
arc: E1_H01E0101 Q3
|
|
arc: M0 H02W0601
|
|
arc: M1 H02E0001
|
|
arc: M2 V00B0100
|
|
arc: M3 H00L0100
|
|
arc: M4 W1_H02E0401
|
|
arc: M5 H00R0100
|
|
arc: M6 V00T0100
|
|
arc: M7 H02E0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0201 Q2
|
|
arc: S1_V02S0501 Q7
|
|
arc: S3_V06S0003 Q0
|
|
arc: S3_V06S0103 Q1
|
|
arc: S3_V06S0203 Q4
|
|
arc: S3_V06S0303 Q5
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C75:PLC2
|
|
arc: E1_H02E0201 V01N0001
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: S3_V06S0103 H01E0101
|
|
arc: S3_V06S0203 H01E0001
|
|
arc: V00B0100 V02S0101
|
|
arc: W1_H02W0001 V02S0001
|
|
arc: W1_H02W0301 V02S0301
|
|
arc: W1_H02W0601 N1_V01S0000
|
|
arc: CE0 V02N0201
|
|
arc: CE1 H02E0101
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: H01W0000 Q1
|
|
arc: H01W0100 Q1
|
|
arc: M1 H00R0000
|
|
arc: M3 H00R0100
|
|
arc: M6 V00B0100
|
|
arc: M7 H02E0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q1
|
|
arc: N1_V02N0101 Q1
|
|
arc: S1_V02S0501 Q7
|
|
arc: S3_V06S0003 Q3
|
|
arc: S3_V06S0303 Q6
|
|
arc: V01S0100 Q1
|
|
arc: W3_H06W0103 Q1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C76:PLC2
|
|
arc: N1_V02N0001 W1_H02E0001
|
|
arc: N1_V02N0401 H02W0401
|
|
|
|
.tile R23C77:PLC2
|
|
arc: E1_H02E0001 E1_H01W0000
|
|
arc: E1_H02E0201 N1_V02S0201
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: E1_H02E0601 V02S0601
|
|
arc: E1_H02E0701 N1_V02S0701
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: S1_V02S0201 N1_V02S0201
|
|
arc: S1_V02S0701 W3_H06E0203
|
|
arc: S3_V06S0103 N1_V02S0201
|
|
arc: S3_V06S0203 N1_V02S0701
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q7
|
|
arc: E1_H02E0501 Q7
|
|
arc: E3_H06E0203 Q7
|
|
arc: M7 W1_H02E0201
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q7
|
|
arc: W3_H06W0203 Q7
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C78:PLC2
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
arc: H00L0000 V02S0001
|
|
arc: H00R0000 V02S0601
|
|
arc: H00R0100 H02E0701
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: S1_V02S0001 H02E0001
|
|
arc: S1_V02S0101 E1_H01W0100
|
|
arc: S1_V02S0201 N1_V02S0201
|
|
arc: S1_V02S0501 W3_H06E0303
|
|
arc: S1_V02S0601 N1_V02S0601
|
|
arc: S1_V02S0701 W3_H06E0203
|
|
arc: V00B0000 V02S0201
|
|
arc: V00B0100 H02W0501
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 H00R0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q7
|
|
arc: E3_H06E0203 Q4
|
|
arc: H01W0000 Q5
|
|
arc: M0 V00B0000
|
|
arc: M1 H02W0001
|
|
arc: M2 H02E0601
|
|
arc: M3 H00R0000
|
|
arc: M4 V00B0100
|
|
arc: M5 H00L0000
|
|
arc: M6 H02W0401
|
|
arc: M7 E1_H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q3
|
|
arc: N1_V01N0101 Q6
|
|
arc: S1_V02S0301 Q1
|
|
arc: V01S0000 Q2
|
|
arc: V01S0100 Q0
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C79:PLC2
|
|
arc: H00L0000 W1_H02E0201
|
|
arc: H00R0000 H02W0401
|
|
arc: H00R0100 V02S0701
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: S1_V02S0001 H01E0001
|
|
arc: S1_V02S0101 N1_V02S0101
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: S1_V02S0501 H02E0501
|
|
arc: S1_V02S0701 W3_H06E0203
|
|
arc: S3_V06S0203 N1_V02S0701
|
|
arc: V00B0000 V02S0201
|
|
arc: W1_H02W0001 V02S0001
|
|
arc: W1_H02W0401 N1_V01S0000
|
|
arc: W1_H02W0501 V02S0501
|
|
arc: CE1 H00L0000
|
|
arc: CE2 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q4
|
|
arc: M3 H00R0100
|
|
arc: M4 V00B0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V01N0101 Q3
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C80:PLC2
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: N1_V02N0401 H06E0203
|
|
arc: N1_V02N0701 H06E0203
|
|
arc: S1_V02S0301 H06E0003
|
|
arc: S1_V02S0501 H01E0101
|
|
arc: V00B0100 V02S0101
|
|
arc: W1_H02W0201 V02S0201
|
|
arc: W1_H02W0401 S1_V02N0401
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0601 Q6
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R23C81:PLC2
|
|
arc: S1_V02S0701 H06E0203
|
|
|
|
.tile R24C65:PLC2
|
|
arc: E3_H06E0003 V06S0003
|
|
arc: E3_H06E0103 V06S0103
|
|
arc: E3_H06E0203 V06S0203
|
|
arc: E3_H06E0303 N1_V01S0100
|
|
arc: H00R0000 N1_V02S0401
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: CE0 V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q1
|
|
arc: M1 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C66:PLC2
|
|
arc: E3_H06E0303 H01E0101
|
|
arc: N1_V02N0001 H06W0003
|
|
arc: N1_V02N0701 E1_H02W0701
|
|
|
|
.tile R24C67:PLC2
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
|
|
.tile R24C68:PLC2
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: W1_H02W0701 S1_V02N0701
|
|
|
|
.tile R24C69:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R24C71:PLC2
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: E3_H06E0003 V06S0003
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: S3_V06S0003 E1_H01W0000
|
|
|
|
.tile R24C72:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
arc: S3_V06S0103 E1_H01W0100
|
|
arc: V00B0100 N1_V02S0101
|
|
arc: CE3 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: H01W0000 Q6
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK3 CLK0
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C73:PLC2
|
|
arc: E1_H02E0001 S3_V06N0003
|
|
arc: E1_H02E0201 S3_V06N0103
|
|
arc: E1_H02E0401 N1_V02S0401
|
|
arc: E3_H06E0303 W1_H02E0501
|
|
arc: H00L0100 N1_V02S0301
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: S3_V06S0203 N1_V01S0000
|
|
arc: V00T0000 N1_V02S0601
|
|
arc: CE0 H02W0101
|
|
arc: CE1 H02W0101
|
|
arc: CE2 H02W0101
|
|
arc: CE3 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: H01W0100 Q1
|
|
arc: M1 H00L0100
|
|
arc: M2 H02W0601
|
|
arc: M4 H02W0401
|
|
arc: M6 V00T0000
|
|
arc: M7 H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S3_V06S0103 Q2
|
|
arc: S3_V06S0303 Q6
|
|
arc: V01S0000 Q7
|
|
arc: V01S0100 Q4
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C74:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0201 S3_V06N0103
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: H00L0000 N1_V02S0001
|
|
arc: H00R0000 H02E0401
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0201 N1_V02S0201
|
|
arc: W1_H02W0401 N1_V02S0401
|
|
arc: W1_H02W0601 N1_V02S0601
|
|
arc: CE1 V02N0201
|
|
arc: CE2 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M3 H00R0000
|
|
arc: M5 H00L0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: S3_V06S0003 Q3
|
|
arc: S3_V06S0303 Q5
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C75:PLC2
|
|
arc: E3_H06E0303 N1_V01S0100
|
|
arc: N1_V02N0001 W1_H02E0001
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: V00T0100 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: H00L0000 Q2
|
|
arc: LSR1 V00T0100
|
|
arc: M2 V00B0000
|
|
arc: M4 H02E0401
|
|
arc: M5 H00L0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: N1_V01N0001 Q2
|
|
arc: N1_V02N0401 Q4
|
|
arc: V00B0000 Q4
|
|
arc: V01S0000 Q5
|
|
arc: W3_H06W0303 Q5
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C76:PLC2
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
|
|
.tile R24C77:PLC2
|
|
arc: E1_H02E0001 V06S0003
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E1_H02E0201 S3_V06N0103
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: E1_H02E0401 W3_H06E0203
|
|
arc: E1_H02E0501 V06S0303
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: E1_H02E0701 V02S0701
|
|
arc: E3_H06E0103 S3_V06N0103
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
|
|
.tile R24C78:PLC2
|
|
arc: E1_H02E0101 N1_V02S0101
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: E1_H02E0501 N1_V01S0100
|
|
arc: E1_H02E0701 V02S0701
|
|
arc: H00L0000 V02S0001
|
|
arc: H00R0000 V02S0601
|
|
arc: H00R0100 N1_V02S0701
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N1_V02N0601 H06E0303
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: V00B0000 V02S0201
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: V00T0100 N1_V02S0501
|
|
arc: A0 S1_V02N0701
|
|
arc: A2 V02S0501
|
|
arc: A3 V00B0000
|
|
arc: A4 V02S0101
|
|
arc: A5 H02E0701
|
|
arc: A6 H02W0701
|
|
arc: A7 H02E0501
|
|
arc: B2 H00L0000
|
|
arc: B3 E1_H01W0100
|
|
arc: B4 H00R0000
|
|
arc: B5 N1_V01S0000
|
|
arc: B6 V00T0000
|
|
arc: B7 V01S0000
|
|
arc: CE0 V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q1
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: M0 V00T0100
|
|
arc: M1 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0001 Q2
|
|
arc: S1_V02S0101 Q3
|
|
arc: S1_V02S0401 Q6
|
|
arc: S1_V02S0701 Q7
|
|
arc: S3_V06S0203 Q4
|
|
arc: S3_V06S0303 Q5
|
|
arc: V01S0000 Q0
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C79:PLC2
|
|
arc: E1_H02E0501 H01E0101
|
|
arc: H00L0000 V02S0001
|
|
arc: H00L0100 N1_V02S0101
|
|
arc: H00R0000 W1_H02E0401
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0201 W1_H02E0201
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: V00B0000 W1_H02E0601
|
|
arc: V00T0000 W1_H02E0001
|
|
arc: W1_H02W0701 V02S0701
|
|
arc: A0 H02W0501
|
|
arc: A1 H00L0100
|
|
arc: A2 H02E0501
|
|
arc: A3 H02E0701
|
|
arc: A4 V02N0301
|
|
arc: A5 V00B0000
|
|
arc: A6 H00R0000
|
|
arc: A7 E1_H02W0701
|
|
arc: B0 V00T0000
|
|
arc: B1 V02S0301
|
|
arc: B2 V02S0101
|
|
arc: B3 H00L0000
|
|
arc: B4 W1_H02E0301
|
|
arc: B5 H02E0101
|
|
arc: B6 V02S0501
|
|
arc: B7 W1_H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0001 Q2
|
|
arc: S1_V02S0101 Q1
|
|
arc: S1_V02S0201 Q0
|
|
arc: S1_V02S0701 Q7
|
|
arc: S3_V06S0003 Q3
|
|
arc: S3_V06S0203 Q4
|
|
arc: S3_V06S0303 Q5
|
|
arc: V01S0100 Q6
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C80:PLC2
|
|
arc: H00R0000 V02S0601
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 H06E0103
|
|
arc: N1_V02N0201 H06E0103
|
|
arc: V00T0000 V02S0601
|
|
arc: W1_H02W0501 V02S0501
|
|
arc: A0 H02E0501
|
|
arc: A1 H00R0000
|
|
arc: A2 V00T0000
|
|
arc: B0 V02S0301
|
|
arc: B1 W1_H02E0301
|
|
arc: B2 W1_H02E0301
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: S1_V02S0001 Q0
|
|
arc: S1_V02S0201 Q2
|
|
arc: S1_V02S0301 Q1
|
|
word: SLICEC.K1.INIT 0000000000001110
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R24C81:PLC2
|
|
arc: W1_H02W0701 V02S0701
|
|
|
|
.tile R25C65:PLC2
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
|
|
.tile R25C66:PLC2
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
|
|
.tile R25C67:PLC2
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
|
|
.tile R25C68:PLC2
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
|
|
.tile R25C69:PLC2
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
|
|
.tile R25C72:PLC2
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: S3_V06S0103 N1_V02S0101
|
|
|
|
.tile R25C73:PLC2
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: S3_V06S0003 N1_V02S0301
|
|
arc: S3_V06S0103 N1_V01S0100
|
|
arc: S3_V06S0203 N1_V01S0000
|
|
arc: S3_V06S0303 N1_V02S0501
|
|
|
|
.tile R25C74:PLC2
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: S1_V02S0201 N3_V06S0103
|
|
arc: S1_V02S0701 N3_V06S0203
|
|
arc: S3_V06S0103 N1_V02S0201
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: S3_V06S0303 N1_V02S0501
|
|
arc: V00T0000 N1_V02S0601
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR0 V00T0000
|
|
arc: M1 H02W0001
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: S1_V02S0101 Q1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C75:PLC2
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: S3_V06S0303 N1_V02S0501
|
|
arc: W1_H02W0001 N1_V01S0000
|
|
|
|
.tile R25C77:PLC2
|
|
arc: E1_H02E0201 N1_V02S0201
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N1_V02N0601 V01N0001
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile R25C78:PLC2
|
|
arc: E1_H02E0301 N1_V02S0301
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile R25C79:PLC2
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: S1_V02S0301 N1_V01S0100
|
|
|
|
.tile R25C80:PLC2
|
|
arc: N1_V02N0401 N3_V06S0203
|
|
|
|
.tile R25C83:PLC2
|
|
arc: S1_V02S0601 N3_V06S0303
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
|
|
.tile R25C86:PLC2
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
|
|
.tile R26C48:PLC2
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
|
|
.tile R26C63:PLC2
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
|
|
.tile R26C65:PLC2
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
|
|
.tile R26C66:PLC2
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
|
|
.tile R26C67:PLC2
|
|
arc: N1_V02N0701 E3_H06W0203
|
|
arc: S3_V06S0203 E3_H06W0203
|
|
|
|
.tile R26C68:PLC2
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: S3_V06S0003 E3_H06W0003
|
|
|
|
.tile R26C71:PLC2
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: S1_V02S0501 E1_H02W0501
|
|
|
|
.tile R26C73:PLC2
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: W1_H02W0501 V06S0303
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q7
|
|
arc: E1_H01E0101 Q7
|
|
arc: E3_H06E0203 Q7
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0701 Q7
|
|
arc: S3_V06S0203 Q7
|
|
arc: W3_H06W0203 Q7
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C74:PLC2
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: E1_H02E0701 V02S0701
|
|
arc: E3_H06E0203 H01E0001
|
|
arc: E3_H06E0303 H01E0101
|
|
arc: H00R0000 V02N0601
|
|
arc: H00R0100 H02W0701
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0103 H01E0101
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: CE1 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0003 Q3
|
|
arc: M3 H00R0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: N1_V02N0301 Q3
|
|
arc: W3_H06W0003 Q3
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C75:PLC2
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: W1_H02W0701 S3_V06N0203
|
|
arc: A0 H02E0701
|
|
arc: C0 H02E0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0001
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: S1_V02S0201 Q0
|
|
word: SLICEA.K0.INIT 1010111110100000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C76:PLC2
|
|
arc: N1_V02N0401 H06E0203
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N3_V06N0203 H06E0203
|
|
|
|
.tile R26C77:PLC2
|
|
arc: N1_V01N0001 S3_V06N0003
|
|
arc: N1_V02N0001 H06E0003
|
|
arc: N1_V02N0301 H06E0003
|
|
arc: N1_V02N0401 H06E0203
|
|
arc: N1_V02N0601 H06E0303
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
|
|
.tile R26C78:PLC2
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: S1_V02S0001 N1_V02S0001
|
|
arc: S1_V02S0201 N1_V02S0701
|
|
arc: S1_V02S0401 N1_V02S0101
|
|
arc: S1_V02S0501 N1_V02S0401
|
|
arc: S1_V02S0701 S3_V06N0203
|
|
|
|
.tile R26C79:PLC2
|
|
arc: S1_V02S0001 N1_V02S0001
|
|
arc: S1_V02S0301 N1_V02S0201
|
|
arc: S1_V02S0401 N1_V02S0101
|
|
arc: S1_V02S0701 N1_V02S0701
|
|
arc: S3_V06S0203 W3_H06E0203
|
|
|
|
.tile R26C80:PLC2
|
|
arc: N1_V02N0001 W3_H06E0003
|
|
arc: S1_V02S0001 N1_V02S0001
|
|
arc: S1_V02S0201 N1_V02S0201
|
|
arc: S1_V02S0601 N1_V02S0301
|
|
|
|
.tile R26C81:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R26C84:PLC2
|
|
arc: S3_V06S0003 H06E0003
|
|
|
|
.tile R26C87:PLC2
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
|
|
.tile R27C71:PLC2
|
|
arc: V01S0000 S3_V06N0103
|
|
arc: V01S0100 S3_V06N0303
|
|
|
|
.tile R27C72:PLC2
|
|
arc: S1_V02S0701 S3_V06N0203
|
|
|
|
.tile R27C73:PLC2
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
|
|
.tile R27C74:PLC2
|
|
arc: E1_H02E0201 N1_V02S0201
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S1_V02S0201 N1_V02S0201
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0103 E1_H01W0100
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
arc: V00B0000 N1_V02S0201
|
|
arc: V00B0100 N1_V02S0101
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR0 V00B0000
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR0
|
|
arc: S1_V02S0601 Q6
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R27C75:PLC2
|
|
arc: H00R0100 H02E0501
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: V00T0000 H02E0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: H01W0100 Q3
|
|
arc: LSR0 V00T0000
|
|
arc: M3 H00R0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R27C79:PLC2
|
|
arc: S1_V02S0001 V01N0001
|
|
arc: S1_V02S0301 N1_V02S0301
|
|
|
|
.tile R27C82:PLC2
|
|
arc: S1_V02S0301 V01N0101
|
|
|
|
.tile R27C83:PLC2
|
|
arc: S1_V02S0601 N1_V02S0601
|
|
|
|
.tile R28C39:PLC2
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
|
|
.tile R28C68:PLC2
|
|
arc: N3_V06N0003 S1_V02N0001
|
|
|
|
.tile R28C69:PLC2
|
|
arc: E1_H02E0101 S3_V06N0103
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile R28C71:PLC2
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: E1_H02E0301 V01N0101
|
|
arc: H00R0100 N1_V02S0501
|
|
arc: V00T0000 V02N0601
|
|
arc: A2 V02N0501
|
|
arc: A3 V02N0701
|
|
arc: A4 V02N0301
|
|
arc: A5 V02N0101
|
|
arc: A6 E1_H02W0701
|
|
arc: A7 S1_V02N0301
|
|
arc: B0 W1_H02E0101
|
|
arc: B2 S1_V02N0101
|
|
arc: B3 H00R0100
|
|
arc: B4 S1_V02N0501
|
|
arc: B5 H02W0101
|
|
arc: B6 V00T0000
|
|
arc: B7 N1_V01S0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0003 Q3
|
|
arc: E3_H06E0103 Q2
|
|
arc: E3_H06E0203 Q7
|
|
arc: E3_H06E0303 Q5
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: V01S0000 Q6
|
|
arc: V01S0100 Q4
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R28C72:PLC2
|
|
arc: H00L0100 H02W0301
|
|
arc: V00B0000 V02N0201
|
|
arc: V00T0000 V02N0601
|
|
arc: W1_H02W0101 V06S0103
|
|
arc: A0 V02S0701
|
|
arc: A1 H00L0100
|
|
arc: A2 V00B0000
|
|
arc: A3 V02N0701
|
|
arc: A4 S1_V02N0101
|
|
arc: A5 H02W0501
|
|
arc: A6 V02N0101
|
|
arc: A7 S1_V02N0301
|
|
arc: B0 V01N0001
|
|
arc: B1 H02E0301
|
|
arc: B2 V02N0301
|
|
arc: B3 H02E0101
|
|
arc: B4 V02N0501
|
|
arc: B5 S1_V02N0701
|
|
arc: B6 H02W0101
|
|
arc: B7 V00T0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q3
|
|
arc: E1_H02E0401 Q4
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0103 Q1
|
|
arc: E3_H06E0203 Q7
|
|
arc: E3_H06E0303 Q5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: V01S0000 Q2
|
|
arc: V01S0100 Q6
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R28C73:PLC2
|
|
arc: E3_H06E0003 H01E0001
|
|
arc: H00L0000 V02N0001
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: V00B0000 V02N0001
|
|
arc: W1_H02W0101 V06S0103
|
|
arc: W1_H02W0301 V06S0003
|
|
arc: W1_H02W0501 V06S0303
|
|
arc: W1_H02W0701 V06S0203
|
|
arc: A0 S1_V02N0701
|
|
arc: A1 H00L0000
|
|
arc: A2 V00B0000
|
|
arc: B0 V02N0301
|
|
arc: B1 H02W0101
|
|
arc: B2 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q2
|
|
arc: E3_H06E0103 Q1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: V01S0000 Q0
|
|
word: SLICEC.K1.INIT 0000000000001110
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R28C74:PLC2
|
|
arc: E1_H02E0101 V02N0101
|
|
arc: E1_H02E0701 V06S0203
|
|
arc: E3_H06E0203 W1_H02E0401
|
|
arc: E3_H06E0303 H01E0101
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: V00B0000 V02S0201
|
|
arc: V00T0000 V02S0601
|
|
arc: W1_H02W0101 N1_V01S0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H02E0301 Q3
|
|
arc: H00R0000 Q6
|
|
arc: H00R0100 Q5
|
|
arc: LSR0 V00B0000
|
|
arc: LSR1 V00B0000
|
|
arc: M3 H00R0100
|
|
arc: M5 H00R0000
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR0
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R28C75:PLC2
|
|
arc: V00B0100 H02E0701
|
|
arc: V00T0100 H02E0301
|
|
arc: A0 H00R0000
|
|
arc: B0 H02E0101
|
|
arc: C0 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 N1_V02S0201
|
|
arc: F0 F0_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H00R0000 Q6
|
|
arc: LSR0 V00B0100
|
|
arc: LSR1 V00B0100
|
|
arc: M4 V00T0100
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V02N0001 Q0
|
|
arc: V00B0000 Q4
|
|
word: SLICEA.K0.INIT 0110100110010110
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET SET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R28C77:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: N3_V06N0003 S1_V02N0301
|
|
arc: N3_V06N0303 S1_V02N0601
|
|
|
|
.tile R28C78:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: H00L0000 N1_V02S0201
|
|
arc: S1_V02S0101 E1_H01W0100
|
|
arc: V00B0000 N1_V02S0001
|
|
arc: V00T0000 N1_V02S0401
|
|
arc: V00T0100 N1_V02S0501
|
|
arc: A0 N1_V02S0701
|
|
arc: A2 V00B0000
|
|
arc: A3 V00T0000
|
|
arc: A4 V02N0101
|
|
arc: A5 H02E0501
|
|
arc: A6 V00T0100
|
|
arc: A7 H00L0000
|
|
arc: B2 H02E0101
|
|
arc: B3 H02E0301
|
|
arc: B4 S1_V02N0701
|
|
arc: B5 S1_V02N0501
|
|
arc: B6 V02N0501
|
|
arc: B7 H01E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0001 Q2
|
|
arc: S1_V02S0301 Q3
|
|
arc: S1_V02S0501 Q5
|
|
arc: S1_V02S0601 Q6
|
|
arc: S1_V02S0701 Q7
|
|
arc: V01S0100 Q4
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R28C79:PLC2
|
|
arc: E1_H01E0001 W3_H06E0003
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: H00L0100 N1_V02S0301
|
|
arc: H00R0000 N1_V02S0401
|
|
arc: V00B0000 N1_V02S0001
|
|
arc: V00T0100 N1_V02S0701
|
|
arc: A0 H00L0100
|
|
arc: A1 H00R0000
|
|
arc: A2 V00B0000
|
|
arc: A3 E1_H01E0001
|
|
arc: A4 H02W0701
|
|
arc: A5 H02E0501
|
|
arc: A6 V02S0301
|
|
arc: A7 V00T0100
|
|
arc: B0 H02E0301
|
|
arc: B1 H02E0101
|
|
arc: B2 V02N0301
|
|
arc: B3 S1_V02N0301
|
|
arc: B4 S1_V02N0701
|
|
arc: B5 S1_V02N0501
|
|
arc: B6 V02N0501
|
|
arc: B7 H01E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 Q6
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q4
|
|
arc: S1_V02S0001 Q2
|
|
arc: S1_V02S0101 Q3
|
|
arc: S1_V02S0301 Q1
|
|
arc: S1_V02S0501 Q7
|
|
arc: S1_V02S0701 Q5
|
|
arc: V01S0100 Q0
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R28C80:PLC2
|
|
arc: H00L0000 N1_V02S0001
|
|
arc: H00R0000 N1_V02S0601
|
|
arc: H01W0100 W3_H06E0303
|
|
arc: V00B0000 N1_V02S0201
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
arc: A0 H00L0000
|
|
arc: A1 H00R0000
|
|
arc: A2 V00B0000
|
|
arc: A3 V00B0000
|
|
arc: B0 V02N0301
|
|
arc: B1 H02E0101
|
|
arc: B2 H01W0100
|
|
arc: B3 H01W0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: S1_V02S0101 Q1
|
|
arc: S1_V02S0301 Q3
|
|
arc: V01S0000 Q2
|
|
arc: V01S0100 Q0
|
|
word: SLICEC.K1.INIT 0000000000001110
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R28C81:PLC2
|
|
arc: E1_H02E0001 S1_V02N0001
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: E3_H06E0303 V01N0101
|
|
|
|
.tile R28C82:PLC2
|
|
arc: E3_H06E0003 V01N0001
|
|
arc: E3_H06E0303 V01N0101
|
|
arc: V00B0000 H02E0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M2 H02E0601
|
|
arc: M5 H02E0001
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q2
|
|
arc: S1_V02S0401 Q6
|
|
arc: V01S0000 Q5
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R28C84:PLC2
|
|
arc: S1_V02S0501 H06E0303
|
|
|
|
.tile R28C85:PLC2
|
|
arc: S1_V02S0301 H06E0003
|
|
arc: S1_V02S0501 H06E0303
|
|
|
|
.tile R29C65:PLC2
|
|
arc: S1_V02S0101 H06W0103
|
|
|
|
.tile R29C66:PLC2
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
|
|
.tile R29C67:PLC2
|
|
arc: N3_V06N0103 E3_H06W0103
|
|
arc: S3_V06S0103 E3_H06W0103
|
|
|
|
.tile R29C68:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R29C71:PLC2
|
|
arc: E1_H02E0101 S3_V06N0103
|
|
arc: E1_H02E0301 S3_V06N0003
|
|
arc: E3_H06E0103 N1_V01S0100
|
|
arc: E3_H06E0203 N1_V01S0000
|
|
arc: N1_V01N0101 S3_V06N0203
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
|
|
.tile R29C72:PLC2
|
|
arc: E1_H02E0601 V02N0601
|
|
arc: E3_H06E0203 N1_V01S0000
|
|
arc: E3_H06E0303 N1_V01S0100
|
|
arc: H00R0000 V02N0601
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V02N0101 H02E0101
|
|
arc: N1_V02N0201 H02W0201
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
arc: N1_V02N0701 H02W0701
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: V00B0100 E1_H02W0701
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H02E0501 Q7
|
|
arc: LSR1 V00B0100
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR1
|
|
arc: S3_V06S0203 Q7
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R29C73:PLC2
|
|
arc: E3_H06E0203 N1_V01S0000
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0301 W1_H02E0301
|
|
arc: W1_H02W0201 N3_V06S0103
|
|
arc: W1_H02W0701 N3_V06S0203
|
|
arc: CE1 V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0103 Q2
|
|
arc: M2 H02E0601
|
|
arc: MUXCLK1 CLK0
|
|
arc: N3_V06N0103 Q2
|
|
arc: S3_V06S0103 Q2
|
|
arc: W3_H06W0103 Q2
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R29C74:PLC2
|
|
arc: E1_H02E0301 N3_V06S0003
|
|
arc: H00L0000 S1_V02N0201
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: S1_V02S0101 N3_V06S0103
|
|
arc: S1_V02S0701 N3_V06S0203
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
arc: V00T0100 S1_V02N0701
|
|
arc: W1_H02W0701 S1_V02N0701
|
|
arc: CLK0 G_HPBX0000
|
|
arc: H01W0100 Q1
|
|
arc: LSR0 V00T0100
|
|
arc: M1 H00L0000
|
|
arc: M3 H01W0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: N1_V02N0101 Q3
|
|
arc: N1_V02N0301 Q1
|
|
arc: W3_H06W0003 Q3
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R29C75:PLC2
|
|
arc: S1_V02S0001 N3_V06S0003
|
|
arc: S1_V02S0701 N3_V06S0203
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
|
|
.tile R29C76:PLC2
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: S3_V06S0103 H06E0103
|
|
|
|
.tile R29C77:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0101 W3_H06E0103
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E1_H02E0701 V02N0701
|
|
arc: S1_V02S0401 N3_V06S0203
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile R29C78:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0101 V01N0101
|
|
arc: E1_H02E0201 V01N0001
|
|
arc: E1_H02E0301 E1_H01W0100
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: E1_H02E0701 V06N0203
|
|
arc: N1_V02N0101 H02E0101
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: S1_V02S0301 N1_V01S0100
|
|
arc: S1_V02S0701 H02W0701
|
|
|
|
.tile R29C79:PLC2
|
|
arc: E1_H01E0101 W3_H06E0203
|
|
arc: E1_H02E0101 V01N0101
|
|
arc: E1_H02E0601 V01N0001
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
arc: H00L0000 H02E0201
|
|
arc: H00R0000 V02N0601
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: N3_V06N0103 W3_H06E0103
|
|
arc: S1_V02S0101 N1_V02S0001
|
|
arc: S1_V02S0701 N1_V01S0100
|
|
arc: S3_V06S0103 W3_H06E0103
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
arc: V00T0000 V02N0401
|
|
arc: V00T0100 S1_V02N0701
|
|
arc: W1_H02W0701 N3_V06S0203
|
|
arc: A0 H02E0701
|
|
arc: A2 E1_H01E0001
|
|
arc: A3 H00L0100
|
|
arc: A4 V00T0000
|
|
arc: A5 W1_H02E0501
|
|
arc: A6 H00L0000
|
|
arc: A7 W1_H02E0701
|
|
arc: B2 H02E0101
|
|
arc: B3 V02N0101
|
|
arc: B4 H02E0301
|
|
arc: B5 V00B0100
|
|
arc: B6 V00B0000
|
|
arc: B7 V01S0000
|
|
arc: CE1 H00R0000
|
|
arc: CE2 V02N0601
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q2
|
|
arc: E3_H06E0003 Q3
|
|
arc: E3_H06E0103 Q2
|
|
arc: E3_H06E0203 Q4
|
|
arc: E3_H06E0303 Q5
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: H01W0100 Q4
|
|
arc: LSR0 V00T0100
|
|
arc: LSR1 V00T0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: V00B0000 Q6
|
|
arc: V00B0100 Q5
|
|
arc: V01S0000 Q7
|
|
arc: V01S0100 Q6
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R29C80:PLC2
|
|
arc: E1_H02E0101 E1_H01W0100
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0301 V01N0101
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E1_H02E0601 V01N0001
|
|
arc: H00L0000 V02N0201
|
|
arc: H00R0000 H02E0601
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: S1_V02S0101 N1_V01S0100
|
|
arc: S1_V02S0401 N1_V01S0000
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 H02E0701
|
|
arc: V00T0000 V02N0401
|
|
arc: A0 E1_H01E0001
|
|
arc: A1 H00L0100
|
|
arc: A2 V00B0000
|
|
arc: A3 S1_V02N0701
|
|
arc: A4 N1_V01N0101
|
|
arc: A5 Q5
|
|
arc: A6 H02W0501
|
|
arc: A7 Q7
|
|
arc: B0 H02E0101
|
|
arc: B1 V02N0301
|
|
arc: B2 H01W0100
|
|
arc: B3 Q3
|
|
arc: B4 H00R0000
|
|
arc: B5 V02N0701
|
|
arc: B6 V00T0000
|
|
arc: B7 V02N0501
|
|
arc: CE0 V02N0201
|
|
arc: CE1 V02N0201
|
|
arc: CE2 V02N0601
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q0
|
|
arc: E1_H01E0101 Q6
|
|
arc: E1_H02E0701 Q7
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0103 Q1
|
|
arc: E3_H06E0203 Q4
|
|
arc: E3_H06E0303 Q5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H01W0100 Q2
|
|
arc: LSR0 V00B0100
|
|
arc: LSR1 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0101 Q4
|
|
arc: S1_V02S0601 Q6
|
|
arc: V01S0000 Q3
|
|
arc: V01S0100 Q2
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R29C81:PLC2
|
|
arc: H00L0000 H02E0201
|
|
arc: H00R0000 H02E0601
|
|
arc: S1_V02S0701 H02E0701
|
|
arc: V00B0000 V02N0201
|
|
arc: V00B0100 W1_H02E0701
|
|
arc: V00T0000 V02N0401
|
|
arc: W1_H02W0501 H01E0101
|
|
arc: A0 E1_H01E0001
|
|
arc: A1 H00L0100
|
|
arc: A2 V02N0501
|
|
arc: A3 H02E0501
|
|
arc: A4 V00T0000
|
|
arc: A5 Q5
|
|
arc: A6 H02W0501
|
|
arc: A7 Q7
|
|
arc: B0 H02E0301
|
|
arc: B1 V02N0101
|
|
arc: B2 H00R0000
|
|
arc: B3 Q3
|
|
arc: B4 H02E0101
|
|
arc: B5 V02N0701
|
|
arc: B6 S1_V02N0701
|
|
arc: B7 V00B0000
|
|
arc: CE0 H00L0000
|
|
arc: CE1 H00L0000
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q0
|
|
arc: E1_H01E0101 Q6
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0103 Q1
|
|
arc: E3_H06E0203 Q4
|
|
arc: E3_H06E0303 Q5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H01W0100 Q4
|
|
arc: LSR0 V00B0100
|
|
arc: LSR1 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0101 Q7
|
|
arc: S1_V02S0001 Q2
|
|
arc: S1_V02S0401 Q6
|
|
arc: V01S0000 Q3
|
|
arc: V01S0100 Q2
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R29C82:PLC2
|
|
arc: E1_H02E0001 V01N0001
|
|
arc: H00L0000 W1_H02E0201
|
|
arc: H00R0000 V02N0601
|
|
arc: S1_V02S0101 H06E0103
|
|
arc: S1_V02S0301 H06E0003
|
|
arc: S1_V02S0501 H06E0303
|
|
arc: S1_V02S0701 H06E0203
|
|
arc: V00T0000 V02S0401
|
|
arc: V00T0100 S1_V02N0701
|
|
arc: W1_H02W0501 H01E0101
|
|
arc: A0 E1_H01E0001
|
|
arc: A1 V02N0501
|
|
arc: A2 V01N0101
|
|
arc: A3 V00T0000
|
|
arc: A4 H02W0701
|
|
arc: A5 Q5
|
|
arc: A6 H00R0000
|
|
arc: A7 V02N0301
|
|
arc: B0 N1_V02S0301
|
|
arc: B1 Q1
|
|
arc: B2 H01W0100
|
|
arc: B3 Q3
|
|
arc: B4 N1_V01S0000
|
|
arc: B5 V02N0701
|
|
arc: B6 V00B0000
|
|
arc: B7 V00B0100
|
|
arc: CE0 H00L0000
|
|
arc: CE1 H00L0000
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q0
|
|
arc: E1_H01E0101 Q4
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0103 Q1
|
|
arc: E3_H06E0203 Q4
|
|
arc: E3_H06E0303 Q5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 Q2
|
|
arc: LSR0 V00T0100
|
|
arc: LSR1 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q6
|
|
arc: N1_V01N0101 Q7
|
|
arc: V00B0000 Q6
|
|
arc: V00B0100 Q7
|
|
arc: V01S0000 Q3
|
|
arc: V01S0100 Q2
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R29C83:PLC2
|
|
arc: E1_H02E0601 V01N0001
|
|
arc: S1_V02S0101 H06E0103
|
|
arc: S1_V02S0301 H06E0003
|
|
arc: S1_V02S0501 H06E0303
|
|
arc: S1_V02S0601 N1_V02S0601
|
|
arc: S1_V02S0701 H06E0203
|
|
arc: W1_H02W0701 H01E0101
|
|
arc: A0 H00L0000
|
|
arc: A1 V02N0701
|
|
arc: B0 V02N0101
|
|
arc: B1 Q1
|
|
arc: CE0 V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0103 Q1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: LSR1 E1_H02W0501
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: V01S0000 Q0
|
|
word: SLICEB.K1.INIT 0000000000001110
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R29C84:PLC2
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: E1_H02E0601 V01N0001
|
|
arc: S1_V02S0101 H06E0103
|
|
arc: S1_V02S0301 H06E0003
|
|
arc: S1_V02S0501 H06E0303
|
|
arc: S1_V02S0701 H06E0203
|
|
arc: A2 V02N0701
|
|
arc: A7 V02N0101
|
|
arc: B2 V02N0301
|
|
arc: B7 V02N0501
|
|
arc: C2 V02N0401
|
|
arc: C4 V01N0101
|
|
arc: C7 V02N0201
|
|
arc: D2 V02N0001
|
|
arc: D4 V02N0601
|
|
arc: D7 V02N0601
|
|
arc: E1_H01E0001 F4
|
|
arc: E1_H02E0101 F1
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: M0 H02E0601
|
|
arc: M1 W1_H02E0001
|
|
arc: M2 H02E0601
|
|
arc: V01S0000 F7
|
|
word: SLICEC.K0.INIT 0000000000001111
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000001
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1000000000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R29C85:PLC2
|
|
arc: E1_H02E0001 H01E0001
|
|
arc: H00R0000 V02N0401
|
|
arc: S1_V02S0101 H06E0103
|
|
arc: S1_V02S0301 H06E0003
|
|
arc: S1_V02S0501 H06E0303
|
|
arc: S1_V02S0701 H06E0203
|
|
arc: V00B0000 H02E0601
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0000 H02E0201
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: A0 V02N0701
|
|
arc: A5 V02N0101
|
|
arc: A6 H00R0000
|
|
arc: B0 V00T0000
|
|
arc: B5 V02N0701
|
|
arc: B6 V02N0501
|
|
arc: C0 V02N0601
|
|
arc: C5 V01N0101
|
|
arc: C6 H02E0601
|
|
arc: D0 S1_V02N0001
|
|
arc: D5 V02N0601
|
|
arc: D6 V01N0001
|
|
arc: E1_H02E0101 F1
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: M0 V00B0100
|
|
arc: M1 V01S0100
|
|
arc: M2 V00B0100
|
|
arc: M4 V00B0000
|
|
arc: S1_V02S0401 F4
|
|
arc: V01S0100 F6
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 1000000000000000
|
|
word: SLICED.K0.INIT 0000000000000001
|
|
word: SLICEA.K0.INIT 0000000000000001
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
|
|
.tile R29C86:PLC2
|
|
arc: H00L0100 H02E0101
|
|
arc: S1_V02S0201 H06E0103
|
|
arc: V00T0100 W1_H02E0101
|
|
arc: A1 V01N0101
|
|
arc: B1 V02N0101
|
|
arc: C1 S1_V02N0401
|
|
arc: D1 H02E0001
|
|
arc: E1_H01E0101 F1
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: M0 V00T0100
|
|
arc: M1 H00L0100
|
|
arc: M2 V00T0100
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0010000000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R29C87:PLC2
|
|
arc: S1_V02S0101 H01E0101
|
|
|
|
.tile R2C48:PLC2
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
|
|
.tile R2C63:PLC2
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
|
|
.tile R2C66:PLC2
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
|
|
.tile R30C67:PLC2
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
|
|
.tile R30C68:PLC2
|
|
arc: N1_V02N0001 S1_V02N0501
|
|
|
|
.tile R30C71:PLC2
|
|
arc: E1_H02E0301 V06N0003
|
|
arc: E1_H02E0701 V06N0203
|
|
arc: N1_V02N0101 E1_H02W0101
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: N1_V02N0501 E1_H02W0501
|
|
|
|
.tile R30C72:PLC2
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N1_V02N0701 H02E0701
|
|
|
|
.tile R30C73:PLC2
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: W1_H02W0101 N3_V06S0103
|
|
arc: W1_H02W0501 N3_V06S0303
|
|
|
|
.tile R30C74:PLC2
|
|
arc: N3_V06N0103 S1_V02N0101
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: S1_V02S0501 V01N0101
|
|
arc: S1_V02S0601 N3_V06S0303
|
|
|
|
.tile R30C77:PLC2
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0501 H02W0501
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: N3_V06N0003 S1_V02N0001
|
|
arc: N3_V06N0103 S1_V02N0101
|
|
|
|
.tile R30C78:PLC2
|
|
arc: E1_H02E0101 N1_V02S0101
|
|
arc: E1_H02E0501 E1_H01W0100
|
|
arc: E1_H02E0701 V06N0203
|
|
arc: H00L0000 N1_V02S0001
|
|
arc: H00L0100 N1_V02S0301
|
|
arc: H00R0000 N1_V02S0601
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
arc: N3_V06N0103 S1_V02N0201
|
|
arc: N3_V06N0203 S1_V02N0401
|
|
arc: V00T0100 N1_V02S0501
|
|
arc: A2 S1_V02N0501
|
|
arc: A3 H00L0100
|
|
arc: A4 V02S0301
|
|
arc: A5 V00T0100
|
|
arc: A6 H00R0000
|
|
arc: A7 S1_V02N0301
|
|
arc: B0 V02N0101
|
|
arc: B2 H00L0000
|
|
arc: B3 V02N0301
|
|
arc: B4 V02N0701
|
|
arc: B5 V02N0501
|
|
arc: B6 S1_V02N0701
|
|
arc: B7 N1_V02S0701
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q3
|
|
arc: E1_H02E0401 Q4
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 Q7
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q6
|
|
arc: N1_V01N0101 Q2
|
|
arc: W1_H02W0501 Q5
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R30C79:PLC2
|
|
arc: E1_H02E0001 N1_V01S0000
|
|
arc: E1_H02E0501 N1_V01S0100
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
arc: H00L0000 N1_V02S0001
|
|
arc: H00L0100 N1_V02S0301
|
|
arc: H00R0000 V02N0401
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
arc: N3_V06N0003 S1_V02N0301
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: V00T0000 S1_V02N0401
|
|
arc: V00T0100 N1_V02S0701
|
|
arc: A0 V02S0701
|
|
arc: A1 H00L0100
|
|
arc: A2 V00T0000
|
|
arc: A3 H02E0701
|
|
arc: A4 V02S0101
|
|
arc: A5 V00T0100
|
|
arc: A6 H00R0000
|
|
arc: A7 S1_V02N0101
|
|
arc: B0 V02N0101
|
|
arc: B1 V02N0301
|
|
arc: B2 H00L0000
|
|
arc: B3 N1_V02S0101
|
|
arc: B4 S1_V02N0501
|
|
arc: B5 V02N0501
|
|
arc: B6 H02E0101
|
|
arc: B7 N1_V02S0501
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q2
|
|
arc: E1_H01E0101 Q1
|
|
arc: E1_H02E0401 Q6
|
|
arc: E1_H02E0701 Q5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0100 Q7
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q4
|
|
arc: N1_V01N0101 Q0
|
|
arc: V01S0100 Q3
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R30C80:PLC2
|
|
arc: E1_H02E0201 N1_V01S0000
|
|
arc: E1_H02E0501 N1_V01S0100
|
|
arc: E1_H02E0601 V02S0601
|
|
arc: H00L0100 N1_V02S0101
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: N1_V02N0701 H02E0701
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00B0100 N1_V02S0301
|
|
arc: V00T0000 V02S0401
|
|
arc: A0 S1_V02N0501
|
|
arc: A1 H00L0100
|
|
arc: A2 V00T0000
|
|
arc: A3 V00B0000
|
|
arc: A4 V00B0000
|
|
arc: A5 V00B0000
|
|
arc: B0 V02S0101
|
|
arc: B1 V02N0101
|
|
arc: B2 V02N0301
|
|
arc: B3 N1_V02S0301
|
|
arc: B4 V00B0100
|
|
arc: B5 V00B0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 F4
|
|
arc: E1_H01E0101 Q1
|
|
arc: E1_H02E0401 F4
|
|
arc: E3_H06E0203 Q4
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V01N0001 Q2
|
|
arc: N1_V01N0101 Q0
|
|
arc: V01S0100 Q3
|
|
word: SLICED.K1.INIT 0000000000001110
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R30C81:PLC2
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0201 H01E0001
|
|
arc: E1_H02E0301 E1_H01W0100
|
|
arc: E1_H02E0401 V02S0401
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: E1_H02E0701 V02S0701
|
|
arc: H00R0000 H02E0401
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0501 N1_V01S0100
|
|
arc: N1_V02N0601 H01E0001
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M0 H01E0001
|
|
arc: M4 H02E0401
|
|
arc: M6 H02E0401
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0201 Q0
|
|
arc: N1_V02N0401 Q6
|
|
arc: N1_V02N0701 Q7
|
|
arc: V01S0100 Q4
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R30C82:PLC2
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: E1_H02E0201 N1_V01S0000
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
arc: E1_H02E0501 W1_H02E0501
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: H00L0000 H02W0201
|
|
arc: H00R0000 W1_H02E0401
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: V00B0000 W1_H02E0401
|
|
arc: V00T0000 V02N0601
|
|
arc: V00T0100 V02N0501
|
|
arc: A2 S1_V02N0501
|
|
arc: A3 S1_V02N0701
|
|
arc: A4 V02N0301
|
|
arc: A5 S1_V02N0301
|
|
arc: A6 H02E0501
|
|
arc: A7 V00T0100
|
|
arc: B0 E1_H02W0301
|
|
arc: B2 V02S0101
|
|
arc: B3 V02S0301
|
|
arc: B4 V02S0701
|
|
arc: B5 V02S0501
|
|
arc: B6 V00T0000
|
|
arc: B7 H02E0101
|
|
arc: CE1 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q1
|
|
arc: F2 F2_SLICE
|
|
arc: H01W0100 Q6
|
|
arc: M0 V00B0000
|
|
arc: M1 H00R0000
|
|
arc: M4 W1_H02E0401
|
|
arc: M5 H00R0000
|
|
arc: M6 W1_H02E0401
|
|
arc: M7 H02E0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q2
|
|
arc: N1_V01N0101 Q0
|
|
arc: N1_V02N0501 Q5
|
|
arc: N1_V02N0601 Q4
|
|
arc: N1_V02N0701 Q7
|
|
arc: V01S0100 Q2
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R30C83:PLC2
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: E1_H02E0601 V01N0001
|
|
arc: E1_H02E0701 W1_H02E0601
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: H00L0100 V02N0301
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0701 H06E0203
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: W1_H02W0201 V01N0001
|
|
arc: A0 V01N0101
|
|
arc: A1 H02W0701
|
|
arc: A2 H02E0501
|
|
arc: A3 V00B0000
|
|
arc: A4 V00B0000
|
|
arc: A5 V00B0000
|
|
arc: A6 H02E0701
|
|
arc: A7 W1_H02E0701
|
|
arc: B0 V02S0301
|
|
arc: B1 V02S0101
|
|
arc: B2 H00L0000
|
|
arc: B3 H02E0301
|
|
arc: B4 V02S0701
|
|
arc: B5 V02S0501
|
|
arc: B6 V00B0000
|
|
arc: B7 V00B0000
|
|
arc: CE0 H00L0100
|
|
arc: CE1 H00L0100
|
|
arc: CE2 H00L0100
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q5
|
|
arc: E1_H02E0301 Q1
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q4
|
|
arc: S1_V02S0101 Q3
|
|
arc: S1_V02S0201 Q2
|
|
arc: S1_V02S0301 Q1
|
|
arc: S1_V02S0401 Q4
|
|
arc: S1_V02S0501 Q7
|
|
arc: S1_V02S0601 Q6
|
|
arc: S1_V02S0701 Q5
|
|
arc: V01S0000 Q2
|
|
arc: V01S0100 Q3
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R30C84:PLC2
|
|
arc: E1_H02E0101 W1_H02E0101
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
arc: H00R0000 H02E0601
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: S1_V02S0401 N1_V01S0000
|
|
arc: W1_H02W0301 V01N0101
|
|
arc: W1_H02W0701 S1_V02N0701
|
|
arc: A0 S1_V02N0501
|
|
arc: A1 S1_V02N0701
|
|
arc: A2 S1_V02N0701
|
|
arc: A3 H02E0701
|
|
arc: A4 S1_V02N0101
|
|
arc: A5 S1_V02N0101
|
|
arc: A6 H02E0501
|
|
arc: A7 S1_V02N0301
|
|
arc: B0 V02S0301
|
|
arc: B1 V02S0101
|
|
arc: B2 H02E0101
|
|
arc: B3 S1_V02N0301
|
|
arc: B4 V02S0701
|
|
arc: B5 V02S0501
|
|
arc: B6 S1_V02N0501
|
|
arc: B7 N1_V02S0501
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q3
|
|
arc: E1_H01E0101 Q6
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q7
|
|
arc: N1_V01N0101 Q1
|
|
arc: N1_V02N0001 Q0
|
|
arc: N1_V02N0101 Q3
|
|
arc: N1_V02N0201 Q2
|
|
arc: N1_V02N0501 Q5
|
|
arc: N1_V02N0601 Q4
|
|
arc: N1_V02N0701 Q5
|
|
arc: S1_V02S0001 Q0
|
|
arc: V01S0000 Q6
|
|
arc: V01S0100 Q1
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R30C85:PLC2
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: H00R0000 H02W0601
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0301 W1_H02E0301
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: V00T0100 H02W0301
|
|
arc: A0 H02E0501
|
|
arc: A1 H02E0501
|
|
arc: A2 H02E0501
|
|
arc: A3 H02E0501
|
|
arc: A4 H02E0701
|
|
arc: A5 H02E0501
|
|
arc: A6 N1_V02S0301
|
|
arc: A7 V00T0100
|
|
arc: B0 V02S0301
|
|
arc: B1 V02S0101
|
|
arc: B2 H02E0101
|
|
arc: B3 H02E0301
|
|
arc: B4 V02S0701
|
|
arc: B5 V02S0501
|
|
arc: B6 H02W0301
|
|
arc: B7 N1_V02S0501
|
|
arc: CE0 H00R0000
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00R0000
|
|
arc: CE3 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q1
|
|
arc: E1_H02E0601 Q4
|
|
arc: E1_H02E0701 Q5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q2
|
|
arc: N1_V01N0101 Q0
|
|
arc: N1_V02N0601 Q6
|
|
arc: N1_V02N0701 Q7
|
|
arc: S1_V02S0101 Q1
|
|
arc: S1_V02S0201 Q2
|
|
arc: S1_V02S0301 Q3
|
|
arc: S1_V02S0501 Q5
|
|
arc: V01S0000 Q3
|
|
arc: V01S0100 Q4
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
|
|
.tile R30C86:PLC2
|
|
arc: H00L0000 V02S0201
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: S1_V02S0401 V01N0001
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0601 V01N0001
|
|
arc: A0 H02E0501
|
|
arc: A1 H00L0000
|
|
arc: A4 H02E0701
|
|
arc: B0 S1_V02N0301
|
|
arc: B1 S1_V02N0301
|
|
arc: C4 H02E0601
|
|
arc: CE0 V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D4 H01W0000
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: H01W0100 Q0
|
|
arc: MUXCLK0 CLK0
|
|
arc: N1_V01N0101 F4
|
|
arc: V01S0100 Q1
|
|
word: SLICEC.K0.INIT 0000000000000101
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000001110
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
|
|
.tile R31C65:PLC2
|
|
arc: S1_V02S0401 N1_V02S0101
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile R31C66:PLC2
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: S3_V06S0003 E3_H06W0003
|
|
|
|
.tile R31C67:PLC2
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile R31C68:PLC2
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile R31C69:PLC2
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile R31C71:PLC2
|
|
arc: E1_H02E0001 E3_H06W0003
|
|
arc: E1_H02E0201 S3_V06N0103
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
|
|
.tile R31C72:PLC2
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: CE1 E1_H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0003 Q3
|
|
arc: M3 E1_H02W0201
|
|
arc: MUXCLK1 CLK0
|
|
arc: N3_V06N0003 Q3
|
|
arc: S3_V06S0003 Q3
|
|
arc: W3_H06W0003 Q3
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R31C73:PLC2
|
|
arc: E1_H02E0001 W1_H02E0001
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile R31C74:PLC2
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: S1_V02S0101 N1_V02S0101
|
|
arc: S1_V02S0201 N3_V06S0103
|
|
arc: S1_V02S0501 N3_V06S0303
|
|
arc: S1_V02S0701 N1_V02S0701
|
|
arc: S3_V06S0003 H06W0003
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: A0 V02S0501
|
|
arc: B0 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0001
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: S1_V02S0001 Q0
|
|
word: SLICEA.K0.INIT 1101110110001000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R31C75:PLC2
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: S1_V02S0101 N1_V02S0001
|
|
arc: S1_V02S0501 N3_V06S0303
|
|
arc: S1_V02S0701 N1_V02S0701
|
|
arc: S3_V06S0003 H06E0003
|
|
arc: W1_H02W0101 N3_V06S0103
|
|
|
|
.tile R31C76:PLC2
|
|
arc: S1_V02S0601 N1_V02S0301
|
|
|
|
.tile R31C77:PLC2
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: S3_V06S0203 N1_V02S0401
|
|
arc: W3_H06W0003 E1_H01W0000
|
|
|
|
.tile R31C78:PLC2
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: N3_V06N0003 W3_H06E0003
|
|
arc: S3_V06S0003 W3_H06E0003
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: A0 N1_V02S0701
|
|
arc: C0 E1_H02W0401
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V01S0100
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: MUXCLK0 CLK0
|
|
word: SLICEA.K0.INIT 1111101001010000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R31C79:PLC2
|
|
arc: E1_H02E0701 N1_V01S0100
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0501 S1_V02N0501
|
|
arc: N1_V02N0701 E3_H06W0203
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
|
|
.tile R31C80:PLC2
|
|
arc: E1_H02E0301 W3_H06E0003
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0501 N1_V01S0100
|
|
arc: N1_V02N0701 H02E0701
|
|
arc: S1_V02S0001 W3_H06E0003
|
|
arc: W1_H02W0401 E1_H02W0101
|
|
|
|
.tile R31C81:PLC2
|
|
arc: N1_V02N0701 N1_V01S0100
|
|
|
|
.tile R31C82:PLC2
|
|
arc: E1_H02E0501 N1_V01S0100
|
|
arc: E1_H02E0601 W1_H02E0301
|
|
arc: N1_V02N0301 V01N0101
|
|
arc: N1_V02N0701 H06W0203
|
|
arc: S1_V02S0301 H02W0301
|
|
arc: V00B0100 S1_V02N0101
|
|
arc: W1_H02W0101 S1_V02N0101
|
|
arc: CE1 H02W0101
|
|
arc: CE2 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR1 H02W0301
|
|
arc: M2 H02W0601
|
|
arc: M4 V00B0100
|
|
arc: M5 E1_H02W0001
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: N1_V02N0501 Q5
|
|
arc: N1_V02N0601 Q4
|
|
arc: V01S0100 Q2
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R31C83:PLC2
|
|
arc: E1_H02E0501 V02S0501
|
|
arc: E1_H02E0601 V02S0601
|
|
arc: H00L0100 V02S0301
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: S1_V02S0001 N3_V06S0003
|
|
arc: V00B0000 H02E0601
|
|
arc: V00T0000 N1_V02S0601
|
|
arc: V00T0100 V02S0501
|
|
arc: W1_H02W0101 V01N0101
|
|
arc: W1_H02W0301 N3_V06S0003
|
|
arc: W1_H02W0601 E1_H02W0301
|
|
arc: A2 H02E0501
|
|
arc: A5 V02S0101
|
|
arc: A7 N1_V01S0100
|
|
arc: B2 V02N0101
|
|
arc: B5 V02S0701
|
|
arc: B7 N1_V01S0000
|
|
arc: C2 H00L0100
|
|
arc: C5 V02S0201
|
|
arc: C7 V00T0100
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D2 V00B0100
|
|
arc: D5 V02S0401
|
|
arc: D7 V02S0601
|
|
arc: E1_H01E0101 F2
|
|
arc: E1_H02E0701 F5
|
|
arc: E3_H06E0203 F7
|
|
arc: F2 F2_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR1 V00T0000
|
|
arc: M4 V00B0000
|
|
arc: M7 H02W0201
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0101 Q4
|
|
arc: V00B0100 Q7
|
|
word: SLICED.K1.INIT 0000000000000001
|
|
word: SLICEC.K1.INIT 1000000000000000
|
|
word: SLICEB.K0.INIT 0000000000100000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET SET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R31C84:PLC2
|
|
arc: E1_H02E0601 N1_V01S0000
|
|
arc: H00L0000 V02S0001
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V01N0101 S3_V06N0203
|
|
arc: W1_H02W0001 W3_H06E0003
|
|
arc: W1_H02W0201 V01N0001
|
|
arc: A1 H02E0701
|
|
arc: A4 N1_V01S0100
|
|
arc: B1 V00B0000
|
|
arc: B4 H00L0000
|
|
arc: C1 V02S0401
|
|
arc: C4 H02E0601
|
|
arc: D1 H01E0101
|
|
arc: D4 H00R0100
|
|
arc: E1_H02E0301 F1
|
|
arc: F1 F1_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: V00B0000 F4
|
|
word: SLICEA.K1.INIT 1000000000000000
|
|
word: SLICEC.K0.INIT 1000000000000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R31C85:PLC2
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: H00R0000 V02N0401
|
|
arc: N1_V02N0001 N1_V01S0000
|
|
arc: S1_V02S0301 H02W0301
|
|
arc: S1_V02S0501 E1_H01W0100
|
|
arc: V00T0100 H02W0101
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: A3 V02S0501
|
|
arc: A5 V02S0101
|
|
arc: A7 E1_H01W0000
|
|
arc: B0 V00T0000
|
|
arc: B3 V02S0301
|
|
arc: B5 F3
|
|
arc: B7 V00T0000
|
|
arc: C0 E1_H01W0000
|
|
arc: C3 N1_V01S0100
|
|
arc: C5 H02E0601
|
|
arc: C7 V02N0001
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: D3 V02S0201
|
|
arc: D5 N1_V02S0401
|
|
arc: D7 H02W0001
|
|
arc: E1_H02E0701 F5
|
|
arc: F0 F0_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: LSR1 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: N1_V02N0501 F7
|
|
arc: S1_V02S0201 Q0
|
|
arc: V00T0000 Q0
|
|
arc: V01S0000 Q0
|
|
arc: W3_H06W0203 F7
|
|
word: SLICEB.K1.INIT 1000000000000000
|
|
word: SLICEC.K1.INIT 1000000000000000
|
|
word: SLICEA.K0.INIT 0000001100110011
|
|
word: SLICED.K1.INIT 1111111100000100
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R31C86:PLC2
|
|
arc: E1_H02E0101 N3_V06S0103
|
|
arc: E1_H02E0301 N1_V01S0100
|
|
arc: E1_H02E0601 W1_H02E0301
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0401 H06E0203
|
|
arc: S1_V02S0001 N3_V06S0003
|
|
arc: S1_V02S0101 N3_V06S0103
|
|
arc: V00B0000 V02N0001
|
|
arc: V00T0000 V02S0401
|
|
arc: W1_H02W0001 N3_V06S0003
|
|
arc: W1_H02W0101 N3_V06S0103
|
|
arc: W1_H02W0301 N3_V06S0003
|
|
arc: B0 H01W0100
|
|
arc: C0 V02N0401
|
|
arc: CE0 V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0001
|
|
arc: F0 F0_SLICE
|
|
arc: H00R0000 Q6
|
|
arc: H01W0000 Q0
|
|
arc: H01W0100 Q0
|
|
arc: LSR0 V00T0000
|
|
arc: LSR1 V00T0000
|
|
arc: M3 H00R0000
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: S1_V02S0401 Q6
|
|
arc: V01S0000 Q0
|
|
arc: V01S0100 Q3
|
|
word: SLICEA.K0.INIT 1111110000001100
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R31C87:PLC2
|
|
arc: V00B0100 N1_V02S0101
|
|
arc: A0 W1_H02E0701
|
|
arc: B0 H02E0301
|
|
arc: C0 H02E0601
|
|
arc: CE0 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: F0 F0_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: V01S0000 Q0
|
|
word: SLICEA.K0.INIT 1010000010110011
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
|
|
.tile R32C48:PLC2
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
|
|
.tile R32C63:PLC2
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
|
|
.tile R32C65:PLC2
|
|
arc: H00R0000 V02S0401
|
|
arc: N3_V06N0103 E3_H06W0103
|
|
arc: S3_V06S0103 E3_H06W0103
|
|
arc: CE1 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0003 Q3
|
|
arc: M3 H00R0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: N3_V06N0003 Q3
|
|
arc: S3_V06S0003 Q3
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R32C66:PLC2
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: W1_H02W0101 E1_H02W0001
|
|
|
|
.tile R32C67:PLC2
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
|
|
.tile R32C68:PLC2
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: S3_V06S0003 H06E0003
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: W1_H02W0001 E3_H06W0003
|
|
|
|
.tile R32C71:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R32C72:PLC2
|
|
arc: E3_H06E0203 V06S0203
|
|
|
|
.tile R32C73:PLC2
|
|
arc: E1_H02E0201 E3_H06W0103
|
|
arc: E1_H02E0501 S3_V06N0303
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: S3_V06S0103 H06W0103
|
|
arc: S3_V06S0203 E1_H01W0000
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile R32C74:PLC2
|
|
arc: E1_H02E0501 V06S0303
|
|
arc: N3_V06N0003 H06E0003
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: S1_V02S0301 N1_V02S0301
|
|
arc: S1_V02S0501 H02E0501
|
|
arc: S1_V02S0701 N1_V02S0601
|
|
arc: A3 N1_V02S0501
|
|
arc: D3 H02E0201
|
|
arc: E1_H01E0001 F3
|
|
arc: E3_H06E0003 F3
|
|
arc: F3 F3_SLICE
|
|
arc: H01W0000 F3
|
|
arc: N1_V02N0101 F3
|
|
arc: S1_V02S0101 F3
|
|
arc: S3_V06S0003 F3
|
|
arc: W3_H06W0003 F3
|
|
word: SLICEB.K1.INIT 0101010100000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
|
|
.tile R32C75:PLC2
|
|
arc: E1_H02E0601 H01E0001
|
|
arc: E3_H06E0003 H01E0001
|
|
arc: N3_V06N0203 H01E0001
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S1_V02S0701 S3_V06N0203
|
|
arc: S3_V06S0203 H01E0001
|
|
|
|
.tile R32C76:PLC2
|
|
arc: N3_V06N0303 E1_H01W0100
|
|
arc: S1_V02S0101 S3_V06N0103
|
|
arc: S1_V02S0501 W1_H02E0501
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
|
|
.tile R32C77:PLC2
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: H00R0100 H02W0701
|
|
arc: N1_V02N0001 W3_H06E0003
|
|
arc: N3_V06N0003 H06E0003
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: CE1 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q3
|
|
arc: E1_H02E0301 Q3
|
|
arc: H01W0100 Q3
|
|
arc: M3 H00R0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: N1_V02N0101 Q3
|
|
arc: N1_V02N0301 Q3
|
|
arc: S3_V06S0003 Q3
|
|
arc: W3_H06W0003 Q3
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R32C78:PLC2
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: N1_V02N0501 V01N0101
|
|
arc: N1_V02N0701 S1_V02N0601
|
|
arc: N3_V06N0203 S1_V02N0401
|
|
arc: S1_V02S0101 S3_V06N0103
|
|
arc: S1_V02S0301 E3_H06W0003
|
|
arc: S1_V02S0701 S3_V06N0203
|
|
arc: S3_V06S0003 H06E0003
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
|
|
.tile R32C79:PLC2
|
|
arc: N1_V02N0101 V01N0101
|
|
arc: N1_V02N0301 W1_H02E0301
|
|
arc: N1_V02N0401 V01N0001
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: S1_V02S0301 S3_V06N0003
|
|
arc: S1_V02S0701 S3_V06N0203
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
arc: V01S0100 S3_V06N0303
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R32C80:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
arc: H01W0000 E3_H06W0103
|
|
arc: N1_V02N0001 V01N0001
|
|
arc: N1_V02N0201 E3_H06W0103
|
|
arc: N1_V02N0501 V01N0101
|
|
arc: S1_V02S0101 S3_V06N0103
|
|
arc: S1_V02S0301 S3_V06N0003
|
|
|
|
.tile R32C82:PLC2
|
|
arc: E1_H02E0601 V01N0001
|
|
arc: H00R0100 H02W0701
|
|
arc: N1_V02N0301 N1_V01S0100
|
|
arc: N1_V02N0501 H02W0501
|
|
arc: N1_V02N0701 E1_H01W0100
|
|
arc: V00B0100 V02S0301
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR0 V00B0100
|
|
arc: M7 H02W0201
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR0
|
|
arc: N1_V01N0101 Q7
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R32C83:PLC2
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E1_H02E0501 E3_H06W0303
|
|
arc: H00L0000 H02W0001
|
|
arc: N1_V02N0201 H06W0103
|
|
arc: S1_V02S0201 H06E0103
|
|
arc: V00B0000 V02S0001
|
|
arc: W1_H02W0201 E1_H02W0201
|
|
arc: C5 E1_H02W0401
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D5 H02W0001
|
|
arc: E1_H01E0001 Q7
|
|
arc: E1_H01E0101 Q0
|
|
arc: E3_H06E0003 Q0
|
|
arc: F5 F5_SLICE
|
|
arc: H00R0100 F5
|
|
arc: H01W0100 Q3
|
|
arc: LSR0 V00B0000
|
|
arc: LSR1 V00B0000
|
|
arc: M0 H02E0601
|
|
arc: M3 H02W0201
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0101 F5
|
|
arc: N1_V02N0001 Q0
|
|
arc: N1_V02N0101 Q3
|
|
arc: V01S0000 F5
|
|
arc: W1_H02W0501 Q7
|
|
arc: W1_H02W0701 F5
|
|
word: SLICEC.K1.INIT 1111000000000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R32C84:PLC2
|
|
arc: E1_H02E0201 H01E0001
|
|
arc: E1_H02E0301 N3_V06S0003
|
|
arc: E1_H02E0701 E1_H01W0100
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0501 H01E0101
|
|
arc: N1_V02N0701 H01E0101
|
|
arc: S1_V02S0001 H02E0001
|
|
arc: W1_H02W0001 N3_V06S0003
|
|
arc: A0 H02E0501
|
|
arc: C0 N1_V01N0001
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02E0001
|
|
arc: F0 F0_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: S3_V06S0003 Q0
|
|
arc: W1_H02W0201 Q0
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEA.K0.INIT 1010101011110000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R32C85:PLC2
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: E1_H02E0501 V02S0501
|
|
arc: S1_V02S0001 N1_V01S0000
|
|
arc: S1_V02S0401 H02W0401
|
|
arc: V00B0000 H02W0601
|
|
arc: V00B0100 V02S0301
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0401 E1_H01W0000
|
|
arc: A2 V00T0000
|
|
arc: A6 F5
|
|
arc: A7 F5
|
|
arc: B0 V00T0000
|
|
arc: B7 H02E0301
|
|
arc: C0 H02W0401
|
|
arc: C2 V02N0401
|
|
arc: C3 H02W0401
|
|
arc: C5 V00T0000
|
|
arc: C6 V02N0001
|
|
arc: C7 V01N0101
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 N1_V01S0000
|
|
arc: D2 V00T0100
|
|
arc: D3 N1_V01S0000
|
|
arc: D5 H01W0000
|
|
arc: D6 V02N0601
|
|
arc: D7 V01N0001
|
|
arc: E1_H01E0001 F6
|
|
arc: E1_H01E0101 Q0
|
|
arc: E1_H02E0201 Q2
|
|
arc: E1_H02E0701 F5
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: H00R0000 F6
|
|
arc: H01W0000 F3
|
|
arc: H01W0100 Q2
|
|
arc: LSR1 V00B0100
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: N1_V02N0001 Q0
|
|
arc: N1_V02N0401 F6
|
|
arc: V00T0000 Q0
|
|
arc: V00T0100 F3
|
|
arc: V01S0100 Q0
|
|
arc: W3_H06W0103 F2
|
|
word: SLICEB.K1.INIT 0000000000001111
|
|
word: SLICEC.K1.INIT 0000111100000000
|
|
word: SLICEB.K0.INIT 1010000000000000
|
|
word: SLICEA.K0.INIT 1100001111001100
|
|
word: SLICED.K0.INIT 0000010100000000
|
|
word: SLICED.K1.INIT 0000000011010000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R32C86:PLC2
|
|
arc: H00R0000 V02S0401
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0301 H06E0003
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: S1_V02S0401 N1_V01S0000
|
|
arc: V00B0100 W1_H02E0701
|
|
arc: W1_H02W0401 N1_V01S0000
|
|
arc: A0 H00R0000
|
|
arc: A2 H02E0501
|
|
arc: A3 V00B0000
|
|
arc: A6 H02E0701
|
|
arc: B0 V00T0000
|
|
arc: B2 V02N0301
|
|
arc: B3 V02N0301
|
|
arc: C0 H00R0100
|
|
arc: C2 H02E0401
|
|
arc: C3 N1_V01S0100
|
|
arc: C6 E1_H01E0101
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00T0100
|
|
arc: D2 H01E0101
|
|
arc: D3 H02E0201
|
|
arc: D6 F0
|
|
arc: E1_H01E0001 Q4
|
|
arc: E1_H01E0101 F3
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00L0000 F2
|
|
arc: H00L0100 Q1
|
|
arc: H00R0100 Q5
|
|
arc: H01W0000 F6
|
|
arc: LSR0 H02E0301
|
|
arc: LSR1 H02E0301
|
|
arc: M1 H02W0001
|
|
arc: M2 N1_V01N0001
|
|
arc: M4 V00B0100
|
|
arc: M5 H00L0100
|
|
arc: M6 H02W0401
|
|
arc: M7 W1_H02E0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q5
|
|
arc: N1_V02N0001 Q2
|
|
arc: S1_V02S0601 Q6
|
|
arc: V00B0000 Q4
|
|
arc: V00T0000 Q2
|
|
arc: V00T0100 Q1
|
|
arc: V01S0000 F6
|
|
arc: V01S0100 Q7
|
|
arc: W1_H02W0601 F6
|
|
arc: W3_H06W0103 Q2
|
|
word: SLICED.K0.INIT 1010000000000000
|
|
word: SLICEA.K0.INIT 0000000000000001
|
|
word: SLICEB.K1.INIT 0000000000000001
|
|
word: SLICEB.K0.INIT 0100000000000000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R32C87:PLC2
|
|
arc: E1_H02E0701 S3_V06N0203
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: W1_H02W0001 H01E0001
|
|
arc: W1_H02W0401 N1_V01S0000
|
|
|
|
.tile R33C71:PLC2
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0103 S1_V02N0201
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile R33C72:PLC2
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
|
|
.tile R33C73:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0201 S3_V06N0103
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E1_H02E0601 S3_V06N0303
|
|
arc: E1_H02E0701 S3_V06N0203
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
|
|
.tile R33C74:PLC2
|
|
arc: E1_H02E0301 N3_V06S0003
|
|
arc: E1_H02E0601 N3_V06S0303
|
|
arc: E1_H02E0701 N3_V06S0203
|
|
arc: H00L0000 N1_V02S0201
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S1_V02S0001 N1_V02S0001
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: V00T0000 H02E0201
|
|
arc: V00T0100 N1_V02S0501
|
|
arc: A0 H02W0701
|
|
arc: A2 V02S0501
|
|
arc: A3 N1_V02S0701
|
|
arc: A4 V00T0100
|
|
arc: A5 N1_V02S0101
|
|
arc: A6 S1_V02N0101
|
|
arc: A7 H00L0000
|
|
arc: B2 V02S0301
|
|
arc: B3 S1_V02N0301
|
|
arc: B4 S1_V02N0701
|
|
arc: B5 S1_V02N0501
|
|
arc: B6 V02S0701
|
|
arc: B7 V00T0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q6
|
|
arc: E1_H02E0101 Q3
|
|
arc: E1_H02E0401 Q4
|
|
arc: E1_H02E0501 Q7
|
|
arc: E3_H06E0103 Q2
|
|
arc: E3_H06E0303 Q5
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R33C75:PLC2
|
|
arc: E1_H02E0401 H01E0001
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: V00B0000 H02E0601
|
|
arc: V00B0100 H02E0701
|
|
arc: W1_H02W0701 V02S0701
|
|
arc: A0 H00R0000
|
|
arc: A1 W1_H02E0501
|
|
arc: A2 W1_H02E0701
|
|
arc: A3 N1_V02S0501
|
|
arc: A4 V02N0301
|
|
arc: A5 N1_V02S0101
|
|
arc: A6 V02N0101
|
|
arc: A7 H02W0701
|
|
arc: B0 S1_V02N0301
|
|
arc: B1 S1_V02N0101
|
|
arc: B2 H02E0301
|
|
arc: B3 W1_H02E0101
|
|
arc: B4 V00B0100
|
|
arc: B5 W1_H02E0301
|
|
arc: B6 V00B0000
|
|
arc: B7 N1_V02S0701
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q6
|
|
arc: E1_H02E0001 Q2
|
|
arc: E1_H02E0101 Q3
|
|
arc: E1_H02E0201 Q0
|
|
arc: E1_H02E0601 Q4
|
|
arc: E3_H06E0103 Q1
|
|
arc: E3_H06E0203 Q7
|
|
arc: E3_H06E0303 Q5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R33C76:PLC2
|
|
arc: E1_H02E0001 W1_H02E0501
|
|
arc: E1_H02E0201 H01E0001
|
|
arc: E1_H02E0401 W1_H02E0101
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: H00R0000 N1_V02S0601
|
|
arc: S3_V06S0103 E3_H06W0103
|
|
arc: V00T0000 N1_V02S0601
|
|
arc: W1_H02W0701 S3_V06N0203
|
|
arc: A0 V02S0501
|
|
arc: A1 H00R0000
|
|
arc: A2 V00T0000
|
|
arc: B0 S1_V02N0101
|
|
arc: B1 V02S0101
|
|
arc: B2 V02S0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H02E0301 Q1
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0103 Q2
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
word: SLICEC.K1.INIT 0000000000001110
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R33C77:PLC2
|
|
arc: E1_H02E0001 W1_H02E0001
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
arc: E1_H02E0401 W1_H02E0101
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: E1_H02E0601 W1_H02E0601
|
|
|
|
.tile R33C78:PLC2
|
|
arc: E1_H02E0301 W1_H02E0201
|
|
arc: E1_H02E0601 W1_H02E0301
|
|
arc: N1_V02N0101 V01N0101
|
|
arc: N3_V06N0203 E1_H01W0000
|
|
arc: V00B0000 W1_H02E0401
|
|
arc: V00B0100 W1_H02E0501
|
|
arc: V00T0000 W1_H02E0001
|
|
arc: A0 V01N0101
|
|
arc: A2 V02S0701
|
|
arc: A3 V00B0000
|
|
arc: A4 N1_V01S0100
|
|
arc: A5 E1_H02W0501
|
|
arc: A6 H02E0501
|
|
arc: A7 V02N0101
|
|
arc: B2 E1_H02W0101
|
|
arc: B3 V02S0101
|
|
arc: B4 V00B0100
|
|
arc: B5 V02N0701
|
|
arc: B6 V02N0501
|
|
arc: B7 V00T0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q2
|
|
arc: N1_V02N0301 Q3
|
|
arc: N1_V02N0501 Q5
|
|
arc: N1_V02N0601 Q4
|
|
arc: V01S0000 Q6
|
|
arc: V01S0100 Q7
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101100
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R33C79:PLC2
|
|
arc: H00L0100 W1_H02E0301
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: V00B0000 W1_H02E0401
|
|
arc: V00T0000 W1_H02E0001
|
|
arc: A0 H00L0100
|
|
arc: A1 V02S0701
|
|
arc: A2 V00T0000
|
|
arc: A3 V00B0000
|
|
arc: A4 N1_V01S0100
|
|
arc: A5 E1_H02W0501
|
|
arc: A6 S1_V02N0101
|
|
arc: A7 E1_H02W0701
|
|
arc: B0 V02S0301
|
|
arc: B1 E1_H02W0101
|
|
arc: B2 V02N0301
|
|
arc: B3 V02N0101
|
|
arc: B4 H00R0000
|
|
arc: B5 V02N0501
|
|
arc: B6 H02E0301
|
|
arc: B7 V02N0701
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 Q3
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q2
|
|
arc: N1_V01N0101 Q7
|
|
arc: N1_V02N0001 Q0
|
|
arc: N1_V02N0301 Q1
|
|
arc: N1_V02N0401 Q6
|
|
arc: N1_V02N0501 Q5
|
|
arc: V01S0000 Q4
|
|
word: SLICED.K1.INIT 0110011001101100
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101100
|
|
word: SLICEC.K0.INIT 0110011001101010
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R33C80:PLC2
|
|
arc: E1_H02E0001 N1_V02S0001
|
|
arc: H00L0000 E1_H02W0001
|
|
arc: H00R0000 W1_H02E0601
|
|
arc: V00T0000 E1_H02W0201
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: W1_H02W0501 W3_H06E0303
|
|
arc: A0 H00L0000
|
|
arc: A1 H00R0000
|
|
arc: A2 V00T0000
|
|
arc: A3 V00T0000
|
|
arc: B0 V02S0301
|
|
arc: B1 V02S0101
|
|
arc: B2 V02N0301
|
|
arc: B3 V02N0301
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: N1_V01N0001 Q3
|
|
arc: N1_V01N0101 Q0
|
|
arc: N1_V02N0101 Q1
|
|
arc: N1_V02N0201 Q2
|
|
word: SLICEC.K1.INIT 0000000000001110
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0110011001101100
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R33C81:PLC2
|
|
arc: W1_H02W0101 W3_H06E0103
|
|
arc: W1_H02W0501 W3_H06E0303
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
|
|
.tile R33C82:PLC2
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: V00T0000 E1_H02W0001
|
|
arc: W1_H02W0001 W3_H06E0003
|
|
arc: W1_H02W0201 W3_H06E0103
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H02E0501 Q5
|
|
arc: LSR0 V00T0000
|
|
arc: M1 W1_H02E0001
|
|
arc: M5 H02W0001
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: N1_V01N0001 Q1
|
|
arc: W3_H06W0103 Q1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R33C83:PLC2
|
|
arc: E1_H02E0001 E1_H01W0000
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D3 V02S0201
|
|
arc: F3 F3_SLICE
|
|
arc: LSR1 V00T0100
|
|
arc: M2 V00B0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR1
|
|
arc: V00T0100 F3
|
|
arc: W1_H02W0001 Q2
|
|
word: SLICEB.K1.INIT 0000000011111111
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R33C84:PLC2
|
|
arc: H00R0100 W1_H02E0501
|
|
arc: V00B0000 V02S0001
|
|
arc: W1_H02W0001 V02S0001
|
|
arc: CLK0 G_HPBX0000
|
|
arc: H00R0000 Q6
|
|
arc: H01W0000 Q4
|
|
arc: LSR0 V00B0000
|
|
arc: LSR1 V00B0000
|
|
arc: M0 V00B0100
|
|
arc: M1 H00R0100
|
|
arc: M4 V00T0000
|
|
arc: M5 H00R0000
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: V00B0100 Q5
|
|
arc: V00T0000 Q0
|
|
arc: V00T0100 Q1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R33C85:PLC2
|
|
arc: E1_H02E0001 V02S0001
|
|
arc: E1_H02E0101 N1_V01S0100
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: V00B0000 N1_V02S0201
|
|
arc: V00T0000 V02S0401
|
|
arc: V00T0100 H02W0101
|
|
arc: A2 V00T0000
|
|
arc: A4 F5
|
|
arc: A5 N1_V01S0100
|
|
arc: A6 N1_V01S0100
|
|
arc: B0 V00T0000
|
|
arc: B2 S1_V02N0301
|
|
arc: B4 H00L0000
|
|
arc: B5 V00B0100
|
|
arc: B6 V00B0000
|
|
arc: C0 N1_V01S0100
|
|
arc: C2 N1_V01S0100
|
|
arc: C4 S1_V02N0001
|
|
arc: C5 V02S0001
|
|
arc: C6 F4
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 N1_V02S0201
|
|
arc: D2 S1_V02N0201
|
|
arc: D4 H01W0000
|
|
arc: D5 V02S0401
|
|
arc: D6 V02S0401
|
|
arc: E1_H01E0001 Q0
|
|
arc: E1_H01E0101 Q5
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00L0000 F0
|
|
arc: H00R0000 F6
|
|
arc: H01W0000 Q0
|
|
arc: LSR0 V00T0100
|
|
arc: M2 V00B0000
|
|
arc: M5 W1_H02E0001
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: N1_V01N0001 F2
|
|
arc: N1_V01N0101 F4
|
|
arc: N1_V02N0001 F2
|
|
arc: N1_V02N0601 F4
|
|
arc: V00B0100 Q5
|
|
word: SLICED.K0.INIT 0001000010000000
|
|
word: SLICEB.K0.INIT 1011000011110000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0101010001000100
|
|
word: SLICEA.K0.INIT 1111111111110011
|
|
word: SLICEC.K1.INIT 0000000000100000
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R33C86:PLC2
|
|
arc: H00L0000 H02E0001
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: S3_V06S0103 N1_V02S0101
|
|
arc: V00B0000 N1_V02S0001
|
|
arc: V00T0000 V02S0601
|
|
arc: W1_H02W0101 N1_V02S0101
|
|
arc: A2 F7
|
|
arc: A3 V00T0000
|
|
arc: A7 N1_V01S0100
|
|
arc: B3 H02E0101
|
|
arc: B7 V01S0000
|
|
arc: C2 H00L0000
|
|
arc: C3 V02S0401
|
|
arc: C7 H01E0001
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D2 N1_V01S0000
|
|
arc: D3 H02E0001
|
|
arc: D7 H01W0000
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H01W0000 F3
|
|
arc: LSR0 V00B0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: V01S0000 Q2
|
|
word: SLICEB.K0.INIT 0101010101011010
|
|
word: SLICEB.K1.INIT 1010101010100110
|
|
word: SLICED.K1.INIT 0110100110010110
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R35C66:PLC2
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile R35C67:PLC2
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile R35C68:PLC2
|
|
arc: S3_V06S0303 E3_H06W0303
|
|
|
|
.tile R35C71:PLC2
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: N3_V06N0303 S1_V02N0601
|
|
|
|
.tile R35C72:PLC2
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
|
|
.tile R35C73:PLC2
|
|
arc: E1_H02E0101 V06N0103
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile R35C74:PLC2
|
|
arc: H00L0000 N1_V02S0001
|
|
arc: H00R0000 V02S0401
|
|
arc: N1_V02N0101 H02E0101
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: N1_V02N0501 H02E0501
|
|
arc: N1_V02N0701 H02E0701
|
|
arc: CE1 H00R0000
|
|
arc: CE2 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0003 Q3
|
|
arc: E3_H06E0303 Q5
|
|
arc: M3 E1_H02W0201
|
|
arc: M5 H00L0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V01N0001 Q3
|
|
arc: N3_V06N0303 Q5
|
|
arc: S3_V06S0003 Q3
|
|
arc: S3_V06S0303 Q5
|
|
arc: W3_H06W0303 Q5
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R35C75:PLC2
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
|
|
.tile R35C76:PLC2
|
|
arc: N1_V02N0101 S1_V02N0101
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: A0 H02W0501
|
|
arc: C0 S1_V02N0401
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 H02W0001
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: W1_H02W0201 Q0
|
|
word: SLICEA.K0.INIT 1111010110100000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R35C77:PLC2
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: W1_H02W0001 E1_H02W0001
|
|
arc: W1_H02W0501 N3_V06S0303
|
|
|
|
.tile R35C78:PLC2
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
|
|
.tile R35C79:PLC2
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
arc: W1_H02W0001 S3_V06N0003
|
|
|
|
.tile R35C80:PLC2
|
|
arc: S3_V06S0003 W3_H06E0003
|
|
arc: S3_V06S0303 W3_H06E0303
|
|
|
|
.tile R35C82:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
arc: N1_V02N0001 W3_H06E0003
|
|
|
|
.tile R35C83:PLC2
|
|
arc: N1_V02N0001 E1_H02W0001
|
|
|
|
.tile R35C85:PLC2
|
|
arc: N1_V02N0001 H06E0003
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: W1_H02W0001 S3_V06N0003
|
|
|
|
.tile R36C67:PLC2
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: S3_V06S0003 E3_H06W0003
|
|
|
|
.tile R36C72:PLC2
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR1 E1_H02W0501
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N3_V06N0303 Q6
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R36C73:PLC2
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: V00T0100 S1_V02N0501
|
|
arc: CE0 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0003 Q0
|
|
arc: M0 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: N3_V06N0003 Q0
|
|
arc: S3_V06S0003 Q0
|
|
arc: W3_H06W0003 Q0
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R36C74:PLC2
|
|
arc: E1_H02E0501 V02N0501
|
|
arc: E1_H02E0701 V06S0203
|
|
arc: W1_H02W0501 V02N0501
|
|
|
|
.tile R36C75:PLC2
|
|
arc: H00R0100 H02E0701
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR0 H02E0501
|
|
arc: M1 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: S1_V02S0101 Q1
|
|
arc: S3_V06S0103 Q1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R36C76:PLC2
|
|
arc: S3_V06S0003 H06E0003
|
|
|
|
.tile R36C78:PLC2
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
|
|
.tile R36C79:PLC2
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: N3_V06N0003 W3_H06E0003
|
|
arc: S3_V06S0003 W3_H06E0003
|
|
|
|
.tile R36C80:PLC2
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
|
|
.tile R37C13:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R37C19:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R37C25:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R37C31:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R37C37:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R37C43:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R37C49:PLC2
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R37C55:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R37C61:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R37C65:PLC2
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
|
|
.tile R37C66:PLC2
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
|
|
.tile R37C67:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
arc: S3_V06S0103 H06W0103
|
|
arc: S3_V06S0303 E3_H06W0303
|
|
|
|
.tile R37C68:PLC2
|
|
arc: N3_V06N0203 H06W0203
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile R37C69:PLC2
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile R37C70:PLC2
|
|
arc: W3_H06W0103 E1_H01W0100
|
|
|
|
.tile R37C71:PLC2
|
|
arc: H00L0100 V02N0301
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N3_V06N0003 S1_V02N0001
|
|
arc: N3_V06N0103 S1_V02N0101
|
|
arc: N3_V06N0203 S1_V02N0701
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0203 Q7
|
|
arc: H01W0100 Q7
|
|
arc: M7 E1_H02W0201
|
|
arc: MUXCLK3 CLK0
|
|
arc: W3_H06W0203 Q7
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R37C72:PLC2
|
|
arc: N3_V06N0303 S1_V02N0601
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
|
|
.tile R37C73:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
arc: H00L0000 V02N0201
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: W1_H02W0201 E1_H01W0000
|
|
arc: CE2 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0303 Q5
|
|
arc: M5 H00L0000
|
|
arc: MUXCLK2 CLK0
|
|
arc: N3_V06N0303 Q5
|
|
arc: S3_V06S0303 Q5
|
|
arc: W3_H06W0303 Q5
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R37C74:PLC2
|
|
arc: E1_H02E0501 N3_V06S0303
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
arc: N3_V06N0203 H06E0203
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: S1_V02S0201 V01N0001
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: S1_V02S0401 E1_H01W0000
|
|
arc: S1_V02S0601 V01N0001
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: S3_V06S0203 H06E0203
|
|
arc: V00B0100 V02N0101
|
|
arc: V00T0000 H02W0001
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: CLK0 G_HPBX0000
|
|
arc: H01W0000 Q2
|
|
arc: LSR0 V00B0100
|
|
arc: M2 V00T0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: N3_V06N0103 Q2
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R37C75:PLC2
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: V00B0100 V02S0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: H01W0000 Q2
|
|
arc: LSR0 H02E0501
|
|
arc: M2 V00B0100
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR1 LSR0
|
|
arc: W1_H02W0001 Q2
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R37C76:PLC2
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0401 H06E0203
|
|
|
|
.tile R37C77:PLC2
|
|
arc: N3_V06N0203 W3_H06E0203
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile R37C78:PLC2
|
|
arc: E3_H06E0203 V06N0203
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
|
|
.tile R37C79:PLC2
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N3_V06N0303 W3_H06E0303
|
|
arc: S3_V06S0303 W3_H06E0303
|
|
|
|
.tile R37C7:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R37C84:PLC2
|
|
arc: N3_V06N0203 W3_H06E0203
|
|
|
|
.tile R38C48:PLC2
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile R38C63:PLC2
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile R38C65:PLC2
|
|
arc: S3_V06S0003 H06W0003
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile R38C66:PLC2
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
|
|
.tile R38C67:PLC2
|
|
arc: S3_V06S0003 E1_H01W0000
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
|
|
.tile R38C68:PLC2
|
|
arc: H01W0000 E3_H06W0103
|
|
arc: N3_V06N0103 E3_H06W0103
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R38C71:PLC2
|
|
arc: N1_V02N0301 H06W0003
|
|
|
|
.tile R38C72:PLC2
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
|
|
.tile R38C73:PLC2
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
arc: CLK0 G_HPBX0000
|
|
arc: H00L0000 Q0
|
|
arc: H01W0100 Q7
|
|
arc: LSR0 H02W0501
|
|
arc: LSR1 H02W0501
|
|
arc: M0 V00T0000
|
|
arc: M2 E1_H02W0601
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V02N0201 Q2
|
|
arc: N1_V02N0501 Q7
|
|
arc: N3_V06N0003 Q0
|
|
arc: V00T0000 Q2
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R38C74:PLC2
|
|
arc: H00R0000 V02S0401
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V02N0101 N1_V01S0100
|
|
arc: S1_V02S0001 N3_V06S0003
|
|
arc: S1_V02S0301 N1_V01S0100
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: W1_H02W0501 N1_V01S0100
|
|
arc: W3_H06W0003 N3_V06S0003
|
|
arc: CE0 V02S0201
|
|
arc: CE2 V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0103 Q1
|
|
arc: E3_H06E0303 Q5
|
|
arc: M1 H00R0000
|
|
arc: M5 H02W0001
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N3_V06N0103 Q1
|
|
arc: N3_V06N0303 Q5
|
|
arc: S3_V06S0103 Q1
|
|
arc: S3_V06S0303 Q5
|
|
arc: W3_H06W0103 Q1
|
|
arc: W3_H06W0303 Q5
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R38C75:PLC2
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
arc: W1_H02W0001 V01N0001
|
|
arc: W1_H02W0601 V01N0001
|
|
|
|
.tile R38C76:PLC2
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
|
|
.tile R38C77:PLC2
|
|
arc: N3_V06N0103 H06E0103
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0103 H06E0103
|
|
arc: S3_V06S0303 H06E0303
|
|
|
|
.tile R38C78:PLC2
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
|
|
.tile R38C79:PLC2
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
|
|
.tile R38C80:PLC2
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
|
|
.tile R38C84:PLC2
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
|
|
.tile R38C87:PLC2
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
|
|
.tile R39C65:PLC2
|
|
arc: E3_H06E0003 S3_V06N0003
|
|
arc: E3_H06E0103 S3_V06N0103
|
|
arc: E3_H06E0203 S3_V06N0203
|
|
arc: E3_H06E0303 S3_V06N0303
|
|
|
|
.tile R39C68:PLC2
|
|
arc: S3_V06S0103 E3_H06W0103
|
|
arc: S3_V06S0203 E3_H06W0203
|
|
|
|
.tile R39C71:PLC2
|
|
arc: E1_H02E0601 W3_H06E0303
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0101 S3_V06N0103
|
|
arc: N1_V02N0301 W3_H06E0003
|
|
arc: N1_V02N0701 W3_H06E0203
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
arc: N3_V06N0103 S1_V02N0201
|
|
arc: N3_V06N0203 S1_V02N0401
|
|
arc: N3_V06N0303 S1_V02N0501
|
|
|
|
.tile R39C72:PLC2
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
|
|
.tile R39C73:PLC2
|
|
arc: E3_H06E0203 S3_V06N0203
|
|
arc: N3_V06N0003 E1_H01W0000
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile R39C74:PLC2
|
|
arc: E1_H02E0301 V02S0301
|
|
arc: H00L0000 V02S0001
|
|
arc: H00L0100 E1_H02W0101
|
|
arc: N3_V06N0203 H06E0203
|
|
arc: V00B0100 N1_V02S0301
|
|
arc: CE0 H00L0000
|
|
arc: CE2 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q4
|
|
arc: E3_H06E0103 Q1
|
|
arc: H01W0000 Q1
|
|
arc: M1 H00L0100
|
|
arc: M4 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N3_V06N0103 Q1
|
|
arc: S3_V06S0103 Q1
|
|
arc: V01S0000 Q1
|
|
arc: V01S0100 Q4
|
|
arc: W3_H06W0103 Q1
|
|
arc: W3_H06W0203 Q4
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R39C75:PLC2
|
|
arc: N3_V06N0003 H01E0001
|
|
arc: CLK0 G_HPBX0000
|
|
arc: LSR1 H02E0301
|
|
arc: M1 V01S0100
|
|
arc: M3 H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR1
|
|
arc: N1_V01N0001 Q1
|
|
arc: S1_V02S0301 Q3
|
|
arc: V01S0100 Q3
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R39C76:PLC2
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N3_V06N0203 H06E0203
|
|
arc: W1_H02W0101 N3_V06S0103
|
|
arc: W1_H02W0201 N3_V06S0103
|
|
|
|
.tile R39C77:PLC2
|
|
arc: S3_V06S0103 H06E0103
|
|
|
|
.tile R39C86:PLC2
|
|
arc: S1_V02S0101 N3_V06S0103
|
|
|
|
.tile R40C39:PLC2
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
|
|
.tile R40C69:PLC2
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
|
|
.tile R40C74:PLC2
|
|
arc: E3_H06E0103 N1_V01S0100
|
|
arc: S3_V06S0003 N1_V01S0000
|
|
arc: S3_V06S0103 N1_V01S0100
|
|
|
|
.tile R40C77:PLC2
|
|
arc: S3_V06S0103 H06E0103
|
|
|
|
.tile R40C78:PLC2
|
|
arc: N3_V06N0103 S1_V02N0201
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: S1_V02S0601 N1_V02S0301
|
|
|
|
.tile R41C65:PLC2
|
|
arc: E3_H06E0003 S3_V06N0003
|
|
arc: E3_H06E0203 S3_V06N0203
|
|
arc: E3_H06E0303 S3_V06N0303
|
|
|
|
.tile R41C66:PLC2
|
|
arc: N3_V06N0103 E3_H06W0103
|
|
arc: S3_V06S0103 E3_H06W0103
|
|
|
|
.tile R41C67:PLC2
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
|
|
.tile R41C68:PLC2
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
|
|
.tile R41C71:PLC2
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0401 W3_H06E0203
|
|
arc: N1_V02N0501 W3_H06E0303
|
|
arc: N3_V06N0003 W3_H06E0003
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile R41C72:PLC2
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R41C73:PLC2
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
|
|
.tile R41C74:PLC2
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
|
|
.tile R41C75:PLC2
|
|
arc: S1_V02S0601 N1_V02S0301
|
|
arc: S3_V06S0003 H06W0003
|
|
|
|
.tile R41C76:PLC2
|
|
arc: S1_V02S0101 H06W0103
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile R41C77:PLC2
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
|
|
.tile R41C78:PLC2
|
|
arc: H00R0000 V02S0601
|
|
arc: S1_V02S0601 S3_V06N0303
|
|
arc: V00B0100 V02N0101
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M0 V00B0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: N3_V06N0003 Q0
|
|
arc: S3_V06S0003 Q0
|
|
arc: W3_H06W0003 Q0
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R41C79:PLC2
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R41C80:PLC2
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
|
|
.tile R41C85:PLC2
|
|
arc: N3_V06N0103 S1_V02N0201
|
|
arc: S1_V02S0101 H02W0101
|
|
arc: A0 E1_H02W0701
|
|
arc: B0 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0201
|
|
arc: F0 F0_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: N3_V06N0003 Q0
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEA.K0.INIT 1011101110001000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R41C86:PLC2
|
|
arc: W1_H02W0101 N1_V02S0101
|
|
|
|
.tile R41C87:PLC2
|
|
arc: W1_H02W0701 E1_H02W0701
|
|
|
|
.tile R42C67:PLC2
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
|
|
.tile R42C73:PLC2
|
|
arc: N3_V06N0003 S1_V02N0001
|
|
arc: S1_V02S0001 N3_V06S0003
|
|
|
|
.tile R42C75:PLC2
|
|
arc: E3_H06E0103 N3_V06S0103
|
|
|
|
.tile R42C76:PLC2
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
|
|
.tile R42C78:PLC2
|
|
arc: N1_V02N0101 H06E0103
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N3_V06N0203 S1_V02N0401
|
|
arc: N3_V06N0303 S1_V02N0501
|
|
arc: S1_V02S0301 N1_V02S0301
|
|
|
|
.tile R42C79:PLC2
|
|
arc: N3_V06N0003 S1_V02N0001
|
|
arc: N3_V06N0103 S1_V02N0101
|
|
arc: N3_V06N0203 S1_V02N0701
|
|
arc: N3_V06N0303 S1_V02N0501
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
|
|
.tile R42C80:PLC2
|
|
arc: N3_V06N0003 S1_V02N0001
|
|
|
|
.tile R43C65:PLC2
|
|
arc: S1_V02S0001 N3_V06S0003
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile R43C66:PLC2
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
|
|
.tile R43C67:PLC2
|
|
arc: S1_V02S0201 N3_V06S0103
|
|
arc: V01S0100 N3_V06S0303
|
|
|
|
.tile R43C68:PLC2
|
|
arc: N3_V06N0303 E3_H06W0303
|
|
|
|
.tile R43C69:PLC2
|
|
arc: E3_H06E0303 F6
|
|
arc: F6 F6_SLICE
|
|
arc: N3_V06N0303 F6
|
|
arc: S3_V06S0303 F6
|
|
word: SLICED.K0.INIT 1111111111111111
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
|
|
.tile R43C71:PLC2
|
|
arc: N3_V06N0203 S1_V02N0701
|
|
|
|
.tile R43C72:PLC2
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
|
|
.tile R43C73:PLC2
|
|
arc: N3_V06N0003 S1_V02N0301
|
|
arc: N3_V06N0103 S1_V02N0101
|
|
arc: N3_V06N0203 S1_V02N0401
|
|
arc: N3_V06N0303 S1_V02N0601
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
|
|
.tile R43C74:PLC2
|
|
arc: H00L0000 V02N0001
|
|
arc: H00R0000 H02W0601
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: S1_V02S0401 N3_V06S0203
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
arc: CE2 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0303 Q5
|
|
arc: M5 H00R0000
|
|
arc: MUXCLK2 CLK0
|
|
arc: N3_V06N0303 Q5
|
|
arc: S3_V06S0303 Q5
|
|
arc: V01S0000 Q5
|
|
arc: V01S0100 Q5
|
|
arc: W3_H06W0303 Q5
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R43C75:PLC2
|
|
arc: E1_H02E0101 V01N0101
|
|
arc: N3_V06N0303 W3_H06E0303
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0303 W3_H06E0303
|
|
arc: W1_H02W0601 N1_V02S0601
|
|
|
|
.tile R43C76:PLC2
|
|
arc: V00B0100 N1_V02S0101
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK3 CLK0
|
|
arc: V01S0000 Q6
|
|
arc: V01S0100 Q6
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R43C77:PLC2
|
|
arc: N3_V06N0303 H06E0303
|
|
arc: S1_V02S0501 N3_V06S0303
|
|
|
|
.tile R43C78:PLC2
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: S1_V02S0701 N1_V02S0601
|
|
arc: V00B0100 V02S0301
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M5 H02W0001
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: V01S0000 Q6
|
|
arc: V01S0100 Q5
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R43C79:PLC2
|
|
arc: N3_V06N0003 V01N0001
|
|
arc: S3_V06S0303 N3_V06S0303
|
|
arc: W1_H02W0001 E3_H06W0003
|
|
|
|
.tile R43C80:PLC2
|
|
arc: S1_V02S0501 W3_H06E0303
|
|
|
|
.tile R43C85:PLC2
|
|
arc: B0 N1_V02S0101
|
|
arc: C0 V02N0401
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: F0 F0_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: N1_V02N0201 Q0
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEA.K0.INIT 1111001111000000
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R44C48:PLC2
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
|
|
.tile R44C63:PLC2
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
|
|
.tile R44C65:PLC2
|
|
arc: S1_V02S0001 N3_V06S0003
|
|
arc: S1_V02S0101 N3_V06S0103
|
|
arc: S1_V02S0401 N3_V06S0203
|
|
|
|
.tile R44C66:PLC2
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
arc: S1_V02S0501 E1_H02W0501
|
|
|
|
.tile R44C67:PLC2
|
|
arc: S1_V02S0001 N3_V06S0003
|
|
arc: S1_V02S0101 N1_V01S0100
|
|
arc: S1_V02S0301 N1_V02S0301
|
|
arc: S1_V02S0401 N3_V06S0203
|
|
arc: S1_V02S0601 N1_V02S0301
|
|
|
|
.tile R44C68:PLC2
|
|
arc: S1_V02S0101 N3_V06S0103
|
|
arc: S1_V02S0201 N3_V06S0103
|
|
arc: S1_V02S0401 N3_V06S0203
|
|
arc: W1_H02W0501 V06S0303
|
|
|
|
.tile R44C72:PLC2
|
|
arc: E1_H02E0601 S1_V02N0601
|
|
|
|
.tile R44C73:PLC2
|
|
arc: E1_H02E0501 N3_V06S0303
|
|
arc: H00L0100 H02W0301
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: H00R0100 E1_H02W0501
|
|
arc: S1_V02S0001 N1_V02S0001
|
|
arc: S1_V02S0101 N3_V06S0103
|
|
arc: S1_V02S0401 H06W0203
|
|
arc: S1_V02S0501 H02W0501
|
|
arc: S1_V02S0601 N3_V06S0303
|
|
arc: V00T0100 E1_H02W0301
|
|
arc: CE0 H00L0100
|
|
arc: CE1 H00L0100
|
|
arc: CE2 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0103 Q2
|
|
arc: M0 E1_H02W0601
|
|
arc: M2 V00T0100
|
|
arc: M3 H00R0100
|
|
arc: M5 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V02N0001 Q0
|
|
arc: N3_V06N0003 Q3
|
|
arc: N3_V06N0303 Q5
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R44C74:PLC2
|
|
arc: E1_H02E0101 N3_V06S0103
|
|
arc: E1_H02E0201 V06S0103
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: E1_H02E0501 N3_V06S0303
|
|
arc: E1_H02E0601 N3_V06S0303
|
|
arc: E3_H06E0003 N1_V01S0000
|
|
arc: E3_H06E0103 V01N0101
|
|
arc: E3_H06E0203 N1_V01S0000
|
|
arc: E3_H06E0303 N3_V06S0303
|
|
arc: H00L0100 V02S0301
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: S1_V02S0201 N3_V06S0103
|
|
arc: S1_V02S0301 N1_V01S0100
|
|
arc: S1_V02S0501 N3_V06S0303
|
|
arc: W1_H02W0301 V02S0301
|
|
arc: W1_H02W0501 V06S0303
|
|
arc: CE1 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H02E0001 Q2
|
|
arc: M2 W1_H02E0601
|
|
arc: MUXCLK1 CLK0
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R44C75:PLC2
|
|
arc: E1_H02E0001 V02N0001
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
arc: S1_V02S0301 S3_V06N0003
|
|
arc: S1_V02S0501 W1_H02E0501
|
|
arc: S1_V02S0601 H06W0303
|
|
arc: S1_V02S0701 H02W0701
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
|
|
.tile R44C76:PLC2
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0201 N1_V01S0000
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: N3_V06N0103 H06E0103
|
|
arc: S1_V02S0101 W1_H02E0101
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0401 W1_H02E0401
|
|
arc: S1_V02S0501 W1_H02E0501
|
|
arc: S1_V02S0601 W1_H02E0601
|
|
arc: W1_H02W0701 N1_V01S0100
|
|
arc: W3_H06W0203 N1_V01S0000
|
|
|
|
.tile R44C77:PLC2
|
|
arc: E1_H02E0101 W1_H02E0001
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0401 V06S0203
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: S1_V02S0001 N3_V06S0003
|
|
arc: S1_V02S0101 N3_V06S0103
|
|
arc: S1_V02S0201 N3_V06S0103
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: S1_V02S0501 N3_V06S0303
|
|
arc: S1_V02S0601 H06E0303
|
|
|
|
.tile R44C78:PLC2
|
|
arc: E1_H02E0201 V01N0001
|
|
arc: E1_H02E0301 V01N0101
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E1_H02E0701 V06N0203
|
|
arc: H00L0000 V02N0201
|
|
arc: H00R0000 H02E0401
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: S1_V02S0001 N1_V01S0000
|
|
arc: S1_V02S0101 N1_V01S0100
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0301 E1_H02W0301
|
|
arc: S1_V02S0501 E1_H02W0501
|
|
arc: S1_V02S0601 H02W0601
|
|
arc: S1_V02S0701 E1_H02W0701
|
|
arc: V00B0000 S1_V02N0201
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: W3_H06W0303 N1_V01S0100
|
|
arc: A0 H02E0501
|
|
arc: A2 V02S0701
|
|
arc: A3 V00B0000
|
|
arc: A4 V02N0101
|
|
arc: A5 V02N0301
|
|
arc: A6 S1_V02N0101
|
|
arc: A7 V00T0100
|
|
arc: B2 W1_H02E0301
|
|
arc: B3 W1_H02E0101
|
|
arc: B4 H00L0000
|
|
arc: B5 V02N0501
|
|
arc: B6 H02E0101
|
|
arc: B7 V02N0701
|
|
arc: CE0 H00R0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: M1 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0401 Q6
|
|
arc: N1_V02N0501 Q5
|
|
arc: N1_V02N0701 Q7
|
|
arc: N3_V06N0003 Q3
|
|
arc: N3_V06N0103 Q2
|
|
arc: N3_V06N0203 Q4
|
|
arc: V00T0100 Q1
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 1111111111111111
|
|
word: SLICEA.K0.INIT 0000000000001010
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 YES
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R44C79:PLC2
|
|
arc: H00L0000 V02N0001
|
|
arc: H00R0000 V02N0401
|
|
arc: S1_V02S0001 H02W0001
|
|
arc: S1_V02S0301 N1_V02S0301
|
|
arc: S1_V02S0401 N3_V06S0203
|
|
arc: S1_V02S0701 H02W0701
|
|
arc: V00B0000 V02N0201
|
|
arc: V00T0000 H02E0201
|
|
arc: W1_H02W0601 V06S0303
|
|
arc: A0 V02N0501
|
|
arc: A1 H02E0701
|
|
arc: A2 V00T0000
|
|
arc: A3 H02E0501
|
|
arc: A4 E1_H01W0000
|
|
arc: A5 E1_H02W0501
|
|
arc: A6 H00R0000
|
|
arc: A7 H00L0000
|
|
arc: B0 V00B0000
|
|
arc: B1 E1_H02W0101
|
|
arc: B2 V02N0101
|
|
arc: B3 V02N0301
|
|
arc: B4 W1_H02E0301
|
|
arc: B5 H02W0101
|
|
arc: B6 V02N0701
|
|
arc: B7 E1_H02W0301
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q6
|
|
arc: N1_V02N0001 Q2
|
|
arc: N1_V02N0101 Q3
|
|
arc: N1_V02N0501 Q5
|
|
arc: N1_V02N0701 Q7
|
|
arc: N3_V06N0003 Q0
|
|
arc: N3_V06N0103 Q1
|
|
arc: N3_V06N0203 Q4
|
|
word: SLICED.K1.INIT 0110011001101010
|
|
word: SLICED.K0.INIT 0110011001101010
|
|
word: SLICEC.K1.INIT 0110011001101010
|
|
word: SLICEC.K0.INIT 0110011001101100
|
|
word: SLICEB.K1.INIT 0110011001101010
|
|
word: SLICEB.K0.INIT 0110011001101010
|
|
word: SLICEA.K1.INIT 0110011001101010
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_1 NO
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
enum: SLICED.MODE CCU2
|
|
enum: SLICED.CCU2.INJECT1_0 NO
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 1
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 1
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 1
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 1
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 1
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R44C80:PLC2
|
|
arc: H01W0000 W3_H06E0103
|
|
arc: W1_H02W0001 W3_H06E0003
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0301 V06S0003
|
|
arc: W1_H02W0501 V06S0303
|
|
arc: W1_H02W0701 W3_H06E0203
|
|
arc: A0 H02W0701
|
|
arc: A1 V02N0701
|
|
arc: A2 V02N0701
|
|
arc: B0 W1_H02E0301
|
|
arc: B1 V02N0301
|
|
arc: B2 V02N0301
|
|
arc: CLK0 G_HPBX0000
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: N1_V02N0001 Q2
|
|
arc: N3_V06N0003 Q0
|
|
arc: N3_V06N0103 Q1
|
|
word: SLICEC.K1.INIT 0000000000001110
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0110011001101100
|
|
word: SLICEA.K1.INIT 0110011001101100
|
|
word: SLICEA.K0.INIT 0110011001101100
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_1 NO
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICEC.MODE CCU2
|
|
enum: SLICEC.CCU2.INJECT1_0 NO
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_1 NO
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEB.MODE CCU2
|
|
enum: SLICEB.CCU2.INJECT1_0 NO
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_1 NO
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEA.MODE CCU2
|
|
enum: SLICEA.CCU2.INJECT1_0 NO
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R44C81:PLC2
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: W1_H02W0701 V02N0701
|
|
|
|
.tile R44C84:PLC2
|
|
arc: E1_H02E0001 N3_V06S0003
|
|
|
|
.tile R44C85:PLC2
|
|
arc: N1_V02N0001 H02E0001
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
|
|
.tile R44C87:PLC2
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile R45C64:PLC2
|
|
arc: E1_H02E0201 V01N0001
|
|
arc: E1_H02E0401 V02N0401
|
|
arc: E1_H02E0501 V02N0501
|
|
|
|
.tile R45C65:PLC2
|
|
arc: E1_H02E0001 N1_V02S0001
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: H00L0000 N1_V02S0001
|
|
arc: H00R0000 V02N0601
|
|
arc: H00R0100 V02N0501
|
|
arc: S1_V02S0601 V01N0001
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 H02E0501
|
|
arc: V00T0000 V02N0401
|
|
arc: CE0 S1_V02N0201
|
|
arc: CE1 H00L0000
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0003 Q3
|
|
arc: E3_H06E0103 Q2
|
|
arc: E3_H06E0203 Q7
|
|
arc: E3_H06E0303 Q6
|
|
arc: M0 V00B0000
|
|
arc: M1 H02W0001
|
|
arc: M2 V00T0000
|
|
arc: M3 H00R0100
|
|
arc: M4 H02E0401
|
|
arc: M5 H00R0000
|
|
arc: M6 V00B0100
|
|
arc: M7 H02E0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N3_V06N0003 Q0
|
|
arc: N3_V06N0103 Q1
|
|
arc: N3_V06N0203 Q4
|
|
arc: N3_V06N0303 Q5
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R45C66:PLC2
|
|
arc: H00L0000 H02E0001
|
|
arc: S1_V02S0401 E1_H02W0401
|
|
arc: W1_H02W0001 V01N0001
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0203 Q7
|
|
arc: M7 H02E0201
|
|
arc: MUXCLK3 CLK0
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R45C67:PLC2
|
|
arc: S1_V02S0301 N1_V02S0201
|
|
|
|
.tile R45C68:PLC2
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: W1_H02W0401 N3_V06S0203
|
|
|
|
.tile R45C71:PLC2
|
|
arc: N1_V02N0701 W3_H06E0203
|
|
arc: N3_V06N0003 W3_H06E0003
|
|
arc: N3_V06N0103 W3_H06E0103
|
|
arc: N3_V06N0303 W3_H06E0303
|
|
|
|
.tile R45C72:PLC2
|
|
arc: N3_V06N0203 W3_H06E0203
|
|
|
|
.tile R45C73:PLC2
|
|
arc: E1_H02E0401 V01N0001
|
|
arc: E1_H02E0701 V01N0101
|
|
arc: H00L0000 S1_V02N0201
|
|
arc: H00L0100 H02W0301
|
|
arc: H00R0100 V02N0701
|
|
arc: N3_V06N0003 S1_V02N0301
|
|
arc: V00B0100 E1_H02W0501
|
|
arc: V00T0000 V02N0601
|
|
arc: V00T0100 V02N0501
|
|
arc: CE0 S1_V02N0201
|
|
arc: CE1 S1_V02N0201
|
|
arc: CE2 H00L0000
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0003 Q0
|
|
arc: M0 V00B0100
|
|
arc: M1 E1_H02W0001
|
|
arc: M2 H02W0601
|
|
arc: M3 H00R0100
|
|
arc: M4 V00T0000
|
|
arc: M5 H00L0100
|
|
arc: M6 V00T0100
|
|
arc: M7 H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0101 Q1
|
|
arc: N1_V02N0301 Q3
|
|
arc: N1_V02N0401 Q4
|
|
arc: N1_V02N0601 Q6
|
|
arc: N3_V06N0103 Q2
|
|
arc: N3_V06N0203 Q7
|
|
arc: N3_V06N0303 Q5
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R45C74:PLC2
|
|
arc: E1_H02E0301 N1_V02S0301
|
|
arc: E1_H02E0601 V01N0001
|
|
arc: H00L0000 V02N0201
|
|
arc: H00L0100 V02N0101
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: H00R0100 V02N0701
|
|
arc: S1_V02S0401 N1_V02S0401
|
|
arc: S1_V02S0501 N1_V02S0401
|
|
arc: V00B0000 V02N0001
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0000 V02N0401
|
|
arc: V01S0000 N3_V06S0103
|
|
arc: W1_H02W0201 E1_H02W0201
|
|
arc: W1_H02W0301 V01N0101
|
|
arc: W1_H02W0601 V02N0601
|
|
arc: CE0 S1_V02N0201
|
|
arc: CE1 S1_V02N0201
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q2
|
|
arc: E1_H02E0401 Q6
|
|
arc: E1_H02E0501 Q7
|
|
arc: E1_H02E0701 Q5
|
|
arc: E3_H06E0003 Q3
|
|
arc: E3_H06E0103 Q1
|
|
arc: E3_H06E0203 Q4
|
|
arc: M0 V00T0000
|
|
arc: M1 H00R0000
|
|
arc: M2 V00B0000
|
|
arc: M3 H00R0100
|
|
arc: M4 V00B0100
|
|
arc: M5 H00L0100
|
|
arc: M6 H02E0401
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0101 Q0
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R45C75:PLC2
|
|
arc: H00L0000 V02N0001
|
|
arc: H00L0100 H02E0301
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 W1_H02E0701
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: V00B0000 V02N0201
|
|
arc: V00B0100 V02N0101
|
|
arc: W1_H02W0001 V01N0001
|
|
arc: W1_H02W0501 V01N0101
|
|
arc: CE0 H00L0100
|
|
arc: CE1 H00L0100
|
|
arc: CE2 H00L0100
|
|
arc: CE3 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q1
|
|
arc: E1_H02E0101 Q3
|
|
arc: E1_H02E0701 Q7
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0103 Q2
|
|
arc: E3_H06E0203 Q4
|
|
arc: M0 V00B0100
|
|
arc: M1 H00R0100
|
|
arc: M2 H02E0601
|
|
arc: M3 H00R0000
|
|
arc: M4 V00B0000
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R45C76:PLC2
|
|
arc: E1_H02E0501 W1_H02E0401
|
|
arc: E1_H02E0701 W1_H02E0701
|
|
arc: E3_H06E0303 W1_H02E0501
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N3_V06N0003 H06E0003
|
|
arc: W1_H02W0201 V02N0201
|
|
|
|
.tile R45C77:PLC2
|
|
arc: E1_H02E0101 W1_H02E0101
|
|
arc: E1_H02E0501 N1_V02S0501
|
|
arc: E1_H02E0701 W1_H02E0701
|
|
arc: N1_V02N0301 E1_H01W0100
|
|
arc: V01S0000 N3_V06S0103
|
|
|
|
.tile R45C78:PLC2
|
|
arc: H00L0100 V02N0301
|
|
arc: H00R0000 V02N0401
|
|
arc: H00R0100 H02E0501
|
|
arc: N1_V02N0101 H02E0101
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: N1_V02N0601 N1_V01S0000
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
arc: S1_V02S0601 N1_V02S0301
|
|
arc: V00B0100 H02W0701
|
|
arc: V00T0000 V02N0601
|
|
arc: V00T0100 E1_H02W0101
|
|
arc: CE0 H00R0100
|
|
arc: CE1 H00R0100
|
|
arc: CE2 V02S0601
|
|
arc: CE3 H00R0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q1
|
|
arc: E1_H02E0001 Q0
|
|
arc: E3_H06E0303 Q6
|
|
arc: H01W0100 Q4
|
|
arc: M0 V00B0100
|
|
arc: M1 H00R0000
|
|
arc: M2 V00T0000
|
|
arc: M3 H00L0100
|
|
arc: M4 E1_H02W0401
|
|
arc: M5 H02W0001
|
|
arc: M6 V00T0100
|
|
arc: M7 H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q5
|
|
arc: N1_V01N0101 Q7
|
|
arc: N1_V02N0301 Q3
|
|
arc: V01S0100 Q2
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R45C79:PLC2
|
|
arc: H00R0100 V02N0701
|
|
arc: N1_V02N0001 H02E0001
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: N1_V02N0401 S1_V02N0101
|
|
arc: N1_V02N0501 H06E0303
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
arc: W1_H02W0001 V02N0001
|
|
arc: W1_H02W0201 V01N0001
|
|
arc: W1_H02W0701 V01N0101
|
|
arc: CE2 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q5
|
|
arc: M5 H00R0100
|
|
arc: MUXCLK2 CLK0
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R45C80:PLC2
|
|
arc: N1_V02N0101 W3_H06E0103
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0701 W3_H06E0203
|
|
arc: S1_V02S0001 N1_V02S0501
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0301 W3_H06E0003
|
|
arc: W1_H02W0401 V02N0401
|
|
|
|
.tile R45C81:PLC2
|
|
arc: N1_V02N0101 W3_H06E0103
|
|
arc: N1_V02N0301 W3_H06E0003
|
|
arc: N1_V02N0501 H06E0303
|
|
arc: N1_V02N0701 W3_H06E0203
|
|
|
|
.tile R47C64:PLC2
|
|
arc: E1_H02E0601 V02S0601
|
|
|
|
.tile R47C65:PLC2
|
|
arc: H00R0000 N1_V02S0601
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: V00B0000 V02S0001
|
|
arc: V00B0100 V02S0101
|
|
arc: V00T0100 V02S0701
|
|
arc: CE0 V02N0201
|
|
arc: CE1 S1_V02N0201
|
|
arc: CE2 S1_V02N0601
|
|
arc: CE3 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0003 Q0
|
|
arc: E3_H06E0103 Q2
|
|
arc: E3_H06E0203 Q4
|
|
arc: E3_H06E0303 Q6
|
|
arc: M0 H02E0601
|
|
arc: M2 V00T0100
|
|
arc: M3 H02W0201
|
|
arc: M4 V00B0100
|
|
arc: M5 H00R0100
|
|
arc: M6 V00B0000
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N3_V06N0003 Q3
|
|
arc: N3_V06N0203 Q7
|
|
arc: N3_V06N0303 Q5
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R47C66:PLC2
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0401 H02W0401
|
|
arc: W1_H02W0201 V02S0201
|
|
|
|
.tile R47C67:PLC2
|
|
arc: W1_H02W0401 N3_V06S0203
|
|
|
|
.tile R47C71:PLC2
|
|
arc: N3_V06N0003 W3_H06E0003
|
|
arc: N3_V06N0103 W3_H06E0103
|
|
arc: N3_V06N0203 W3_H06E0203
|
|
arc: N3_V06N0303 W3_H06E0303
|
|
|
|
.tile R47C73:PLC2
|
|
arc: H00L0000 H02W0201
|
|
arc: H00L0100 V02S0301
|
|
arc: N1_V02N0201 H02W0201
|
|
arc: N1_V02N0401 N3_V06S0203
|
|
arc: V00B0000 V02S0001
|
|
arc: V00B0100 H02W0701
|
|
arc: V00T0100 V02S0501
|
|
arc: CE0 H00L0000
|
|
arc: CE1 H00L0000
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M0 V00B0000
|
|
arc: M1 H00L0100
|
|
arc: M2 V00B0100
|
|
arc: M6 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0301 Q1
|
|
arc: N3_V06N0003 Q0
|
|
arc: N3_V06N0103 Q2
|
|
arc: N3_V06N0303 Q6
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R47C74:PLC2
|
|
arc: N1_V01N0001 N3_V06S0003
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: N1_V02N0401 N1_V01S0000
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: V00T0000 V02S0401
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0701 V02S0701
|
|
arc: CE1 S1_V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E3_H06E0103 Q2
|
|
arc: M2 V00T0000
|
|
arc: MUXCLK1 CLK0
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R47C75:PLC2
|
|
arc: W1_H02W0301 N3_V06S0003
|
|
|
|
.tile R47C76:PLC2
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
|
|
.tile R47C78:PLC2
|
|
arc: H00L0000 V02S0201
|
|
arc: H00R0000 V02S0401
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
arc: N1_V02N0401 H02W0401
|
|
arc: V00B0000 V02S0001
|
|
arc: V00B0100 V02S0101
|
|
arc: V00T0100 V02S0501
|
|
arc: CE0 H02W0101
|
|
arc: CE1 H02W0101
|
|
arc: CE2 H02W0101
|
|
arc: CE3 V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q4
|
|
arc: M0 V00B0000
|
|
arc: M3 H00R0000
|
|
arc: M4 V00T0100
|
|
arc: M5 H00L0000
|
|
arc: M6 V00B0100
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q6
|
|
arc: N1_V01N0101 Q3
|
|
arc: N1_V02N0201 Q0
|
|
arc: N3_V06N0203 Q7
|
|
arc: N3_V06N0303 Q5
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX INV
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R47C79:PLC2
|
|
arc: N1_V02N0001 E1_H01W0000
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
arc: V01S0100 N3_V06S0303
|
|
arc: W1_H02W0101 V02N0101
|
|
arc: W1_H02W0401 N3_V06S0203
|
|
|
|
.tile R47C80:PLC2
|
|
arc: H01W0000 W3_H06E0103
|
|
|
|
.tile R48C65:PLC2
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
|
|
.tile R48C67:PLC2
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
|
|
.tile R48C69:PLC2
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
|
|
.tile R48C76:PLC2
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
|
|
.tile R48C78:PLC2
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
|
|
.tile R48C79:PLC2
|
|
arc: N1_V02N0101 N1_V01S0100
|
|
|
|
.tile R49C65:PLC2
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0601 N3_V06S0303
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
arc: V01S0100 N3_V06S0303
|
|
|
|
.tile R49C74:PLC2
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0301 N3_V06S0003
|
|
|
|
.tile R4C39:PLC2
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
|
|
.tile R50C48:PLC2
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile R50C63:PLC2
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
|
|
.tile R50C65:PLC2
|
|
arc: N1_V02N0701 N1_V01S0100
|
|
|
|
.tile R50C66:PLC2
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile R50C69:PLC2
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
|
|
.tile R50C75:PLC2
|
|
arc: N3_V06N0003 S3_V06N0303
|
|
|
|
.tile R50C78:PLC2
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
|
|
.tile R50C87:PLC2
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
|
|
.tile R52C39:PLC2
|
|
arc: N3_V06N0303 S3_V06N0303
|
|
|
|
.tile R56C48:PLC2
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
|
|
.tile R56C63:PLC2
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
|
|
.tile R56C66:PLC2
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
|
|
.tile R56C69:PLC2
|
|
arc: N3_V06N0103 S3_V06N0103
|
|
|
|
.tile R56C75:PLC2
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile R56C78:PLC2
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
|
|
.tile R56C87:PLC2
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
|
|
.tile R62C18:PLC2
|
|
arc: S3_V06S0203 E3_H06W0203
|
|
|
|
.tile R62C24:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R62C30:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R62C36:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R62C42:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R62C48:PLC2
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R62C54:PLC2
|
|
arc: E3_H06E0003 F3
|
|
arc: F3 F3_SLICE
|
|
arc: W3_H06W0003 F3
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
|
|
.tile R62C60:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R62C63:PLC2
|
|
arc: N3_V06N0103 H06E0103
|
|
|
|
.tile R62C66:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
arc: N3_V06N0103 W3_H06E0103
|
|
|
|
.tile R62C69:PLC2
|
|
arc: N3_V06N0103 H06E0103
|
|
|
|
.tile R62C72:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R62C75:PLC2
|
|
arc: N3_V06N0203 H06E0203
|
|
|
|
.tile R62C78:PLC2
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
arc: N3_V06N0203 W3_H06E0203
|
|
|
|
.tile R62C84:PLC2
|
|
arc: E1_H02E0501 W3_H06E0303
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R62C86:PLC2
|
|
arc: E3_H06E0303 W1_H02E0501
|
|
|
|
.tile R62C87:PLC2
|
|
arc: N3_V06N0003 H06E0003
|
|
|
|
.tile R64C39:PLC2
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile R68C16:PLC2
|
|
arc: S1_V02S0701 E1_H02W0701
|
|
|
|
.tile R68C18:PLC2
|
|
arc: W1_H02W0701 N3_V06S0203
|
|
|
|
.tile R7C65:PLC2
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
|
|
.tile R7C74:PLC2
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
|
|
.tile R7C75:PLC2
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
|
|
.tile R7C77:PLC2
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
|
|
.tile R7C78:PLC2
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
|
|
.tile R7C80:PLC2
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
|
|
.tile R7C83:PLC2
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile R7C86:PLC2
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile R8C48:PLC2
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
|
|
.tile R8C63:PLC2
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile R8C66:PLC2
|
|
arc: N3_V06N0303 S3_V06N0203
|
|
|
|
.tile TAP_R21C78:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R23C78:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R24C78:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R25C78:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R26C78:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R27C78:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R28C78:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R29C78:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R30C78:TAP_DRIVE
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R31C78:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R32C78:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R33C78:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R35C78:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R36C78:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R37C78:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R38C78:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R39C78:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R41C78:TAP_DRIVE
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R43C78:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R44C78:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R45C78:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R47C78:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
arc: R_HPBX0000 G_VPTX0000
|
|
|
|
.tile_group MIB_R22C64:MIB_DSP4 MIB_R22C64:MIB2_DSP4 MIB_R22C65:MIB_DSP5 MIB_R22C65:MIB2_DSP5 MIB_R22C66:MIB_DSP6 MIB_R22C66:MIB2_DSP6 MIB_R22C67:MIB_DSP7 MIB_R22C67:MIB2_DSP7 MIB_R22C68:MIB_DSP8 MIB_R22C68:MIB2_DSP8
|
|
enum: MULT18_5.REG_INPUTA_CLK NONE
|
|
enum: MULT18_5.REG_INPUTA_CE CE0
|
|
enum: MULT18_5.REG_INPUTA_RST RST0
|
|
enum: MULT18_5.REG_INPUTB_CLK NONE
|
|
enum: MULT18_5.REG_INPUTB_CE CE0
|
|
enum: MULT18_5.REG_INPUTB_RST RST0
|
|
enum: MULT18_5.REG_INPUTC_CLK NONE
|
|
enum: MULT18_5.REG_PIPELINE_CLK NONE
|
|
enum: MULT18_5.REG_PIPELINE_CE CE0
|
|
enum: MULT18_5.REG_PIPELINE_RST RST0
|
|
enum: MULT18_5.REG_OUTPUT_CLK NONE
|
|
enum: MULT18_5.CLK0_DIV ENABLED
|
|
enum: MULT18_5.CLK1_DIV ENABLED
|
|
enum: MULT18_5.CLK2_DIV ENABLED
|
|
enum: MULT18_5.CLK3_DIV ENABLED
|
|
enum: MULT18_5.GSR ENABLED
|
|
enum: MULT18_5.SOURCEB_MODE B_SHIFT
|
|
enum: MULT18_5.RESETMODE SYNC
|
|
enum: MULT18_5.MODE MULT18X18D
|
|
enum: MULT18_5.CIBOUT_BYP ON
|
|
enum: DSP_RIGHT.CIBOUT ON
|
|
enum: MULT18_5.CLK0MUX CLK0
|
|
enum: MULT18_5.CLK1MUX CLK1
|
|
enum: MULT18_5.CLK2MUX CLK2
|
|
enum: MULT18_5.CLK3MUX CLK3
|
|
enum: MULT18_5.CE0MUX CE0
|
|
enum: MULT18_5.CE1MUX CE1
|
|
enum: MULT18_5.CE2MUX CE2
|
|
enum: MULT18_5.CE3MUX CE3
|
|
enum: MULT18_5.RST0MUX RST0
|
|
enum: MULT18_5.RST1MUX RST1
|
|
enum: MULT18_5.RST2MUX RST2
|
|
enum: MULT18_5.RST3MUX RST3
|
|
|
|
.tile_group MIB_R22C78:MIB_DSP0 MIB_R22C78:MIB2_DSP0 MIB_R22C79:MIB_DSP1 MIB_R22C79:MIB2_DSP1 MIB_R22C80:MIB_DSP2 MIB_R22C80:MIB2_DSP2 MIB_R22C81:MIB_DSP3 MIB_R22C81:MIB2_DSP3 MIB_R22C82:MIB_DSP4 MIB_R22C82:MIB2_DSP4
|
|
enum: MULT18_0.REG_INPUTA_CLK NONE
|
|
enum: MULT18_0.REG_INPUTA_CE CE0
|
|
enum: MULT18_0.REG_INPUTA_RST RST0
|
|
enum: MULT18_0.REG_INPUTB_CLK NONE
|
|
enum: MULT18_0.REG_INPUTB_CE CE0
|
|
enum: MULT18_0.REG_INPUTB_RST RST0
|
|
enum: MULT18_0.REG_INPUTC_CLK NONE
|
|
enum: MULT18_0.REG_PIPELINE_CLK NONE
|
|
enum: MULT18_0.REG_PIPELINE_CE CE0
|
|
enum: MULT18_0.REG_PIPELINE_RST RST0
|
|
enum: MULT18_0.REG_OUTPUT_CLK NONE
|
|
enum: MULT18_0.REG_OUTPUT_RST RST0
|
|
enum: MULT18_0.CLK0_DIV ENABLED
|
|
enum: MULT18_0.CLK1_DIV ENABLED
|
|
enum: MULT18_0.CLK2_DIV ENABLED
|
|
enum: MULT18_0.CLK3_DIV ENABLED
|
|
enum: MULT18_0.GSR ENABLED
|
|
enum: MULT18_0.SOURCEB_MODE B_SHIFT
|
|
enum: MULT18_0.RESETMODE SYNC
|
|
enum: MULT18_0.MODE MULT18X18D
|
|
enum: MULT18_0.CIBOUT_BYP ON
|
|
enum: DSP_LEFT.CIBOUT ON
|
|
enum: MULT18_0.CLK0MUX CLK0
|
|
enum: MULT18_0.CLK1MUX CLK1
|
|
enum: MULT18_0.CLK2MUX CLK2
|
|
enum: MULT18_0.CLK3MUX CLK3
|
|
enum: MULT18_0.CE0MUX CE0
|
|
enum: MULT18_0.CE1MUX CE1
|
|
enum: MULT18_0.CE2MUX CE2
|
|
enum: MULT18_0.CE3MUX CE3
|
|
enum: MULT18_0.RST0MUX RST0
|
|
enum: MULT18_0.RST1MUX RST1
|
|
enum: MULT18_0.RST2MUX RST2
|
|
enum: MULT18_0.RST3MUX RST3
|
|
|
|
.tile_group MIB_R22C73:MIB_DSP4 MIB_R22C73:MIB2_DSP4 MIB_R22C74:MIB_DSP5 MIB_R22C74:MIB2_DSP5 MIB_R22C75:MIB_DSP6 MIB_R22C75:MIB2_DSP6 MIB_R22C76:MIB_DSP7 MIB_R22C76:MIB2_DSP7 MIB_R22C77:MIB_DSP8 MIB_R22C77:MIB2_DSP8
|
|
enum: MULT18_4.REG_INPUTA_CLK NONE
|
|
enum: MULT18_4.REG_INPUTA_CE CE0
|
|
enum: MULT18_4.REG_INPUTA_RST RST0
|
|
enum: MULT18_4.REG_INPUTB_CLK NONE
|
|
enum: MULT18_4.REG_INPUTB_CE CE0
|
|
enum: MULT18_4.REG_INPUTB_RST RST0
|
|
enum: MULT18_4.REG_INPUTC_CLK NONE
|
|
enum: MULT18_4.REG_PIPELINE_CLK NONE
|
|
enum: MULT18_4.REG_PIPELINE_CE CE0
|
|
enum: MULT18_4.REG_PIPELINE_RST RST0
|
|
enum: MULT18_4.REG_OUTPUT_CLK NONE
|
|
enum: MULT18_4.REG_OUTPUT_RST RST0
|
|
enum: MULT18_4.CLK0_DIV ENABLED
|
|
enum: MULT18_4.CLK1_DIV ENABLED
|
|
enum: MULT18_4.CLK2_DIV ENABLED
|
|
enum: MULT18_4.CLK3_DIV ENABLED
|
|
enum: MULT18_4.GSR ENABLED
|
|
enum: MULT18_4.SOURCEB_MODE B_SHIFT
|
|
enum: MULT18_4.RESETMODE SYNC
|
|
enum: MULT18_4.MODE MULT18X18D
|
|
enum: MULT18_4.CIBOUT_BYP ON
|
|
enum: DSP_RIGHT.CIBOUT ON
|
|
enum: MULT18_4.CLK0MUX CLK0
|
|
enum: MULT18_4.CLK1MUX CLK1
|
|
enum: MULT18_4.CLK2MUX CLK2
|
|
enum: MULT18_4.CLK3MUX CLK3
|
|
enum: MULT18_4.CE0MUX CE0
|
|
enum: MULT18_4.CE1MUX CE1
|
|
enum: MULT18_4.CE2MUX CE2
|
|
enum: MULT18_4.CE3MUX CE3
|
|
enum: MULT18_4.RST0MUX RST0
|
|
enum: MULT18_4.RST1MUX RST1
|
|
enum: MULT18_4.RST2MUX RST2
|
|
enum: MULT18_4.RST3MUX RST3
|
|
|
|
.tile_group MIB_R46C64:MIB_DSP4 MIB_R46C64:MIB2_DSP4 MIB_R46C65:MIB_DSP5 MIB_R46C65:MIB2_DSP5 MIB_R46C66:MIB_DSP6 MIB_R46C66:MIB2_DSP6 MIB_R46C67:MIB_DSP7 MIB_R46C67:MIB2_DSP7 MIB_R46C68:MIB_DSP8 MIB_R46C68:MIB2_DSP8
|
|
enum: MULT18_5.REG_INPUTA_CLK NONE
|
|
enum: MULT18_5.REG_INPUTA_CE CE0
|
|
enum: MULT18_5.REG_INPUTA_RST RST0
|
|
enum: MULT18_5.REG_INPUTB_CLK NONE
|
|
enum: MULT18_5.REG_INPUTB_CE CE0
|
|
enum: MULT18_5.REG_INPUTB_RST RST0
|
|
enum: MULT18_5.REG_INPUTC_CLK NONE
|
|
enum: MULT18_5.REG_PIPELINE_CLK NONE
|
|
enum: MULT18_5.REG_PIPELINE_CE CE0
|
|
enum: MULT18_5.REG_PIPELINE_RST RST0
|
|
enum: MULT18_5.REG_OUTPUT_CLK NONE
|
|
enum: MULT18_5.CLK0_DIV ENABLED
|
|
enum: MULT18_5.CLK1_DIV ENABLED
|
|
enum: MULT18_5.CLK2_DIV ENABLED
|
|
enum: MULT18_5.CLK3_DIV ENABLED
|
|
enum: MULT18_5.GSR ENABLED
|
|
enum: MULT18_5.SOURCEB_MODE B_SHIFT
|
|
enum: MULT18_5.RESETMODE SYNC
|
|
enum: MULT18_5.MODE MULT18X18D
|
|
enum: MULT18_5.CIBOUT_BYP ON
|
|
enum: DSP_RIGHT.CIBOUT ON
|
|
enum: MULT18_5.CLK0MUX CLK0
|
|
enum: MULT18_5.CLK1MUX CLK1
|
|
enum: MULT18_5.CLK2MUX CLK2
|
|
enum: MULT18_5.CLK3MUX CLK3
|
|
enum: MULT18_5.CE0MUX CE0
|
|
enum: MULT18_5.CE1MUX CE1
|
|
enum: MULT18_5.CE2MUX CE2
|
|
enum: MULT18_5.CE3MUX CE3
|
|
enum: MULT18_5.RST0MUX RST0
|
|
enum: MULT18_5.RST1MUX RST1
|
|
enum: MULT18_5.RST2MUX RST2
|
|
enum: MULT18_5.RST3MUX RST3
|
|
|
|
.tile_group MIB_R22C73:MIB_DSP4 MIB_R22C73:MIB2_DSP4 MIB_R22C74:MIB_DSP5 MIB_R22C74:MIB2_DSP5 MIB_R22C75:MIB_DSP6 MIB_R22C75:MIB2_DSP6 MIB_R22C76:MIB_DSP7 MIB_R22C76:MIB2_DSP7 MIB_R22C77:MIB_DSP8 MIB_R22C77:MIB2_DSP8
|
|
enum: MULT18_5.REG_INPUTA_CLK NONE
|
|
enum: MULT18_5.REG_INPUTA_CE CE0
|
|
enum: MULT18_5.REG_INPUTA_RST RST0
|
|
enum: MULT18_5.REG_INPUTB_CLK NONE
|
|
enum: MULT18_5.REG_INPUTB_CE CE0
|
|
enum: MULT18_5.REG_INPUTB_RST RST0
|
|
enum: MULT18_5.REG_INPUTC_CLK NONE
|
|
enum: MULT18_5.REG_PIPELINE_CLK NONE
|
|
enum: MULT18_5.REG_PIPELINE_CE CE0
|
|
enum: MULT18_5.REG_PIPELINE_RST RST0
|
|
enum: MULT18_5.REG_OUTPUT_CLK NONE
|
|
enum: MULT18_5.CLK0_DIV ENABLED
|
|
enum: MULT18_5.CLK1_DIV ENABLED
|
|
enum: MULT18_5.CLK2_DIV ENABLED
|
|
enum: MULT18_5.CLK3_DIV ENABLED
|
|
enum: MULT18_5.GSR ENABLED
|
|
enum: MULT18_5.SOURCEB_MODE B_SHIFT
|
|
enum: MULT18_5.RESETMODE SYNC
|
|
enum: MULT18_5.MODE MULT18X18D
|
|
enum: MULT18_5.CIBOUT_BYP ON
|
|
enum: DSP_RIGHT.CIBOUT ON
|
|
enum: MULT18_5.CLK0MUX CLK0
|
|
enum: MULT18_5.CLK1MUX CLK1
|
|
enum: MULT18_5.CLK2MUX CLK2
|
|
enum: MULT18_5.CLK3MUX CLK3
|
|
enum: MULT18_5.CE0MUX CE0
|
|
enum: MULT18_5.CE1MUX CE1
|
|
enum: MULT18_5.CE2MUX CE2
|
|
enum: MULT18_5.CE3MUX CE3
|
|
enum: MULT18_5.RST0MUX RST0
|
|
enum: MULT18_5.RST1MUX RST1
|
|
enum: MULT18_5.RST2MUX RST2
|
|
enum: MULT18_5.RST3MUX RST3
|
|
|
|
.tile_group MIB_R46C73:MIB_DSP4 MIB_R46C73:MIB2_DSP4 MIB_R46C74:MIB_DSP5 MIB_R46C74:MIB2_DSP5 MIB_R46C75:MIB_DSP6 MIB_R46C75:MIB2_DSP6 MIB_R46C76:MIB_DSP7 MIB_R46C76:MIB2_DSP7 MIB_R46C77:MIB_DSP8 MIB_R46C77:MIB2_DSP8
|
|
enum: MULT18_4.REG_INPUTA_CLK NONE
|
|
enum: MULT18_4.REG_INPUTA_CE CE0
|
|
enum: MULT18_4.REG_INPUTA_RST RST0
|
|
enum: MULT18_4.REG_INPUTB_CLK NONE
|
|
enum: MULT18_4.REG_INPUTB_CE CE0
|
|
enum: MULT18_4.REG_INPUTB_RST RST0
|
|
enum: MULT18_4.REG_INPUTC_CLK NONE
|
|
enum: MULT18_4.REG_PIPELINE_CLK NONE
|
|
enum: MULT18_4.REG_PIPELINE_CE CE0
|
|
enum: MULT18_4.REG_PIPELINE_RST RST0
|
|
enum: MULT18_4.REG_OUTPUT_CLK NONE
|
|
enum: MULT18_4.REG_OUTPUT_RST RST0
|
|
enum: MULT18_4.CLK0_DIV ENABLED
|
|
enum: MULT18_4.CLK1_DIV ENABLED
|
|
enum: MULT18_4.CLK2_DIV ENABLED
|
|
enum: MULT18_4.CLK3_DIV ENABLED
|
|
enum: MULT18_4.GSR ENABLED
|
|
enum: MULT18_4.SOURCEB_MODE B_SHIFT
|
|
enum: MULT18_4.RESETMODE SYNC
|
|
enum: MULT18_4.MODE MULT18X18D
|
|
enum: MULT18_4.CIBOUT_BYP ON
|
|
enum: DSP_RIGHT.CIBOUT ON
|
|
enum: MULT18_4.CLK0MUX CLK0
|
|
enum: MULT18_4.CLK1MUX CLK1
|
|
enum: MULT18_4.CLK2MUX CLK2
|
|
enum: MULT18_4.CLK3MUX CLK3
|
|
enum: MULT18_4.CE0MUX CE0
|
|
enum: MULT18_4.CE1MUX CE1
|
|
enum: MULT18_4.CE2MUX CE2
|
|
enum: MULT18_4.CE3MUX CE3
|
|
enum: MULT18_4.RST0MUX RST0
|
|
enum: MULT18_4.RST1MUX RST1
|
|
enum: MULT18_4.RST2MUX RST2
|
|
enum: MULT18_4.RST3MUX RST3
|
|
|
|
.tile_group MIB_R46C73:MIB_DSP4 MIB_R46C73:MIB2_DSP4 MIB_R46C74:MIB_DSP5 MIB_R46C74:MIB2_DSP5 MIB_R46C75:MIB_DSP6 MIB_R46C75:MIB2_DSP6 MIB_R46C76:MIB_DSP7 MIB_R46C76:MIB2_DSP7 MIB_R46C77:MIB_DSP8 MIB_R46C77:MIB2_DSP8
|
|
enum: MULT18_5.REG_INPUTA_CLK NONE
|
|
enum: MULT18_5.REG_INPUTA_CE CE0
|
|
enum: MULT18_5.REG_INPUTA_RST RST0
|
|
enum: MULT18_5.REG_INPUTB_CLK NONE
|
|
enum: MULT18_5.REG_INPUTB_CE CE0
|
|
enum: MULT18_5.REG_INPUTB_RST RST0
|
|
enum: MULT18_5.REG_INPUTC_CLK NONE
|
|
enum: MULT18_5.REG_PIPELINE_CLK NONE
|
|
enum: MULT18_5.REG_PIPELINE_CE CE0
|
|
enum: MULT18_5.REG_PIPELINE_RST RST0
|
|
enum: MULT18_5.REG_OUTPUT_CLK NONE
|
|
enum: MULT18_5.CLK0_DIV ENABLED
|
|
enum: MULT18_5.CLK1_DIV ENABLED
|
|
enum: MULT18_5.CLK2_DIV ENABLED
|
|
enum: MULT18_5.CLK3_DIV ENABLED
|
|
enum: MULT18_5.GSR ENABLED
|
|
enum: MULT18_5.SOURCEB_MODE B_SHIFT
|
|
enum: MULT18_5.RESETMODE SYNC
|
|
enum: MULT18_5.MODE MULT18X18D
|
|
enum: MULT18_5.CIBOUT_BYP ON
|
|
enum: DSP_RIGHT.CIBOUT ON
|
|
enum: MULT18_5.CLK0MUX CLK0
|
|
enum: MULT18_5.CLK1MUX CLK1
|
|
enum: MULT18_5.CLK2MUX CLK2
|
|
enum: MULT18_5.CLK3MUX CLK3
|
|
enum: MULT18_5.CE0MUX CE0
|
|
enum: MULT18_5.CE1MUX CE1
|
|
enum: MULT18_5.CE2MUX CE2
|
|
enum: MULT18_5.CE3MUX CE3
|
|
enum: MULT18_5.RST0MUX RST0
|
|
enum: MULT18_5.RST1MUX RST1
|
|
enum: MULT18_5.RST2MUX RST2
|
|
enum: MULT18_5.RST3MUX RST3
|
|
|
|
.tile_group MIB_R46C78:MIB_DSP0 MIB_R46C78:MIB2_DSP0 MIB_R46C79:MIB_DSP1 MIB_R46C79:MIB2_DSP1 MIB_R46C80:MIB_DSP2 MIB_R46C80:MIB2_DSP2 MIB_R46C81:MIB_DSP3 MIB_R46C81:MIB2_DSP3 MIB_R46C82:MIB_DSP4 MIB_R46C82:MIB2_DSP4
|
|
enum: MULT18_0.REG_INPUTA_CLK NONE
|
|
enum: MULT18_0.REG_INPUTA_CE CE0
|
|
enum: MULT18_0.REG_INPUTA_RST RST0
|
|
enum: MULT18_0.REG_INPUTB_CLK NONE
|
|
enum: MULT18_0.REG_INPUTB_CE CE0
|
|
enum: MULT18_0.REG_INPUTB_RST RST0
|
|
enum: MULT18_0.REG_INPUTC_CLK NONE
|
|
enum: MULT18_0.REG_PIPELINE_CLK NONE
|
|
enum: MULT18_0.REG_PIPELINE_CE CE0
|
|
enum: MULT18_0.REG_PIPELINE_RST RST0
|
|
enum: MULT18_0.REG_OUTPUT_CLK NONE
|
|
enum: MULT18_0.REG_OUTPUT_RST RST0
|
|
enum: MULT18_0.CLK0_DIV ENABLED
|
|
enum: MULT18_0.CLK1_DIV ENABLED
|
|
enum: MULT18_0.CLK2_DIV ENABLED
|
|
enum: MULT18_0.CLK3_DIV ENABLED
|
|
enum: MULT18_0.GSR ENABLED
|
|
enum: MULT18_0.SOURCEB_MODE B_SHIFT
|
|
enum: MULT18_0.RESETMODE SYNC
|
|
enum: MULT18_0.MODE MULT18X18D
|
|
enum: MULT18_0.CIBOUT_BYP ON
|
|
enum: DSP_LEFT.CIBOUT ON
|
|
enum: MULT18_0.CLK0MUX CLK0
|
|
enum: MULT18_0.CLK1MUX CLK1
|
|
enum: MULT18_0.CLK2MUX CLK2
|
|
enum: MULT18_0.CLK3MUX CLK3
|
|
enum: MULT18_0.CE0MUX CE0
|
|
enum: MULT18_0.CE1MUX CE1
|
|
enum: MULT18_0.CE2MUX CE2
|
|
enum: MULT18_0.CE3MUX CE3
|
|
enum: MULT18_0.RST0MUX RST0
|
|
enum: MULT18_0.RST1MUX RST1
|
|
enum: MULT18_0.RST2MUX RST2
|
|
enum: MULT18_0.RST3MUX RST3
|
|
|