micheleandClaude Sonnet 5
3026dcd997
Implements M2 of the V2 roadmap: neural_processor_array.v instantiates
N_PROCESSORS independent neural_processor (M1) units, each with its
own dedicated point-to-point job/operand/result interface -- no shared
bus or mux at this level (arbitration is explicitly the Neural
Director's job, M5).
Verified with Verilator (tb_neural_processor_array.v, N_PROCESSORS=4):
7/7 tests pass, including a same-cycle 4-way concurrent launch with
different tile counts and a staggered-start test where a
later-launched, shorter job completes before an earlier-launched,
longer one -- confirming genuine independent concurrent execution
(§18/§34: a blocked/busy processor must not block the others).
Real resource/timing sweep for N_PROCESSORS in {1,2,4,8} (Yosys +
nextpnr-ecp5, real place&route): Fmax stays above the 80MHz target
throughout (159.11 -> 134.70 MHz), but MULT18X18D usage scales
linearly and reaches 88% of the LFE5U-45F's 72 DSPs at N=8 while
LUT/FF stay under 6% -- DSP, not LUT/FF/routing, is the first hard
ceiling on N_PROCESSORS at P_IN=8 (decisions.log DEC-0005). Measured
via a dedicated synthesis-only timing harness after the array's wide
per-processor buses were found to exhaust the device's TRELLIS_IO pin
budget as a bare top-level module beyond N=1 (errors.log ERR-0005) --
not a logic limit, an artifact of testing the array in isolation
before the Memory Manager/Director (M4/M5) exist to consume those
ports on-chip.
Full log trail (development/experiments/errors/decisions/simulation/
synthesis/timing/benchmark.log) in hardware/v2/logs/ per the project's
logging mandate.
Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
162 lines
8.6 KiB
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162 lines
8.6 KiB
Plaintext
# V2 experiments log -- REGISTRO PRINCIPALE (docs/v2-description.md §25).
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# Un EXP-XXXX per ogni esperimento end-to-end (config -> sim/synth/timing ->
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# risultato). ID mai riutilizzati, anche per i FAIL. Ogni EXP rimanda a
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# reports/experiments/EXP-XXXX/ (experiment.yaml, simulation.log,
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# synthesis.log, timing.log, results.txt, notes.md).
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#
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# Nessun esperimento ancora eseguito.
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EXP-0001
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timestamp: 2026-09-05T12:03:12Z
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git_commit: 07a48e401f56d395f9d1a6e22f1b5ebc6b598e64 (+ uncommitted M1 work)
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session: v2-M1-neural-processor
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module: hardware/v2/rtl/neural_processor.v
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configuration: DATA_WIDTH=8, P_IN=8, ACC_WIDTH=32
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action: first M1 implementation -- 8-stage pipelined perceptron unit,
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bit-exact vs hardware/v1/rtl/neuron_parallel.v + mac8.v + mac_unit.v
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command (sim, Verilator): verilator --binary --timing -j 0 -Wno-fatal
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--top-module tb -o /tmp/vtb_np hardware/v1/rtl/neuron_parallel.v
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hardware/v1/rtl/mac8.v hardware/v1/rtl/mac_unit.v
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hardware/v2/rtl/neural_processor.v hardware/v2/sim/tb_neural_processor.v
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&& /tmp/vtb_np
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command (synth): yosys -p "synth_ecp5 -json
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hardware/v2/synthesis/neural_processor_p8/top.json -top neural_processor"
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hardware/v2/rtl/neural_processor.v
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command (timing): nextpnr-ecp5 --45k --package CABGA381 --speed 8
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--freq 80 --json hardware/v2/synthesis/neural_processor_p8/top.json
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--lpf-allow-unconstrained --textcfg .../top.config
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result:
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SIMULATED: 7/7 tests PASS, bit-exact vs V1 (functional +
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extreme-INT8 + back-to-back-tiles + 64-input/8-tile coverage).
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SYNTHESIZED: 0 CHECK problems, 8 MULT18X18D, 533 TRELLIS_FF,
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96 CCU2C, 55 LUT4 (36 benign integer-loop-variable warnings, see
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hardware/v2/logs/synthesis.log).
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POST-P&R: Fmax = 183.12 MHz, PASS at 80MHz target (real
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nextpnr-ecp5 measurement, hardware/v2/synthesis/neural_processor_p8/
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nextpnr.log). Compare V1 isolated PARALLEL=8: 61.71 MHz
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(hardware/v1/synthesis/p8/) -- ~3x higher Fmax for the pipelined
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single-processor datapath alone (not yet a system-level
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comparison -- no Memory Manager/Director/multi-processor overhead
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included at this milestone).
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errors: ERR-0001, ERR-0002, ERR-0003 (see errors.log) encountered and
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resolved/worked around during development.
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decision: see decisions.log DEC-0002, DEC-0003, DEC-0004.
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next_action: EXP-0002 (ACC_WIDTH=24 comparison), then M2 (Processor
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Array, N_PROCESSORS sweep).
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EXP-0002
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timestamp: 2026-09-05T12:03:12Z
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git_commit: 07a48e401f56d395f9d1a6e22f1b5ebc6b598e64 (+ uncommitted M1 work)
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session: v2-M1-neural-processor
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module: hardware/v2/rtl/neural_processor.v
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configuration: DATA_WIDTH=8, P_IN=8, ACC_WIDTH=24 (vs EXP-0001's
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ACC_WIDTH=32 baseline) -- requested explicitly by the user as a test
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variant ("come test nel perceptrone crea una versione con
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accumulatori a 24 bit anziche' a 32 bit").
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reason: ACC_WIDTH is already fully parametric throughout
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neural_processor.v (no code duplication needed); 24 bits is a real,
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non-degenerate choice -- worst-case realistic accumulation (e.g. 256
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INT8 inputs all at +-127/+-128) needs at most 23 signed bits
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(256 * 128 = 32768, |value| <= 2^22 for the largest single-tile-
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chain sums this project's configs reach), so 24 bits carries a
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legitimate 1-bit margin, not an arbitrary/unsafe truncation.
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command (sim, Verilator): same as EXP-0001 with a copy of
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tb_neural_processor.v with ACC_WIDTH localparam changed to 24 (V1's
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own neuron_parallel instantiated at ACC_WIDTH=24 too, for a true
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bit-exact comparison at the SAME width -- V1's ACC_WIDTH is also a
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module parameter, no V1 modification needed).
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command (synth): yosys -p "read_verilog
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hardware/v2/rtl/neural_processor.v; chparam -set ACC_WIDTH 24
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neural_processor; synth_ecp5 -json
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hardware/v2/synthesis/neural_processor_p8_acc24/top.json -top
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neural_processor"
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command (timing): nextpnr-ecp5, same flags as EXP-0001, json from
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the ACC_WIDTH=24 build.
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result:
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SIMULATED: 7/7 tests PASS, bit-exact vs V1 at ACC_WIDTH=24 (no
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overflow in any test vector, as expected from the margin analysis
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above).
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SYNTHESIZED: 0 CHECK problems, 8 MULT18X18D (unchanged, multiplier
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width is DATA_WIDTH-driven not ACC_WIDTH-driven), 509 TRELLIS_FF
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(was 533 at ACC_WIDTH=32, -24 FF as expected for 8 fewer
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accumulator bits carried through ~3 pipeline-stage copies),
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88 CCU2C (was 96), 49 LUT4 (was 55).
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POST-P&R: Fmax = 176.21 MHz (was 183.12 MHz at ACC_WIDTH=32) --
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REAL measurement, both from nextpnr-ecp5. The 24-bit build is
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~4% SLOWER despite fewer resources -- almost certainly placement
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noise (consistent with this project's established finding,
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hardware/v1/docs/WORKLOG.md "Timing closure", that seed-to-seed
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placement variance on this device dominates small logic-width
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differences), NOT attributed to a real architectural effect
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without a seed sweep to confirm. Reported as-measured, not
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overinterpreted -- see hardware/v2/logs/benchmark.log.
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errors: none.
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decision: ACC_WIDTH=32 remains the M1 default (matches V1 exactly for
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ongoing bit-exact comparisons); ACC_WIDTH=24 confirmed as a viable,
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correctly-functioning, slightly-smaller alternative, not adopted as
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default without a proper seed sweep (out of scope for this single
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comparison run).
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next_action: revisit ACC_WIDTH choice during M10 (Optimization) with a
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real seed sweep, not before.
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EXP-0003
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timestamp: 2026-09-05T14:30:00Z
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git_commit: dc0b331 (+ uncommitted M2 work)
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session: v2-M2-processor-array
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module: hardware/v2/rtl/neural_processor_array.v
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configuration: N_PROCESSORS in {1,2,4,8}, P_IN=8, ACC_WIDTH=32 each
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action: M2 -- functional array + real N_PROCESSORS resource/timing sweep
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command (sim, Verilator): verilator --binary --timing -j 0 -Wno-fatal
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--top-module tb -o /tmp/vtb_array hardware/v2/rtl/neural_processor.v
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hardware/v2/rtl/neural_processor_array.v
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hardware/v2/sim/tb_neural_processor_array.v && /tmp/vtb_array
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command (synth/timing): see hardware/v2/synthesis/harness_n{1,2,4,8}/
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(yosys.log, nextpnr.log) -- synthesized via
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hardware/v2/synthesis/harness_neural_processor_array.v, a
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synthesis-only timing harness (see its own header comment and
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errors.log ERR-0005 for why the array cannot be synthesized as a
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bare top-level module beyond N_PROCESSORS=1 without it).
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result:
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SIMULATED (N_PROCESSORS=4, tb_neural_processor_array.v): 7/7 tests
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PASS -- single-processor sanity, 4 processors launched the SAME
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cycle with different tile counts (finish at different times,
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proving true concurrency), and a staggered-start test (processor 1
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launched mid-way through processor 0's 6-tile job, both complete
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correctly and independently, confirming §18/§34's "un processor
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bloccato non deve bloccare gli altri").
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SYNTHESIZED (resource scaling, harness): perfectly linear in
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N_PROCESSORS, confirming no unintended resource sharing:
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N=1: LUT=59 FF=409 MULT18X18D=8 CCU2C=96
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N=2: LUT=106 FF=786 MULT18X18D=16 CCU2C=192
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N=4: LUT=207 FF=1540 MULT18X18D=32 CCU2C=384
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N=8: LUT=374 FF=3048 MULT18X18D=64 CCU2C=768
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0 CHECK problems in every configuration.
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POST-P&R (real nextpnr-ecp5, --45k --package CABGA381 --speed 8
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--freq 80): Fmax PASS at 80MHz in every configuration:
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N=1: 159.11 MHz N=2: 149.59 MHz
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N=4: 151.01 MHz N=8: 134.70 MHz
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Fmax decreases gently with N (routing congestion), never close to
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failing the 80MHz target up to N=8.
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REAL RESOURCE CEILING FOUND (not assumed, measured via nextpnr's own
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device utilisation report): MULT18X18D usage is 22%/44%/88% of the
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LFE5U-45F's 72 total DSPs at N=2/4/8 respectively, while LUT4/FF
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usage stays under 6% even at N=8. **DSP (not LUT/FF/routing) is
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the first hard ceiling as N_PROCESSORS grows at P_IN=8** --
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N_PROCESSORS=9 would already exceed the device's 72 MULT18X18D
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budget at P_IN=8, before accounting for any multipliers the rest
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of a real system (Memory Manager, PSRAM path, etc.) might need.
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See decisions.log DEC-0005 and benchmark.log.
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errors: ERR-0005 (toplevel-pin-count synthesis artifact, worked around
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with the timing harness -- see errors.log); a first harness attempt
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fed every processor and every MAC lane identical LFSR-derived data,
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which Yosys correctly (from pure logic-equivalence) collapsed via
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CSE down to 1 processor's worth of multipliers regardless of N --
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fixed by giving each processor AND each of its P_IN MAC lanes a
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distinct bit-rotated data source, confirmed by the corrected,
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properly-linear MULT18X18D counts above.
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decision: see decisions.log DEC-0005 (DSP is the binding constraint,
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not LUT/FF -- informs how the N_PROCESSORS x P_IN trade-off should
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be explored going forward).
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next_action: M3 -- activation_buffer.v / weight_buffer.v /
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result_buffer.v.
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