micheleandClaude Sonnet 5
3026dcd997
Implements M2 of the V2 roadmap: neural_processor_array.v instantiates
N_PROCESSORS independent neural_processor (M1) units, each with its
own dedicated point-to-point job/operand/result interface -- no shared
bus or mux at this level (arbitration is explicitly the Neural
Director's job, M5).
Verified with Verilator (tb_neural_processor_array.v, N_PROCESSORS=4):
7/7 tests pass, including a same-cycle 4-way concurrent launch with
different tile counts and a staggered-start test where a
later-launched, shorter job completes before an earlier-launched,
longer one -- confirming genuine independent concurrent execution
(§18/§34: a blocked/busy processor must not block the others).
Real resource/timing sweep for N_PROCESSORS in {1,2,4,8} (Yosys +
nextpnr-ecp5, real place&route): Fmax stays above the 80MHz target
throughout (159.11 -> 134.70 MHz), but MULT18X18D usage scales
linearly and reaches 88% of the LFE5U-45F's 72 DSPs at N=8 while
LUT/FF stay under 6% -- DSP, not LUT/FF/routing, is the first hard
ceiling on N_PROCESSORS at P_IN=8 (decisions.log DEC-0005). Measured
via a dedicated synthesis-only timing harness after the array's wide
per-processor buses were found to exhaust the device's TRELLIS_IO pin
budget as a bare top-level module beyond N=1 (errors.log ERR-0005) --
not a logic limit, an artifact of testing the array in isolation
before the Memory Manager/Director (M4/M5) exist to consume those
ports on-chip.
Full log trail (development/experiments/errors/decisions/simulation/
synthesis/timing/benchmark.log) in hardware/v2/logs/ per the project's
logging mandate.
Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
30 lines
1.6 KiB
Plaintext
30 lines
1.6 KiB
Plaintext
# V2 synthesis log -- solo append, mai troncato/sovrascritto (vedi README.md)
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# Nessuna entry ancora -- popolato incrementalmente man mano che avanza lo sviluppo V2.
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[2026-09-05] EXP-0001 -- neural_processor (P_IN=8, ACC_WIDTH=32)
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LUT: 55 FF: 533 DSP(MULT18X18D): 8 BRAM: 0 CCU2C: 96
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CHECK: 0 problems. 36 warnings, all "multiple conflicting drivers for
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neural_processor.\gi" -- benign Yosys quirk for an `integer` used as
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a synthesizable for-loop index in stage 0's unrolled always block,
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not a real multi-driver conflict (cross-verified functionally
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correct on 2 independent simulators). Log: hardware/v2/synthesis/
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neural_processor_p8/yosys.log
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[2026-09-05] EXP-0002 -- neural_processor (P_IN=8, ACC_WIDTH=24)
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LUT: 49 FF: 509 DSP(MULT18X18D): 8 BRAM: 0 CCU2C: 88
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CHECK: 0 problems, same 36 benign warnings as EXP-0001.
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Log: hardware/v2/synthesis/neural_processor_p8_acc24/yosys.log
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[2026-09-05] EXP-0003 -- neural_processor_array via
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harness_neural_processor_array.v (synthesis-only wrapper, see
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errors.log ERR-0005), N_PROCESSORS in {1,2,4,8}, P_IN=8
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N=1: LUT=59 FF=409 MULT18X18D=8 CCU2C=96
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N=2: LUT=106 FF=786 MULT18X18D=16 CCU2C=192
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N=4: LUT=207 FF=1540 MULT18X18D=32 CCU2C=384
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N=8: LUT=374 FF=3048 MULT18X18D=64 CCU2C=768
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CHECK: 0 problems in all 4 configurations. Perfectly linear scaling in
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N confirms no unintended cross-processor resource sharing (a first,
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flawed harness attempt fed identical data to every processor/lane
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and Yosys silently deduplicated down to 1x regardless of N -- caught
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by checking for exactly this linearity before trusting the numbers).
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