michele ee708775c7 Revert "feat: integrate flash #1 (neural-network data) RTL into V2 top-level" ...

This reverts commit 59901a4905.

2026-09-07 19:02:44 +02:00

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constraints

Revert "feat: integrate flash #1 (neural-network data) RTL into V2 top-level"

2026-09-07 19:02:44 +02:00

docs

docs: datasheet addendum for two-flash programming architecture + FPGA_DATA_READY

2026-09-07 13:11:12 +02:00

logs

Revert "feat: integrate flash #1 (neural-network data) RTL into V2 top-level"

2026-09-07 19:02:44 +02:00

nms

Revert "feat: integrate flash #1 (neural-network data) RTL into V2 top-level"

2026-09-07 19:02:44 +02:00

reports

V2 final synthesis/P&R sign-off + LaTeX datasheet port (NOT SILICON READY)

2026-09-06 17:50:53 +02:00

rtl

Revert "feat: integrate flash #1 (neural-network data) RTL into V2 top-level"

2026-09-07 19:02:44 +02:00

sim

feat: SDRAM 8MB->64MB upgrade (AS4C32M16SB-7BIN) + N_SLOTS=8 support

2026-09-07 00:20:53 +02:00

synthesis

feat(v2): M7 Dataflow Core - full M1-M6 integration, wake-up loop closed end-to-end

2026-09-05 15:05:28 +02:00