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michele ee708775c7 Revert "feat: integrate flash #1 (neural-network data) RTL into V2 top-level" 
This reverts commit 59901a4905.
2026-09-07 19:02:44 +02:00
..
activation_buffer.v
feat(v2): M3 activation/weight/result buffers, real BRAM mapping
2026-09-05 14:19:11 +02:00
activation_cache.v
perf(v2): shared activation cache - further 1.66-2.00x real speedup (DEC-0016)
2026-09-05 20:59:14 +02:00
dataflow_core.v
perf(v2): shared activation cache - further 1.66-2.00x real speedup (DEC-0016)
2026-09-05 20:59:14 +02:00
dependency_manager.v
feat: two-flash programming architecture, FPGA_DATA_READY, real JTAG/config pinout
2026-09-07 12:46:00 +02:00
ecp5_pll_sys_clk.v
V2.1.0-dev: SPI host bridge + clock/reset architecture (NOT release-ready)
2026-09-06 14:35:14 +02:00
memory_manager.v
perf(v2): shared activation cache - further 1.66-2.00x real speedup (DEC-0016)
2026-09-05 20:59:14 +02:00
neural_director.v
feat: two-flash programming architecture, FPGA_DATA_READY, real JTAG/config pinout
2026-09-07 12:46:00 +02:00
neural_multiprocessor.v
perf(v2): shared activation cache - further 1.66-2.00x real speedup (DEC-0016)
2026-09-05 20:59:14 +02:00
neural_processor_array.v
feat(v2): M2 Neural Processor Array, N_PROCESSORS resource sweep
2026-09-05 14:15:11 +02:00
neural_processor.v
feat(v2): scaffold hardware/v1 frozen baseline + M1 Neural Processor
2026-09-05 14:06:53 +02:00
prefetch_engine.v
perf(v2): shared activation cache - further 1.66-2.00x real speedup (DEC-0016)
2026-09-05 20:59:14 +02:00
reset_sync.v
V2.1.0-dev: SPI host bridge + clock/reset architecture (NOT release-ready)
2026-09-06 14:35:14 +02:00
result_buffer.v
feat(v2): M3 activation/weight/result buffers, real BRAM mapping
2026-09-05 14:19:11 +02:00
slot_mem_arbiter_wide.v
feat: SDRAM 8MB->64MB upgrade (AS4C32M16SB-7BIN) + N_SLOTS=8 support
2026-09-07 00:20:53 +02:00
slot_mem_arbiter.v
feat: SDRAM 8MB->64MB upgrade (AS4C32M16SB-7BIN) + N_SLOTS=8 support
2026-09-07 00:20:53 +02:00
spi_host_bridge.v
Revert "feat: integrate flash #1 (neural-network data) RTL into V2 top-level"
2026-09-07 19:02:44 +02:00
weight_buffer.v
feat(v2): M3 activation/weight/result buffers, real BRAM mapping
2026-09-05 14:19:11 +02:00