micheleandClaude Sonnet 5
91bbbe2fe5
Final milestone of docs/v2-description.md's §33 roadmap, scoped exactly to its own mandate: optimize only on data already gathered in M1-M9, across the pipeline/P_IN/processor-count/scheduling/memory axes - no speculative new features. Three concrete, data-driven results: 1. N_SLOTS=8 (numero processor axis): real synthesis + nextpnr-ecp5 P&R for dataflow_core at N_SLOTS=8, extending M7's N_SLOTS=2/4 sweep to the real DSP ceiling DEC-0005 predicted. 92.63 MHz POST-P&R, PASS at 80MHz, DSP 64/72 (88.9%). DEC-0012 recommends N_SLOTS=8 as the practical ceiling for P_IN=8 on the LFE5U-45F-8BG381. 2. ACC_WIDTH 24 vs 32 (pipeline axis): a real 6-seed nextpnr-ecp5 placement sweep (reusing already-synthesized netlists, no new synthesis needed) resolves EXP-0002's single-seed inconclusiveness. ACC_WIDTH=24 wins on both mean Fmax (+6.2%, 180.71 vs 170.12 MHz) and seed-to-seed variance (~3.4x tighter), on top of its already-known resource advantage. DEC-0013 recommends ACC_WIDTH=24 as the new default. 3. Stall %/utilization (scheduling/memory axes): testbench-only cycle counters added to tb_neural_multiprocessor.v (no RTL touched) close DEC-0011's deferred measurement gap with real data - shared PSRAM port 81.7% utilized, slot 0 95.2%, slot 1 65.2%, no conclusive evidence of harmful fixed-priority starvation at this scale. The 10-milestone V2 roadmap (docs/v2-description.md §33) is now complete end-to-end: real Verilator simulation, real Yosys synthesis, real nextpnr-ecp5 place & route for every milestone, fully logged (EXP-0001..EXP-0013, DEC-0001..DEC-0013, ERR-0001..ERR-0008) with no invented results (§30) and V1 kept frozen and untouched throughout (§1/§34). Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
121 lines
6.4 KiB
Plaintext
121 lines
6.4 KiB
Plaintext
# V2 simulation log -- solo append, mai troncato/sovrascritto (vedi README.md)
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# Nessuna entry ancora -- popolato incrementalmente man mano che avanza lo sviluppo V2.
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[2026-09-05] EXP-0001/EXP-0002 -- hardware/v2/sim/tb_neural_processor.v
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test: 7 cases (16/32/8/8/8/8/64-input jobs; ACT_NONE + ACT_RELU;
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extreme INT8 saturation; back-to-back zero-idle-gap tiles)
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vectors: regular positive, mixed-sign cancellation, extreme INT8
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(-128,-127,-1,0,1,126,127,127 in one 8-lane tile), back-to-back
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jobs, 8-tile (64-input) job
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simulator: Verilator 5.050 (--binary --timing) -- see decisions.log
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DEC-0004 for why Icarus v13.0 is not trusted for this testbench
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cycles: not separately profiled at this milestone (throughput/stall
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cycle counting deferred to M9 per §22)
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PASS/FAIL: 7/7 PASS (ACC_WIDTH=32); 7/7 PASS (ACC_WIDTH=24, EXP-0002)
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bit-exact result: V1.y === V2.result_data for every case, both widths
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stall cycles / memory wait / utilization: N/A (no Memory Manager yet,
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M1 operands fed directly by testbench per the roadmap)
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[2026-09-05] EXP-0003 -- hardware/v2/sim/tb_neural_processor_array.v
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(N_PROCESSORS=4)
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test: 7 cases (single-processor sanity; 4-way same-cycle concurrent
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launch with different tile counts; staggered-start 2-processor test)
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simulator: Verilator 5.050 (--binary --timing)
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PASS/FAIL: 7/7 PASS
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bit-exact result: N/A at this milestone (hand-computed expected
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values, arithmetic itself already bit-exact-certified vs V1 at M1)
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concurrency: confirmed genuine -- in the staggered test, the
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later-launched, shorter job (processor 1) completes BEFORE the
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earlier-launched, longer job (processor 0), proving independent
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progress rather than serialization.
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[2026-09-05] EXP-0004 -- hardware/v2/sim/tb_buffers.v
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test: 10 cases across activation_buffer/weight_buffer/result_buffer
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vectors: extreme INT8 (-128, 127, -100, 100), regular values, full
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64-bit tile round-trip (weight_buffer), re-reads confirming earlier
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writes undisturbed
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simulator: Verilator 5.050 (--binary --timing)
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PASS/FAIL: 10/10 PASS
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[2026-09-05] EXP-0005 -- hardware/v2/sim/tb_memory_manager.v
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test: 3 end-to-end jobs (3-tile/saturating, 1-tile/non-saturating,
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5-tile/steady-state-swap), real V1 PSRAM backend chain (unmodified),
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real M1 neural_processor
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simulator: Verilator 5.050 (--binary --timing)
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PASS/FAIL: 3/3 PASS
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bit-exact result: PSRAM-read-back result byte matches hand-computed
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expectation in every case (independent oracle, not derived from the
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RTL under test)
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cycles: 446 (3 tiles), 166 (1 tile), 728 (5 tiles) -- real PSRAM
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latency dominates, not memory_manager's own control overhead
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[2026-09-05] EXP-0006 -- hardware/v2/sim/tb_neural_director.v
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test: 4 cases (3-jobs-2-slots first-free dispatch + queueing,
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backpressure fill/recover)
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simulator: Verilator 5.050 (--binary --timing)
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PASS/FAIL: 4/4 PASS
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[2026-09-05] EXP-0007 -- hardware/v2/sim/tb_dependency_manager.v
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test: 4 cases on a 4-node DAG (2 independent + 1 dual-dependency +
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1 single-dependency-shared-producer)
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simulator: Verilator 5.050 (--binary --timing)
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PASS/FAIL: 4/4 PASS
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[2026-09-05] EXP-0008 -- hardware/v2/sim/tb_dataflow_core.v
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test: full end-to-end M1-M6 integration through dataflow_core.v (M7),
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a 3-node DAG (node0/node1 independent, node2 depends on BOTH) run
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through the REAL dependency_manager -> neural_director -> N_SLOTS x
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(memory_manager + neural_processor) chain for the first time, each
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slot backed by its own independent behavioral byte memory
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simulator: Verilator 5.050 (--binary --timing)
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PASS/FAIL: 4/4 PASS -- node0=48, node1=8 (both real neural_processor
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computations via the full stack), node2=40 dispatched only after
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BOTH node0 and node1 genuinely completed (continuously polled every
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cycle up to completion, not just checked at the end) -- the
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dependency-manager-to-director wake-up loop closes correctly
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end-to-end with real hardware in between, not just in isolation
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(M6's own testbench already proved the wake-up logic alone)
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[2026-09-05] EXP-0009 -- hardware/v2/sim/tb_neural_multiprocessor.v
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test: same 3-node DAG as EXP-0008 (node0/node1 independent, node2
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depends on both), routed through neural_multiprocessor.v (M8): the
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REAL, UNMODIFIED V1 PSRAM backend chain (int8_memory_access ->
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memory_interface -> psram_controller -> psram_model) shared across
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N_SLOTS=2 genuinely concurrent memory_manager instances via the new
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slot_mem_arbiter.v -- node0 and node1 are registered back-to-back
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with no dependencies, so both dispatch to their slots essentially
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simultaneously and genuinely contend for the one real PSRAM port.
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simulator: Verilator 5.050 (--binary --timing)
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PASS/FAIL: 4/4 PASS after fixing a real dropped-request bug in the
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first arbiter draft (errors.log ERR-0008) -- node0=48, node1=8
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(concurrent, real PSRAM, real arbitration), node2=40 dispatched only
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after both genuinely completed. 444 cycles end-to-end (vs 20000-cycle
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watchdog timeout with the buggy first draft, where node1's request
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was silently dropped and its slot hung forever).
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regression: hardware/v2/sim/tb_memory_manager.v (M4) re-run unchanged
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(no M4 file touched) -- still 3/3 PASS, identical cycle counts
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(446/166/728), confirming slot_mem_arbiter.v is purely additive.
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[2026-09-05] EXP-0013 -- hardware/v2/sim/tb_neural_multiprocessor.v,
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M10 cycle-accounting instrumentation (closes decisions.log DEC-0011's
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deferred stall %/utilization gap with real data, testbench-only
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addition, no RTL touched)
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test: same EXP-0009 scenario (3-node DAG, N_SLOTS=2, real V1 PSRAM
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chain, real slot_mem_arbiter contention), instrumented with cycle
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counters (shared PSRAM port busy cycles via
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u_nmp.u_arbiter.owner!=0, each slot's memory_manager busy cycles via
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its own state!=MM_IDLE), measured from the first node registration
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to test completion.
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simulator: Verilator 5.050 (--binary --timing)
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PASS/FAIL: 4/4 PASS (unchanged from EXP-0009), plus real measured
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data: 684 total cycles measured; shared PSRAM port busy 559/684
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(81.7% utilization, 18.3% idle); slot 0 (memory_manager) busy
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651/684 (95.2%); slot 1 (memory_manager) busy 446/684 (65.2%).
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note: slot 0's higher utilization is at least partly explained by it
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serving TWO sequential jobs in this run (node0, then whichever slot
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frees first serves node2 -- likely slot 0, first-free/lowest-index)
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while slot 1 only ever serves node1 -- NOT conclusive evidence of
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harmful priority starvation on its own; see decisions.log DEC-0010's
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original fairness deferral, now informed by this real (if small)
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data point.
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