Final milestone of docs/v2-description.md's §33 roadmap, scoped
exactly to its own mandate: optimize only on data already gathered in
M1-M9, across the pipeline/P_IN/processor-count/scheduling/memory
axes - no speculative new features.
Three concrete, data-driven results:
1. N_SLOTS=8 (numero processor axis): real synthesis + nextpnr-ecp5
P&R for dataflow_core at N_SLOTS=8, extending M7's N_SLOTS=2/4
sweep to the real DSP ceiling DEC-0005 predicted. 92.63 MHz
POST-P&R, PASS at 80MHz, DSP 64/72 (88.9%). DEC-0012 recommends
N_SLOTS=8 as the practical ceiling for P_IN=8 on the
LFE5U-45F-8BG381.
2. ACC_WIDTH 24 vs 32 (pipeline axis): a real 6-seed nextpnr-ecp5
placement sweep (reusing already-synthesized netlists, no new
synthesis needed) resolves EXP-0002's single-seed
inconclusiveness. ACC_WIDTH=24 wins on both mean Fmax (+6.2%,
180.71 vs 170.12 MHz) and seed-to-seed variance (~3.4x tighter),
on top of its already-known resource advantage. DEC-0013
recommends ACC_WIDTH=24 as the new default.
3. Stall %/utilization (scheduling/memory axes): testbench-only cycle
counters added to tb_neural_multiprocessor.v (no RTL touched)
close DEC-0011's deferred measurement gap with real data - shared
PSRAM port 81.7% utilized, slot 0 95.2%, slot 1 65.2%, no
conclusive evidence of harmful fixed-priority starvation at this
scale.
The 10-milestone V2 roadmap (docs/v2-description.md §33) is now
complete end-to-end: real Verilator simulation, real Yosys synthesis,
real nextpnr-ecp5 place & route for every milestone, fully logged
(EXP-0001..EXP-0013, DEC-0001..DEC-0013, ERR-0001..ERR-0008) with no
invented results (§30) and V1 kept frozen and untouched throughout
(§1/§34).
Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
micheleandClaude Sonnet 5
91bbbe2fe5