micheleandClaude Sonnet 5
77baa8fc16
dataflow_core.v integrates dependency_manager (M6) -> neural_director (M5) -> N_SLOTS x (memory_manager (M4) + neural_processor (M1)) for the first time. A slot's completion (via neural_director's new slot_node_id tracking, an additive port) feeds back as a producer_done event to dependency_manager, waking up any node that depended on it - closing the dataflow loop without external glue. Verified end-to-end (Verilator) on a 3-node DAG: two independent nodes plus a third depending on both, confirmed to dispatch only after both genuinely complete via real neural_processor computation. 4/4 PASS. Real synthesis + nextpnr-ecp5 P&R via a synthesis-only timing harness (bare per-slot backend ports exceed the LFE5U-45F's TRELLIS_IO budget, same pattern as ERR-0005): N_SLOTS=2 -> 165.15 MHz, N_SLOTS=4 -> 133.19 MHz, both PASS at 80MHz, 0 synthesis problems. Scope explicitly deferred to M8 (DEC-0009): M3's BRAM buffers not wired in yet, per-slot Memory Backend Interface ports not arbitrated to one shared PSRAM master yet - both need real measured data before committing to a design, not guessed at here. Logged: simulation/synthesis/timing/benchmark/decisions (DEC-0009)/ experiments (EXP-0008)/errors (ERR-0007, a Yosys chparam-ordering build quirk, not an RTL bug)/development.log, ROADMAP.md updated. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
106 lines
5.5 KiB
Plaintext
106 lines
5.5 KiB
Plaintext
# V2 benchmark log -- solo append, mai troncato/sovrascritto (vedi README.md)
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# Nessuna entry ancora -- popolato incrementalmente man mano che avanza lo sviluppo V2.
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[2026-09-05] M1 single Neural Processor, isolated (no array/director/
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memory manager yet -- system-level numbers deferred to M9)
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| Config | Fmax (POST-P&R) | LUT | FF | DSP | BRAM |
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|----------------------|------------------|-----|-----|-----|------|
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| P_IN=8, ACC_WIDTH=32 | 183.12 MHz | 55 | 533 | 8 | 0 |
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| P_IN=8, ACC_WIDTH=24 | 176.21 MHz | 49 | 509 | 8 | 0 |
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Reference (V1, hardware/v1/synthesis/p8/, isolated neuron_parallel,
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PARALLEL=8, N_INPUTS=256): 61.71 MHz POST-P&R.
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All Fmax figures above are POST-P&R (real nextpnr-ecp5), not
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theoretical or simulated-only. MAC/cycle, cycles/neuron, neurons/s,
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stall %, effective MAC/s: not yet meaningful at this milestone (single
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isolated processor, no streaming benchmark harness yet -- deferred to
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M2 once neural_processor_array.v exists and a real workload can be
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timed end-to-end).
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[2026-09-05] M2 Neural Processor Array, N_PROCESSORS sweep (P_IN=8,
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ACC_WIDTH=32 each; synthesized via the timing harness, see errors.log
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ERR-0005 for why)
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| N_PROCESSORS | Fmax (POST-P&R) | LUT | FF | DSP (MULT18X18D) | DSP % of 72 |
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|--------------|------------------|-----|------|-------------------|-------------|
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| 1 | 159.11 MHz | 59 | 409 | 8 | 11% |
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| 2 | 149.59 MHz | 106 | 786 | 16 | 22% |
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| 4 | 151.01 MHz | 207 | 1540 | 32 | 44% |
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| 8 | 134.70 MHz | 374 | 3048 | 64 | 88% |
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All figures POST-P&R (real nextpnr-ecp5), all PASS at the 80MHz
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target. LUT4 utilization stays under 6% of the device even at N=8;
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DSP is the binding resource (see decisions.log DEC-0005), reaching 88%
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at N=8 -- N_PROCESSORS=9 would already exceed the LFE5U-45F's 72
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MULT18X18D budget at P_IN=8. Theoretical MAC/cycle (THEORETICAL, not
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yet measured end-to-end -- no real workload/benchmark harness exists
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until M9): N_PROCESSORS * P_IN MACs/cycle when all processors are
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simultaneously streaming tiles (8, 16, 32, 64 for N=1/2/4/8 -- verified
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achievable in principle by EXP-0003's concurrent/staggered simulation,
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not yet measured as a sustained throughput number).
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[2026-09-05] M3 buffers -- BRAM cost vs DEPTH (real Yosys synth_ecp5)
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| Module | DEPTH | DP16KD | LUT4 | FF |
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|--------------------|-------|--------|------|-----|
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| activation_buffer | 4096 | 2 | 37 | 30 |
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| activation_buffer | 256 | 1 | 21 | 26 |
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| weight_buffer | 512 | 2 | 88 | 139 |
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| weight_buffer | 64 | 2 | 73 | 136 |
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| result_buffer | 4096 | 2 | 37 | 30 |
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| result_buffer | 256 | 1 | 21 | 26 |
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weight_buffer's DP16KD count is flat across an 8x depth reduction --
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its 64-bit TILE_WIDTH (P_IN=8 * DATA_WIDTH=8), not DEPTH, determines
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BRAM count for this module. activation_buffer/result_buffer (byte-
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wide) scale as expected with depth. Confirms §14's warning literally:
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"non assumere che buffer piu' grandi siano automaticamente migliori"
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-- here, smaller was not cheaper either, because depth was the wrong
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lever for this specific buffer's cost.
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[2026-09-05] M4 Memory Manager + Prefetch Engine (standalone resource
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count; Fmax via timing harness -- see errors.log ERR-0005)
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| Module | Fmax (POST-P&R) | LUT | FF | DSP | CCU2C |
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|----------------------------------|------------------|-----|-----|-----|-------|
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| memory_manager + prefetch_engine | 165.86 MHz | 851 | 789 | 0 | 108 |
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End-to-end (real PSRAM + real neural_processor, SIMULATED only, no
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system-level P&R yet -- deferred to M7/M9): 3-tile job = 446 cycles,
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1-tile job = 166 cycles, 5-tile job = 728 cycles. ~140-150 cycles/tile,
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dominated by psram_model.v's real ~70ns TAA access latency, not by
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memory_manager's own control overhead (its bank-swap turnaround is
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documented as a fixed +1 cycle/tile in decisions.log DEC-0006, a small
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fraction of the ~140-cycle PSRAM-dominated total).
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[2026-09-05] M5 Neural Director (standalone resource count; Fmax via
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timing harness -- see errors.log ERR-0005)
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| Module | Fmax (POST-P&R) | LUT | FF | DSP | CCU2C |
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|------------------|------------------|-----|-----|-----|-------|
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| neural_director (N_SLOTS=4) | 250.50 MHz | 382 | 366 | 0 | 4 |
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[2026-09-05] M6 Dependency Manager (real standalone synthesis + P&R,
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no harness needed)
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| Module | Fmax (POST-P&R) | LUT | FF | DSP | CCU2C |
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|----------------------|------------------|-----|-----|-----|-------|
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| dependency_manager (N_NODES=16) | 155.30 MHz | 763 | 474 | 0 | 0 |
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[2026-09-05] M7 Dataflow Core (full M1-M6 integration; resources via
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real standalone synthesis, Fmax via timing harness -- see errors.log
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ERR-0005)
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| Module (config) | Fmax (POST-P&R) | LUT4 | CCU2C | FF | DSP | BRAM |
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|-------------------------------|------------------|------|-------|------|-----|------|
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| dataflow_core (N_SLOTS=2) | 165.15 MHz | 2127 | 248 | 2505 | 16 | 0 |
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| dataflow_core (N_SLOTS=4) | 133.19 MHz | 3953 | 500 | 4688 | 32 | 0 |
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DSP budget on the LFE5U-45F is 72 MULT18X18D total: N_SLOTS=4 already
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uses 32/72 (44%), consistent with DEC-0005's finding that DSP, not
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LUT/FF, is the first resource to saturate as concurrency grows (M2's
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own N_PROCESSORS=8 measurement: 88%). BRAM=0 on both is expected --
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M3's buffers are not wired into dataflow_core yet (DEC-0009).
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