# V2 benchmark log -- solo append, mai troncato/sovrascritto (vedi README.md)
# Nessuna entry ancora -- popolato incrementalmente man mano che avanza lo sviluppo V2.

[2026-09-05] M1 single Neural Processor, isolated (no array/director/
  memory manager yet -- system-level numbers deferred to M9)

| Config              | Fmax (POST-P&R) | LUT | FF  | DSP | BRAM |
|----------------------|------------------|-----|-----|-----|------|
| P_IN=8, ACC_WIDTH=32 | 183.12 MHz       | 55  | 533 | 8   | 0    |
| P_IN=8, ACC_WIDTH=24 | 176.21 MHz       | 49  | 509 | 8   | 0    |

Reference (V1, hardware/v1/synthesis/p8/, isolated neuron_parallel,
PARALLEL=8, N_INPUTS=256): 61.71 MHz POST-P&R.

All Fmax figures above are POST-P&R (real nextpnr-ecp5), not
theoretical or simulated-only. MAC/cycle, cycles/neuron, neurons/s,
stall %, effective MAC/s: not yet meaningful at this milestone (single
isolated processor, no streaming benchmark harness yet -- deferred to
M2 once neural_processor_array.v exists and a real workload can be
timed end-to-end).

[2026-09-05] M2 Neural Processor Array, N_PROCESSORS sweep (P_IN=8,
ACC_WIDTH=32 each; synthesized via the timing harness, see errors.log
ERR-0005 for why)

| N_PROCESSORS | Fmax (POST-P&R) | LUT | FF   | DSP (MULT18X18D) | DSP % of 72 |
|--------------|------------------|-----|------|-------------------|-------------|
| 1            | 159.11 MHz       | 59  | 409  | 8                 | 11%         |
| 2            | 149.59 MHz       | 106 | 786  | 16                | 22%         |
| 4            | 151.01 MHz       | 207 | 1540 | 32                | 44%         |
| 8            | 134.70 MHz       | 374 | 3048 | 64                | 88%         |

All figures POST-P&R (real nextpnr-ecp5), all PASS at the 80MHz
target. LUT4 utilization stays under 6% of the device even at N=8;
DSP is the binding resource (see decisions.log DEC-0005), reaching 88%
at N=8 -- N_PROCESSORS=9 would already exceed the LFE5U-45F's 72
MULT18X18D budget at P_IN=8. Theoretical MAC/cycle (THEORETICAL, not
yet measured end-to-end -- no real workload/benchmark harness exists
until M9): N_PROCESSORS * P_IN MACs/cycle when all processors are
simultaneously streaming tiles (8, 16, 32, 64 for N=1/2/4/8 -- verified
achievable in principle by EXP-0003's concurrent/staggered simulation,
not yet measured as a sustained throughput number).

[2026-09-05] M3 buffers -- BRAM cost vs DEPTH (real Yosys synth_ecp5)

| Module             | DEPTH | DP16KD | LUT4 | FF  |
|--------------------|-------|--------|------|-----|
| activation_buffer   | 4096  | 2      | 37   | 30  |
| activation_buffer   | 256   | 1      | 21   | 26  |
| weight_buffer       | 512   | 2      | 88   | 139 |
| weight_buffer       | 64    | 2      | 73   | 136 |
| result_buffer       | 4096  | 2      | 37   | 30  |
| result_buffer       | 256   | 1      | 21   | 26  |

weight_buffer's DP16KD count is flat across an 8x depth reduction --
its 64-bit TILE_WIDTH (P_IN=8 * DATA_WIDTH=8), not DEPTH, determines
BRAM count for this module. activation_buffer/result_buffer (byte-
wide) scale as expected with depth. Confirms §14's warning literally:
"non assumere che buffer piu' grandi siano automaticamente migliori"
-- here, smaller was not cheaper either, because depth was the wrong
lever for this specific buffer's cost.

[2026-09-05] M4 Memory Manager + Prefetch Engine (standalone resource
count; Fmax via timing harness -- see errors.log ERR-0005)

| Module                          | Fmax (POST-P&R) | LUT | FF  | DSP | CCU2C |
|----------------------------------|------------------|-----|-----|-----|-------|
| memory_manager + prefetch_engine | 165.86 MHz       | 851 | 789 | 0   | 108   |

End-to-end (real PSRAM + real neural_processor, SIMULATED only, no
system-level P&R yet -- deferred to M7/M9): 3-tile job = 446 cycles,
1-tile job = 166 cycles, 5-tile job = 728 cycles. ~140-150 cycles/tile,
dominated by psram_model.v's real ~70ns TAA access latency, not by
memory_manager's own control overhead (its bank-swap turnaround is
documented as a fixed +1 cycle/tile in decisions.log DEC-0006, a small
fraction of the ~140-cycle PSRAM-dominated total).

[2026-09-05] M5 Neural Director (standalone resource count; Fmax via
timing harness -- see errors.log ERR-0005)

| Module          | Fmax (POST-P&R) | LUT | FF  | DSP | CCU2C |
|------------------|------------------|-----|-----|-----|-------|
| neural_director (N_SLOTS=4) | 250.50 MHz | 382 | 366 | 0 | 4 |

[2026-09-05] M6 Dependency Manager (real standalone synthesis + P&R,
no harness needed)

| Module              | Fmax (POST-P&R) | LUT | FF  | DSP | CCU2C |
|----------------------|------------------|-----|-----|-----|-------|
| dependency_manager (N_NODES=16) | 155.30 MHz | 763 | 474 | 0 | 0 |

[2026-09-05] M7 Dataflow Core (full M1-M6 integration; resources via
real standalone synthesis, Fmax via timing harness -- see errors.log
ERR-0005)

| Module (config)              | Fmax (POST-P&R) | LUT4 | CCU2C | FF   | DSP | BRAM |
|-------------------------------|------------------|------|-------|------|-----|------|
| dataflow_core (N_SLOTS=2)     | 165.15 MHz       | 2127 | 248   | 2505 | 16  | 0    |
| dataflow_core (N_SLOTS=4)     | 133.19 MHz       | 3953 | 500   | 4688 | 32  | 0    |

DSP budget on the LFE5U-45F is 72 MULT18X18D total: N_SLOTS=4 already
uses 32/72 (44%), consistent with DEC-0005's finding that DSP, not
LUT/FF, is the first resource to saturate as concurrency grows (M2's
own N_PROCESSORS=8 measurement: 88%). BRAM=0 on both is expected --
M3's buffers are not wired into dataflow_core yet (DEC-0009).