micheleandClaude Sonnet 5
d8ccc9d494
Adds a real, dated section to ch.10 (Hardware and board) covering the two-independent-flash architecture (neural-network data vs. boot bitstream), the ESP32<->ECP5 JTAG-only link, and the real CABGA381 ball assignments (JTAG/PROGRAMN/INITN/DONE/CFG[2:0]/MSPI dedicated pins), matching decisions.log DEC-0041. Also closes ch.7's (Host interface) own long-standing "still needed" list: the physical transport (spi_host_bridge.v) and the completion- notification path (FPGA_DATA_READY) it used to flag as missing are both now real -- described with the same system-idle-detector formula implemented in the RTL. Compiled clean (44 pages, 0 errors). Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
318 lines
15 KiB
TeX
318 lines
15 KiB
TeX
\chapter{Hardware and board}
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\label{ch:hw}
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\section{Unchanged from V1}
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V2 targets the identical board and component set as V1: Lattice ECP5
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\code{LFE5U-45F-8BG381C} ($-8$, CABGA381), ISSI
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\code{IS66WVE4M16EBLL-70BLI} PSRAM (64\,Mb, 4M$\times$16), same 16\,MHz
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reference oscillator. The real PSRAM controller
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(\code{psram\_controller.v}) and its byte$\leftrightarrow$word adapter
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(\code{memory\_interface.v}) are reused byte-for-byte, unmodified, from
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\code{hardware/v1/} throughout every V2 milestone --- their real,
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already-verified electrical/timing requirements and page-mode behavior
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are unchanged, because the controller itself was never touched.
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\begin{fnnote}[Real ball assignment: defer to V1's own chapter]
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V1's own hardware chapter documents a real, \code{iodb.json}-verified,
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place\&route-confirmed ball assignment for every PSRAM signal
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(\code{psram\_a}, \code{psram\_dq}, \code{psram\_ce\_n/oe\_n/we\_n/
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lb\_n/ub\_n/zz\_n}). Since V2's own \code{neural\_multiprocessor.v}
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drives these signals through the identical, unmodified controller, that
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same real ball assignment applies unchanged if V2 is deployed on the
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same physical board --- it is not repeated here to avoid maintaining two
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copies of the same real data; see the V1 datasheet directly.
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\end{fnnote}
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\section{What V2 has not yet placed on real hardware}
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As stated in ch.~\ref{ch:host}, V2's own node-registration bus has no
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physical pin assignment in this revision --- every V2 characterization
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to date used either a Verilator testbench or an unconstrained
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(\code{--lpf-allow-unconstrained}) synthesis top-level. A real deployment
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would need:
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\begin{itemize}
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\item A physical host transport for the registration bus (ch.~\ref{ch:host}).
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\item A real, constrained \code{nextpnr-ecp5} place\&route run
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producing a genuine \code{.lpf}/ball assignment for
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\code{neural\_multiprocessor.v}'s own top-level pins, analogous to
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V1's own \code{tools/pinout/gen\_lpf.py} flow.
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\item Re-verification that the real Fmax numbers in ch.~\ref{ch:impl2}
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(obtained unconstrained) hold once real pin locations are fixed ---
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pin placement can itself affect routing and therefore Fmax.
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\end{itemize}
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\section{Power supply, oscillator, configuration}
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Unchanged from V1: same board-level power sequencing, same oscillator,
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same JTAG/config-SPI boot path (fixed-function dedicated pins, outside
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RTL scope). No V2-specific hardware change was made or is required
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beyond the (not yet placed) registration-bus transport above.
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\section{SDRAM upgrade addendum (2026-09-07) --- current, authoritative
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board state}
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\label{sec:sdram-addendum}
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\begin{fnwarn}[This section supersedes the PSRAM description above for
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the current hardware baseline]
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The sections above describe an earlier V2 milestone that still reused
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V1's own PSRAM chain unconstrained. The project has since made a
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closed architectural decision (real \code{decisions.log} DEC-0034) to
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replace external memory with a single SDR SDRAM device, and has since
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upgraded that device's capacity and re-verified real, constrained
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place\&route timing. This section is the current, real, measured state
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--- see \code{hardware/v2/docs/MEMORY\_UPGRADE\_64MB\_N8.md} in the
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repository for the full investigation.
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\end{fnwarn}
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\subsection{Memory device}
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\textbf{Alliance Memory AS4C32M16SB-7BIN} --- 512\,Mbit (64\,MByte) SDR
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SDRAM, organized 4 banks $\times$ 8M words $\times$ 16 bits, 54-ball
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FBGA package (8$\times$8$\times$1.2\,mm max), $-40$ to $85^{\circ}$C
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industrial, $-7$ speed grade (143\,MHz max). VDD/VDDQ 3.3\,V $\pm$0.3\,V.
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Single-ended \code{CLK} --- \textbf{no \code{CLK\_N}}, this is SDR, not
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DDR, SDRAM. Real distributor availability confirmed: DigiKey product
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11613071, 568 units in stock, \$31.12/unit (qty 1), 16-week
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manufacturer lead time.
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\subsection{Complete AS4C32M16SB-7BIN ball assignment}
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From the manufacturer's own \code{-7BIN}-specific datasheet (Alliance
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Memory, Rev.\,1.4, June 2024, Figure~1.1 --- the real TFBGA ball
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diagram, not inferred from the TSOP-II \code{-7TIN} pinout).
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\begin{fnnote}[Address / Bank]
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A0=H7, A1=H8, A2=J8, A3=J7, A4=J3, A5=J2, A6=H3, A7=H2, A8=H1, A9=G3,
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A10/AP=H9, A11=G2, A12=G1, BA0=G7, BA1=G8.
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\end{fnnote}
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\begin{fnnote}[Data / Masks]
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DQ0=A8, DQ1=B9, DQ2=B8, DQ3=C9, DQ4=C8, DQ5=D9, DQ6=D8, DQ7=E9, DQ8=E1,
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DQ9=D2, DQ10=D1, DQ11=C2, DQ12=C1, DQ13=B2, DQ14=B1, DQ15=A2, LDQM=E8,
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UDQM=F1.
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\end{fnnote}
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\begin{fnnote}[Control / Power]
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CLK=F2, CKE=F3, CS\#=G9, RAS\#=F8, CAS\#=F7, WE\#=F9. VDD=\{A9,E7,J9\},
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VSS=\{A1,E3,J1\}, VDDQ=\{A7,B3,C7,D3\}, VSSQ=\{A3,B7,C3,D7\}, NC=E2.
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\end{fnnote}
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\subsection{FPGA $\leftrightarrow$ SDRAM mapping (real, LPF-verified)}
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From \code{hardware/v2/constraints/v2\_board\_top.lpf} (45/45 unique
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FPGA balls, no duplicates, LFE5U-45F-8BG381 rev.\,3.0 CSV-verified).
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\begin{fnnote}[FPGA ball $\to$ SDRAM ball, by signal group]
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\code{sdram\_a[0..12]}: D5,D3,F4,E5,E3,F5,A2,B1,C2,C1,D2,D1,F1 $\to$
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A0..A12 (H7,H8,J8,J7,J3,J2,H3,H2,H1,G3,H9,G2,G1). \code{sdram\_ba[0:1]}:
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E4,C3 $\to$ BA0,BA1 (G7,G8). \code{sdram\_dq[0..15]}:
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E1,G5,H3,J5,K3,K2,H1,J1,K1,K4,L4,L5,M5,M4,N4,N5 $\to$ DQ0..DQ15.
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\code{sdram\_dqm[0:1]}: P5,N3 $\to$ LDQM,UDQM. Control:
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\code{sdram\_cke/cs\_n/ras\_n/cas\_n/we\_n}: B5,C5,C4,A3,B3 $\to$
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CKE,CS\#,RAS\#,CAS\#,WE\#.
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\end{fnnote}
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\subsection{Real, measured clock closure (nextpnr-ecp5, 8 seeds/config)}
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\begin{tabularx}{\textwidth}{L{4.0cm} C{1.6cm} C{2.2cm} X}
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\toprule
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\rowh \thd{Configuration} & \thd{Pass} & \thd{Worst Fmax} & \thd{Notes} \\
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\midrule
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N\_SLOTS=4 @ 64\,MHz & 8/8 & 66.58\,MHz & Production baseline, GO \\
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\rowa N\_SLOTS=8 @ 64\,MHz & 5/8 & 60.12\,MHz & Open, not production-frozen \\
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N\_SLOTS=4/8 @ 80\,MHz & 0/8 & --- & NO-GO, genuine \code{ecppll}-regenerated PLL \\
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\bottomrule
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\end{tabularx}
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Real, measured after the ERR-0029 weight-cache hit-index optimization
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(serial priority scan $\to$ flat one-hot compare); see
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\code{hardware/v2/logs/errors.log} and \code{decisions.log} DEC-0040.
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\section{Power supply design (2026-09-07) --- verified against the real
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Lattice hardware checklist}
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\label{sec:power-addendum}
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\begin{fnwarn}[Supersedes the generic \S3 stub above]
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The ``Power supply, oscillator, configuration'' section earlier in
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this chapter only said ``unchanged from V1'' without real design data.
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This section replaces that stub with the actual rail topology, sized
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against the real, primary-source Lattice and TI documents below --- not
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estimated.
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\end{fnwarn}
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\subsection{Rail topology}
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Three rails, one simplification from the original V1 reference design:
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\textbf{no separate buck regulator for the 3.3\,V I/O rail} --- the
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board's own external input is specified as \textbf{3.3\,V}, so
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\code{VCCIO}, the SDRAM (VDD/VDDQ, 3.3\,V per its own datasheet), and
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the flash (3.3\,V) are fed directly from the board input. A buck
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targeting 3.3\,V output from a 3.3\,V input would run at 100\% duty
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cycle permanently --- zero regulation margin, no benefit over a direct
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connection.
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\begin{tabularx}{\textwidth}{L{2.6cm} L{2.0cm} L{3.2cm} X}
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\toprule
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\rowh \thd{Rail} & \thd{Value} & \thd{Source} & \thd{Feeds} \\
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\midrule
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I/O & 3.3\,V & Direct board input & FPGA \code{VCCIO0--8}, SDRAM VDD/VDDQ, SPI flash, PMOD \\
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\rowa Core & 1.1\,V & TLV62568 (buck), from the 3.3\,V rail & FPGA \code{VCC} \\
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Auxiliary & 2.5\,V & TLV73325 (LDO), from the 3.3\,V rail & FPGA \code{VCCAUX} \\
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\bottomrule
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\end{tabularx}
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\subsection{Power-up sequencing --- real Lattice requirement, verified
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compliant}
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Per Lattice's own \emph{ECP5 and ECP5-5G Hardware Checklist}
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(FPGA-TN-02038-2.0, July 2024), \S4: \emph{``\code{VCCIO} supplies
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should be powered up before or together with the \code{VCC} and
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\code{VCCAUX} supplies.''} The same document's \S2 adds: all three
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monitored rails must rise \textbf{monotonically}, and the on-chip
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Power-On-Reset de-asserts only once \code{VCC}$\geq$0.9\,V,
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\code{VCCAUX}$\geq$2.0\,V, and \code{VCCIO8}$\geq$0.95\,V are all
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simultaneously satisfied --- device initialization waits for whichever
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of the three is slowest.
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This board's topology satisfies the requirement \textbf{by construction},
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with no sequencer IC needed: \code{VCCIO} (3.3\,V) is a direct,
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unregulated connection to the board input, so it rises first/fastest,
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strictly before the two regulated rails (Core, Aux) can even begin
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their own soft-start ramps --- ``before or together with'' is met on
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every possible power-up transient, not just the typical case.
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\subsection{Decoupling --- real Lattice-recommended values (not a
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generic ``one cap per pin'' guess)}
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Per FPGA-TN-02038-2.0 Table~3.1 (\S3.1), applied per-rail:
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\begin{tabularx}{\textwidth}{L{2.0cm} L{5.0cm} X}
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\toprule
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\rowh \thd{Rail} & \thd{Filter} & \thd{Notes} \\
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\midrule
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\code{VCC} & 10\,\textmu F $\times$3 (bulk) $+$ 100\,nF per pin & Core, 1.1\,V \\
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\rowa \code{VCCAUX} & 120\,$\Omega$ ferrite bead $+$ 10\,\textmu F $+$
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100\,nF per pin & 2.5\,V; \textbf{new part not in the earlier power
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tree draft} --- a ferrite bead in series was missing before this
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verification pass \\
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\code{VCCIO[0--8]} & 10\,\textmu F $+$ 100\,nF per pin (per bank in
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use) & 1\textmu F acceptable on unused banks; 22\,\textmu F (or a
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second 10\,\textmu F) on banks with heavy output loading \\
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\bottomrule
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\end{tabularx}
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Capacitor selection, also per the same document: X5R/X7R dielectric
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(avoid Y5V/Z5U), voltage rating $\geq$80\% above the rail's maximum ---
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for the 3.3\,V rail this means a \textbf{6.3\,V minimum} rating, not
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the bare 3.3\,V-rated parts sometimes used to save cost. All ground
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pins tie to the board's ground plane (no star grounding on this
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family).
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\subsection{Regulator component values (real, computed from datasheet
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constants)}
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\textbf{TLV62568} (core, 1.1\,V): input range 2.5--5.5\,V (3.3\,V
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input has full margin); feedback reference \code{VFB}$=0.6$\,V
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(typical, per TI SLVSD89B). Output set via
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$V_{OUT}=V_{FB}\left(1+\frac{R1}{R2}\right)$: choosing
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\textbf{R1$=$100\,k$\Omega$, R2$=$120\,k$\Omega$} gives
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$0.6\times(1+100/120)=1.1$\,V exactly. Per TI's own typical
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application circuit: C1$=$4.7\,\textmu F on \code{VIN}, L1$=$2.2\,
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\textmu H inductor, C2$=$10\,\textmu F on \code{VOUT}.
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\textbf{TLV73325} (auxiliary, 2.5\,V fixed-output LDO): input range
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1.4--5.5\,V (per TI SBVS221, real datasheet), dropout 125\,mV at
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300\,mA --- far above this rail's $\sim$10\,mA real load, so dropout is
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not a concern at 3.3\,V input. Capacitor-free architecture (stable
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without external caps at the regulator itself); the 10\,\textmu F$+$
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100\,nF on \code{VCCAUX} above are the FPGA-side filter from
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FPGA-TN-02038, not regulator-stability caps, and are still required.
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\begin{fnnote}[Open item carried from \S3 above]
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The 16\,MHz reference oscillator's exact manufacturer part number is
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not yet specified in this document (only ``16\,MHz'' as a frequency
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requirement) --- flagged, not invented, pending the schematic capture
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the user is preparing separately.
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\end{fnnote}
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\subsection{Power tree}
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\begin{center}
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\begin{tikzpicture}[node distance=10mm and 14mm,font=\footnotesize]
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\node[fnblockD,minimum width=30mm,minimum height=11mm] (in){Board input\\3.3\,V};
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\node[fnblock,below left=14mm and -6mm of in,minimum width=32mm,minimum height=13mm] (u3){TLV62568 (buck)\\R1/R2 $\to$ 1.1\,V};
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\node[fnblockT,below right=14mm and -6mm of in,minimum width=32mm,minimum height=13mm] (u5){TLV73325 (LDO)\\fixed 2.5\,V};
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\node[fnblockA,right=30mm of in,minimum width=26mm,minimum height=11mm] (io){\code{VCCIO0--8}\\3.3\,V direct};
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\node[fnreg,below=8mm of io,minimum width=26mm] (sd){SDRAM VDD/VDDQ};
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\node[fnreg,below=6mm of sd,minimum width=26mm] (fl){SPI flash \code{VCC}};
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\node[fnblock,below=18mm of u3,minimum width=30mm,minimum height=11mm] (core){FPGA \code{VCC}\\1.1\,V core};
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\node[fnblockT,below=18mm of u5,minimum width=30mm,minimum height=11mm] (aux){FPGA \code{VCCAUX}\\2.5\,V};
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\draw[fnbus] (in) -- (io);
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\draw[fnarrow] (io) -- (sd);
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\draw[fnarrow] (io) -- (fl);
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\draw[fnbus] (in) -- (u3);
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\draw[fnbus] (in) -- (u5);
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\draw[fnbus] (u3) -- node[fnlbl,right]{10\textmu F$\times$3 + 100nF/pin} (core);
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\draw[fnbus] (u5) -- node[fnlbl,right]{120$\Omega$ FB + 10\textmu F + 100nF/pin} (aux);
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\end{tikzpicture}
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\end{center}
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\begin{center}
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{\scriptsize Power tree, direct 3.3\,V I/O rail (no redundant buck), verified against
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FPGA-TN-02038-2.0 \S3--4. Full schematic capture (BOM, connectors,
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FPGA--RAM/FLASH and PROG sections) pending separately.}
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\end{center}
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\section{Programming architecture (2026-09-07) --- two independent
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flash devices, ESP32 over JTAG only}
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\label{sec:prog-addendum}
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\begin{fnwarn}[Real, closed design -- not a placeholder]
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Converged after evaluating and rejecting a single-shared-flash and an
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SSPI-every-boot alternative (see \code{decisions.log} DEC-0041 for the
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full comparison). This is the current, real architecture.
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\end{fnwarn}
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\subsection{Two physically separate flash chips}
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\begin{itemize}
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\item \textbf{Flash \#1} --- neural-network weights/graph data.
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V1's own real subsystem (\code{flash\_copy\_engine.v}/
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\code{flash\_slot\_manager.v}), 4 ordinary GPIO balls. V1's own
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real balls (\code{flash\_sclk}=E3, \code{flash\_mosi}=D3,
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\code{flash\_miso}=D5, \code{flash\_cs\_n}=E4) are \textbf{not}
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reusable in V2 --- confirmed conflict, all four already carry
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V2's own SDRAM bus. New balls reserved (bank~7, 3.3\,V):
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\code{flash\_sclk}=B2, \code{flash\_mosi}=E2,
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\code{flash\_miso}=F2, \code{flash\_cs\_n}=F3. \textbf{Not yet
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in the LPF} --- the RTL port does not exist in
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\code{fpga\_neural\_v2\_top.v} yet (a real, separate, open
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integration task).
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\item \textbf{Flash \#2} --- boot bitstream only. Connects
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exclusively to the ECP5's own dedicated sysCONFIG pins, Master
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SPI mode, auto-boots every power-up, zero ESP32 involvement in
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normal operation.
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\end{itemize}
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\subsection{ESP32 $\leftrightarrow$ ECP5: JTAG only}
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Neither ESP32-S3 nor ESP32-C6 has a hardware JTAG \emph{master}
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peripheral (verified against Espressif's own documentation): their
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native ``USB Serial/JTAG Controller'' lets an external host debug the
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ESP32 itself --- the wrong direction for driving the ECP5. TCK/TMS/
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TDI/TDO are therefore bit-banged from ordinary ESP32 GPIO, standard
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practice. ESP32 updates flash~\#2 by commanding the ECP5's own
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internal sysCONFIG engine to bridge JTAG writes through to the
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external flash (real Lattice mechanism, FPGA-TN-02038-2.0 Figure~6.3,
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``Programming external Flash via JTAG'') --- ESP32 never drives
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flash~\#2's own SPI pins directly, zero bus contention by
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construction.
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\subsection{Real ball assignments (CABGA381)}
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From the official Lattice pinout CSV (\code{FPGA-SC-02034-3-0-
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ECP5U-45-Pinout.csv} rev.\,3.0) cross-checked against Project
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Trellis's \code{iodb.json}.
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\begin{fnnote}[JTAG (bank 40/TAP) --- to ESP32]
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TCK=T5, TMS=U5, TDI=R5, TDO=V4.
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\end{fnnote}
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\begin{fnnote}[Dedicated config (bank 8) --- to ESP32]
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PROGRAMN=W3, INITN=V3, DONE=Y3.
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\end{fnnote}
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\begin{fnnote}[CFG{[}2:0{]} (bank 8) --- board jumpers/0$\Omega$, NOT to ESP32]
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For MSPI, CFG[2:0]$=$[0,1,0] read MSB-first: CFG\_2(R4)$=$GND,
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CFG\_1(T4)$=$pull-up 1--10\,k$\Omega$ to VCCIO8, CFG\_0(U4)$=$GND.
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\end{fnnote}
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\begin{fnnote}[MSPI dedicated/dual-function pins to flash \#2 (bank 8) --- NOT to ESP32]
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MCLK/CCLK=U3, CSSPIN=R2 (dual w/ HOLDN/DI/BUSY/CEN), D0/MOSI=W2,
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D1/MISO=V2.
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\end{fnnote}
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Confirmed real and safe (Lattice FPGA-TN-02039-2.3 sysCONFIG User
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Guide, \S6.1.2): once User Mode is reached, the MSPI dedicated pins
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tristate with a weak pull-up, so they never contend with another
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driver on the same net --- not load-bearing for this specific
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two-chip architecture (flash \#1/\#2 are physically separate), but
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confirms the mechanism is real should a future revision ever share a
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single chip.
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