micheleandClaude Sonnet 5
d8ccc9d494
Adds a real, dated section to ch.10 (Hardware and board) covering the two-independent-flash architecture (neural-network data vs. boot bitstream), the ESP32<->ECP5 JTAG-only link, and the real CABGA381 ball assignments (JTAG/PROGRAMN/INITN/DONE/CFG[2:0]/MSPI dedicated pins), matching decisions.log DEC-0041. Also closes ch.7's (Host interface) own long-standing "still needed" list: the physical transport (spi_host_bridge.v) and the completion- notification path (FPGA_DATA_READY) it used to flag as missing are both now real -- described with the same system-idle-detector formula implemented in the RTL. Compiled clean (44 pages, 0 errors). Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v