michele

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• Joined on 2026-09-15

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michele pushed to v3-artix7 at michele/FPGA-Neural 2026-09-17 06:43:26 +00:00

e25e4a1506 feat: real DDR3 memory path verified against MIG's own ddr3_model.sv (EXP-0068)

michele pushed to v3-artix7 at michele/FPGA-Neural 2026-09-16 22:21:04 +00:00

0589620b58 exp: real P&R of the N=2 multi-core system, first genuine system Fmax (EXP-0067)

michele pushed to v3-artix7 at michele/FPGA-Neural 2026-09-16 22:16:51 +00:00

09fbf01ea5 feat: first genuine N=2 multi-core system, two real bugs found+fixed (EXP-0066)

michele pushed to v3-artix7 at michele/FPGA-Neural 2026-09-16 22:02:37 +00:00

124a0dbca0 feat: packed_slot.v, real per-slot sequencer FSM (EXP-0065)

michele pushed to v3-artix7 at michele/FPGA-Neural 2026-09-16 21:52:22 +00:00

71600096f9 feat: neural_director_packed.v, job-pairing scheduler for packed cores (EXP-0064)

michele pushed to v3-artix7 at michele/FPGA-Neural 2026-09-16 21:44:27 +00:00

5afa6a7477 exp: real P&R of verified weight-reuse memory path + packed core (EXP-0063)

michele pushed to v3-artix7 at michele/FPGA-Neural 2026-09-16 21:41:37 +00:00

9ca180a787 test: first real end-to-end weight-reuse -> packed-core integration, bug found+fixed (EXP-0062)

michele pushed to v3-artix7 at michele/FPGA-Neural 2026-09-16 21:34:12 +00:00

5c127fb069 feat: weight_tile_gather.v, real synthesizable byte-to-tile adapter (EXP-0061)

michele pushed to v3-artix7 at michele/FPGA-Neural 2026-09-16 21:29:57 +00:00

94b63705be exp: N=8 packed-core array real P&R, isolates placement density from interconnect (EXP-0060)

michele pushed to v3-artix7 at michele/FPGA-Neural 2026-09-16 21:18:25 +00:00

34b15cc0a7 exp: first real Vivado synthesis+P&R on XC7A100T for V3 DSP-packed core (EXP-0059)

michele pushed to v3-artix7 at michele/FPGA-Neural 2026-09-16 21:04:26 +00:00

9851930613 docs: extract V2 datasheet into submodule

michele pushed to main at michele/FPGA-Neural-Datasheet 2026-09-16 20:58:49 +00:00

07f8ec0460 docs: consolidate all V2 datasheets into one current, complete document

b7b4ada99f docs: polish V2 datasheet to professional third-person English

85d473a79b docs: embed real KiCad schematic export in V2 datasheet, verify BOM from source

86581e1521 docs: resolve FPGA grade to commercial (8BG381C), correct temp range data

a3ba8f93ac docs: resolve the +1V1 label mystery and close remaining schematic open items

Compare 10 commits »

michele created branch main in michele/FPGA-Neural-Datasheet 2026-09-16 20:58:49 +00:00

michele created repository michele/FPGA-Neural-Datasheet 2026-09-16 20:57:45 +00:00

michele pushed to v3-artix7 at michele/FPGA-Neural 2026-09-16 17:49:06 +00:00

1cbe7b85d5 v3: real Artix-7 compute core -- DSP48 packing verified, 2 real bugs found and fixed

michele pushed to v3-artix7 at michele/FPGA-Neural 2026-09-16 15:25:38 +00:00

michele created branch v3-artix7 in michele/FPGA-Neural 2026-09-16 15:25:38 +00:00

michele pushed tag v22-final to michele/FPGA-Neural 2026-09-16 15:25:32 +00:00

michele pushed to v22 at michele/FPGA-Neural 2026-09-16 13:38:43 +00:00

ff5908f25f docs: log DEC-0009 -- project v22 paused, hard DSP resource ceiling on ECP5

michele pushed to v22 at michele/FPGA-Neural 2026-09-16 13:38:16 +00:00

3416b8d3cf exp: fix pulse-race hang in tb_layer_reuse_vs_zero_reuse.v (EXP-0058 follow-up); real remaining bug still open, 7.16x NOT yet re-verified