michele

michele pushed to v22 at michele/FPGA-Neural

2026-09-16 13:38:16 +00:00

3416b8d3cf exp: fix pulse-race hang in tb_layer_reuse_vs_zero_reuse.v (EXP-0058 follow-up); real remaining bug still open, 7.16x NOT yet re-verified

michele pushed to v22 at michele/FPGA-Neural

2026-09-16 12:26:19 +00:00

80c89fa10d exp: real end-to-end weight-reuse integration with neural_processor.v (EXP-0058)

michele pushed to v22 at michele/FPGA-Neural

2026-09-16 10:29:56 +00:00

ca94083366 prod: promote EXP-0056 fixes into production RTL (dependency_manager.v, nms_activation_fill_ctrl_v3.v)

michele pushed to v22 at michele/FPGA-Neural

2026-09-16 10:25:34 +00:00

49b25f6eb6 exp: layer_prefetch_ctrl.v, real synthesizable RTL for layer-weight-reuse prefetch, fixes a real address-truncation bug (EXP-0057b)

michele pushed to v22 at michele/FPGA-Neural

2026-09-16 10:01:17 +00:00

1ce78dff6e exp: N=16 timing closure fixed (EXP-0056), weight-reuse gives real 7.16x memory speedup without DDR3 (EXP-0057)

michele pushed to v22 at michele/FPGA-Neural

2026-09-16 08:09:56 +00:00

fce8ff2d66 exp: fork real board top (fpga_neural_v2_top_openrow.v) with open-row SDRAM backend, verified functionally identical

ee5a68f6e6 exp: SDRAM CDC bridge + open-row policy (EXP-0053/54/55) -- open-row is a real ~5% D-Stress win, CDC bridge measured net-negative once integrated

03b5cbc25b exp: bank-interleaved SDRAM pipelining works in isolation, ~0.3% gain integrated (EXP-0052)

cc5db09f61 exp: dual-bank SDRAM sim shows W/AR split gives only ~9% cycle gain, not thrashing removal (EXP-0051)

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michele created branch v22 in michele/FPGA-Neural

2026-09-16 08:09:56 +00:00

michele synced commits to refs/heads/v21 at michele/FPGA-Neural from mirror 2026-09-16 06:18:41 +00:00

e809b71806 docs+synth: post-fix Fmax measurement (EXP-0051) - honest result, N=8 regressed

6a46dc857f fix: propagate runtime-indexed-crossbar fix to slot_mem_arbiter(_wide) + dataflow_core mux

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