Commit Graph
71 Commits
Author SHA1 Message Date
michele 89a484830e Unstick analysis running when the worker is dead.
A container rebuild left Emmaforo status=running with no process, so
PCB start kept 409. Heal on GET now matches placement/PCB: complete if
report.json exists, otherwise error.
2026-09-20 00:59:22 +02:00
michele 3e2ba269f9 Write project.json to the storage owner prefix.
update_project used meta.user_id for the path, so JWT projects that still
have user_id=local never persisted pcb_status=queued and the PCB worker
exited as draft. Point writes at the prefix used to read the project.
2026-09-20 00:57:15 +02:00
michele 16c606ae3d Add MODE=pcb layout exam job with AI and deterministic checks.
Parallel pcb_status pipeline: parse board, classify domains/groups,
inventory traces, PE-LAY/PLC/SI/DRT checks, per-IC datasheet review.
Findings merge into the report UI. No auto-place or pcbnew write-back.
2026-09-19 22:54:17 +02:00
micheleandCursor dc364f5926 Fix sign-in links and legacy JWT after Periscope rebrand.
/login 404ed from marketing CTAs; redirect to /sign-in and accept pinscope-local tokens plus dual-host CORS so login works on both hostnames.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-13 20:12:53 +02:00
micheleandCursor 8d2b85600f Rebrand Pinscope to Periscope across product and codebase.
Rename the core package to periscopex, update UI/docs/Docker/deploy defaults to periscope.michelebigi.it, and keep legacy version/storage key aliases so existing projects keep working.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-13 20:02:04 +02:00
micheleandCursor 556306bf4d Add IFA/meander/stub antenna templates with SVG and KiCad export.
Progetta now returns a parametric radiator geometry (segments + preview + .kicad_mod) so the layout can be replicated without inventing EM results.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-13 19:27:06 +02:00
micheleandCursor 1d3cf12482 Add RF antenna verify and design recipe to Impedance tab.
Detect matching toward ANT*/ANT_FEED, compute 50 Ω feed width from stackup, and optional λ/4 length from f0 — before auto-draw or F2 packing.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-13 18:57:59 +02:00
micheleandCursor 68af0fd432 Classify strap/bootstrap caps and drop unclassified satellites.
EN/BOOT/REGN/PMID bypass and flying bootstrap caps get real roles; other is omitted from assemble_order.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-13 18:37:01 +02:00
micheleandCursor d47ad91cee Keep power satellites on each IC primary rail only.
Stop LDO 3V3 groups from inheriting VSYS caps/filters, drop connector/switch noise, and align Power rails with domain membership.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-13 18:24:07 +02:00
micheleandCursor 21e2be1cd0 Strengthen pintable layout_rules skill and refresh empty extractions.
Treat PCB/application layout guidance as a first-class extract, keep those pages in PDF trim, and re-run IC extraction once when rules are still empty under older model_version.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-13 18:01:15 +02:00
micheleandCursor 86121e6547 Add gated Placement F2 pack skeleton for satellite xy.
Propose positions only from PCB footprints plus numeric decoupling max_distance_mm; otherwise skip with an explicit reason.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-13 17:50:47 +02:00
micheleandCursor 54b0b07917 Split Domains by primary supply rail instead of POWER union-find.
Converters bridging VBUS/VSYS/3V3 no longer collapse the whole board into one domain.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-13 17:39:11 +02:00
micheleandCursor fc11df59fc Add Domains and Power rails views for functional groups.
Sidebar tabs show routing-first topology from placement_plan/functional_groups, with IC groups and satellite roles highlighted per domain and per supply rail.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-13 17:17:16 +02:00
micheleandCursor e124ac2de7 Heal zombie running projects stuck on Review forever.
If the event log already ends with pipeline_complete, flip meta to complete on project/status fetch so Progress no longer spins on a dead worker.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-13 16:45:07 +02:00
micheleandCursor 4882c9206a Prevent finished projects from bouncing progress to report.
Gate /progress SSE and auto-redirect on a live queued/running status so historical pipeline_complete events no longer flash Processing then open the report.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-13 16:31:32 +02:00
micheleandCursor 4c4b604cca Add parallel Placement pipeline for routing-first topology plans.
Ship a free, analysis-independent job that writes placement_plan.json (domains/satellites, no mm) with API, SSE progress, and a minimal project UI.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-12 16:41:00 +02:00
micheleandCursor 2950446e12 Add Layout F1 functional groups and crystal/NC checks.
Write routing-first domain/satellite topology after graph_build, and
flag crystal CL mismatches and NC pins on active nets without inventing
millimetres.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-12 16:22:56 +02:00
micheleandCursor 30aaf55de6 Ship DeepSeek roadmap P0-5/P2 integrations.
Smoke simple_project offline, reviewer shortest_path, library promotion
gate, PDF drop logs, and per-stage cache hit-rate helper — without
touching Layout placement packing.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-12 15:48:39 +02:00
micheleandCursor 5a69b380da Add local Pinscope multi-user auth for shared projects.
Self-host email/password accounts enable the existing collaborator
invite flow without Clerk; first admin inherits users/local projects.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-11 14:31:37 +02:00
micheleandCursor c5b260b404 Prefer .kicad_pcb pad nets when building the design graph.
Schematic geometry on KiCad 10 boards was swapping rails and inventing
floating pins; board connectivity is authoritative when a PCB is uploaded.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-11 12:39:49 +02:00
micheleandCursor a1a2b2a944 Fix KiCad .kicad_sch power/label net merging.
Disconnected GND power flags were named GND_/GND__/… so the reviewer
flagged swapped rails and floating pins on correctly wired designs.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-11 12:15:41 +02:00
micheleandCursor aebe8f6cc3 Accept a KiCad project zip as the upload unit for hierarchical sheets.
Sheets, optional BOM, and PCB are extracted together; a storage round-trip test proves the pipeline can re-parse child Sheetfiles.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-11 08:15:00 +02:00
micheleandCursor a56dda2358 Accept a KiCad project drop so hierarchical sheets and the board upload in one step.
A single .kicad_sch was parsed in isolation, so child sheets looked like an empty netlist. Report 404s now surface the real API error instead of a generic fetch failure.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-11 07:26:27 +02:00
micheleandCursor 3f6082ae6d Run ImpedenceFinder Z0 on routed signal nets during project analysis.
Pipeline samples PCB traces when stackup εr/h is present; power/ground are skipped. Named nets can be re-analyzed from the Impedance tab.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-11 00:21:49 +02:00
micheleandCursor 796cd9d8a2 Flag keepout tracks in the courtyard and mark the plan map OK.
PS-PLC-004 is a foreign net endpoint inside the KiCad courtyard. The lista↔codice table and sprints 0–10+ get an OK column where the hole is closed without invented millimetres.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-11 00:11:02 +02:00
micheleandCursor 412c32e9b2 Measure crystal load-cap and track path against max_distance_mm.
X1 uses the same proximity rule as ICs. A detour is shortest path on PCB segments versus that millimetre, not a guessed loop ratio.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-10 23:59:01 +02:00
micheleandCursor ba2a5c1b29 Warn when same_layer decoupling is on the opposite copper.
PS-PLC-003 uses the same_layer flag plus F/B layers from the PCB. A via in the courtyard is enough; an unset flag skips.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-10 23:45:59 +02:00
micheleandCursor 0fafbbbb06 Count thermal vias in the courtyard against min_via_count.
Skip without courtyard geometry or a numeric count — no pad-radius default. Tests use simple_project plus explicit coordinates as parameters.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-10 23:39:05 +02:00
micheleandCursor 45e820fabc Add PCB intra-pair skew only when the datasheet gives millimetres.
PS-SI-001 and decoupling skip without a numeric layout_rule. Tests use simple_project nets, not invented USBPHY boards.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-10 23:34:57 +02:00
micheleandCursor be0fed7979 Add PCB decoupling-proximity check from datasheet layout_rules.
PS-PLC-001 fires only with a LayoutGraph: 15 mm vs a 2 mm rule is an error, a 1 mm cap is silent, and a null millimetre uses the declared 3 mm default as WARNING.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-10 23:26:10 +02:00
micheleandCursor de15402309 Add finding review states, ECO export, and a report release signature.
Accepted findings become ECO rows with a required reason; false-positive and wontfix stay off the change list. Pipeline re-runs keep dispositions by finding_id like comments.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-10 23:21:36 +02:00
micheleandCursor 6fc2ac583d Integrate ImpedenceFinder closed-form Z0 into the project Impedance tab.
Use the vendored Hammerstad-Jensen/Cohn engine for microstrip, stripline, and coupled-diff advice. Skip OpenEMS/pcbnew and refuse CPWG rather than inventing a number.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-10 23:14:57 +02:00
micheleandCursor 3e43bb6ecb Force every LLM stage onto DeepSeek and stop Anthropic Console uploads.
PROVIDER_*=anthropic and Claude fallbacks now coerce to DeepSeek, skills stay local, and default_model_version bumps without upload_skills.py.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-10 22:56:49 +02:00
micheleandCursor 7aed64cae5 Add lifecycle, errata, internal-features, and layout_rules checks.
Cache distributor EOL/NRND/RoHS without inventing replacements, flag catalogued errata pull-ups only, and store layout_rules with a closed kind enum so millimetres stay null unless the datasheet stated a number.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-10 22:48:27 +02:00
micheleandCursor aa375349bd Add KiCad cad-bridge JSON and an action plugin for finding focus.
Write pinscope-findings.json from the report, keep symbol uuid and child-sheet on the graph, and let the pcbnew plugin jump to a footprint or show the schematic uuid when IPC focus is unavailable.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-10 22:40:28 +02:00
micheleandCursor 78013bd404 Add power-margin, PG-to-EN sequencing, and DNP enable checks.
Compare only specified IQ plus I_load to Iout_max and series-R drop, flag sequencing only when power_sequence is in specs, and treat DNP as a fitted-variant graph so a missing enable pull is ERROR only when the BOM actually marks DNP.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-10 22:34:06 +02:00
micheleandCursor a45a06e761 Add schematic filter topology and LDO/resistor thermal checks.
Match RC/LC/π/T without inventing fc, compare to ADC rate only when specs list it, and skip ferrite DCR unless the IC gives a limit. LDO Tj uses I_load not Iout_max, and missing θJA stays INFO.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-10 22:28:40 +02:00
micheleandCursor 4403c38d96 Add DC-bias C_eff stima to derating and INFO when bulk C has no HF ceramic.
Keep both as labelled estimates: no Murata lot curve and no invented Z(f) target without f_sw.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-10 22:23:05 +02:00
micheleandCursor 4fca789517 Size I2C pull-ups, flag NRST pull-downs, and distinguish LDO Cout from MCU decoupling.
Keep these as WARNING hints with wide bounds so a 4.7 kΩ or 100 nF VDD cap is not treated as a datasheet µF error.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-10 22:07:14 +02:00
micheleandCursor e4fd6c3849 Ship Sprint 0 CAD foundations so findings, KiCad hierarchy, BOM match, eval, and optional PCB ingest have a stable contract.
Extend Finding with rule_id/net/pins, flatten multi-sheet .kicad_sch, flag MPN mismatches, score simple_project, and parse .kicad_pcb without running layout DRC.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-10 21:54:37 +02:00
micheleandCursor 61f85f519b Default to DeepSeek V4.1 Flash, show API cost in USD, and re-analyze after replacing BOM and netlist.
V4.1 is natively multimodal so every stage uses deepseek-flash; pricing and the UI now surface dollars instead of empty credits. KiCad netlists and neighborhood fingerprints land in the same cut so a second run can keep the project and skip unchanged ICs.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-10 20:55:35 +02:00
micheleandCursor d454cf75af Tie decoupling and I2C checks to pintable pin names, not mux tables.
Ignore enable straps on a power rail, NC nets, and SPI aliases; treat FB as an inductor and RN as a resistor so pull-ups and beads classify correctly.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-08-28 21:00:04 +02:00
micheleandCursor edbb47a08b Resolve passives from catalog, BOM value, and Murata LQW18AN without an LLM.
Skip the model (and the credit gate) when LCSC/DigiKey already list C/V/Z, when the BOM value is a single R/C/L/FB token, or when the MPN is an LQW18AN inductor. Ferrite beads keep impedance, not invented henries; value-only specs stay out of the shared library.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-08-28 20:25:34 +02:00
micheleandCursor 2113e3975e Finish datasheet acquisition: more vendors, Mouser, browser download links.
Add Microchip/Murata/Silicon Labs URL tables, optional Mouser search, and suggested URLs on a miss so the wizard can open PDFs in the user's browser when the VPS is blocked.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-08-28 19:42:50 +02:00
micheleandCursor 7a255a9807 Treat 3V3_/1V8_ nets as power and ignore SPI pins aliased as SDA/SCL.
Hub Audio pull-ups sit on 3V3_DIGITAL typed as signal, and ADAU/TAC5212 SPI pins list SDA in the name — both produced false I2C/reset warnings.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-08-28 17:09:59 +02:00
micheleandCursor b1ee445da8 Add deterministic decoupling, I2C pull-up, and reset-float checks.
Flag supply nets with no cap to ground and open-drain I2C/reset nets with no pull-up, without guessing datasheet capacitor values.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-08-28 16:59:32 +02:00
micheleandCursor d6b8b0086c Reconstruct datasheet pages with reading-order blocks and table markdown.
DeepSeek review/extraction was using raw get_text; sparse pin drawings now get vision slots and quote checks share the same page text.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-08-28 16:29:52 +02:00
micheleandCursor 6bde06d2cc Harden datasheet downloads and try more manufacturer PDF URLs.
Follow HTML interstitials to a matching .pdf, send a real Referer, retry http as https, and probe TI gpn plus Espressif/ST/ADI/NXP/onsemi paths when LCSC is blocked.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-08-28 16:06:38 +02:00
micheleandCursor 53db287ab4 Verify review quotes against datasheet PDF text and extract ESD Vrwm/polarity.
ERROR/WARNING without a real citation are demoted to Unverified so invented topologies like a unidirectional TPD2E007 clamp cannot ship as ERROR.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-08-28 15:43:14 +02:00
micheleandCursor 4c54d064d3 Add missing simple_mpn_types on PipelineContext so BOM parse can classify crystals and discretes.
Co-authored-by: Cursor <cursoragent@cursor.com>
2026-08-28 11:09:43 +02:00