Classify strap/bootstrap caps and drop unclassified satellites.
EN/BOOT/REGN/PMID bypass and flying bootstrap caps get real roles; other is omitted from assemble_order. Co-authored-by: Cursor <cursoragent@cursor.com>
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Cursor
@@ -38,6 +38,30 @@ RoleHint = Literal[
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"other",
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]
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# Roles kept in satellites / assemble_order. Unclassified "other" is dropped.
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_ASSEMBLE_ROLES = frozenset({
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"decoupling", "bulk", "load_cap", "filter", "pullup",
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"series", "divider", "bridge", "crystal",
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})
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_POWER_SAT_ROLES = frozenset({"decoupling", "bulk", "filter", "pullup"})
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_SKIP_OTHER_TYPES = frozenset({
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ComponentType.CONNECTOR,
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ComponentType.SWITCH,
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ComponentType.TEST_POINT,
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ComponentType.FIDUCIAL,
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ComponentType.MECHANICAL,
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})
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# Bias / charge-pump / bootstrap nets often stay SIGNAL in the graph.
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_BIAS_NET_RE = re.compile(
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r"(?:^|[_/\-])(REGN|PMID|BTST|BOOT|SW|LX|BST|VREG|VLDO|VREF)"
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r"(?:$|[_/\-\d])",
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re.IGNORECASE,
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)
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_STRAP_NET_RE = re.compile(
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r"(?:EN|ENABLE|RESET|NRST|BOOT|CHIP_PU|GPIO0)",
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re.IGNORECASE,
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)
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_BULK_F = 1e-6 # >= 1 µF → bulk candidate
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_XTAL_RE = re.compile(
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r"(?:^|[_/])(X(?:IN|OUT)|XTAL|OSC|HFX(?:IN|OUT)|LFX(?:IN|OUT)|CLK(?:IN|OUT)?)(?:$|[_/\d])",
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@@ -177,16 +201,6 @@ def _ic_rank(comp: Component) -> int:
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return 9
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_POWER_SAT_ROLES = frozenset({"decoupling", "bulk", "filter", "pullup"})
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_SKIP_OTHER_TYPES = frozenset({
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ComponentType.CONNECTOR,
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ComponentType.SWITCH,
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ComponentType.TEST_POINT,
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ComponentType.FIDUCIAL,
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ComponentType.MECHANICAL,
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})
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def _group_for_ic(
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graph: DesignGraph,
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ref: str,
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@@ -210,12 +224,17 @@ def _group_for_ic(
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continue
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role = _role_hint(graph, comp, cons, other, net_name)
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sat_nets = {n for n in other.pins.values() if n}
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# Keep decoupling/bulk/filter/pullup on the IC primary rail only —
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# otherwise an LDO on 3V3 also inherits VSYS input caps/inductors.
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if role in _POWER_SAT_ROLES and primary and primary not in sat_nets:
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continue
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# Drop power-role parts that sit on a *different* named power rail
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# (LDO must not inherit VSYS input caps). Strap/bias caps with no
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# typed POWER net still attach.
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if role in _POWER_SAT_ROLES and primary:
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sat_power = {n for n in sat_nets if _is_power_net(graph, n)}
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if sat_power and primary not in sat_power:
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continue
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if role == "other" and other.component_type in _SKIP_OTHER_TYPES:
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continue
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if role not in _ASSEMBLE_ROLES:
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continue
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sat_map[oref] = PlacementSatellite(
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ref=oref,
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component_type=other.component_type.value,
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@@ -298,22 +317,40 @@ def _role_hint(
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if other.component_type == ComponentType.CAPACITOR:
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if _looks_xtal_net(via_net) or _ic_pin_is_xtal(cons, via_net, ic):
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return "load_cap"
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others = {n for n in other.pins.values() if n != via_net}
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if any(_is_ground_net(graph, n) for n in others) and (
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_is_power_net(graph, via_net) or _net_is_ic_supply(graph, ic, cons, via_net)
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):
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farads = _cap_farads(other)
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return "bulk" if farads is not None and farads >= _BULK_F else "decoupling"
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pin_nets = {n for n in other.pins.values() if n}
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gnd_nets = {n for n in pin_nets if _is_ground_net(graph, n)}
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live = [n for n in pin_nets if n not in gnd_nets]
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ic_nets = {n for n in ic.pins.values() if n}
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# Bootstrap / flying cap between two pins of this IC.
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if len(live) == 2 and all(n in ic_nets for n in live):
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return "bridge"
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# Cap to GND on an IC pin / bias / strap / power net → local bypass.
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if gnd_nets and len(live) == 1:
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net = live[0]
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if (
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net in ic_nets
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or _is_power_net(graph, net)
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or _net_is_ic_supply(graph, ic, cons, net)
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or _BIAS_NET_RE.search(net or "")
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or _STRAP_NET_RE.search(net or "")
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):
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farads = _cap_farads(other)
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return "bulk" if farads is not None and farads >= _BULK_F else "decoupling"
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return "other"
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if other.component_type == ComponentType.INDUCTOR:
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return "filter"
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if other.component_type == ComponentType.RESISTOR:
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nets = list(dict.fromkeys(other.pins.values()))
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nets = list(dict.fromkeys(n for n in other.pins.values() if n))
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if len(nets) == 2:
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a, b = nets
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if _is_power_net(graph, a) or _is_power_net(graph, b):
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if _is_power_net(graph, a) or _is_power_net(graph, b) or (
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_BIAS_NET_RE.search(a or "") or _BIAS_NET_RE.search(b or "")
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):
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if _is_ground_net(graph, a) or _is_ground_net(graph, b):
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return "divider"
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return "pullup"
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@@ -321,12 +358,12 @@ def _role_hint(
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if a in ic_nets and b in ic_nets:
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return "bridge"
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if a in ic_nets or b in ic_nets:
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# Set resistor / NTC leg to GND stays series (placement-local).
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return "series"
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return "other"
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return "other"
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def _looks_xtal_net(name: str) -> bool:
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return bool(_XTAL_RE.search(name or ""))
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@@ -44,6 +44,15 @@ Obiettivo unico: **routing migliore** (loop corti, meno crossing, canali liberi)
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| 5 | `assemble_order` dominio → chip → gruppi (contratto packer) | F1 metadato |
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| 6 | Packing mm / zone PCB / export | **F2 partial** — `placement_pack.json` (skip senza PCB + `max_distance_mm`); zone/export dopo |
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### Roadmap Placement (da qui a coordinate utili)
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1. **F1 polish (ora)** — satelliti classificatì; `other` nascosti; Domains/Rails = primary rail.
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2. **C4 fill** — riestrazione IC → `layout_rules` con `max_distance_mm` dove il PDF lo dice (skill 1.10.0).
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3. **PCB gate** — upload `.kicad_pcb` → `layout_graph.json` (footprint xy già usati da PS-PLC*).
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4. **F2 pack v1** — per ogni `decoupling_proximity` numerica: proporre xy satellite entro `max_distance_mm` dal pad (già skeleton); UI Pack lista proposte.
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5. **F2 pack v2** — collisioni courtyard, stesso layer, ordine `assemble_order` per dominio, ancore IC fissi se già piazzati.
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6. **F2 export** — scrivere posizioni proposte in file/plugin (pcbnew) senza muovere rame; `placement_check` resta verifica.
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Output F1: `functional_groups.json` scritto in `graph_build`. Pipeline parallela Placement (`POST …/placement/start`) riscrive anche `placement_plan.json` senza toccare lo `status` di analisi, poi tenta F2 pack. Verifica PCB esistente resta `placement_check` (PS-PLC*) — non confondere con packing.
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---
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@@ -2,6 +2,13 @@
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What's new in Pinscope.
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## 2.28.10 — 2026-09-13 — Classify strap/bootstrap satellites; hide other
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Caps on EN/BOOT/REGN/PMID and bootstrap caps between IC pins get real roles. Unclassified `other` parts are dropped from satellites and assemble_order.
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- [Changed] `_role_hint` classifies GND bypass on bias/strap nets and flying bootstrap caps.
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- [Changed] Assemble / IC groups omit `role_hint=other`.
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## 2.28.9 — 2026-09-13 — Cleaner Domains / Power rails membership
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Power rails follow primary domain only. IC satellites for decoupling/bulk/filter/pullup stay on the IC’s primary supply rail (LDO 3V3 no longer inherits VSYS input caps). Connectors/switches drop out of noisy “other” satellites.
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@@ -85,7 +85,7 @@ def test_ldo_power_satellites_stay_on_primary_rail():
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reference="U1", value="LDO", footprint="",
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component_type=ComponentType.IC,
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component_subtype="ic.power.ldo",
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pins={"1": "VSYS", "2": "3V3_DIGITAL", "3": "GND"},
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pins={"1": "VSYS", "2": "3V3_DIGITAL", "3": "GND", "4": "EN"},
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),
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"C_in": Component(
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reference="C_in", value="10u", footprint="",
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@@ -105,12 +105,32 @@ def test_ldo_power_satellites_stay_on_primary_rail():
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pins={"1": "3V3_DIGITAL", "2": "GND"},
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specs=CapacitorSpecs(value_farads=100e-9, value_formatted="100nF"),
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),
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"C_en": Component(
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reference="C_en", value="1u", footprint="",
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component_type=ComponentType.CAPACITOR,
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pins={"1": "EN", "2": "GND"},
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specs=CapacitorSpecs(value_farads=1e-6, value_formatted="1uF"),
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),
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"C_boot": Component(
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reference="C_boot", value="47n", footprint="",
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component_type=ComponentType.CAPACITOR,
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pins={"1": "BTST", "2": "SW"},
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specs=CapacitorSpecs(value_farads=47e-9, value_formatted="47nF"),
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),
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"J1": Component(
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reference="J1", value="USB", footprint="",
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component_type=ComponentType.CONNECTOR,
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pins={"1": "3V3_DIGITAL", "2": "GND"},
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),
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"C_noise": Component(
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reference="C_noise", value="100n", footprint="",
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component_type=ComponentType.CAPACITOR,
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pins={"1": "orphan", "2": "somewhere"},
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),
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}
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# Extend U1 pins for bootstrap
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components["U1"].pins["5"] = "BTST"
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components["U1"].pins["6"] = "SW"
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nets = {
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"VSYS": Net(
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name="VSYS", net_type=NetType.POWER,
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@@ -128,23 +148,57 @@ def test_ldo_power_satellites_stay_on_primary_rail():
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PinConnection(component_ref="J1", pin_number="1"),
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],
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),
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"EN": Net(
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name="EN", net_type=NetType.SIGNAL,
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pins=[
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PinConnection(component_ref="U1", pin_number="4"),
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PinConnection(component_ref="C_en", pin_number="1"),
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],
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),
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"BTST": Net(
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name="BTST", net_type=NetType.SIGNAL,
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pins=[
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PinConnection(component_ref="U1", pin_number="5"),
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PinConnection(component_ref="C_boot", pin_number="1"),
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],
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),
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"SW": Net(
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name="SW", net_type=NetType.SIGNAL,
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pins=[
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PinConnection(component_ref="U1", pin_number="6"),
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PinConnection(component_ref="C_boot", pin_number="2"),
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],
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),
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"GND": Net(
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name="GND", net_type=NetType.GROUND,
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pins=[
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PinConnection(component_ref="U1", pin_number="3"),
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PinConnection(component_ref="C_in", pin_number="2"),
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PinConnection(component_ref="C_out", pin_number="2"),
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PinConnection(component_ref="C_en", pin_number="2"),
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PinConnection(component_ref="J1", pin_number="2"),
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],
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),
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"orphan": Net(
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name="orphan", net_type=NetType.SIGNAL,
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pins=[PinConnection(component_ref="C_noise", pin_number="1")],
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),
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"somewhere": Net(
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name="somewhere", net_type=NetType.SIGNAL,
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pins=[PinConnection(component_ref="C_noise", pin_number="2")],
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),
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}
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report = build_functional_groups(DesignGraph(components=components, nets=nets))
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u1 = next(g for g in report.groups if g.ref == "U1")
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sat = {s.ref: s.role_hint for s in u1.satellites}
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assert "C_out" in sat
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assert sat.get("C_out") == "decoupling"
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assert sat.get("C_en") == "bulk"
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assert sat.get("C_boot") == "bridge"
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assert "C_in" not in sat
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assert "L1" not in sat
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assert "J1" not in sat
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assert "C_noise" not in sat
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assert "other" not in sat.values()
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def test_multi_rail_board_does_not_collapse_to_one_domain():
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