Size I2C pull-ups, flag NRST pull-downs, and distinguish LDO Cout from MCU decoupling.
Keep these as WARNING hints with wide bounds so a 4.7 kΩ or 100 nF VDD cap is not treated as a datasheet µF error. Co-authored-by: Cursor <cursoragent@cursor.com>
This commit is contained in:
@@ -10,13 +10,18 @@ from __future__ import annotations
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import re
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from backend.pinscopex.models import (
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CapacitorSpecs,
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Component,
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ComponentConstraints,
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ComponentType,
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DesignGraph,
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Finding,
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NetType,
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ResistorSpecs,
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)
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from backend.pinscopex.validate import _match_constraints
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from backend.pinscopex.led_current_check import _parse_resistance
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from backend.pinscopex.resolve_passives import _parse_spice_value
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_SUPPLY_PIN_RE = re.compile(
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r"(?:^|[_/])(VDD|VCC|VDDA|VDDD|VDDIO|DVDD|AVDD|IOVDD|VDD33|VDD18|"
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@@ -38,13 +43,27 @@ _NC_NET_RE = re.compile(
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r"^(?:n/?c|n\.c\.|nc|unconnected|no[_-]?connect|not[_-]?connected)$",
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re.IGNORECASE,
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)
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_OUT_PIN_RE = re.compile(
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r"(?:^|[_/])(VOUT|V_OUT|VO|VREG|SWOUT)(?:$|[_/\d])",
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re.IGNORECASE,
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)
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_ACTIVE_LOW_RESET_RE = re.compile(
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r"(?:N/?RST|NRST|NRESET|RESET[_-]?N|RSTN)\b",
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re.IGNORECASE,
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)
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# NXP UM10204-style Rp window, widened so 2.2k–10k never false-positives.
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_RP_MIN_OHM = 1_000.0
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_RP_MAX_OHM = 22_000.0
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_VDD_MIN_FARADS = 50e-9
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_VOUT_MIN_FARADS = 0.47e-6
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def check_supply_decoupling(
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graph: DesignGraph,
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constraints_map: dict[str, ComponentConstraints],
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) -> list[Finding]:
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"""WARNING when an IC supply net has no capacitor to ground."""
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"""WARNING when an IC supply/VOUT net has no capacitor to ground, or
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only farads well below a typical Cin/Cout when every cap is valued."""
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findings: list[Finding] = []
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seen_nets: set[str] = set()
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for ref, comp in sorted(graph.components.items()):
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@@ -56,38 +75,77 @@ def check_supply_decoupling(
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continue
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if _is_nc_net(net_name):
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continue
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if not _is_ic_supply_pin(graph, cons, pin_num, net_name):
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role = None
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if _is_ic_supply_pin(graph, cons, pin_num, net_name):
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role = "supply"
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elif _is_regulator_output_pin(cons, pin_num):
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role = "output"
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if role is None:
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continue
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seen_nets.add(net_name)
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if _capacitor_to_ground(graph, net_name):
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continue
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pin_label = _pin_label(cons, pin_num, net_name)
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findings.append(Finding(
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designator=ref,
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mpn=comp.mpn or "",
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aspect="decoupling",
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source="supply_decoupling_check",
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source_page=None,
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status="WARNING",
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finding=(
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f"{ref} supply net '{net_name}' ({pin_label}) has no "
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f"capacitor to ground."
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),
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why=(
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f"Pin {pin_label} sits on '{net_name}' and that net has no "
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f"capacitor whose other end is ground. Local decoupling "
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f"may be missing (or only present on a different island "
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f"behind a ferrite)."
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),
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recommendation=(
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f"Add a decoupling capacitor from '{net_name}' to ground "
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f"near {ref}."
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),
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reference="netlist topology",
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net=net_name,
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pins=[f"{ref}.{pin_num}"],
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rule_id="PS-DEC-001",
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))
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if not _capacitor_to_ground(graph, net_name):
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findings.append(Finding(
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designator=ref,
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mpn=comp.mpn or "",
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aspect="decoupling",
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source="supply_decoupling_check",
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source_page=None,
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status="WARNING",
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finding=(
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f"{ref} supply net '{net_name}' ({pin_label}) has no "
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f"capacitor to ground."
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if role == "supply"
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else (
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f"{ref} regulator output '{net_name}' ({pin_label}) "
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f"has no Cout capacitor to ground."
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)
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),
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why=(
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f"Pin {pin_label} sits on '{net_name}' and that net has no "
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f"capacitor whose other end is ground. Local decoupling "
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f"may be missing (or only present on a different island "
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f"behind a ferrite)."
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),
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recommendation=(
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f"Add a decoupling capacitor from '{net_name}' to ground "
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f"near {ref}."
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),
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reference="netlist topology",
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net=net_name,
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pins=[f"{ref}.{pin_num}"],
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rule_id="PS-DEC-001",
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))
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continue
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min_f = _VOUT_MIN_FARADS if role == "output" else _VDD_MIN_FARADS
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max_c = _max_known_cap_farads(graph, net_name)
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if max_c is not None and max_c < min_f:
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findings.append(Finding(
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designator=ref,
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mpn=comp.mpn or "",
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aspect="decoupling",
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source="supply_decoupling_check",
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source_page=None,
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status="WARNING",
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finding=(
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f"{ref} net '{net_name}' ({pin_label}) only has "
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f"{max_c * 1e6:.3g} µF to ground; typical "
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f"{'Cout' if role == 'output' else 'decoupling'} is larger."
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),
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why=(
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"Cap values are known on this net and the largest is "
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"below a wide typical minimum. This is not a datasheet "
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"µF requirement — treat as a sizing hint."
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),
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recommendation=(
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f"Add bulk capacitance on '{net_name}' (often ≥1 µF on "
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f"LDO VOUT, ≥100 nF on MCU VDD) if the datasheet agrees."
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),
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reference="netlist topology",
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net=net_name,
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pins=[f"{ref}.{pin_num}"],
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rule_id="PS-DEC-002",
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))
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return findings
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@@ -114,6 +172,38 @@ def check_i2c_pullups(
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if net and net.net_type in (NetType.POWER, NetType.GROUND):
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continue
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if _resistor_to_power(graph, net_name):
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ohms = _parallel_pullup_ohms(graph, net_name)
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if ohms is not None and (
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ohms < _RP_MIN_OHM or ohms > _RP_MAX_OHM
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):
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pin_label = _pin_label(cons, pin_num, net_name)
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findings.append(Finding(
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designator=ref,
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mpn=comp.mpn or "",
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aspect="i2c_pullup",
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source="i2c_pullup_check",
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source_page=None,
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status="WARNING",
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finding=(
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f"I2C net '{net_name}' ({ref} {pin_label}) pull-up "
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f"is {ohms:.3g} Ω (wide NXP-style band "
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f"{_RP_MIN_OHM:.0f}–{_RP_MAX_OHM:.0f} Ω)."
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),
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why=(
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"UM10204 Rp depends on Vdd, Iol and bus capacitance. "
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"This bound is wide on purpose; 2.2–10 kΩ at 3.3 V "
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"is typical. Unknown resistor values are not sized."
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),
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recommendation=(
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f"Use a pull-up on '{net_name}' inside "
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f"{_RP_MIN_OHM:.0f}–{_RP_MAX_OHM:.0f} Ω unless the "
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f"bus capacitance/Iol calculation says otherwise."
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),
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reference="NXP UM10204 (wide bound)",
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net=net_name,
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pins=[f"{ref}.{pin_num}"],
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rule_id="PS-I2C-002",
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))
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continue
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pin_label = _pin_label(cons, pin_num, net_name)
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findings.append(Finding(
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@@ -167,9 +257,38 @@ def check_reset_pullups(
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continue
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if _other_ic_on_net(graph, net_name, ref):
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continue
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pin_label = _pin_label(cons, pin_num, net_name)
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if _is_active_low_reset(cons, pin_num, net_name) and _resistor_to_ground(
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graph, net_name
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):
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findings.append(Finding(
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designator=ref,
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mpn=comp.mpn or "",
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aspect="reset_pullup",
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source="reset_pullup_check",
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source_page=None,
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status="WARNING",
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finding=(
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f"{ref} active-low reset '{net_name}' ({pin_label}) "
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f"has a pull-down to ground."
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),
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why=(
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"An active-low NRST/RESET_N pin held down by a resistor "
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"will sit in reset unless a stronger pull-up wins. "
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"Datasheets that omit an internal pull-up expect a pull-up, "
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"not a pull-down."
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),
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recommendation=(
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f"Remove the pull-down on '{net_name}' or replace it "
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f"with a pull-up to the I/O rail."
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),
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reference="netlist topology",
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net=net_name,
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pins=[f"{ref}.{pin_num}"],
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rule_id="PS-RST-002",
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))
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if _resistor_to_power(graph, net_name):
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continue
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pin_label = _pin_label(cons, pin_num, net_name)
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findings.append(Finding(
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designator=ref,
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mpn=comp.mpn or "",
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@@ -311,6 +430,90 @@ def _resistor_to_power(graph: DesignGraph, net_name: str) -> bool:
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return False
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def _resistor_to_ground(graph: DesignGraph, net_name: str) -> bool:
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for ref in graph.components_on_net(net_name):
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comp = graph.components[ref]
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if comp.component_type != ComponentType.RESISTOR:
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continue
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others = {n for n in comp.pins.values() if n != net_name}
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if any(_is_ground_net(graph, n) for n in others):
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return True
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return False
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def _resistor_ohms(comp: Component) -> float | None:
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specs = comp.specs
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if isinstance(specs, ResistorSpecs) and specs.value_ohms > 0:
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return float(specs.value_ohms)
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return _parse_resistance(comp.value)
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def _parallel_pullup_ohms(graph: DesignGraph, net_name: str) -> float | None:
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acc = 0.0
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known = 0
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for ref in graph.components_on_net(net_name):
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comp = graph.components[ref]
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if comp.component_type != ComponentType.RESISTOR:
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continue
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others = {n for n in comp.pins.values() if n != net_name}
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if not any(_is_power_net(graph, n) for n in others):
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continue
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ohms = _resistor_ohms(comp)
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if ohms is None or ohms <= 0:
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return None
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acc += 1.0 / ohms
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known += 1
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if not known or acc <= 0:
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return None
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return 1.0 / acc
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def _cap_farads(comp: Component) -> float | None:
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specs = comp.specs
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if isinstance(specs, CapacitorSpecs) and specs.value_farads > 0:
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return float(specs.value_farads)
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raw = (comp.value or "").strip()
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if not raw:
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return None
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try:
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v = _parse_spice_value(raw)
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except ValueError:
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return None
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return v if v > 0 else None
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def _max_known_cap_farads(graph: DesignGraph, power_net: str) -> float | None:
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known: list[float] = []
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any_unknown = False
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for ref in graph.capacitors_on_net(power_net):
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cap = graph.components[ref]
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others = {n for n in cap.pins.values() if n != power_net}
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if not any(_is_ground_net(graph, n) for n in others):
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continue
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farads = _cap_farads(cap)
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if farads is None:
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any_unknown = True
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continue
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known.append(farads)
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if any_unknown or not known:
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return None
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return max(known)
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def _is_regulator_output_pin(
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cons: ComponentConstraints | None, pin_num: str,
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) -> bool:
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return any(_OUT_PIN_RE.search(t) for t in _pin_name_tokens(cons, pin_num))
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def _is_active_low_reset(
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cons: ComponentConstraints | None, pin_num: str, net_name: str,
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) -> bool:
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if _ACTIVE_LOW_RESET_RE.search(net_name or ""):
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return True
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return any(_ACTIVE_LOW_RESET_RE.search(t) for t in _pin_name_tokens(cons, pin_num))
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def _other_ic_on_net(graph: DesignGraph, net_name: str, self_ref: str) -> bool:
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for ref in graph.components_on_net(net_name):
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if ref == self_ref:
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