micheleandClaude Sonnet 5
91bbbe2fe5
Final milestone of docs/v2-description.md's §33 roadmap, scoped exactly to its own mandate: optimize only on data already gathered in M1-M9, across the pipeline/P_IN/processor-count/scheduling/memory axes - no speculative new features. Three concrete, data-driven results: 1. N_SLOTS=8 (numero processor axis): real synthesis + nextpnr-ecp5 P&R for dataflow_core at N_SLOTS=8, extending M7's N_SLOTS=2/4 sweep to the real DSP ceiling DEC-0005 predicted. 92.63 MHz POST-P&R, PASS at 80MHz, DSP 64/72 (88.9%). DEC-0012 recommends N_SLOTS=8 as the practical ceiling for P_IN=8 on the LFE5U-45F-8BG381. 2. ACC_WIDTH 24 vs 32 (pipeline axis): a real 6-seed nextpnr-ecp5 placement sweep (reusing already-synthesized netlists, no new synthesis needed) resolves EXP-0002's single-seed inconclusiveness. ACC_WIDTH=24 wins on both mean Fmax (+6.2%, 180.71 vs 170.12 MHz) and seed-to-seed variance (~3.4x tighter), on top of its already-known resource advantage. DEC-0013 recommends ACC_WIDTH=24 as the new default. 3. Stall %/utilization (scheduling/memory axes): testbench-only cycle counters added to tb_neural_multiprocessor.v (no RTL touched) close DEC-0011's deferred measurement gap with real data - shared PSRAM port 81.7% utilized, slot 0 95.2%, slot 1 65.2%, no conclusive evidence of harmful fixed-priority starvation at this scale. The 10-milestone V2 roadmap (docs/v2-description.md §33) is now complete end-to-end: real Verilator simulation, real Yosys synthesis, real nextpnr-ecp5 place & route for every milestone, fully logged (EXP-0001..EXP-0013, DEC-0001..DEC-0013, ERR-0001..ERR-0008) with no invented results (§30) and V1 kept frozen and untouched throughout (§1/§34). Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
104 lines
5.5 KiB
Plaintext
104 lines
5.5 KiB
Plaintext
# V2 timing log -- solo append, mai troncato/sovrascritto (vedi README.md)
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# Nessuna entry ancora -- popolato incrementalmente man mano che avanza lo sviluppo V2.
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[2026-09-05] EXP-0001 -- neural_processor (P_IN=8, ACC_WIDTH=32)
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nextpnr-ecp5 --45k --package CABGA381 --speed 8 --freq 80
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--lpf-allow-unconstrained
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Fmax: 183.12 MHz -- PASS at 80 MHz (real place&route measurement)
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Critical path: job_ready -> TRELLIS_IO output pad (i.e. the design's
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own logic is NOT the bottleneck at this Fmax -- an unconstrained
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output pin dominates; a real system-level Fmax will differ once
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this signal is consumed on-chip instead of driven to a pad in
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isolation). Log: hardware/v2/synthesis/neural_processor_p8/nextpnr.log
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WNS/TNS: not reported by this nextpnr version in this invocation.
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[2026-09-05] EXP-0002 -- neural_processor (P_IN=8, ACC_WIDTH=24)
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Same command as above, ACC_WIDTH=24 build.
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Fmax: 176.21 MHz -- PASS at 80 MHz (real place&route measurement)
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Delta vs ACC_WIDTH=32: -6.91 MHz (-3.8%) despite FEWER resources --
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attributed to placement noise, not a real architectural effect
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(no seed sweep run to confirm either way -- see experiments.log
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EXP-0002 and benchmark.log). Log: hardware/v2/synthesis/
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neural_processor_p8_acc24/nextpnr.log
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[2026-09-05] EXP-0003 -- N_PROCESSORS sweep (P_IN=8), real nextpnr-ecp5
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--45k --package CABGA381 --speed 8 --freq 80 --lpf-allow-unconstrained
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N=1: Fmax=159.11 MHz PASS MULT18X18D 8/72 (11%)
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N=2: Fmax=149.59 MHz PASS MULT18X18D 16/72 (22%)
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N=4: Fmax=151.01 MHz PASS MULT18X18D 32/72 (44%)
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N=8: Fmax=134.70 MHz PASS MULT18X18D 64/72 (88%)
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TRELLIS_IO stays at 18/245 (7%) throughout (harness has only
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clk/rst/seed/checksum as real pins, by design -- see ERR-0005).
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See decisions.log DEC-0005: DSP, not Fmax or LUT/FF, is the resource
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that will first prevent scaling N_PROCESSORS further at P_IN=8.
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[2026-09-05] EXP-0004 -- default-depth buffer configs, real nextpnr-ecp5
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activation_buffer (D=4096): Fmax=325.20 MHz PASS
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weight_buffer (D=512): Fmax=339.67 MHz PASS
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result_buffer (D=4096): Fmax=325.20 MHz PASS
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All far above the 80MHz target -- buffers are not a timing concern in
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isolation at these depths.
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[2026-09-05] EXP-0005 -- memory_manager + prefetch_engine (via
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harness_memory_manager.v, see errors.log ERR-0005 for why a harness
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was needed), real nextpnr-ecp5 --45k --package CABGA381 --speed 8
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--freq 80 --lpf-allow-unconstrained
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Fmax: 165.86 MHz -- PASS at 80MHz (real place&route measurement)
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[2026-09-05] EXP-0006 -- neural_director (via harness_neural_director.v,
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see errors.log ERR-0005 for why), real nextpnr-ecp5 --45k --package
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CABGA381 --speed 8 --freq 80 --lpf-allow-unconstrained
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Fmax: 250.50 MHz -- PASS at 80MHz (real place&route measurement)
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[2026-09-05] EXP-0007 -- dependency_manager (N_NODES=16, standalone,
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no harness needed), real nextpnr-ecp5 --45k --package CABGA381
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--speed 8 --freq 80 --lpf-allow-unconstrained
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Fmax: 155.30 MHz -- PASS at 80MHz (real place&route measurement)
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[2026-09-05] EXP-0008 -- dataflow_core (via harness_dataflow_core.v,
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see errors.log ERR-0005 for why a harness was needed), real
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nextpnr-ecp5 --45k --package CABGA381 --speed 8 --freq 80
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--lpf-allow-unconstrained
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N_SLOTS=2: Fmax = 165.15 MHz -- PASS at 80MHz (real place&route)
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N_SLOTS=4: Fmax = 133.19 MHz -- PASS at 80MHz (real place&route)
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Fmax drops as N_SLOTS grows (more concurrent memory_manager+
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neural_processor instances competing for the same routing fabric
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around the shared neural_director/dependency_manager hub) -- both
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configs still clear the 80MHz target with real margin.
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[2026-09-05] EXP-0009 -- neural_multiprocessor (M8, N_SLOTS=2, real
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standalone synthesis, no harness needed), real nextpnr-ecp5 --45k
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--package CABGA381 --speed 8 --freq 80 --lpf-allow-unconstrained
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Fmax: 142.45 MHz -- PASS at 80MHz (real place&route measurement)
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[2026-09-05] EXP-0011 -- dataflow_core N_SLOTS=8 (via
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harness_dataflow_core.v), real nextpnr-ecp5 --45k --package CABGA381
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--speed 8 --freq 80 --lpf-allow-unconstrained
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Fmax: 92.63 MHz -- PASS at 80MHz (real place&route measurement), but
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with a much thinner margin than N_SLOTS=2 (165.15 MHz) or N_SLOTS=4
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(133.19 MHz) -- Fmax falls monotonically with N_SLOTS (165.15 ->
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133.19 -> 92.63 MHz for N_SLOTS=2/4/8) as routing congestion around
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the shared neural_director/dependency_manager hub grows, while DSP
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usage (88.9% at N_SLOTS=8) approaches its hard ceiling at the same
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time -- see decisions.log DEC-0012.
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[2026-09-05] EXP-0012 -- ACC_WIDTH 24 vs 32 real placement-seed sweep
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(M10, "pipeline" axis, resolving EXP-0002's single-seed
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inconclusiveness), 5 additional real nextpnr-ecp5 seeds (1-5) plus the
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original default-seed run (EXP-0001/EXP-0002), same synthesized
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netlists (hardware/v2/synthesis/neural_processor_p8/top.json and
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neural_processor_p8_acc24/top.json), --45k --package CABGA381 --speed
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8 --freq 80 --lpf-allow-unconstrained
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ACC_WIDTH=32: seeds [default,1,2,3,4,5] -> [183.12, 164.85, 174.25,
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168.83, 183.96, 145.73] MHz. n=6, mean=170.12 MHz, min=145.73 MHz,
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max=183.96 MHz, stdev=14.16 MHz.
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ACC_WIDTH=24: seeds [default,1,2,3,4,5] -> [176.21, 183.72, 180.57,
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183.08, 185.49, 175.16] MHz. n=6, mean=180.71 MHz, min=175.16 MHz,
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max=185.49 MHz, stdev=4.21 MHz.
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Conclusion: over 6 real placement seeds, ACC_WIDTH=24 has a HIGHER
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mean Fmax (+10.6 MHz, +6.2%) AND a much lower seed-to-seed variance
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(stdev 4.21 vs 14.16 MHz, ~3.4x tighter) than ACC_WIDTH=32 --
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EXP-0002's single-seed result (176.21 < 183.12, i.e. ACC=24 looked
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WORSE) was placement-seed noise, not a real trend. See decisions.log
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DEC-0013.
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