micheleandClaude Sonnet 5
91bbbe2fe5
Final milestone of docs/v2-description.md's §33 roadmap, scoped exactly to its own mandate: optimize only on data already gathered in M1-M9, across the pipeline/P_IN/processor-count/scheduling/memory axes - no speculative new features. Three concrete, data-driven results: 1. N_SLOTS=8 (numero processor axis): real synthesis + nextpnr-ecp5 P&R for dataflow_core at N_SLOTS=8, extending M7's N_SLOTS=2/4 sweep to the real DSP ceiling DEC-0005 predicted. 92.63 MHz POST-P&R, PASS at 80MHz, DSP 64/72 (88.9%). DEC-0012 recommends N_SLOTS=8 as the practical ceiling for P_IN=8 on the LFE5U-45F-8BG381. 2. ACC_WIDTH 24 vs 32 (pipeline axis): a real 6-seed nextpnr-ecp5 placement sweep (reusing already-synthesized netlists, no new synthesis needed) resolves EXP-0002's single-seed inconclusiveness. ACC_WIDTH=24 wins on both mean Fmax (+6.2%, 180.71 vs 170.12 MHz) and seed-to-seed variance (~3.4x tighter), on top of its already-known resource advantage. DEC-0013 recommends ACC_WIDTH=24 as the new default. 3. Stall %/utilization (scheduling/memory axes): testbench-only cycle counters added to tb_neural_multiprocessor.v (no RTL touched) close DEC-0011's deferred measurement gap with real data - shared PSRAM port 81.7% utilized, slot 0 95.2%, slot 1 65.2%, no conclusive evidence of harmful fixed-priority starvation at this scale. The 10-milestone V2 roadmap (docs/v2-description.md §33) is now complete end-to-end: real Verilator simulation, real Yosys synthesis, real nextpnr-ecp5 place & route for every milestone, fully logged (EXP-0001..EXP-0013, DEC-0001..DEC-0013, ERR-0001..ERR-0008) with no invented results (§30) and V1 kept frozen and untouched throughout (§1/§34). Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
90 lines
4.9 KiB
Plaintext
90 lines
4.9 KiB
Plaintext
# V2 synthesis log -- solo append, mai troncato/sovrascritto (vedi README.md)
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# Nessuna entry ancora -- popolato incrementalmente man mano che avanza lo sviluppo V2.
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[2026-09-05] EXP-0001 -- neural_processor (P_IN=8, ACC_WIDTH=32)
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LUT: 55 FF: 533 DSP(MULT18X18D): 8 BRAM: 0 CCU2C: 96
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CHECK: 0 problems. 36 warnings, all "multiple conflicting drivers for
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neural_processor.\gi" -- benign Yosys quirk for an `integer` used as
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a synthesizable for-loop index in stage 0's unrolled always block,
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not a real multi-driver conflict (cross-verified functionally
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correct on 2 independent simulators). Log: hardware/v2/synthesis/
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neural_processor_p8/yosys.log
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[2026-09-05] EXP-0002 -- neural_processor (P_IN=8, ACC_WIDTH=24)
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LUT: 49 FF: 509 DSP(MULT18X18D): 8 BRAM: 0 CCU2C: 88
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CHECK: 0 problems, same 36 benign warnings as EXP-0001.
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Log: hardware/v2/synthesis/neural_processor_p8_acc24/yosys.log
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[2026-09-05] EXP-0003 -- neural_processor_array via
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harness_neural_processor_array.v (synthesis-only wrapper, see
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errors.log ERR-0005), N_PROCESSORS in {1,2,4,8}, P_IN=8
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N=1: LUT=59 FF=409 MULT18X18D=8 CCU2C=96
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N=2: LUT=106 FF=786 MULT18X18D=16 CCU2C=192
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N=4: LUT=207 FF=1540 MULT18X18D=32 CCU2C=384
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N=8: LUT=374 FF=3048 MULT18X18D=64 CCU2C=768
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CHECK: 0 problems in all 4 configurations. Perfectly linear scaling in
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N confirms no unintended cross-processor resource sharing (a first,
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flawed harness attempt fed identical data to every processor/lane
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and Yosys silently deduplicated down to 1x regardless of N -- caught
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by checking for exactly this linearity before trusting the numbers).
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[2026-09-05] EXP-0004 -- activation_buffer/weight_buffer/result_buffer,
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2 depths each
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activation_buffer D=4096: LUT=37 FF=30 DP16KD=2 (D=256: LUT=21 FF=26 DP16KD=1)
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weight_buffer D=512: LUT=88 FF=139 DP16KD=2 (D=64: LUT=73 FF=136 DP16KD=2)
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result_buffer D=4096: LUT=37 FF=30 DP16KD=2 (D=256: LUT=21 FF=26 DP16KD=1)
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CHECK: 0 problems, all 6 configs correctly infer DP16KD (no LUT-RAM
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fallback). weight_buffer's DP16KD count does NOT drop with depth
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(width-bound, not depth-bound -- see decisions.log / benchmark.log).
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[2026-09-05] EXP-0005 -- memory_manager + prefetch_engine (standalone)
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LUT4=851 TRELLIS_FF=789 CCU2C=108 MULT18X18D=0 (expected, no
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multiplication in this module). CHECK: 0 problems.
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[2026-09-05] EXP-0006 -- neural_director (N_SLOTS=4, standalone)
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LUT4=382 TRELLIS_FF=366 CCU2C=4 DSP=0. CHECK: 0 problems.
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[2026-09-05] EXP-0007 -- dependency_manager (N_NODES=16, MAX_DEPS=4)
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LUT4=763 TRELLIS_FF=474 CCU2C=0 DSP=0. CHECK: 0 problems.
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[2026-09-05] EXP-0008 -- dataflow_core (M7 full integration, via
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harness_dataflow_core.v -- see errors.log ERR-0005 for why a harness
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is needed: bare per-slot Memory Backend Interface ports alone total
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280 bits at N_SLOTS=4, exceeding the LFE5U-45F-8BG381's ~245 TRELLIS_IO
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budget)
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N_SLOTS=2: LUT4=2127 CCU2C=248 TRELLIS_FF=2505 MULT18X18D=16 DP16KD=0
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N_SLOTS=4: LUT4=3953 CCU2C=500 TRELLIS_FF=4688 MULT18X18D=32 DP16KD=0
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CHECK: 0 problems on both configs (same 32 benign "multiple conflicting
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drivers for ...neural_processor.\gi" warnings per neural_processor
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instance already documented in EXP-0001 -- an `integer` for-loop
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index shared across two of neural_processor's own always blocks, not
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a real multi-driver conflict). DP16KD=0 on both is expected: M3's
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BRAM-backed buffers (activation/weight/result_buffer) are
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deliberately NOT instantiated inside dataflow_core yet (decisions.log
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DEC-0009). DSP scales exactly 8/slot (matches P_IN=8, consistent with
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every prior per-processor DSP measurement since M1/M2).
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[2026-09-05] EXP-0009 -- neural_multiprocessor (M8, N_SLOTS=2, real
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standalone top-level synthesis -- no timing harness needed: real PSRAM
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pins replace dataflow_core's wide per-slot arrays, total 157 port bits,
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well under the LFE5U-45F-8BG381's ~245 TRELLIS_IO budget)
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LUT4=3145 CCU2C=388 TRELLIS_FF=3659 MULT18X18D=16 DP16KD=0
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TRELLIS_DPR16X4=45 (small LUT-based distributed RAM, inferred from
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neural_director's shallow QUEUE_DEPTH-entry job queue -- not BRAM,
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same primitive class already seen in M7's own harness stat)
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$_TBUF_=16 (tri-state buffers for the bidirectional psram_dq bus,
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from V1's own unmodified psram_controller.v)
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CHECK: 0 problems (same 32 benign "multiple conflicting drivers for
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...neural_processor.\gi" warnings documented since EXP-0001).
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[2026-09-05] EXP-0011 -- dataflow_core N_SLOTS=8 (M10, "numero
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processor" axis, via harness_dataflow_core.v, extending M7's own
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N_SLOTS=2/4 sweep to the real DSP ceiling predicted by DEC-0005)
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LUT4=6439 CCU2C=996 TRELLIS_FF=9053 MULT18X18D=64 (64/72=88.9% of
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the LFE5U-45F's total DSP budget -- matches DEC-0005's M2-era
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prediction almost exactly, since dataflow_core's per-slot DSP cost
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is just neural_processor's own P_IN=8 DSP cost x N_SLOTS)
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DP16KD=0 (expected, DEC-0009). CHECK: 0 problems (same benign
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"multiple conflicting drivers" warnings as every other neural_processor
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instantiation since EXP-0001).
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