micheleandClaude Sonnet 5
91bbbe2fe5
Final milestone of docs/v2-description.md's §33 roadmap, scoped exactly to its own mandate: optimize only on data already gathered in M1-M9, across the pipeline/P_IN/processor-count/scheduling/memory axes - no speculative new features. Three concrete, data-driven results: 1. N_SLOTS=8 (numero processor axis): real synthesis + nextpnr-ecp5 P&R for dataflow_core at N_SLOTS=8, extending M7's N_SLOTS=2/4 sweep to the real DSP ceiling DEC-0005 predicted. 92.63 MHz POST-P&R, PASS at 80MHz, DSP 64/72 (88.9%). DEC-0012 recommends N_SLOTS=8 as the practical ceiling for P_IN=8 on the LFE5U-45F-8BG381. 2. ACC_WIDTH 24 vs 32 (pipeline axis): a real 6-seed nextpnr-ecp5 placement sweep (reusing already-synthesized netlists, no new synthesis needed) resolves EXP-0002's single-seed inconclusiveness. ACC_WIDTH=24 wins on both mean Fmax (+6.2%, 180.71 vs 170.12 MHz) and seed-to-seed variance (~3.4x tighter), on top of its already-known resource advantage. DEC-0013 recommends ACC_WIDTH=24 as the new default. 3. Stall %/utilization (scheduling/memory axes): testbench-only cycle counters added to tb_neural_multiprocessor.v (no RTL touched) close DEC-0011's deferred measurement gap with real data - shared PSRAM port 81.7% utilized, slot 0 95.2%, slot 1 65.2%, no conclusive evidence of harmful fixed-priority starvation at this scale. The 10-milestone V2 roadmap (docs/v2-description.md §33) is now complete end-to-end: real Verilator simulation, real Yosys synthesis, real nextpnr-ecp5 place & route for every milestone, fully logged (EXP-0001..EXP-0013, DEC-0001..DEC-0013, ERR-0001..ERR-0008) with no invented results (§30) and V1 kept frozen and untouched throughout (§1/§34). Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
201 lines
12 KiB
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201 lines
12 KiB
Plaintext
# V2 benchmark log -- solo append, mai troncato/sovrascritto (vedi README.md)
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# Nessuna entry ancora -- popolato incrementalmente man mano che avanza lo sviluppo V2.
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[2026-09-05] M1 single Neural Processor, isolated (no array/director/
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memory manager yet -- system-level numbers deferred to M9)
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| Config | Fmax (POST-P&R) | LUT | FF | DSP | BRAM |
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|----------------------|------------------|-----|-----|-----|------|
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| P_IN=8, ACC_WIDTH=32 | 183.12 MHz | 55 | 533 | 8 | 0 |
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| P_IN=8, ACC_WIDTH=24 | 176.21 MHz | 49 | 509 | 8 | 0 |
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Reference (V1, hardware/v1/synthesis/p8/, isolated neuron_parallel,
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PARALLEL=8, N_INPUTS=256): 61.71 MHz POST-P&R.
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All Fmax figures above are POST-P&R (real nextpnr-ecp5), not
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theoretical or simulated-only. MAC/cycle, cycles/neuron, neurons/s,
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stall %, effective MAC/s: not yet meaningful at this milestone (single
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isolated processor, no streaming benchmark harness yet -- deferred to
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M2 once neural_processor_array.v exists and a real workload can be
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timed end-to-end).
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[2026-09-05] M2 Neural Processor Array, N_PROCESSORS sweep (P_IN=8,
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ACC_WIDTH=32 each; synthesized via the timing harness, see errors.log
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ERR-0005 for why)
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| N_PROCESSORS | Fmax (POST-P&R) | LUT | FF | DSP (MULT18X18D) | DSP % of 72 |
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|--------------|------------------|-----|------|-------------------|-------------|
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| 1 | 159.11 MHz | 59 | 409 | 8 | 11% |
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| 2 | 149.59 MHz | 106 | 786 | 16 | 22% |
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| 4 | 151.01 MHz | 207 | 1540 | 32 | 44% |
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| 8 | 134.70 MHz | 374 | 3048 | 64 | 88% |
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All figures POST-P&R (real nextpnr-ecp5), all PASS at the 80MHz
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target. LUT4 utilization stays under 6% of the device even at N=8;
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DSP is the binding resource (see decisions.log DEC-0005), reaching 88%
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at N=8 -- N_PROCESSORS=9 would already exceed the LFE5U-45F's 72
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MULT18X18D budget at P_IN=8. Theoretical MAC/cycle (THEORETICAL, not
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yet measured end-to-end -- no real workload/benchmark harness exists
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until M9): N_PROCESSORS * P_IN MACs/cycle when all processors are
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simultaneously streaming tiles (8, 16, 32, 64 for N=1/2/4/8 -- verified
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achievable in principle by EXP-0003's concurrent/staggered simulation,
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not yet measured as a sustained throughput number).
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[2026-09-05] M3 buffers -- BRAM cost vs DEPTH (real Yosys synth_ecp5)
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| Module | DEPTH | DP16KD | LUT4 | FF |
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|--------------------|-------|--------|------|-----|
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| activation_buffer | 4096 | 2 | 37 | 30 |
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| activation_buffer | 256 | 1 | 21 | 26 |
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| weight_buffer | 512 | 2 | 88 | 139 |
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| weight_buffer | 64 | 2 | 73 | 136 |
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| result_buffer | 4096 | 2 | 37 | 30 |
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| result_buffer | 256 | 1 | 21 | 26 |
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weight_buffer's DP16KD count is flat across an 8x depth reduction --
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its 64-bit TILE_WIDTH (P_IN=8 * DATA_WIDTH=8), not DEPTH, determines
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BRAM count for this module. activation_buffer/result_buffer (byte-
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wide) scale as expected with depth. Confirms §14's warning literally:
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"non assumere che buffer piu' grandi siano automaticamente migliori"
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-- here, smaller was not cheaper either, because depth was the wrong
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lever for this specific buffer's cost.
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[2026-09-05] M4 Memory Manager + Prefetch Engine (standalone resource
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count; Fmax via timing harness -- see errors.log ERR-0005)
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| Module | Fmax (POST-P&R) | LUT | FF | DSP | CCU2C |
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|----------------------------------|------------------|-----|-----|-----|-------|
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| memory_manager + prefetch_engine | 165.86 MHz | 851 | 789 | 0 | 108 |
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End-to-end (real PSRAM + real neural_processor, SIMULATED only, no
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system-level P&R yet -- deferred to M7/M9): 3-tile job = 446 cycles,
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1-tile job = 166 cycles, 5-tile job = 728 cycles. ~140-150 cycles/tile,
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dominated by psram_model.v's real ~70ns TAA access latency, not by
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memory_manager's own control overhead (its bank-swap turnaround is
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documented as a fixed +1 cycle/tile in decisions.log DEC-0006, a small
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fraction of the ~140-cycle PSRAM-dominated total).
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[2026-09-05] M5 Neural Director (standalone resource count; Fmax via
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timing harness -- see errors.log ERR-0005)
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| Module | Fmax (POST-P&R) | LUT | FF | DSP | CCU2C |
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|------------------|------------------|-----|-----|-----|-------|
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| neural_director (N_SLOTS=4) | 250.50 MHz | 382 | 366 | 0 | 4 |
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[2026-09-05] M6 Dependency Manager (real standalone synthesis + P&R,
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no harness needed)
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| Module | Fmax (POST-P&R) | LUT | FF | DSP | CCU2C |
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|----------------------|------------------|-----|-----|-----|-------|
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| dependency_manager (N_NODES=16) | 155.30 MHz | 763 | 474 | 0 | 0 |
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[2026-09-05] M7 Dataflow Core (full M1-M6 integration; resources via
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real standalone synthesis, Fmax via timing harness -- see errors.log
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ERR-0005)
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| Module (config) | Fmax (POST-P&R) | LUT4 | CCU2C | FF | DSP | BRAM |
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|-------------------------------|------------------|------|-------|------|-----|------|
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| dataflow_core (N_SLOTS=2) | 165.15 MHz | 2127 | 248 | 2505 | 16 | 0 |
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| dataflow_core (N_SLOTS=4) | 133.19 MHz | 3953 | 500 | 4688 | 32 | 0 |
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DSP budget on the LFE5U-45F is 72 MULT18X18D total: N_SLOTS=4 already
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uses 32/72 (44%), consistent with DEC-0005's finding that DSP, not
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LUT/FF, is the first resource to saturate as concurrency grows (M2's
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own N_PROCESSORS=8 measurement: 88%). BRAM=0 on both is expected --
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M3's buffers are not wired into dataflow_core yet (DEC-0009).
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[2026-09-05] M8 Neural Multiprocessor top (real standalone synthesis +
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P&R, no harness needed -- real PSRAM pins keep the bare top-level
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pin count at 157, under the TRELLIS_IO budget)
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| Module (config) | Fmax (POST-P&R) | LUT4 | CCU2C | FF | DSP | BRAM |
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|--------------------------------------|------------------|------|-------|------|-----|------|
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| neural_multiprocessor (N_SLOTS=2) | 142.45 MHz | 3145 | 388 | 3659 | 16 | 0 |
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Compare to M7's dataflow_core alone (N_SLOTS=2): 165.15 MHz / LUT4=2127
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/ CCU2C=248 / FF=2505 / DSP=16. Adding the real V1 PSRAM chain +
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slot_mem_arbiter costs ~1000 LUT4/140 CCU2C/1150 FF and drops Fmax by
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~23 MHz (165.15 -> 142.45) -- both real, measured costs of real PSRAM
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integration, not assumed.
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[2026-09-05] M9 -- Confronto finale V1 vs V2 (docs/v2-description.md
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§32). Basi di confronto: entrambi i sistemi COMPLETI (full-system,
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non moduli isolati), stessa larghezza di dot-product per neurone
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(PARALLEL=8 / P_IN=8), stesso backend PSRAM reale V1 non modificato
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in entrambi i casi.
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V1 = hardware/v1's spi_neuron_top (post_fix_verify synthesis,
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PARALLEL=8) + neuron_memory_tb.v TEST 5 (1 neuron, N_INPUTS
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ridotto a 8, catena PSRAM reale) -- entrambi dati gia'
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certificati/congelati in hardware/v1/.
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V2 = hardware/v2/rtl/neural_multiprocessor.v (N_SLOTS=2, P_IN=8,
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M8) -- EXP-0009 (1 tile/8 input via memory_manager standalone,
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EXP-0005) + EXP-0009 stesso (catena PSRAM reale condivisa).
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| Metrica | V1 | V2 | Classificazione |
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|------------------------|---------------------------|------------------------------|-------------------|
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| Fmax | 68.65 MHz (FAIL @80MHz) | 142.45 MHz (PASS @80MHz) | POST-P&R (reale, nextpnr-ecp5, entrambi full-system) |
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| LUT (Total LUT4s) | 8907 | 4191 | POST-P&R (nextpnr "Total LUT4s", stessa metrica per entrambi) |
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| FF (Total DFFs) | 4900 | 3659 | POST-P&R |
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| DSP (MULT18X18D) | 16 | 16 | POST-P&R |
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| BRAM (DP16KD) | 2 | 0 (M3 non ancora collegato, DEC-0009) | POST-P&R |
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| MAC/cycle (picco) | 8 (PARALLEL=8, core singolo sequenziale) | 16 (N_SLOTS=2 x P_IN=8, concorrenti) | THEORETICAL (parametri architetturali noti, non ancora un picco sostenuto misurato con contesa reale su entrambi gli slot) |
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| cycles/neuron | 209 (1 neurone, 8 input reali, PSRAM reale -- hardware/v1/docs/FPGA-NeuralNetwork-Engine.md, TEST 5 neuron_memory_tb.v, gia' certificato) | 166 (1 tile/8 input, PSRAM reale -- EXP-0005) | SIMULATED (Verilator per V2; V1 dato gia' certificato in hardware/v1/, non ri-simulato in questa sessione) |
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| neurons/s | 328,469 (Fmax POST-P&R / cycles SIMULATED) | 858,133 (idem) | DERIVATO (Fmax POST-P&R reale x cycles/neuron SIMULATED reale -- non un numero misurato direttamente in un'unica prova, ma calcolato da due misure reali indipendenti, entrambe citate) |
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| stall % | NON MISURATO questo milestone | NON MISURATO questo milestone | -- vedi decisions.log DEC-0011 |
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| memory utilization | NON MISURATO questo milestone | NON MISURATO questo milestone | -- vedi decisions.log DEC-0011 |
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| processor utilization | NON MISURATO questo milestone | NON MISURATO questo milestone | -- vedi decisions.log DEC-0011 |
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| effective MAC/s | 2.63 MMAC/s (8 MAC/neurone / 209 cicli x 68.65MHz) | 6.87 MMAC/s (8 MAC/neurone / 166 cicli x 142.45MHz) | DERIVATO (stessa base di neurons/s) |
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| effective MAC/s (picco teorico) | 549.2 MMAC/s (8 x 68.65MHz) | 2279.2 MMAC/s (16 x 142.45MHz) | THEORETICAL |
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Osservazioni (tutte da dati reali sopra, nessun numero inventato):
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- V2 e' 2.6x piu' veloce in wall-clock per un singolo neurone/8 input
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attraverso la catena PSRAM reale (1.165us vs 3.044us), pur usando lo
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STESSO backend PSRAM V1 non modificato -- il guadagno viene sia da
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meno cicli (166 vs 209, pipeline M1 piu' efficiente) sia da un Fmax
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POST-P&R piu' che doppio (142.45 vs 68.65 MHz).
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- V1's full system FALLISCE il target 80MHz (68.65 MHz); V2's full
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system lo supera con margine (142.45 MHz) -- confermato da vero
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nextpnr-ecp5 place&route su entrambi.
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- Il vantaggio "MAC/cycle di picco" di V2 (16 vs 8) viene dalla
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concorrenza reale a livello di sistema (N_SLOTS=2, EXP-0009 lo
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dimostra con vera contesa PSRAM tra 2 slot), non da un core piu'
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largo -- V1 e' strutturalmente un acceleratore sequenziale (un solo
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neuron_parallel attivo alla volta), esattamente il limite che
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l'intero mandato V2 (docs/v2-description.md, titolo) si propone di
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superare.
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- BRAM=0 per V2 riflette una scelta di scope esplicita (M3 non ancora
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collegato, DEC-0009), non un vantaggio architetturale reale -- un
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confronto onesto lo nota piuttosto che nasconderlo.
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[2026-09-05] M10 -- Optimization, closing M9's deferred gaps with real
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data (§32/DEC-0011 follow-up)
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Stall %/utilization (EXP-0013, real SIMULATED data, N_SLOTS=2, 3-node
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DAG scenario, replacing M9's "NOT MEASURED" placeholder for V2 -- V1's
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own equivalent instrumentation was not built this session, still NOT
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MEASURED for V1):
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| Metric | V2 (SIMULATED, real) |
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|------------------------------------|------------------------|
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| shared PSRAM port utilization | 81.7% (18.3% idle) |
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| slot 0 (memory_manager) utilization| 95.2% |
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| slot 1 (memory_manager) utilization| 65.2% |
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N_SLOTS sweep, extended to the real DSP ceiling (EXP-0008/EXP-0011):
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| N_SLOTS | Fmax (POST-P&R) | DSP used/total |
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|-----------|-------------------|------------------|
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| 2 | 165.15 MHz | 16/72 (22%) |
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| 4 | 133.19 MHz | 32/72 (44%) |
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| 8 | 92.63 MHz | 64/72 (89%) |
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All three PASS at 80MHz; N_SLOTS=8 recommended as the practical
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ceiling for P_IN=8 on this chip (DEC-0012).
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ACC_WIDTH 6-seed real placement sweep (EXP-0012, resolves EXP-0002's
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single-seed inconclusiveness):
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| ACC_WIDTH | mean Fmax | min | max | stdev |
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|-------------|-------------|-------|-------|---------|
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| 32 | 170.12 MHz | 145.73| 183.96| 14.16 |
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| 24 | 180.71 MHz | 175.16| 185.49| 4.21 |
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ACC_WIDTH=24 recommended as the new default (DEC-0013): higher mean
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Fmax, much tighter variance, fewer resources, same bit-exact
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correctness.
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