micheleandClaude Sonnet 5 7f9ece12dc docs: real P&R signoff for the result-writeback engine (EXP-0088) ...

Real in-context P&R confirms the result-writeback engine (EXP-0088)
closes timing with essentially zero cost: WNS=+0.099962ns (vs
EXP-0086's +0.095707ns), WHS=+0.036275ns, 0 failing endpoints. 6642
LUTs (+260 for the new engine), 16 DSP48E1 unchanged. This is now the
current, trustworthy signoff, promoted over EXP-0086/0087's own
pointers in both docs.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC

2026-09-20 19:27:00 +02:00

..

constraints

docs+synth: Phase 0 baseline (N_SLOTS=4, real board top), fix stale LPF freq

2026-09-15 20:28:16 +00:00

ddr3

exp: N=16 timing closure fixed (EXP-0056), weight-reuse gives real 7.16x memory speedup without DDR3 (EXP-0057)

2026-09-16 12:01:11 +02:00

docs

docs: extract V2 datasheet into submodule

2026-09-16 23:03:43 +02:00

logs

docs: real P&R signoff for the result-writeback engine (EXP-0088)

2026-09-20 19:27:00 +02:00

nms

prod: promote EXP-0056 fixes into production RTL (dependency_manager.v, nms_activation_fill_ctrl_v3.v)

2026-09-16 12:29:52 +02:00

reports

V2 final synthesis/P&R sign-off + LaTeX datasheet port (NOT SILICON READY)

2026-09-06 17:50:53 +02:00

rtl

feat: real 32-bit DDR3 channel widening - functionally complete, timing NOT yet closed (EXP-0084)

2026-09-20 16:28:44 +02:00

sim

exp: fix pulse-race hang in tb_layer_reuse_vs_zero_reuse.v (EXP-0058 follow-up); real remaining bug still open, 7.16x NOT yet re-verified

2026-09-16 15:38:12 +02:00

synthesis

feat(v2): M7 Dataflow Core - full M1-M6 integration, wake-up loop closed end-to-end

2026-09-05 15:05:28 +02:00