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micheleandClaude Sonnet 5 264950923b feat: N=8 hybrid systolic promoted to the real, definitive deployment target (EXP-0096) 
New n8_system_ddr3_top.v: a real, permanent, named top-level (not a
build-time -generic override), byte-for-byte the same RTL as
n16_system_ddr3_top.v with N_GROUPS defaulting to 2. Real, full P&R
under this file's own name reproduces EXP-0095's own generic-override
result exactly: WNS=0.000ns, WHS=+0.017ns, 0 failing setup endpoints,
64 DSP48E1/26.7%, 12535 LUTs/19.77%.

New tb_n8_system_ddr3.v (real DDR3-model methodology, adapted from
tb_n16_system_ddr3.v, M=16 positions covering every one of the 2
groups x 4 PEs x 2 lanes exactly once): real functional xsim, 16/16
PASS, 0 errors -- closes the real functional-verification gap this
specific N previously had.

N=8 is now BOTH functionally verified AND timing-closed under its own
permanent name -- the real, definitive deployment target. N=2 kept as
a documented, valid fallback; N=16 kept as documented, functionally-
verified-but-not-timing-closed future work, not abandoned.

docs/PHYSICAL_REALIZATION.md, docs/ARCHITECTURE_ANALYSIS.md,
docs/PINOUT.md updated to reflect N=8 as the current real signoff.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
2026-09-21 08:29:04 +02:00

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# FPGA-Neural V3 — Consolidated Pinout Reference
Single-source pinout for the custom PCB (bare **XC7A100T-CSG324-2**, no dev
board). This is a flattened, board-layout-ready extract of
`docs/PHYSICAL_REALIZATION.md` §2 — that document remains the authoritative,
narrated source (it explains *why* each pin was chosen and every real
conflict/fix found along the way); this file is the quick reference for
schematic capture. Every pin below comes from a real routed design
(originally `n2_system_ddr3_top_routed.dcp`, EXP-0086; the same real pin
set — DDR3/SPI/flash/config are all package-level, unaffected by internal
core count — was re-confirmed real and unchanged in `n8_system_ddr3_top.v`'s
own real routed signoff, EXP-0095/0096, now the current definitive
deployment target, see `docs/PHYSICAL_REALIZATION.md` §3) or the
MIG-generated `mig_7series_0.xdc` — none of it is guessed. Re-generate
this file if `docs/PHYSICAL_REALIZATION.md` §2 ever changes.
## Bank summary
| Bank | Voltage (VCCO) | Standard | Used for |
|---|---|---|---|
| 0 | per board config rail | LVCMOS (per UG470) | FPGA configuration control (PROGRAM_B/INIT_B/DONE/mode pins/CFGBVS) |
| 14 | 2.5V | LVDS_25 | `clk_ref_p/n` only (differential IDELAYCTRL reference clock) |
| 15 | 3.3V | LVCMOS33 | Management SPI (ESP32↔FPGA), `sys_rst`, `data_ready_n` |
| 16 | 3.3V | LVCMOS33 | Config flash SPI (FPGA↔flash) |
| 34 | 1.5V | SSTL15 / DIFF_SSTL15 | DDR3 addr/ba/control/ck, `sys_clk_p/n` |
| 35 | 1.5V | SSTL15 / DIFF_SSTL15 | DDR3 dq/dqs/dm |
## DDR3 (bank 34/35 — two MT41J128M16JT-125:K chips in parallel, 32-bit channel)
Address/command/control fan out identically to BOTH chips (not duplicated
per chip); DQ/DQS/DM are split 16 bits per chip.
| Signal | Pin | Signal | Pin | Signal | Pin |
|---|---|---|---|---|---|
| ddr3_dq[0] | C5 | ddr3_dq[16] | F4 | ddr3_addr[0] | U3 |
| ddr3_dq[1] | B7 | ddr3_dq[17] | F3 | ddr3_addr[1] | U4 |
| ddr3_dq[2] | B6 | ddr3_dq[18] | E2 | ddr3_addr[2] | V1 |
| ddr3_dq[3] | D8 | ddr3_dq[19] | D2 | ddr3_addr[3] | U1 |
| ddr3_dq[4] | C7 | ddr3_dq[20] | C1 | ddr3_addr[4] | L5 |
| ddr3_dq[5] | E6 | ddr3_dq[21] | H1 | ddr3_addr[5] | L6 |
| ddr3_dq[6] | E5 | ddr3_dq[22] | G1 | ddr3_addr[6] | L4 |
| ddr3_dq[7] | E7 | ddr3_dq[23] | F1 | ddr3_addr[7] | K5 |
| ddr3_dq[8] | B4 | ddr3_dq[24] | F6 | ddr3_addr[8] | M2 |
| ddr3_dq[9] | A4 | ddr3_dq[25] | G4 | ddr3_addr[9] | M3 |
| ddr3_dq[10] | A3 | ddr3_dq[26] | G3 | ddr3_addr[10] | L3 |
| ddr3_dq[11] | B3 | ddr3_dq[27] | J3 | ddr3_addr[11] | K3 |
| ddr3_dq[12] | B2 | ddr3_dq[28] | J2 | ddr3_addr[12] | M1 |
| ddr3_dq[13] | D5 | ddr3_dq[29] | K2 | ddr3_addr[13] | L1 |
| ddr3_dq[14] | D4 | ddr3_dq[30] | K1 | ddr3_ba[0] | V5 |
| ddr3_dq[15] | E3 | ddr3_dq[31] | H6 | ddr3_ba[1] | V2 |
| ddr3_dm[0] | C6 | ddr3_dm[2] | C2 | ddr3_ba[2] | U2 |
| ddr3_dm[1] | C4 | ddr3_dm[3] | G6 | ddr3_cas_n | R3 |
| ddr3_dqs_p[0] | A6 (DIFF) | ddr3_dqs_n[0] | A5 (DIFF) | ddr3_cke[0] | P2 |
| ddr3_dqs_p[1] | B1 (DIFF) | ddr3_dqs_n[1] | A1 (DIFF) | ddr3_cs_n[0] | T5 |
| ddr3_dqs_p[2] | H2 (DIFF) | ddr3_dqs_n[2] | G2 (DIFF) | ddr3_odt[0] | R2 |
| ddr3_dqs_p[3] | J4 (DIFF) | ddr3_dqs_n[3] | H4 (DIFF) | ddr3_ras_n | V4 |
| ddr3_ck_p[0] | N2 (DIFF) | ddr3_ck_n[0] | N1 (DIFF) | ddr3_we_n | T3 |
| ddr3_reset_n | D7 (LVCMOS15) | | | | |
| **sys_clk_p** | **N5 (DIFF_SSTL15)** | **sys_clk_n** | **P5 (DIFF_SSTL15)** | real, required freq **310.077 MHz** | |
## Reference clock (bank 14)
| Signal | Pin | Standard | Notes |
|---|---|---|---|
| clk_ref_p | T14 | LVDS_25 (2.5V) | required freq **200 MHz**, differential |
| clk_ref_n | T15 | LVDS_25 (2.5V) | |
Bank 14 hosts ONLY `clk_ref_p/n` — the config-flash bus was moved out of
this bank (to bank 16, see below) specifically because it can't share a
VCCO with this signal (EXP-0084).
## Management SPI — ESP32 ↔ FPGA, FPGA is slave (bank 15, 3.3V)
| Signal | Pin | Direction (FPGA side) | Notes |
|---|---|---|---|
| sclk | A15 | input | |
| mosi | B16 | input | |
| miso | B17 | output | |
| cs_n | A16 | input | |
| sys_rst | G13 | input | tentative pin, not yet a final board decision (§7 of PHYSICAL_REALIZATION.md) |
| data_ready_n | D14 | output | active-low sticky IRQ (EXP-0085); tentative pin, same caveat as sys_rst |
## Config flash SPI — FPGA ↔ Winbond W25Q32JVSSIQ, FPGA is master (bank 16, 3.3V)
| Signal | Pin | Direction (FPGA side) | Notes |
|---|---|---|---|
| flash_mosi | D9 | output | connects to flash DI |
| flash_miso | D10 | input | connects to flash DO |
| flash_cs_n | C9 | output | connects to flash /CS |
| (CCLK) | E9 | output | **not a top-level RTL port** — internally driven via `STARTUPE2`; wire the flash's own CLK pin directly to package pin E9 |
No direct ESP32↔flash connection exists by design — the ESP32 can only
reach the flash by relaying bytes through the FPGA over the management SPI
bus (`FLASH_XFER` opcode 0x40, see §5/§6 of PHYSICAL_REALIZATION.md).
## FPGA configuration control (bank 0, fixed by the device, not negotiable)
| Signal | Pin | Purpose |
|---|---|---|
| PROGRAM_B | P9 | pulse low to force reconfiguration from flash |
| INIT_B | P7 | low during config; re-asserting can indicate a config error |
| DONE | P10 | goes high once configuration succeeds — good status-LED candidate |
| M0 | P12 | mode select — tie per the Master SPI boot setting below |
| M1 | P13 | mode select |
| M2 | P11 | mode select |
| CFGBVS | P8 | tie to match bank 0's own VCCO logic level (see UG470) |
**Master SPI boot mode pins**: `M[2:0] = 001` — tie via pull-up/pull-down
resistors on the board (static, not driven dynamically).
## JTAG (bank 0, always available)
| Signal | Pin |
|---|---|
| TCK | E10 |
| TDI | E11 |
| TMS | E12 |
| TDO | E13 |
Intended to be driven by the ESP32 bit-banging the TAP state machine
(factory programming, recovery, development) — see §5.1 of
`docs/ARCHITECTURE_ANALYSIS.md`; that firmware doesn't exist yet.
## Reserved / do-not-use (bank 14)
`L16` (EMCCLK), `R16` (RDWR_B), `V15` (CSI_B) — config-mode-reserved,
`PROHIBIT`ed in the project XDC (via `get_sites -of_objects`, not directly
on the `package_pin` objects — a real Vivado property gotcha, see
CLAUDE.md). Kept clear for any future Quad-SPI/BPI expansion; not used by
this design's own Master-SPI-only configuration scheme.
## Open items (not yet finalized — do not treat as final for PCB layout)
- `sys_rst` (G13) and `data_ready_n` (D14) are real, verified-free pins
chosen only to unblock P&R — not yet a final board decision pending the
rest of the layout (reset circuit, status LEDs).
- Bank 15/16 VCCO is *assumed* 3.3V in this pinout — confirm against the
real board power plan before finalizing.
- `sys_clk_p/n` and `clk_ref_p/n` oscillator part selection (real,
in-stock candidates) is tracked in `docs/BOM.md`.
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