micheleandClaude Sonnet 5
785e9461a0
Real, from-source spec for the ESP32-S3 host firmware -- every field layout, address formula, and timing number is read directly from the committed RTL (spi_host_bridge_v3.v, neural_director_grouped.v, result_writeback.v, host_mem_bridge.v, flash_spi_master.v), not guessed. Covers: physical interfaces, boot/bootstrap (JTAG factory, Master-SPI autonomous, FLASH_XFER field update), the full management SPI opcode reference and register map, job submission (including the critical, real N=16 octet-dispatch requirement -- 8 jobs must share w_base/n_tiles or the Director's queue stalls permanently with no in-band recovery), result readback addressing, raw memory access, config-flash relay with its real 2-dummy-byte timing requirement, error handling, and honestly disclosed open items (no firmware exists yet -- this is the specification). Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC