micheleandClaude Sonnet 5
d6376e8f2a
Real synthesis and place-and-route of the actual final board-level
top (fpga_neural_v2_top.v -- SPI bridge, real EHXPLLL, reset_sync,
compute+memory core), against a real, fully ball-assigned LPF. Also
ports the V2 datasheet to LaTeX using V1's own preamble/macros/
typography, and records a real (non-ESP32, honestly labeled) software
reference comparison.
Synthesis (Yosys, real run): 0 CHECK-pass problems, 38 unique warnings
(43 total), all matching this project's own previously-reviewed benign
set (neural_processor.v's known genvar multi-driver artifact, small-
array-to-register unrolling, the real SDRAM DQ tristate bus) -- no new
warnings from the SPI bridge, PLL, or reset synchronizer.
TRELLIS_FF=6322, TRELLIS_COMB=7084, MULT18X18D=32, EHXPLLL=1 (real PLL
confirmed present), DP16KD=0 (all small SRAMs -> distributed RAM).
Place-and-route (nextpnr-ecp5, real runs, 8 seeds, new
v2_board_top.lpf with all 44 top-level signals ball-assigned from the
official Lattice pinout CSV -- no placeholders): 8/8 PASS at 64MHz.
Worst 68.51MHz (seed 4), best 74.17MHz (seed 7), mean 71.16MHz. Zero
unrouted nets, zero placement/routing errors, TRELLIS_IO=44/245 (17%).
Critical path alternates between dependency_manager's own priority
encoder and sdram_unified_backend's own weight-cache hit-index logic,
matching this project's own prior documented timing investigations --
not a new defect.
New: hardware/v2/constraints/v2_board_top.lpf (final LPF, supersedes
v2_unified.lpf for the board-level top), hardware/v2/reports/
step_final_{synthesis,pnr_worst_seed4,timing}.* (raw evidence),
hardware/v2/docs/DatasheetLatex/ (V2 datasheet, real LaTeX build,
16 pages, visually inspected, ported from hardware/v1/docs/
DatasheetLatex/'s own preamble and macros).
Real, honestly-labeled software baseline: the D-Stress arithmetic
(256 neurons x 128 INT8 MACs) compiled and run on THIS development
machine (Apple M4, arm64, NOT an embedded target, NOT ESP32) --
1.28us/inference, included in the datasheet with an explicit
disclosure that no physical ESP32 hardware was available for a real
embedded-target comparison.
Remaining, disclosed, NOT-yet-closed items (this commit does NOT
claim silicon readiness): real KiCad schematic + ERC, PCB layout,
sourced BOM, real power current-budget estimate, SDRAM-datasheet-
parameter cross-check, configuration-flash selection, and (necessarily)
physical fabrication/bring-up. See hardware/v2/docs/DatasheetLatex/
chapters/08-status-roadmap.tex for the complete, itemized checklist.
Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
43 lines
2.1 KiB
TeX
43 lines
2.1 KiB
TeX
\chapter{Power, SDRAM electrical, and configuration}
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\section{Power architecture -- status: OPEN}
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Rail \emph{voltages} are real, DATASHEET VALUEs from the actual ECP5
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and \code{AS4C4M16SA-6TIN} datasheets; regulator selection, current
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budget, and decoupling are \textbf{not} finalized in this revision.
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\begin{tabularx}{\textwidth}{L{2.6cm}L{2.2cm}Y}
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\toprule
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\rowh \thd{Rail} & \thd{Nominal} & \thd{Status} \\
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\midrule
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VCC (core) & 1.1\,V & DATASHEET VALUE; regulator TBD \\
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\rowa VCCAUX & 2.5\,V & DATASHEET VALUE; regulator TBD \\
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VCCIO 6/7 (SDRAM) & 3.3\,V (assumed) & matches SDRAM's own LVCMOS33 need; not independently re-verified \\
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\rowa SDRAM VDD/VDDQ & 3.3\,V & DATASHEET VALUE (\code{AS4C4M16SA-6TIN}) \\
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\bottomrule
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\end{tabularx}
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No real power-estimation tool was run against the actual synthesized
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netlist this revision; a real, computed current budget therefore
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remains an OPEN item, not an invented number.
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\section{SDRAM electrical / timing sign-off -- status: PARTIAL}
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\code{AS4C4M16SA-6TIN} is a standard JEDEC SDR SDRAM; the controller
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(\code{sdram\_controller.v}) implements a real power-up wait, mode
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register set, and periodic AUTO REFRESH, verified functionally in
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simulation (init/refresh/read/write/burst/masked-write, 40 real
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refresh events per D-Stress run, zero corruption). A byte-for-byte
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cross-check of the controller's own timing constants against the
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device's real datasheet parameters (CAS latency, \sig{tRCD},
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\sig{tRP}, refresh interval, setup/hold) was \textbf{not} independently
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re-performed this revision -- simulation-level correctness is
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established; a dedicated datasheet-parameter audit remains an OPEN
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item before board layout.
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\section{Configuration -- status: OPEN}
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Standard ECP5 JTAG (\sig{TDI}/\sig{TDO}/\sig{TCK}/\sig{TMS}) and
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configuration (\sig{PROGRAMN}/\sig{INITN}/\sig{DONE}/\sig{CCLK}) pins
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are identified and standard (real balls listed in
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\code{docs/pinouts.md}); JTAG remains available regardless of boot
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mode. No configuration-flash part number has been selected, and no
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SPI-flash-boot-vs-JTAG-only decision has been made this revision.
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