From d6376e8f2ad4a9e0126704e1a7fd05b849df2e5b Mon Sep 17 00:00:00 2001 From: Michele Bigi Date: Sun, 6 Sep 2026 17:50:53 +0200 Subject: [PATCH] V2 final synthesis/P&R sign-off + LaTeX datasheet port (NOT SILICON READY) Real synthesis and place-and-route of the actual final board-level top (fpga_neural_v2_top.v -- SPI bridge, real EHXPLLL, reset_sync, compute+memory core), against a real, fully ball-assigned LPF. Also ports the V2 datasheet to LaTeX using V1's own preamble/macros/ typography, and records a real (non-ESP32, honestly labeled) software reference comparison. Synthesis (Yosys, real run): 0 CHECK-pass problems, 38 unique warnings (43 total), all matching this project's own previously-reviewed benign set (neural_processor.v's known genvar multi-driver artifact, small- array-to-register unrolling, the real SDRAM DQ tristate bus) -- no new warnings from the SPI bridge, PLL, or reset synchronizer. TRELLIS_FF=6322, TRELLIS_COMB=7084, MULT18X18D=32, EHXPLLL=1 (real PLL confirmed present), DP16KD=0 (all small SRAMs -> distributed RAM). Place-and-route (nextpnr-ecp5, real runs, 8 seeds, new v2_board_top.lpf with all 44 top-level signals ball-assigned from the official Lattice pinout CSV -- no placeholders): 8/8 PASS at 64MHz. Worst 68.51MHz (seed 4), best 74.17MHz (seed 7), mean 71.16MHz. Zero unrouted nets, zero placement/routing errors, TRELLIS_IO=44/245 (17%). Critical path alternates between dependency_manager's own priority encoder and sdram_unified_backend's own weight-cache hit-index logic, matching this project's own prior documented timing investigations -- not a new defect. New: hardware/v2/constraints/v2_board_top.lpf (final LPF, supersedes v2_unified.lpf for the board-level top), hardware/v2/reports/ step_final_{synthesis,pnr_worst_seed4,timing}.* (raw evidence), hardware/v2/docs/DatasheetLatex/ (V2 datasheet, real LaTeX build, 16 pages, visually inspected, ported from hardware/v1/docs/ DatasheetLatex/'s own preamble and macros). Real, honestly-labeled software baseline: the D-Stress arithmetic (256 neurons x 128 INT8 MACs) compiled and run on THIS development machine (Apple M4, arm64, NOT an embedded target, NOT ESP32) -- 1.28us/inference, included in the datasheet with an explicit disclosure that no physical ESP32 hardware was available for a real embedded-target comparison. Remaining, disclosed, NOT-yet-closed items (this commit does NOT claim silicon readiness): real KiCad schematic + ERC, PCB layout, sourced BOM, real power current-budget estimate, SDRAM-datasheet- parameter cross-check, configuration-flash selection, and (necessarily) physical fabrication/bring-up. See hardware/v2/docs/DatasheetLatex/ chapters/08-status-roadmap.tex for the complete, itemized checklist. Co-Authored-By: Claude Sonnet 5 Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v --- hardware/v2/constraints/v2_board_top.lpf | 98 + .../FPGA-Neural-V2-Datasheet-EN.aux | 21 + .../FPGA-Neural-V2-Datasheet-EN.log | 1667 ++ .../FPGA-Neural-V2-Datasheet-EN.out | 29 + .../FPGA-Neural-V2-Datasheet-EN.pdf | Bin 0 -> 158407 bytes .../FPGA-Neural-V2-Datasheet-EN.tex | 120 + .../FPGA-Neural-V2-Datasheet-EN.toc | 30 + .../DatasheetLatex/chapters/00-features.tex | 123 + .../DatasheetLatex/chapters/01-overview.aux | 53 + .../DatasheetLatex/chapters/01-overview.tex | 64 + .../chapters/02-architecture.aux | 54 + .../chapters/02-architecture.tex | 86 + .../chapters/03-clock-reset.aux | 49 + .../chapters/03-clock-reset.tex | 54 + .../chapters/04-host-interface.aux | 54 + .../chapters/04-host-interface.tex | 47 + .../chapters/05-pinout-timing.aux | 64 + .../chapters/05-pinout-timing.tex | 84 + .../chapters/06-power-configuration.aux | 54 + .../chapters/06-power-configuration.tex | 42 + .../DatasheetLatex/chapters/07-benchmarks.aux | 58 + .../DatasheetLatex/chapters/07-benchmarks.tex | 67 + .../chapters/08-status-roadmap.aux | 54 + .../chapters/08-status-roadmap.tex | 59 + hardware/v2/docs/DatasheetLatex/preamble.tex | 184 + .../v2/reports/step_final_pnr_worst_seed4.log | 378 + hardware/v2/reports/step_final_synthesis.log | 18198 ++++++++++++++++ hardware/v2/reports/step_final_timing.csv | 9 + 28 files changed, 21800 insertions(+) create mode 100644 hardware/v2/constraints/v2_board_top.lpf create mode 100644 hardware/v2/docs/DatasheetLatex/FPGA-Neural-V2-Datasheet-EN.aux create mode 100644 hardware/v2/docs/DatasheetLatex/FPGA-Neural-V2-Datasheet-EN.log create mode 100644 hardware/v2/docs/DatasheetLatex/FPGA-Neural-V2-Datasheet-EN.out create mode 100644 hardware/v2/docs/DatasheetLatex/FPGA-Neural-V2-Datasheet-EN.pdf create mode 100644 hardware/v2/docs/DatasheetLatex/FPGA-Neural-V2-Datasheet-EN.tex create mode 100644 hardware/v2/docs/DatasheetLatex/FPGA-Neural-V2-Datasheet-EN.toc create mode 100644 hardware/v2/docs/DatasheetLatex/chapters/00-features.tex create mode 100644 hardware/v2/docs/DatasheetLatex/chapters/01-overview.aux create mode 100644 hardware/v2/docs/DatasheetLatex/chapters/01-overview.tex create mode 100644 hardware/v2/docs/DatasheetLatex/chapters/02-architecture.aux create mode 100644 hardware/v2/docs/DatasheetLatex/chapters/02-architecture.tex create mode 100644 hardware/v2/docs/DatasheetLatex/chapters/03-clock-reset.aux create mode 100644 hardware/v2/docs/DatasheetLatex/chapters/03-clock-reset.tex create mode 100644 hardware/v2/docs/DatasheetLatex/chapters/04-host-interface.aux create mode 100644 hardware/v2/docs/DatasheetLatex/chapters/04-host-interface.tex create mode 100644 hardware/v2/docs/DatasheetLatex/chapters/05-pinout-timing.aux create mode 100644 hardware/v2/docs/DatasheetLatex/chapters/05-pinout-timing.tex create mode 100644 hardware/v2/docs/DatasheetLatex/chapters/06-power-configuration.aux create mode 100644 hardware/v2/docs/DatasheetLatex/chapters/06-power-configuration.tex create mode 100644 hardware/v2/docs/DatasheetLatex/chapters/07-benchmarks.aux create mode 100644 hardware/v2/docs/DatasheetLatex/chapters/07-benchmarks.tex create mode 100644 hardware/v2/docs/DatasheetLatex/chapters/08-status-roadmap.aux create mode 100644 hardware/v2/docs/DatasheetLatex/chapters/08-status-roadmap.tex create mode 100644 hardware/v2/docs/DatasheetLatex/preamble.tex create mode 100644 hardware/v2/reports/step_final_pnr_worst_seed4.log create mode 100644 hardware/v2/reports/step_final_synthesis.log create mode 100644 hardware/v2/reports/step_final_timing.csv diff --git a/hardware/v2/constraints/v2_board_top.lpf b/hardware/v2/constraints/v2_board_top.lpf new file mode 100644 index 0000000..9fe3c5d --- /dev/null +++ b/hardware/v2/constraints/v2_board_top.lpf @@ -0,0 +1,98 @@ +// FPGA-Neural V2 -- FINAL board-level top constraints (STEP-final). +// Target: fpga_neural_v2_top (N_SLOTS=2 default in this file's own +// simulation-facing top; the frozen hardware reference is N_SLOTS=4, +// synthesized separately at that parameter value -- see the synthesis +// log for the actual instantiation used for these P&R runs). +// FPGA: LFE5U-45F-8BG381, package CABGA381, speed grade -8 +// +// This supersedes hardware/v2/constraints/v2_unified.lpf (which +// constrained the OLDER nms_neural_multiprocessor_sdram_unified.v +// simulation-facing top, with its raw 110-pin reg_* bus and an +// assumed-already-80MHz `clk` input). The board-level top has NO +// reg_* ports at all -- job registration is via 4 real SPI pins, +// and the input clock is a real 16MHz oscillator feeding a real +// EHXPLLL (ecp5_pll_sys_clk.v), not a pre-generated 80MHz. +// +// Every ball below is real, sourced from the official Lattice +// pinout CSV (FPGA-SC-02034-3-0-ECP5U-45-Pinout.csv rev 3.0, +// ~/Downloads/, cross-referenced against docs/pinouts.md) -- none +// invented. osc_clk/ext_rst_n reuse the SAME real balls (H5/B4) as +// V1's own validated spi_neuron_top.lpf and the previous v2_unified +// .lpf (same physical clock/reset pins on this package regardless of +// which V2 top-level is programmed). The 4 SPI pins and pll_locked +// are NEW real balls from banks 6/7 (plain GPIO, dual function "-" +// in the CSV, not previously used by the 37-signal SDRAM bus). + +BLOCK ASYNCPATHS; +BLOCK RESETPATHS; + +// Real 16MHz board oscillator (external to the FPGA; EHXPLLL inside +// the design generates the internal 64MHz system clock -- see +// ecp5_pll_sys_clk.v's own FREQUENCY_PIN_CLKI/CLKOP attributes, +// which nextpnr-ecp5 reads automatically for the generated-clock +// domain; no separate LPF entry is needed for the internal 64MHz net). +FREQUENCY PORT "osc_clk" 16 MHZ; +LOCATE COMP "osc_clk" SITE "H5"; +IOBUF PORT "osc_clk" IO_TYPE=LVCMOS33; + +LOCATE COMP "ext_rst_n" SITE "B4"; +IOBUF PORT "ext_rst_n" IO_TYPE=LVCMOS33; + +// ---- real SPI host interface (4 pins, banks 6/7) ---- +LOCATE COMP "spi_sclk" SITE "L3"; IOBUF PORT "spi_sclk" IO_TYPE=LVCMOS33; +LOCATE COMP "spi_mosi" SITE "M3"; IOBUF PORT "spi_mosi" IO_TYPE=LVCMOS33; +LOCATE COMP "spi_miso" SITE "L2"; IOBUF PORT "spi_miso" IO_TYPE=LVCMOS33; +LOCATE COMP "spi_cs_n" SITE "N2"; IOBUF PORT "spi_cs_n" IO_TYPE=LVCMOS33; + +// ---- PLL lock status (debug/bring-up signal, real ball) ---- +LOCATE COMP "pll_locked" SITE "L1"; IOBUF PORT "pll_locked" IO_TYPE=LVCMOS33; + +// ---- SDRAM interface (37 signals), unchanged from v2_unified.lpf, +// real balls, banks 6/7 ---- +LOCATE COMP "sdram_cke" SITE "B5"; IOBUF PORT "sdram_cke" IO_TYPE=LVCMOS33; +LOCATE COMP "sdram_cs_n" SITE "C5"; IOBUF PORT "sdram_cs_n" IO_TYPE=LVCMOS33; +LOCATE COMP "sdram_ras_n" SITE "C4"; IOBUF PORT "sdram_ras_n" IO_TYPE=LVCMOS33; +LOCATE COMP "sdram_cas_n" SITE "A3"; IOBUF PORT "sdram_cas_n" IO_TYPE=LVCMOS33; +LOCATE COMP "sdram_we_n" SITE "B3"; IOBUF PORT "sdram_we_n" IO_TYPE=LVCMOS33; + +LOCATE COMP "sdram_ba[0]" SITE "E4"; IOBUF PORT "sdram_ba[0]" IO_TYPE=LVCMOS33; +LOCATE COMP "sdram_ba[1]" SITE "C3"; IOBUF PORT "sdram_ba[1]" IO_TYPE=LVCMOS33; + +LOCATE COMP "sdram_a[0]" SITE "D5"; IOBUF PORT "sdram_a[0]" IO_TYPE=LVCMOS33; +LOCATE COMP "sdram_a[1]" SITE "D3"; IOBUF PORT "sdram_a[1]" IO_TYPE=LVCMOS33; +LOCATE COMP "sdram_a[2]" SITE "F4"; IOBUF PORT "sdram_a[2]" IO_TYPE=LVCMOS33; +LOCATE COMP "sdram_a[3]" SITE "E5"; IOBUF PORT "sdram_a[3]" IO_TYPE=LVCMOS33; +LOCATE COMP "sdram_a[4]" SITE "E3"; IOBUF PORT "sdram_a[4]" IO_TYPE=LVCMOS33; +LOCATE COMP "sdram_a[5]" SITE "F5"; IOBUF PORT "sdram_a[5]" IO_TYPE=LVCMOS33; +LOCATE COMP "sdram_a[6]" SITE "A2"; IOBUF PORT "sdram_a[6]" IO_TYPE=LVCMOS33; +LOCATE COMP "sdram_a[7]" SITE "B1"; IOBUF PORT "sdram_a[7]" IO_TYPE=LVCMOS33; +LOCATE COMP "sdram_a[8]" SITE "C2"; IOBUF PORT "sdram_a[8]" IO_TYPE=LVCMOS33; +LOCATE COMP "sdram_a[9]" SITE "C1"; IOBUF PORT "sdram_a[9]" IO_TYPE=LVCMOS33; +LOCATE COMP "sdram_a[10]" SITE "D2"; IOBUF PORT "sdram_a[10]" IO_TYPE=LVCMOS33; +LOCATE COMP "sdram_a[11]" SITE "D1"; IOBUF PORT "sdram_a[11]" IO_TYPE=LVCMOS33; + +LOCATE COMP "sdram_dq[0]" SITE "E1"; IOBUF PORT "sdram_dq[0]" IO_TYPE=LVCMOS33; +LOCATE COMP "sdram_dq[1]" SITE "G5"; IOBUF PORT "sdram_dq[1]" IO_TYPE=LVCMOS33; +LOCATE COMP "sdram_dq[2]" SITE "H3"; IOBUF PORT "sdram_dq[2]" IO_TYPE=LVCMOS33; +LOCATE COMP "sdram_dq[3]" SITE "J5"; IOBUF PORT "sdram_dq[3]" IO_TYPE=LVCMOS33; +LOCATE COMP "sdram_dq[4]" SITE "K3"; IOBUF PORT "sdram_dq[4]" IO_TYPE=LVCMOS33; +LOCATE COMP "sdram_dq[5]" SITE "K2"; IOBUF PORT "sdram_dq[5]" IO_TYPE=LVCMOS33; +LOCATE COMP "sdram_dq[6]" SITE "H1"; IOBUF PORT "sdram_dq[6]" IO_TYPE=LVCMOS33; +LOCATE COMP "sdram_dq[7]" SITE "J1"; IOBUF PORT "sdram_dq[7]" IO_TYPE=LVCMOS33; +LOCATE COMP "sdram_dq[8]" SITE "K1"; IOBUF PORT "sdram_dq[8]" IO_TYPE=LVCMOS33; +LOCATE COMP "sdram_dq[9]" SITE "K4"; IOBUF PORT "sdram_dq[9]" IO_TYPE=LVCMOS33; +LOCATE COMP "sdram_dq[10]" SITE "L4"; IOBUF PORT "sdram_dq[10]" IO_TYPE=LVCMOS33; +LOCATE COMP "sdram_dq[11]" SITE "L5"; IOBUF PORT "sdram_dq[11]" IO_TYPE=LVCMOS33; +LOCATE COMP "sdram_dq[12]" SITE "M5"; IOBUF PORT "sdram_dq[12]" IO_TYPE=LVCMOS33; +LOCATE COMP "sdram_dq[13]" SITE "M4"; IOBUF PORT "sdram_dq[13]" IO_TYPE=LVCMOS33; +LOCATE COMP "sdram_dq[14]" SITE "N4"; IOBUF PORT "sdram_dq[14]" IO_TYPE=LVCMOS33; +LOCATE COMP "sdram_dq[15]" SITE "N5"; IOBUF PORT "sdram_dq[15]" IO_TYPE=LVCMOS33; + +LOCATE COMP "sdram_dqm[0]" SITE "P5"; IOBUF PORT "sdram_dqm[0]" IO_TYPE=LVCMOS33; +LOCATE COMP "sdram_dqm[1]" SITE "N3"; IOBUF PORT "sdram_dqm[1]" IO_TYPE=LVCMOS33; + +// All 16 top-level ports of fpga_neural_v2_top are now real-ball +// assigned: osc_clk, ext_rst_n, spi_sclk, spi_mosi, spi_miso, +// spi_cs_n, sdram_cke, sdram_cs_n, sdram_ras_n, sdram_cas_n, +// sdram_we_n, sdram_ba[1:0], sdram_a[11:0], sdram_dq[15:0], +// sdram_dqm[1:0], pll_locked -- no placeholders remain in THIS LPF. diff --git a/hardware/v2/docs/DatasheetLatex/FPGA-Neural-V2-Datasheet-EN.aux b/hardware/v2/docs/DatasheetLatex/FPGA-Neural-V2-Datasheet-EN.aux new file mode 100644 index 0000000..3985760 --- /dev/null +++ b/hardware/v2/docs/DatasheetLatex/FPGA-Neural-V2-Datasheet-EN.aux @@ -0,0 +1,21 @@ +\relax +\providecommand \babel@aux [2]{\global \let \babel@toc \@gobbletwo } +\@nameuse{bbl@beforestart} +\providecommand\hyper@newdestlabel[2]{} +\providecommand\HyField@AuxAddToFields[1]{} +\providecommand\HyField@AuxAddToCoFields[2]{} +\babel@aux{english}{} +\pgfsyspdfmark {pgfid1}{5216401}{50184874} +\gdef \LT@i {\LT@entry + {1}{108.73918pt}\LT@entry + {1}{120.12054pt}\LT@entry + {1}{243.45622pt}} +\@input{chapters/01-overview.aux} +\@input{chapters/02-architecture.aux} +\@input{chapters/03-clock-reset.aux} +\@input{chapters/04-host-interface.aux} +\@input{chapters/05-pinout-timing.aux} +\@input{chapters/06-power-configuration.aux} +\@input{chapters/07-benchmarks.aux} +\@input{chapters/08-status-roadmap.aux} +\gdef \@abspage@last{16} diff --git a/hardware/v2/docs/DatasheetLatex/FPGA-Neural-V2-Datasheet-EN.log b/hardware/v2/docs/DatasheetLatex/FPGA-Neural-V2-Datasheet-EN.log new file mode 100644 index 0000000..37c2b29 --- /dev/null +++ b/hardware/v2/docs/DatasheetLatex/FPGA-Neural-V2-Datasheet-EN.log @@ -0,0 +1,1667 @@ +This is pdfTeX, Version 3.141592653-2.6-1.40.27 (TeX Live 2025) (preloaded format=pdflatex 2025.11.21) 6 SEP 2026 17:49 +entering extended mode + restricted \write18 enabled. + %&-line parsing enabled. +**FPGA-Neural-V2-Datasheet-EN.tex +(./FPGA-Neural-V2-Datasheet-EN.tex +LaTeX2e <2024-11-01> patch level 2 +L3 programming layer <2025-01-18> +(/usr/local/texlive/2025/texmf-dist/tex/latex/base/report.cls +Document Class: report 2024/06/29 v1.4n Standard LaTeX document class +(/usr/local/texlive/2025/texmf-dist/tex/latex/base/size11.clo +File: size11.clo 2024/06/29 v1.4n Standard LaTeX file (size option) +) +\c@part=\count196 +\c@chapter=\count197 +\c@section=\count198 +\c@subsection=\count199 +\c@subsubsection=\count266 +\c@paragraph=\count267 +\c@subparagraph=\count268 +\c@figure=\count269 +\c@table=\count270 +\abovecaptionskip=\skip49 +\belowcaptionskip=\skip50 +\bibindent=\dimen141 +) (./preamble.tex (/usr/local/texlive/2025/texmf-dist/tex/latex/base/fontenc.st +y +Package: fontenc 2021/04/29 v2.0v Standard LaTeX package +) +(/usr/local/texlive/2025/texmf-dist/tex/latex/base/inputenc.sty +Package: inputenc 2024/02/08 v1.3d Input encoding file +\inpenc@prehook=\toks17 +\inpenc@posthook=\toks18 +) +(/usr/local/texlive/2025/texmf-dist/tex/generic/babel/babel.sty +Package: babel 2025/02/14 v25.4 The multilingual framework for pdfLaTeX, LuaLaT +eX and XeLaTeX +\babel@savecnt=\count271 +\U@D=\dimen142 +\l@unhyphenated=\language90 + +(/usr/local/texlive/2025/texmf-dist/tex/generic/babel/txtbabel.def) +\bbl@readstream=\read2 +\bbl@dirlevel=\count272 + +(/usr/local/texlive/2025/texmf-dist/tex/generic/babel-english/english.ldf +Language: english 2017/06/06 v3.3r English support from the babel system +Package babel Info: Hyphen rules for 'canadian' set to \l@english +(babel) (\language0). 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+\renewcommand{\arraystretch}{1.25} +\arrayrulecolor{fnRule} + +% intestazione tabella colorata +\newcommand{\thd}[1]{\textbf{\color{white}#1}} +\newcommand{\rowh}{\rowcolor{fnDark}} +\newcommand{\rowa}{\rowcolor{fnLight}} + +% ---------- Caption ---------------------------------------------------- +\usepackage{caption} +\captionsetup{font=small,labelfont={bf,color=fnTeal},labelsep=period} + +% ---------- TikZ / pgfplots ------------------------------------------- +\usepackage{tikz} +\usetikzlibrary{arrows.meta,positioning,calc,shapes.geometric,shapes.misc, + fit,backgrounds,chains,decorations.pathreplacing,decorations.markings, + matrix,shadows.blur} +\usepackage{pgfplots} +\pgfplotsset{compat=1.17} +\usepackage{tikz-timing} + +% stili di blocco riusabili +\tikzset{ + fnblock/.style={draw=fnBlue,fill=fnLight,rounded corners=2pt, + minimum height=9mm,minimum width=24mm,align=center,font=\small, + inner sep=4pt,line width=0.7pt}, + fnblockT/.style={fnblock,draw=fnTeal,fill=fnLight2}, + fnblockD/.style={fnblock,draw=fnDark,fill=fnDark,text=white}, + fnblockA/.style={fnblock,draw=fnAmber,fill=white}, + fnreg/.style={draw=fnGrey,fill=white,minimum height=8mm,align=center, + font=\footnotesize,inner sep=3pt}, + fnstate/.style={draw=fnBlue,fill=fnLight,circle,minimum size=13mm, + align=center,font=\scriptsize,line width=0.7pt}, + fnarrow/.style={-{Stealth[length=2.6mm]},line width=0.8pt,draw=fnDark}, + fnarrowT/.style={-{Stealth[length=2.6mm]},line width=0.8pt,draw=fnTeal}, + fnbus/.style={-{Stealth[length=3mm]},line width=1.6pt,draw=fnBlue}, + fnlbl/.style={font=\scriptsize\itshape,fill=white,inner sep=1pt,text=fnGrey} +} + +% ---------- varie ------------------------------------------------------ +\newcommand{\reg}[1]{\texttt{\textbf{#1}}} +\newcommand{\sig}[1]{\texttt{#1}} +\newcommand{\op}[1]{\texttt{\color{fnBlue}#1}} +\newcommand{\PASS}{\textcolor{fnGreen}{\textbf{PASS}}} +\newcommand{\FAIL}{\textcolor{fnRed}{\textbf{FAIL}}} +\newcommand{\OK}{\textcolor{fnGreen}{\textbf{OK}}} +\newcommand{\code}[1]{\texttt{#1}} + +\usepackage{enumitem} +\setlist{noitemsep,topsep=2pt,leftmargin=1.4em} + +\usepackage[hidelinks,colorlinks=true,linkcolor=fnBlue,urlcolor=fnTeal, + citecolor=fnBlue]{hyperref} diff --git a/hardware/v2/reports/step_final_pnr_worst_seed4.log b/hardware/v2/reports/step_final_pnr_worst_seed4.log new file mode 100644 index 0000000..cd6ca06 --- /dev/null +++ b/hardware/v2/reports/step_final_pnr_worst_seed4.log @@ -0,0 +1,378 @@ +Info: constraining clock net 'osc_clk' to 16.00 MHz + +Info: Logic utilisation before packing: +Info: Total LUT4s: 6634/43848 15% +Info: logic LUTs: 4074/43848 9% +Info: carry LUTs: 1426/43848 3% +Info: RAM LUTs: 756/ 5481 13% +Info: RAMW LUTs: 378/10962 3% + +Info: Total DFFs: 6322/43848 14% + +Info: Packing IOs.. +Info: $sdram_dq[15]$iobuf_i: sdram_dq_$_TBUF__Y.Y +Info: pin 'sdram_dq[15]$tr_io' constrained to Bel 'X0/Y59/PIOB'. +Info: $sdram_dq[14]$iobuf_i: sdram_dq_$_TBUF__Y_15.Y +Info: pin 'sdram_dq[14]$tr_io' constrained to Bel 'X0/Y59/PIOC'. +Info: $sdram_dq[13]$iobuf_i: sdram_dq_$_TBUF__Y_14.Y +Info: pin 'sdram_dq[13]$tr_io' constrained to Bel 'X0/Y59/PIOA'. +Info: $sdram_dq[12]$iobuf_i: sdram_dq_$_TBUF__Y_13.Y +Info: pin 'sdram_dq[12]$tr_io' constrained to Bel 'X0/Y53/PIOA'. +Info: $sdram_dq[11]$iobuf_i: sdram_dq_$_TBUF__Y_12.Y +Info: pin 'sdram_dq[11]$tr_io' constrained to Bel 'X0/Y44/PIOD'. +Info: $sdram_dq[10]$iobuf_i: sdram_dq_$_TBUF__Y_11.Y +Info: pin 'sdram_dq[10]$tr_io' constrained to Bel 'X0/Y44/PIOC'. +Info: $sdram_dq[9]$iobuf_i: sdram_dq_$_TBUF__Y_10.Y +Info: pin 'sdram_dq[9]$tr_io' constrained to Bel 'X0/Y44/PIOA'. +Info: $sdram_dq[8]$iobuf_i: sdram_dq_$_TBUF__Y_9.Y +Info: pin 'sdram_dq[8]$tr_io' constrained to Bel 'X0/Y41/PIOD'. +Info: $sdram_dq[7]$iobuf_i: sdram_dq_$_TBUF__Y_8.Y +Info: pin 'sdram_dq[7]$tr_io' constrained to Bel 'X0/Y41/PIOB'. +Info: $sdram_dq[6]$iobuf_i: sdram_dq_$_TBUF__Y_7.Y +Info: pin 'sdram_dq[6]$tr_io' constrained to Bel 'X0/Y41/PIOC'. +Info: $sdram_dq[5]$iobuf_i: sdram_dq_$_TBUF__Y_6.Y +Info: pin 'sdram_dq[5]$tr_io' constrained to Bel 'X0/Y41/PIOA'. +Info: $sdram_dq[4]$iobuf_i: sdram_dq_$_TBUF__Y_5.Y +Info: pin 'sdram_dq[4]$tr_io' constrained to Bel 'X0/Y38/PIOD'. +Info: $sdram_dq[3]$iobuf_i: sdram_dq_$_TBUF__Y_4.Y +Info: pin 'sdram_dq[3]$tr_io' constrained to Bel 'X0/Y38/PIOB'. +Info: $sdram_dq[2]$iobuf_i: sdram_dq_$_TBUF__Y_3.Y +Info: pin 'sdram_dq[2]$tr_io' constrained to Bel 'X0/Y29/PIOD'. +Info: $sdram_dq[1]$iobuf_i: sdram_dq_$_TBUF__Y_2.Y +Info: pin 'sdram_dq[1]$tr_io' constrained to Bel 'X0/Y29/PIOB'. +Info: $sdram_dq[0]$iobuf_i: sdram_dq_$_TBUF__Y_1.Y +Info: pin 'sdram_dq[0]$tr_io' constrained to Bel 'X0/Y26/PIOD'. +Info: pin 'spi_sclk$tr_io' constrained to Bel 'X0/Y62/PIOC'. +Info: pin 'spi_mosi$tr_io' constrained to Bel 'X0/Y62/PIOB'. +Info: pin 'spi_miso$tr_io' constrained to Bel 'X0/Y62/PIOD'. +Info: pin 'spi_cs_n$tr_io' constrained to Bel 'X0/Y65/PIOA'. +Info: pin 'sdram_we_n$tr_io' constrained to Bel 'X0/Y14/PIOD'. +Info: pin 'sdram_ras_n$tr_io' constrained to Bel 'X0/Y14/PIOA'. +Info: pin 'sdram_dqm[1]$tr_io' constrained to Bel 'X0/Y62/PIOA'. +Info: pin 'sdram_dqm[0]$tr_io' constrained to Bel 'X0/Y59/PIOD'. +Info: pin 'sdram_cs_n$tr_io' constrained to Bel 'X0/Y11/PIOD'. +Info: pin 'sdram_cke$tr_io' constrained to Bel 'X0/Y11/PIOC'. +Info: pin 'sdram_cas_n$tr_io' constrained to Bel 'X0/Y14/PIOC'. +Info: pin 'sdram_ba[1]$tr_io' constrained to Bel 'X0/Y17/PIOC'. +Info: pin 'sdram_ba[0]$tr_io' constrained to Bel 'X0/Y17/PIOA'. +Info: pin 'sdram_a[11]$tr_io' constrained to Bel 'X0/Y26/PIOB'. +Info: pin 'sdram_a[10]$tr_io' constrained to Bel 'X0/Y26/PIOC'. +Info: pin 'sdram_a[9]$tr_io' constrained to Bel 'X0/Y26/PIOA'. +Info: pin 'sdram_a[8]$tr_io' constrained to Bel 'X0/Y23/PIOD'. +Info: pin 'sdram_a[7]$tr_io' constrained to Bel 'X0/Y23/PIOB'. +Info: pin 'sdram_a[6]$tr_io' constrained to Bel 'X0/Y23/PIOA'. +Info: pin 'sdram_a[5]$tr_io' constrained to Bel 'X0/Y20/PIOD'. +Info: pin 'sdram_a[4]$tr_io' constrained to Bel 'X0/Y20/PIOB'. +Info: pin 'sdram_a[3]$tr_io' constrained to Bel 'X0/Y20/PIOC'. +Info: pin 'sdram_a[2]$tr_io' constrained to Bel 'X0/Y20/PIOA'. +Info: pin 'sdram_a[1]$tr_io' constrained to Bel 'X0/Y17/PIOD'. +Info: pin 'sdram_a[0]$tr_io' constrained to Bel 'X0/Y17/PIOB'. +Info: pin 'pll_locked$tr_io' constrained to Bel 'X0/Y65/PIOC'. +Info: pin 'osc_clk$tr_io' constrained to Bel 'X0/Y29/PIOC'. +Info: pin 'ext_rst_n$tr_io' constrained to Bel 'X0/Y14/PIOB'. +Info: placed PLL 'u_pll.pll_i' at bel 'X1/Y4/EHXPLL_UL' +Info: Packing constants.. +Info: Packing carries... +Info: Packing LUTs... +Info: Packing LUT5-7s... +Info: Packing FFs... +Info: 2575 FFs paired with LUTs. +Info: Generating derived timing constraints... +Info: Input frequency of PLL 'u_pll.pll_i' is constrained to 16.0 MHz +Info: Derived frequency constraint of 64.0 MHz for net clk +Info: Promoting globals... +Info: promoting clock net clk to global network +Info: Checksum: 0xb24b3184 + +Info: Device utilisation: +Info: TRELLIS_IO: 44/ 245 17% +Info: DCCA: 1/ 56 1% +Info: DP16KD: 0/ 108 0% +Info: MULT18X18D: 32/ 72 44% +Info: ALU54B: 0/ 36 0% +Info: EHXPLLL: 1/ 4 25% +Info: EXTREFB: 0/ 2 0% +Info: DCUA: 0/ 2 0% +Info: PCSCLKDIV: 0/ 2 0% +Info: IOLOGIC: 0/ 160 0% +Info: SIOLOGIC: 0/ 85 0% +Info: GSR: 0/ 1 0% +Info: JTAGG: 0/ 1 0% +Info: OSCG: 0/ 1 0% +Info: SEDGA: 0/ 1 0% +Info: DTR: 0/ 1 0% +Info: USRMCLK: 0/ 1 0% +Info: CLKDIVF: 0/ 4 0% +Info: ECLKSYNCB: 0/ 10 0% +Info: DLLDELD: 0/ 8 0% +Info: DDRDLL: 0/ 4 0% +Info: DQSBUFM: 0/ 10 0% +Info: TRELLIS_ECLKBUF: 0/ 8 0% +Info: ECLKBRIDGECS: 0/ 2 0% +Info: DCSC: 0/ 2 0% +Info: TRELLIS_FF: 6322/ 43848 14% +Info: TRELLIS_COMB: 7084/ 43848 16% +Info: TRELLIS_RAMW: 189/ 5481 3% + +Info: Placed 45 cells based on constraints. +Info: Creating initial analytic placement for 7811 cells, random placement wirelen = 635413. +Info: at initial placer iter 0, wirelen = 3641 +Info: at initial placer iter 1, wirelen = 3058 +Info: at initial placer iter 2, wirelen = 2978 +Info: at initial placer iter 3, wirelen = 3006 +Info: Running main analytical placer, max placement attempts per cell = 23368866. +Info: at iteration #1, type ALL: wirelen solved = 2851, spread = 105823, legal = 123819; time = 0.20s +Info: at iteration #2, type ALL: wirelen solved = 12848, spread = 74308, legal = 90806; time = 0.19s +Info: at iteration #3, type ALL: wirelen solved = 18878, spread = 70946, legal = 86425; time = 0.16s +Info: at iteration #4, type ALL: wirelen solved = 23629, spread = 67877, legal = 80958; time = 0.16s +Info: at iteration #5, type ALL: wirelen solved = 25972, spread = 66034, legal = 82304; time = 0.14s +Info: at iteration #6, type ALL: wirelen solved = 27044, spread = 64778, legal = 81280; time = 0.16s +Info: at iteration #7, type ALL: wirelen solved = 27677, spread = 65077, legal = 78916; time = 0.13s +Info: at iteration #8, type ALL: wirelen solved = 28674, spread = 64171, legal = 80070; time = 0.16s +Info: at iteration #9, type ALL: wirelen solved = 29347, spread = 64047, legal = 77328; time = 0.15s +Info: at iteration #10, type ALL: wirelen solved = 29869, spread = 64168, legal = 79757; time = 0.15s +Info: at iteration #11, type ALL: wirelen solved = 30347, spread = 63680, legal = 78577; time = 0.14s +Info: at iteration #12, type ALL: wirelen solved = 30887, spread = 67391, legal = 77285; time = 0.14s +Info: at iteration #13, type ALL: wirelen solved = 34628, spread = 66938, legal = 79231; time = 0.14s +Info: at iteration #14, type ALL: wirelen solved = 35255, spread = 66705, legal = 76218; time = 0.11s +Info: at iteration #15, type ALL: wirelen solved = 35781, spread = 66489, legal = 76421; time = 0.12s +Info: at iteration #16, type ALL: wirelen solved = 35889, spread = 66722, legal = 79650; time = 0.13s +Info: at iteration #17, type ALL: wirelen solved = 35933, spread = 66113, legal = 76579; time = 0.14s +Info: at iteration #18, type ALL: wirelen solved = 36378, spread = 66541, legal = 79035; time = 0.14s +Info: at iteration #19, type ALL: wirelen solved = 36628, spread = 66908, legal = 79994; time = 0.13s +Info: HeAP Placer Time: 3.65s +Info: of which solving equations: 1.79s +Info: of which spreading cells: 0.31s +Info: of which strict legalisation: 1.01s + +Info: Running simulated annealing placer for refinement. +Info: at iteration #1: temp = 0.000000, timing cost = 811, wirelen = 76218 +Info: at iteration #5: temp = 0.000000, timing cost = 1839, wirelen = 70366 +Info: at iteration #10: temp = 0.000000, timing cost = 1064, wirelen = 68627 +Info: at iteration #15: temp = 0.000000, timing cost = 998, wirelen = 68181 +Info: at iteration #20: temp = 0.000000, timing cost = 989, wirelen = 68031 +Info: at iteration #25: temp = 0.000000, timing cost = 981, wirelen = 67961 +Info: at iteration #26: temp = 0.000000, timing cost = 976, wirelen = 67948 +Info: SA placement time 5.68s + +Info: Max frequency for clock '$glbnet$clk': 55.01 MHz (FAIL at 64.00 MHz) + +Info: Max delay -> posedge $glbnet$clk: 5.11 ns +Info: Max delay posedge $glbnet$clk -> : 11.47 ns + +Info: Slack histogram: +Info: legend: * represents 35 endpoint(s) +Info: + represents [1,35) endpoint(s) +Info: [ -2553, -1682) |+ +Info: [ -1682, -811) |+ +Info: [ -811, 60) |***+ +Info: [ 60, 931) |***+ +Info: [ 931, 1802) |****+ +Info: [ 1802, 2673) |******+ +Info: [ 2673, 3544) |********+ +Info: [ 3544, 4415) |************+ +Info: [ 4415, 5286) |****************+ +Info: [ 5286, 6157) |*********************************+ +Info: [ 6157, 7028) |***************************************+ +Info: [ 7028, 7899) |******************************************+ +Info: [ 7899, 8770) |******************************+ +Info: [ 8770, 9641) |********************************+ +Info: [ 9641, 10512) |******************************+ +Info: [ 10512, 11383) |********************************+ +Info: [ 11383, 12254) |*****************************************************+ +Info: [ 12254, 13125) |************************************************************ +Info: [ 13125, 13996) |*******************************************************+ +Info: [ 13996, 14867) |*********************************************+ +Info: Checksum: 0x5d5c6e8a +Info: Routing globals... +Info: routing clock net $glbnet$clk using global 0 + +Info: Routing.. +Info: Setting up routing queue. +Info: Routing 37675 arcs. +Info: | (re-)routed arcs | delta | remaining| time spent | +Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| +Info: 1000 | 419 580 | 419 580 | 37353| 0.43 0.43| +Info: 2000 | 583 1416 | 164 836 | 36558| 0.23 0.66| +Info: 3000 | 770 2229 | 187 813 | 35851| 0.20 0.86| +Info: 4000 | 911 3088 | 141 859 | 35050| 0.16 1.02| +Info: 5000 | 1030 3969 | 119 881 | 34240| 0.14 1.16| +Info: 6000 | 1126 4873 | 96 904 | 33433| 0.15 1.31| +Info: 7000 | 1228 5771 | 102 898 | 32626| 0.13 1.44| +Info: 8000 | 1315 6684 | 87 913 | 31773| 0.15 1.60| +Info: 9000 | 1415 7584 | 100 900 | 30983| 0.14 1.73| +Info: 10000 | 1551 8448 | 136 864 | 30319| 0.16 1.90| +Info: 11000 | 1652 9347 | 101 899 | 29468| 0.14 2.04| +Info: 12000 | 1762 10237 | 110 890 | 28715| 0.12 2.15| +Info: 13000 | 1904 11095 | 142 858 | 27921| 0.14 2.29| +Info: 14000 | 2069 11930 | 165 835 | 27228| 0.13 2.42| +Info: 15000 | 2184 12815 | 115 885 | 26471| 0.13 2.55| +Info: 16000 | 2327 13672 | 143 857 | 25781| 0.17 2.71| +Info: 17000 | 2504 14495 | 177 823 | 25060| 0.12 2.84| +Info: 18000 | 2737 15262 | 233 767 | 24524| 0.15 2.98| +Info: 19000 | 2876 16123 | 139 861 | 23853| 0.19 3.17| +Info: 20000 | 3048 16948 | 172 825 | 23152| 0.13 3.30| +Info: 21000 | 3336 17659 | 288 711 | 22496| 0.12 3.42| +Info: 22000 | 3544 18440 | 208 781 | 21769| 0.11 3.54| +Info: 23000 | 3769 19204 | 225 764 | 21250| 0.18 3.71| +Info: 24000 | 4012 19949 | 243 745 | 20632| 0.15 3.86| +Info: 25000 | 4252 20697 | 240 748 | 19952| 0.14 4.00| +Info: 26000 | 4517 21413 | 265 716 | 19279| 0.12 4.12| +Info: 27000 | 4726 22171 | 209 758 | 18550| 0.13 4.25| +Info: 28000 | 4914 22961 | 188 790 | 17871| 0.13 4.39| +Info: 29000 | 5077 23715 | 163 754 | 17083| 0.12 4.51| +Info: 30000 | 5244 24483 | 167 768 | 16309| 0.11 4.62| +Info: 31000 | 5441 25242 | 197 759 | 15588| 0.12 4.74| +Info: 32000 | 5647 26002 | 206 760 | 15031| 0.15 4.89| +Info: 33000 | 5815 26811 | 168 809 | 14346| 0.11 5.00| +Info: 34000 | 5963 27591 | 148 780 | 13591| 0.12 5.12| +Info: 35000 | 6114 28372 | 151 781 | 12881| 0.15 5.28| +Info: 36000 | 6255 29197 | 141 825 | 12144| 0.12 5.40| +Info: 37000 | 6417 30013 | 162 816 | 11508| 0.16 5.56| +Info: 38000 | 6512 30859 | 95 846 | 10796| 0.12 5.68| +Info: 39000 | 6634 31704 | 122 845 | 9991| 0.15 5.83| +Info: 40000 | 6755 32507 | 121 803 | 9206| 0.11 5.94| +Info: 41000 | 6919 33305 | 164 798 | 8538| 0.21 6.15| +Info: 42000 | 7054 34113 | 135 808 | 7753| 0.15 6.30| +Info: 43000 | 7173 34919 | 119 806 | 6932| 0.12 6.42| +Info: 44000 | 7402 35656 | 229 737 | 6354| 0.24 6.66| +Info: 45000 | 7499 36517 | 97 861 | 5552| 0.09 6.76| +Info: 46000 | 7761 37251 | 262 734 | 5018| 0.24 7.00| +Info: 47000 | 8050 37956 | 289 705 | 4602| 0.23 7.23| +Info: 48000 | 8179 38827 | 129 871 | 3829| 0.10 7.33| +Info: 49000 | 8436 39570 | 257 743 | 3221| 0.29 7.61| +Info: 50000 | 8700 40306 | 264 736 | 2865| 0.31 7.92| +Info: 51000 | 8962 41044 | 262 738 | 2239| 0.16 8.08| +Info: 52000 | 9165 41792 | 203 748 | 1504| 0.15 8.23| +Info: 53000 | 9312 42547 | 147 755 | 895| 0.22 8.45| +Info: 54000 | 9443 43303 | 131 756 | 142| 0.19 8.64| +Info: 54162 | 9461 43421 | 18 118 | 0| 0.05 8.69| +Info: Routing complete. +Info: Router1 time 8.69s +Info: Checksum: 0x662d74ce + +Info: Critical path report for clock '$glbnet$clk' (posedge -> posedge): +Info: type curr total name +Info: clk-to-q 0.52 0.52 Source u_arbiter_wide.m_addr_TRELLIS_FF_Q_15.Q +Info: routing 0.92 1.45 Net wide_arb_m_addr[16] (19,3) -> (18,3) +Info: Sink u_sdram_backend.w_hit_idx_c_LUT4_Z_D_LUT4_Z_1_D_LUT4_Z_D_LUT4_Z_3_D_LUT4_Z.C +Info: Defined in: +Info: hardware/v2/nms/rtl/fpga_neural_v2_top.v:217.28-217.43 +Info: logic 0.24 1.68 Source u_sdram_backend.w_hit_idx_c_LUT4_Z_D_LUT4_Z_1_D_LUT4_Z_D_LUT4_Z_3_D_LUT4_Z.F +Info: routing 0.62 2.31 Net u_sdram_backend.w_hit_idx_c_LUT4_Z_D_LUT4_Z_1_D_LUT4_Z_D_LUT4_Z_3_D[2] (18,3) -> (18,3) +Info: Sink u_sdram_backend.w_hit_idx_c_LUT4_Z_D_LUT4_Z_1_D_LUT4_Z_D_LUT4_Z_3.D +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 +Info: logic 0.24 2.54 Source u_sdram_backend.w_hit_idx_c_LUT4_Z_D_LUT4_Z_1_D_LUT4_Z_D_LUT4_Z_3.F +Info: routing 1.13 3.67 Net u_sdram_backend.w_hit_idx_c_LUT4_Z_D_LUT4_Z_1_D_LUT4_Z_D[2] (18,3) -> (17,4) +Info: Sink u_sdram_backend.w_hit_idx_c_LUT4_Z_D_LUT4_Z_1_D_LUT4_Z.C +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 +Info: logic 0.24 3.90 Source u_sdram_backend.w_hit_idx_c_LUT4_Z_D_LUT4_Z_1_D_LUT4_Z.F +Info: routing 0.88 4.78 Net u_sdram_backend.w_hit_idx_c_LUT4_Z_D_LUT4_Z_1_D[3] (17,4) -> (16,4) +Info: Sink u_sdram_backend.w_hit_idx_c_LUT4_Z_D_LUT4_Z_1.D +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 +Info: logic 0.24 5.02 Source u_sdram_backend.w_hit_idx_c_LUT4_Z_D_LUT4_Z_1.F +Info: routing 1.78 6.80 Net u_sdram_backend.w_hit_idx_c_LUT4_Z_C[0] (16,4) -> (13,21) +Info: Sink u_sdram_backend.w_hit_idx_c_LUT4_Z_1.C +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 +Info: logic 0.24 7.03 Source u_sdram_backend.w_hit_idx_c_LUT4_Z_1.F +Info: routing 1.39 8.43 Net u_sdram_backend.w_hit_idx_c[1] (13,21) -> (14,11) +Info: Sink u_sdram_backend.w_hit_idx_c_LUT4_Z_C_LUT4_C.D +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 +Info: logic 0.24 8.66 Source u_sdram_backend.w_hit_idx_c_LUT4_Z_C_LUT4_C.F +Info: routing 0.43 9.09 Net u_sdram_backend.w_hit_idx_c_LUT4_Z_C_LUT4_C_Z[1] (14,11) -> (14,11) +Info: Sink u_sdram_backend.w_hit_idx_c_LUT4_Z_C_LUT4_C_Z_LUT4_D.D +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 +Info: logic 0.24 9.32 Source u_sdram_backend.w_hit_idx_c_LUT4_Z_C_LUT4_C_Z_LUT4_D.F +Info: routing 2.36 11.69 Net u_sdram_backend.w_hit_idx_c_LUT4_Z_C_LUT4_C_Z_LUT4_D_Z[1] (14,11) -> (12,40) +Info: Sink u_sdram_backend.w_hit_idx_c_LUT4_Z_C_LUT4_C_Z_LUT4_D_Z_LUT4_D.D +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 +Info: logic 0.24 11.92 Source u_sdram_backend.w_hit_idx_c_LUT4_Z_C_LUT4_C_Z_LUT4_D_Z_LUT4_D.F +Info: routing 2.67 14.60 Net u_sdram_backend.w_hit_idx_c_LUT4_Z_C_LUT4_C_Z_LUT4_D_Z_LUT4_D_Z (12,40) -> (14,7) +Info: Sink u_sdram_backend.w_rdata_TRELLIS_FF_Q_51.CE +Info: setup 0.00 14.60 Source u_sdram_backend.w_rdata_TRELLIS_FF_Q_51.CE +Info: 2.41 ns logic, 12.18 ns routing + +Info: Critical path report for cross-domain path '' -> 'posedge $glbnet$clk': +Info: type curr total name +Info: source 0.00 0.00 Source sdram_dq[3]$tr_io.O +Info: routing 3.24 3.24 Net sdram_dq[3]$TRELLIS_IO_IN (0,38) -> (14,18) +Info: Sink u_sdram_backend.u_sdram_ctrl.rdata_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_S1_S0_LUT4_D_2_Z_LUT4_D_Z_LUT4_Z_14_D_LUT4_Z.B +Info: Defined in: +Info: hardware/v2/nms/rtl/sdram_controller.v:80.25-80.33 +Info: logic 0.24 3.47 Source u_sdram_backend.u_sdram_ctrl.rdata_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_S1_S0_LUT4_D_2_Z_LUT4_D_Z_LUT4_Z_14_D_LUT4_Z.F +Info: routing 0.70 4.17 Net u_sdram_backend.u_sdram_ctrl.rdata_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_S1_S0_LUT4_D_2_Z_LUT4_D_Z_LUT4_Z_14_D[2] (14,18) -> (14,19) +Info: Sink u_sdram_backend.u_sdram_ctrl.rdata_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_S1_S0_LUT4_D_2_Z_LUT4_D_Z_LUT4_Z_14.D +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 +Info: logic 0.24 4.41 Source u_sdram_backend.u_sdram_ctrl.rdata_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_S1_S0_LUT4_D_2_Z_LUT4_D_Z_LUT4_Z_14.F +Info: routing 0.13 4.53 Net u_sdram_backend.u_sdram_ctrl.rdata_TRELLIS_FF_Q_DI_LUT4_Z_D_CCU2C_S1_S0_LUT4_D_2_Z_LUT4_D_Z[51] (14,19) -> (14,19) +Info: Sink u_sdram_backend.u_sdram_ctrl.rdata_TRELLIS_FF_Q_51.DI +Info: setup 0.00 4.53 Source u_sdram_backend.u_sdram_ctrl.rdata_TRELLIS_FF_Q_51.DI +Info: 0.47 ns logic, 4.06 ns routing + +Info: Critical path report for cross-domain path 'posedge $glbnet$clk' -> '': +Info: type curr total name +Info: clk-to-q 0.52 0.52 Source u_spi_bridge.byte_idx_TRELLIS_FF_Q.Q +Info: routing 2.25 2.78 Net u_spi_bridge.byte_idx[0] (24,52) -> (25,29) +Info: Sink u_spi_bridge.rx_valid_LUT4_C_Z_LUT4_Z_C_LUT4_Z.D +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 +Info: logic 0.24 3.01 Source u_spi_bridge.rx_valid_LUT4_C_Z_LUT4_Z_C_LUT4_Z.F +Info: routing 0.43 3.44 Net u_spi_bridge.rx_valid_LUT4_C_Z_LUT4_Z_C[0] (25,29) -> (25,29) +Info: Sink u_spi_bridge.rx_valid_LUT4_C_Z_LUT4_Z.C +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 +Info: logic 0.24 3.68 Source u_spi_bridge.rx_valid_LUT4_C_Z_LUT4_Z.F +Info: routing 2.89 6.57 Net u_spi_bridge.byte_idx_TRELLIS_FF_Q_DI_LUT4_Z_D[1] (25,29) -> (21,56) +Info: Sink spi_miso_LUT4_Z_D_LUT4_Z.D +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 +Info: logic 0.24 6.80 Source spi_miso_LUT4_Z_D_LUT4_Z.F +Info: routing 0.22 7.02 Net spi_miso_LUT4_Z_B[3] (21,56) -> (21,56) +Info: Sink spi_miso_LUT4_Z.D +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 +Info: logic 0.24 7.26 Source spi_miso_LUT4_Z.F +Info: routing 2.13 9.39 Net spi_miso$TRELLIS_IO_OUT (21,56) -> (0,62) +Info: Sink spi_miso$tr_io.I +Info: Defined in: +Info: hardware/v2/rtl/spi_host_bridge.v:83.17-83.21 +Info: 1.47 ns logic, 7.92 ns routing + +Info: Max frequency for clock '$glbnet$clk': 68.51 MHz (PASS at 64.00 MHz) + +Info: Max delay -> posedge $glbnet$clk: 4.53 ns +Info: Max delay posedge $glbnet$clk -> : 9.39 ns + +Info: Slack histogram: +Info: legend: * represents 35 endpoint(s) +Info: + represents [1,35) endpoint(s) +Info: [ 1029, 1712) |+ +Info: [ 1712, 2395) |+ +Info: [ 2395, 3078) |**+ +Info: [ 3078, 3761) |****+ +Info: [ 3761, 4444) |******+ +Info: [ 4444, 5127) |******+ +Info: [ 5127, 5810) |*******+ +Info: [ 5810, 6493) |**********+ +Info: [ 6493, 7176) |***************+ +Info: [ 7176, 7859) |*******************+ +Info: [ 7859, 8542) |***********************************+ +Info: [ 8542, 9225) |*************************************************+ +Info: [ 9225, 9908) |**********************************+ +Info: [ 9908, 10591) |******************************+ +Info: [ 10591, 11274) |*************************************+ +Info: [ 11274, 11957) |***************************+ +Info: [ 11957, 12640) |**********************************************+ +Info: [ 12640, 13323) |***********************************************************+ +Info: [ 13323, 14006) |************************************************************ +Info: [ 14006, 14689) |********************************************************+ + +Info: Program finished normally. diff --git a/hardware/v2/reports/step_final_synthesis.log b/hardware/v2/reports/step_final_synthesis.log new file mode 100644 index 0000000..f2f12ca --- /dev/null +++ b/hardware/v2/reports/step_final_synthesis.log @@ -0,0 +1,18198 @@ + + /----------------------------------------------------------------------------\ + | yosys -- Yosys Open SYnthesis Suite | + | Copyright (C) 2012 - 2026 Claire Xenia Wolf | + | Distributed under an ISC-like license, type "license" to see terms | + \----------------------------------------------------------------------------/ + Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101) + +-- Executing script file `/tmp/v2_final_synth/synth.ys' -- + +1. Executing Verilog-2005 frontend: hardware/v2/rtl/dependency_manager.v +Parsing SystemVerilog input from `hardware/v2/rtl/dependency_manager.v' to AST representation. +Generating RTLIL representation for module `\dependency_manager'. +Successfully finished Verilog frontend. + +2. Executing Verilog-2005 frontend: hardware/v2/rtl/neural_director.v +Parsing SystemVerilog input from `hardware/v2/rtl/neural_director.v' to AST representation. +Generating RTLIL representation for module `\neural_director'. +Successfully finished Verilog frontend. + +3. Executing Verilog-2005 frontend: hardware/v2/rtl/neural_processor.v +Parsing SystemVerilog input from `hardware/v2/rtl/neural_processor.v' to AST representation. +Generating RTLIL representation for module `\neural_processor'. +Warning: Replacing memory \tree with list of registers. See hardware/v2/rtl/neural_processor.v:193 +Warning: Replacing memory \prod1 with list of registers. See hardware/v2/rtl/neural_processor.v:151 +Warning: Replacing memory \w0 with list of registers. See hardware/v2/rtl/neural_processor.v:122 +Warning: Replacing memory \x0 with list of registers. See hardware/v2/rtl/neural_processor.v:121 +Successfully finished Verilog frontend. + +4. Executing Verilog-2005 frontend: hardware/v2/rtl/slot_mem_arbiter.v +Parsing SystemVerilog input from `hardware/v2/rtl/slot_mem_arbiter.v' to AST representation. +Generating RTLIL representation for module `\slot_mem_arbiter'. +Successfully finished Verilog frontend. + +5. Executing Verilog-2005 frontend: hardware/v2/rtl/slot_mem_arbiter_wide.v +Parsing SystemVerilog input from `hardware/v2/rtl/slot_mem_arbiter_wide.v' to AST representation. +Generating RTLIL representation for module `\slot_mem_arbiter_wide'. +Successfully finished Verilog frontend. + +6. Executing Verilog-2005 frontend: hardware/v2/rtl/prefetch_engine.v +Parsing SystemVerilog input from `hardware/v2/rtl/prefetch_engine.v' to AST representation. +Generating RTLIL representation for module `\prefetch_engine'. +Successfully finished Verilog frontend. + +7. Executing Verilog-2005 frontend: hardware/v2/rtl/spi_host_bridge.v +Parsing SystemVerilog input from `hardware/v2/rtl/spi_host_bridge.v' to AST representation. +Generating RTLIL representation for module `\spi_host_bridge'. +Successfully finished Verilog frontend. + +8. Executing Verilog-2005 frontend: hardware/v2/rtl/ecp5_pll_sys_clk.v +Parsing SystemVerilog input from `hardware/v2/rtl/ecp5_pll_sys_clk.v' to AST representation. +Generating RTLIL representation for module `\ecp5_pll_sys_clk'. +Successfully finished Verilog frontend. + +9. Executing Verilog-2005 frontend: hardware/v2/rtl/reset_sync.v +Parsing SystemVerilog input from `hardware/v2/rtl/reset_sync.v' to AST representation. +Generating RTLIL representation for module `\reset_sync'. +Successfully finished Verilog frontend. + +10. Executing Verilog-2005 frontend: hardware/v2/nms/rtl/nms_dataflow_core_sdram.v +Parsing SystemVerilog input from `hardware/v2/nms/rtl/nms_dataflow_core_sdram.v' to AST representation. +Generating RTLIL representation for module `\nms_dataflow_core_sdram'. +Successfully finished Verilog frontend. + +11. Executing Verilog-2005 frontend: hardware/v2/nms/rtl/nms_activation_replicated.v +Parsing SystemVerilog input from `hardware/v2/nms/rtl/nms_activation_replicated.v' to AST representation. +Generating RTLIL representation for module `\nms_activation_replicated'. +Successfully finished Verilog frontend. + +12. Executing Verilog-2005 frontend: hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v +Parsing SystemVerilog input from `hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v' to AST representation. +Generating RTLIL representation for module `\nms_activation_fill_ctrl_v3'. +Warning: Replacing memory \n_tiles_masked with list of registers. See hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:117 +Successfully finished Verilog frontend. + +13. Executing Verilog-2005 frontend: hardware/v2/nms/rtl/nms_weight_packed.v +Parsing SystemVerilog input from `hardware/v2/nms/rtl/nms_weight_packed.v' to AST representation. +Generating RTLIL representation for module `\nms_weight_packed'. +Successfully finished Verilog frontend. + +14. Executing Verilog-2005 frontend: hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v +Parsing SystemVerilog input from `hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v' to AST representation. +Generating RTLIL representation for module `\nms_memory_manager_stream_wide'. +Successfully finished Verilog frontend. + +15. Executing Verilog-2005 frontend: hardware/v2/nms/rtl/weight_prefetch_engine_wide.v +Parsing SystemVerilog input from `hardware/v2/nms/rtl/weight_prefetch_engine_wide.v' to AST representation. +Generating RTLIL representation for module `\weight_prefetch_engine_wide'. +Successfully finished Verilog frontend. + +16. Executing Verilog-2005 frontend: hardware/v2/nms/rtl/sdram_unified_backend.v +Parsing SystemVerilog input from `hardware/v2/nms/rtl/sdram_unified_backend.v' to AST representation. +Generating RTLIL representation for module `\sdram_unified_backend'. +Successfully finished Verilog frontend. + +17. Executing Verilog-2005 frontend: hardware/v2/nms/rtl/sdram_controller.v +Parsing SystemVerilog input from `hardware/v2/nms/rtl/sdram_controller.v' to AST representation. +hardware/v2/nms/rtl/sdram_controller.v:180: Warning: Yosys has only limited support for tri-state logic at the moment. +Generating RTLIL representation for module `\sdram_controller'. +Successfully finished Verilog frontend. + +18. Executing Verilog-2005 frontend: hardware/v2/nms/rtl/fpga_neural_v2_top.v +Parsing SystemVerilog input from `hardware/v2/nms/rtl/fpga_neural_v2_top.v' to AST representation. +Generating RTLIL representation for module `\fpga_neural_v2_top'. +Successfully finished Verilog frontend. + +19. Executing SYNTH_LATTICE pass. + +19.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v' to AST representation. +Generating RTLIL representation for module `\LUT4'. +Generating RTLIL representation for module `\$__ABC9_LUT5'. +Generating RTLIL representation for module `\$__ABC9_LUT6'. +Generating RTLIL representation for module `\$__ABC9_LUT7'. +Generating RTLIL representation for module `\L6MUX21'. +Generating RTLIL representation for module `\TRELLIS_RAM16X2'. +Generating RTLIL representation for module `\PFUMX'. +Generating RTLIL representation for module `\TRELLIS_DPR16X4'. +Generating RTLIL representation for module `\DPR16X4C'. +Generating RTLIL representation for module `\LUT2'. +Generating RTLIL representation for module `\TRELLIS_FF'. +Generating RTLIL representation for module `\TRELLIS_IO'. +Generating RTLIL representation for module `\INV'. +Generating RTLIL representation for module `\TRELLIS_COMB'. +Generating RTLIL representation for module `\VLO'. +Generating RTLIL representation for module `\VHI'. +Generating RTLIL representation for module `\FD1P3AX'. +Generating RTLIL representation for module `\FD1P3AY'. +Generating RTLIL representation for module `\FD1P3BX'. +Generating RTLIL representation for module `\FD1P3DX'. +Generating RTLIL representation for module `\FD1P3IX'. +Generating RTLIL representation for module `\FD1P3JX'. +Generating RTLIL representation for module `\FD1S3AX'. +Generating RTLIL representation for module `\FD1S3AY'. +Generating RTLIL representation for module `\FD1S3BX'. +Generating RTLIL representation for module `\FD1S3DX'. +Generating RTLIL representation for module `\FD1S3IX'. +Generating RTLIL representation for module `\FD1S3JX'. +Generating RTLIL representation for module `\IFS1P3BX'. +Generating RTLIL representation for module `\IFS1P3DX'. +Generating RTLIL representation for module `\IFS1P3IX'. +Generating RTLIL representation for module `\IFS1P3JX'. +Generating RTLIL representation for module `\OFS1P3BX'. +Generating RTLIL representation for module `\OFS1P3DX'. +Generating RTLIL representation for module `\OFS1P3IX'. +Generating RTLIL representation for module `\OFS1P3JX'. +Generating RTLIL representation for module `\IB'. +Generating RTLIL representation for module `\IBPU'. +Generating RTLIL representation for module `\IBPD'. +Generating RTLIL representation for module `\OB'. +Generating RTLIL representation for module `\OBZ'. +Generating RTLIL representation for module `\OBZPU'. +Generating RTLIL representation for module `\OBZPD'. +Generating RTLIL representation for module `\OBCO'. +Generating RTLIL representation for module `\BB'. +Generating RTLIL representation for module `\BBPU'. +Generating RTLIL representation for module `\BBPD'. +Generating RTLIL representation for module `\ILVDS'. +Generating RTLIL representation for module `\OLVDS'. +Generating RTLIL representation for module `\CCU2C'. +Generating RTLIL representation for module `\DP16KD'. +Replacing existing blackbox module `\FD1P3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:2.1-2.261. +Generating RTLIL representation for module `\FD1P3AX'. +Replacing existing blackbox module `\FD1P3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:3.1-3.261. +Generating RTLIL representation for module `\FD1P3AY'. +Replacing existing blackbox module `\FD1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:4.1-4.261. +Generating RTLIL representation for module `\FD1P3BX'. +Replacing existing blackbox module `\FD1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:5.1-5.261. +Generating RTLIL representation for module `\FD1P3DX'. +Replacing existing blackbox module `\FD1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:6.1-6.261. +Generating RTLIL representation for module `\FD1P3IX'. +Replacing existing blackbox module `\FD1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:7.1-7.261. +Generating RTLIL representation for module `\FD1P3JX'. +Replacing existing blackbox module `\FD1S3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:8.1-8.261. +Generating RTLIL representation for module `\FD1S3AX'. +Replacing existing blackbox module `\FD1S3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:9.1-9.261. +Generating RTLIL representation for module `\FD1S3AY'. +Replacing existing blackbox module `\FD1S3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:10.1-10.261. +Generating RTLIL representation for module `\FD1S3BX'. +Replacing existing blackbox module `\FD1S3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:11.1-11.261. +Generating RTLIL representation for module `\FD1S3DX'. +Replacing existing blackbox module `\FD1S3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:12.1-12.261. +Generating RTLIL representation for module `\FD1S3IX'. +Replacing existing blackbox module `\FD1S3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:13.1-13.261. +Generating RTLIL representation for module `\FD1S3JX'. +Replacing existing blackbox module `\IFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:26.1-26.301. +Generating RTLIL representation for module `\IFS1P3BX'. +Replacing existing blackbox module `\IFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:27.1-27.301. +Generating RTLIL representation for module `\IFS1P3DX'. +Replacing existing blackbox module `\IFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:28.1-28.301. +Generating RTLIL representation for module `\IFS1P3IX'. +Replacing existing blackbox module `\IFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:29.1-29.301. +Generating RTLIL representation for module `\IFS1P3JX'. +Replacing existing blackbox module `\OFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:31.1-31.302. +Generating RTLIL representation for module `\OFS1P3BX'. +Replacing existing blackbox module `\OFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:32.1-32.302. +Generating RTLIL representation for module `\OFS1P3DX'. +Replacing existing blackbox module `\OFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:33.1-33.302. +Generating RTLIL representation for module `\OFS1P3IX'. +Replacing existing blackbox module `\OFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:34.1-34.302. +Generating RTLIL representation for module `\OFS1P3JX'. +Replacing existing blackbox module `\IB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:2.1-2.157. +Generating RTLIL representation for module `\IB'. +Replacing existing blackbox module `\IBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:3.1-3.157. +Generating RTLIL representation for module `\IBPU'. +Replacing existing blackbox module `\IBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:4.1-4.157. +Generating RTLIL representation for module `\IBPD'. +Replacing existing blackbox module `\OB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:5.1-5.157. +Generating RTLIL representation for module `\OB'. +Replacing existing blackbox module `\OBZ' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:6.1-6.164. +Generating RTLIL representation for module `\OBZ'. +Replacing existing blackbox module `\OBZPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:7.1-7.164. +Generating RTLIL representation for module `\OBZPU'. +Replacing existing blackbox module `\OBZPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:8.1-8.164. +Generating RTLIL representation for module `\OBZPD'. +Replacing existing blackbox module `\OBCO' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:9.1-9.90. +Generating RTLIL representation for module `\OBCO'. +Replacing existing blackbox module `\BB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:10.1-10.179. +Generating RTLIL representation for module `\BB'. +Replacing existing blackbox module `\BBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:11.1-11.179. +Generating RTLIL representation for module `\BBPU'. +Replacing existing blackbox module `\BBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:12.1-12.179. +Generating RTLIL representation for module `\BBPD'. +Replacing existing blackbox module `\ILVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:13.1-13.139. +Generating RTLIL representation for module `\ILVDS'. +Replacing existing blackbox module `\OLVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:14.1-14.146. +Generating RTLIL representation for module `\OLVDS'. +Successfully finished Verilog frontend. + +19.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v' to AST representation. +Generating RTLIL representation for module `\GSR'. +Generating RTLIL representation for module `\PUR'. +Generating RTLIL representation for module `\SGSR'. +Generating RTLIL representation for module `\PDPW16KD'. +Generating RTLIL representation for module `\MULT18X18D'. +Generating RTLIL representation for module `\ALU54B'. +Generating RTLIL representation for module `\CLKDIVF'. +Generating RTLIL representation for module `\PCSCLKDIV'. +Generating RTLIL representation for module `\DCSC'. +Generating RTLIL representation for module `\DCCA'. +Generating RTLIL representation for module `\ECLKSYNCB'. +Generating RTLIL representation for module `\ECLKBRIDGECS'. +Generating RTLIL representation for module `\DELAYF'. +Generating RTLIL representation for module `\DELAYG'. +Generating RTLIL representation for module `\USRMCLK'. +Generating RTLIL representation for module `\DQSBUFM'. +Generating RTLIL representation for module `\DDRDLLA'. +Generating RTLIL representation for module `\DLLDELD'. +Generating RTLIL representation for module `\IDDRX1F'. +Generating RTLIL representation for module `\IDDRX2F'. +Generating RTLIL representation for module `\IDDR71B'. +Generating RTLIL representation for module `\IDDRX2DQA'. +Generating RTLIL representation for module `\ODDRX1F'. +Generating RTLIL representation for module `\ODDRX2F'. +Generating RTLIL representation for module `\ODDR71B'. +Generating RTLIL representation for module `\OSHX2A'. +Generating RTLIL representation for module `\TSHX2DQA'. +Generating RTLIL representation for module `\TSHX2DQSA'. +Generating RTLIL representation for module `\ODDRX2DQA'. +Generating RTLIL representation for module `\ODDRX2DQSB'. +Generating RTLIL representation for module `\EHXPLLL'. +Generating RTLIL representation for module `\DTR'. +Generating RTLIL representation for module `\OSCG'. +Generating RTLIL representation for module `\EXTREFB'. +Generating RTLIL representation for module `\JTAGG'. +Generating RTLIL representation for module `\DCUA'. +Successfully finished Verilog frontend. + +19.3. Executing HIERARCHY pass (managing design hierarchy). + +19.3.1. Analyzing design hierarchy.. +Top module: \fpga_neural_v2_top +Used module: \sdram_unified_backend +Used module: \sdram_controller +Used module: \slot_mem_arbiter_wide +Used module: \slot_mem_arbiter +Used module: \nms_dataflow_core_sdram +Used module: \neural_processor +Used module: \nms_memory_manager_stream_wide +Used module: \weight_prefetch_engine_wide +Used module: \nms_weight_packed +Used module: \nms_activation_fill_ctrl_v3 +Used module: \prefetch_engine +Used module: \nms_activation_replicated +Used module: \neural_director +Used module: \dependency_manager +Used module: \spi_host_bridge +Used module: \reset_sync +Used module: \ecp5_pll_sys_clk +Parameter \DATA_WIDTH = 8 +Parameter \P_IN = 8 +Parameter \ACC_WIDTH = 32 + +19.3.2. Executing AST frontend in derive mode using pre-parsed AST for module `\neural_processor'. +Parameter \DATA_WIDTH = 8 +Parameter \P_IN = 8 +Parameter \ACC_WIDTH = 32 +Generating RTLIL representation for module `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor'. +Warning: Replacing memory \tree with list of registers. See hardware/v2/rtl/neural_processor.v:193 +Warning: Replacing memory \prod1 with list of registers. See hardware/v2/rtl/neural_processor.v:151 +Warning: Replacing memory \w0 with list of registers. See hardware/v2/rtl/neural_processor.v:122 +Warning: Replacing memory \x0 with list of registers. See hardware/v2/rtl/neural_processor.v:121 +Parameter \MEM_DATA_WIDTH = 64 +Parameter \DATA_WIDTH = 8 +Parameter \P_IN = 8 +Parameter \ADDR_WIDTH = 23 +Parameter \MAX_TILES = 16 +Parameter \PREFETCH_DISTANCE = 8 + +19.3.3. Executing AST frontend in derive mode using pre-parsed AST for module `\nms_memory_manager_stream_wide'. +Parameter \MEM_DATA_WIDTH = 64 +Parameter \DATA_WIDTH = 8 +Parameter \P_IN = 8 +Parameter \ADDR_WIDTH = 23 +Parameter \MAX_TILES = 16 +Parameter \PREFETCH_DISTANCE = 8 +Generating RTLIL representation for module `$paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide'. +Parameter \DATA_WIDTH = 8 +Parameter \P_IN = 8 +Parameter \ACC_WIDTH = 32 +Found cached RTLIL representation for module `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor'. +Parameter \MEM_DATA_WIDTH = 64 +Parameter \DATA_WIDTH = 8 +Parameter \P_IN = 8 +Parameter \ADDR_WIDTH = 23 +Parameter \MAX_TILES = 16 +Parameter \PREFETCH_DISTANCE = 8 +Found cached RTLIL representation for module `$paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide'. +Parameter \DATA_WIDTH = 8 +Parameter \P_IN = 8 +Parameter \ACC_WIDTH = 32 +Found cached RTLIL representation for module `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor'. +Parameter \MEM_DATA_WIDTH = 64 +Parameter \DATA_WIDTH = 8 +Parameter \P_IN = 8 +Parameter \ADDR_WIDTH = 23 +Parameter \MAX_TILES = 16 +Parameter \PREFETCH_DISTANCE = 8 +Found cached RTLIL representation for module `$paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide'. +Parameter \DATA_WIDTH = 8 +Parameter \P_IN = 8 +Parameter \ACC_WIDTH = 32 +Found cached RTLIL representation for module `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor'. +Parameter \MEM_DATA_WIDTH = 64 +Parameter \DATA_WIDTH = 8 +Parameter \P_IN = 8 +Parameter \ADDR_WIDTH = 23 +Parameter \MAX_TILES = 16 +Parameter \PREFETCH_DISTANCE = 8 +Found cached RTLIL representation for module `$paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide'. +Parameter \DATA_WIDTH = 8 +Parameter \P_IN = 8 +Parameter \N_SLOTS = 4 +Parameter \MAX_TILES = 16 + +19.3.4. Executing AST frontend in derive mode using pre-parsed AST for module `\nms_weight_packed'. +Parameter \DATA_WIDTH = 8 +Parameter \P_IN = 8 +Parameter \N_SLOTS = 4 +Parameter \MAX_TILES = 16 +Generating RTLIL representation for module `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed'. +Parameter \DATA_WIDTH = 8 +Parameter \P_IN = 8 +Parameter \N_SLOTS = 4 +Parameter \ADDR_WIDTH = 23 +Parameter \MAX_TILES = 16 + +19.3.5. Executing AST frontend in derive mode using pre-parsed AST for module `\nms_activation_fill_ctrl_v3'. +Parameter \DATA_WIDTH = 8 +Parameter \P_IN = 8 +Parameter \N_SLOTS = 4 +Parameter \ADDR_WIDTH = 23 +Parameter \MAX_TILES = 16 +Generating RTLIL representation for module `$paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3'. +Warning: Replacing memory \n_tiles_masked with list of registers. See hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:117 +Parameter \DATA_WIDTH = 8 +Parameter \P_IN = 8 +Parameter \N_SLOTS = 4 +Parameter \MAX_TILES = 16 + +19.3.6. Executing AST frontend in derive mode using pre-parsed AST for module `\nms_activation_replicated'. +Parameter \DATA_WIDTH = 8 +Parameter \P_IN = 8 +Parameter \N_SLOTS = 4 +Parameter \MAX_TILES = 16 +Generating RTLIL representation for module `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated'. +Parameter \ADDR_WIDTH = 23 +Parameter \N_SLOTS = 4 +Parameter \QUEUE_DEPTH = 8 + +19.3.7. Executing AST frontend in derive mode using pre-parsed AST for module `\neural_director'. +Parameter \ADDR_WIDTH = 23 +Parameter \N_SLOTS = 4 +Parameter \QUEUE_DEPTH = 8 +Generating RTLIL representation for module `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director'. +Parameter \N_NODES = 16 +Parameter \MAX_DEPS = 4 +Parameter \ADDR_WIDTH = 23 + +19.3.8. Executing AST frontend in derive mode using pre-parsed AST for module `\dependency_manager'. +Parameter \N_NODES = 16 +Parameter \MAX_DEPS = 4 +Parameter \ADDR_WIDTH = 23 +Generating RTLIL representation for module `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager'. +Reprocessing module nms_dataflow_core_sdram because instantiated module nms_memory_manager_stream_wide has become available. +Generating RTLIL representation for module `\nms_dataflow_core_sdram'. +Parameter \DATA_WIDTH = 8 +Parameter \P_IN = 8 +Parameter \ADDR_WIDTH = 23 +Parameter \MAX_TILES = 16 +Parameter \PREFETCH_DISTANCE = 8 +Parameter \MEM_DATA_WIDTH = 64 + +19.3.9. Executing AST frontend in derive mode using pre-parsed AST for module `\weight_prefetch_engine_wide'. +Parameter \DATA_WIDTH = 8 +Parameter \P_IN = 8 +Parameter \ADDR_WIDTH = 23 +Parameter \MAX_TILES = 16 +Parameter \PREFETCH_DISTANCE = 8 +Parameter \MEM_DATA_WIDTH = 64 +Generating RTLIL representation for module `$paramod$a83886fe79b03d603caba252b5389bc5341a5c19\weight_prefetch_engine_wide'. +Parameter \DATA_WIDTH = 8 +Parameter \P_IN = 8 +Parameter \ADDR_WIDTH = 23 + +19.3.10. Executing AST frontend in derive mode using pre-parsed AST for module `\prefetch_engine'. +Parameter \DATA_WIDTH = 8 +Parameter \P_IN = 8 +Parameter \ADDR_WIDTH = 23 +Generating RTLIL representation for module `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine'. +Parameter \CLK_FREQ_MHZ = 80 +Parameter \BURST_LEN = 8 +Parameter \ADDR_WIDTH = 22 + +19.3.11. Executing AST frontend in derive mode using pre-parsed AST for module `\sdram_controller'. +Parameter \CLK_FREQ_MHZ = 80 +Parameter \BURST_LEN = 8 +Parameter \ADDR_WIDTH = 22 +Generating RTLIL representation for module `$paramod$5e41e2f2469e9e5942dab766e736710259c3f58c\sdram_controller'. +Parameter \ADDR_WIDTH = 23 +Parameter \CLK_FREQ_MHZ = 64 + +19.3.12. Executing AST frontend in derive mode using pre-parsed AST for module `\sdram_unified_backend'. +Parameter \ADDR_WIDTH = 23 +Parameter \CLK_FREQ_MHZ = 64 +Generating RTLIL representation for module `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend'. +Parameter \DATA_WIDTH = 64 +Parameter \ADDR_WIDTH = 23 +Parameter \N_PORTS = 4 + +19.3.13. Executing AST frontend in derive mode using pre-parsed AST for module `\slot_mem_arbiter_wide'. +Parameter \DATA_WIDTH = 64 +Parameter \ADDR_WIDTH = 23 +Parameter \N_PORTS = 4 +Generating RTLIL representation for module `$paramod$8ef509dd8065f2599f8ea3948e2930abb5d7b7b0\slot_mem_arbiter_wide'. +Parameter \ADDR_WIDTH = 23 +Parameter \N_PORTS = 2 + +19.3.14. Executing AST frontend in derive mode using pre-parsed AST for module `\slot_mem_arbiter'. +Parameter \ADDR_WIDTH = 23 +Parameter \N_PORTS = 2 +Generating RTLIL representation for module `$paramod$13018cccabdf3dac026b50531aeca2ed1853451d\slot_mem_arbiter'. +Parameter \ADDR_WIDTH = 23 +Parameter \N_PORTS = 5 + +19.3.15. Executing AST frontend in derive mode using pre-parsed AST for module `\slot_mem_arbiter'. +Parameter \ADDR_WIDTH = 23 +Parameter \N_PORTS = 5 +Generating RTLIL representation for module `$paramod$8ec81e5664842acf17791930d1f62ccccc9cf0b8\slot_mem_arbiter'. +Parameter \DATA_WIDTH = 8 +Parameter \P_IN = 8 +Parameter \ACC_WIDTH = 32 +Parameter \ADDR_WIDTH = 23 +Parameter \N_SLOTS = 4 +Parameter \N_NODES = 16 +Parameter \MAX_DEPS = 4 +Parameter \QUEUE_DEPTH = 8 +Parameter \MAX_TILES = 16 +Parameter \PREFETCH_DISTANCE = 8 + +19.3.16. Executing AST frontend in derive mode using pre-parsed AST for module `\nms_dataflow_core_sdram'. +Parameter \DATA_WIDTH = 8 +Parameter \P_IN = 8 +Parameter \ACC_WIDTH = 32 +Parameter \ADDR_WIDTH = 23 +Parameter \N_SLOTS = 4 +Parameter \N_NODES = 16 +Parameter \MAX_DEPS = 4 +Parameter \QUEUE_DEPTH = 8 +Parameter \MAX_TILES = 16 +Parameter \PREFETCH_DISTANCE = 8 +Generating RTLIL representation for module `$paramod$5eff1de9335b9030234048498b6a1d64bf783cb3\nms_dataflow_core_sdram'. +Parameter \ADDR_WIDTH = 23 +Parameter \N_NODES = 16 +Parameter \MAX_DEPS = 4 + +19.3.17. Executing AST frontend in derive mode using pre-parsed AST for module `\spi_host_bridge'. +Parameter \ADDR_WIDTH = 23 +Parameter \N_NODES = 16 +Parameter \MAX_DEPS = 4 +Generating RTLIL representation for module `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge'. + +19.3.18. Analyzing design hierarchy.. +Top module: \fpga_neural_v2_top +Used module: $paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend +Used module: \sdram_controller +Used module: $paramod$8ef509dd8065f2599f8ea3948e2930abb5d7b7b0\slot_mem_arbiter_wide +Used module: $paramod$13018cccabdf3dac026b50531aeca2ed1853451d\slot_mem_arbiter +Used module: $paramod$8ec81e5664842acf17791930d1f62ccccc9cf0b8\slot_mem_arbiter +Used module: $paramod$5eff1de9335b9030234048498b6a1d64bf783cb3\nms_dataflow_core_sdram +Used module: \neural_processor +Used module: \nms_memory_manager_stream_wide +Used module: $paramod$a83886fe79b03d603caba252b5389bc5341a5c19\weight_prefetch_engine_wide +Used module: \nms_weight_packed +Used module: \nms_activation_fill_ctrl_v3 +Used module: $paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine +Used module: \nms_activation_replicated +Used module: \neural_director +Used module: \dependency_manager +Used module: $paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge +Used module: \reset_sync +Used module: \ecp5_pll_sys_clk +Parameter \CLK_FREQ_MHZ = 64 +Parameter \BURST_LEN = 8 +Parameter \ADDR_WIDTH = 22 + +19.3.19. Executing AST frontend in derive mode using pre-parsed AST for module `\sdram_controller'. +Parameter \CLK_FREQ_MHZ = 64 +Parameter \BURST_LEN = 8 +Parameter \ADDR_WIDTH = 22 +Generating RTLIL representation for module `$paramod$d1bf252c98cb2b8284c90cfb859e00756f939daa\sdram_controller'. +Parameter \DATA_WIDTH = 8 +Parameter \P_IN = 8 +Parameter \ACC_WIDTH = 32 +Found cached RTLIL representation for module `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor'. +Parameter \MEM_DATA_WIDTH = 64 +Parameter \DATA_WIDTH = 8 +Parameter \P_IN = 8 +Parameter \ADDR_WIDTH = 23 +Parameter \MAX_TILES = 16 +Parameter \PREFETCH_DISTANCE = 8 +Found cached RTLIL representation for module `$paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide'. +Parameter \DATA_WIDTH = 8 +Parameter \P_IN = 8 +Parameter \ACC_WIDTH = 32 +Found cached RTLIL representation for module `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor'. +Parameter \MEM_DATA_WIDTH = 64 +Parameter \DATA_WIDTH = 8 +Parameter \P_IN = 8 +Parameter \ADDR_WIDTH = 23 +Parameter \MAX_TILES = 16 +Parameter \PREFETCH_DISTANCE = 8 +Found cached RTLIL representation for module `$paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide'. +Parameter \DATA_WIDTH = 8 +Parameter \P_IN = 8 +Parameter \ACC_WIDTH = 32 +Found cached RTLIL representation for module `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor'. +Parameter \MEM_DATA_WIDTH = 64 +Parameter \DATA_WIDTH = 8 +Parameter \P_IN = 8 +Parameter \ADDR_WIDTH = 23 +Parameter \MAX_TILES = 16 +Parameter \PREFETCH_DISTANCE = 8 +Found cached RTLIL representation for module `$paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide'. +Parameter \DATA_WIDTH = 8 +Parameter \P_IN = 8 +Parameter \ACC_WIDTH = 32 +Found cached RTLIL representation for module `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor'. +Parameter \MEM_DATA_WIDTH = 64 +Parameter \DATA_WIDTH = 8 +Parameter \P_IN = 8 +Parameter \ADDR_WIDTH = 23 +Parameter \MAX_TILES = 16 +Parameter \PREFETCH_DISTANCE = 8 +Found cached RTLIL representation for module `$paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide'. +Parameter \DATA_WIDTH = 8 +Parameter \P_IN = 8 +Parameter \N_SLOTS = 4 +Parameter \MAX_TILES = 16 +Found cached RTLIL representation for module `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed'. +Parameter \DATA_WIDTH = 8 +Parameter \P_IN = 8 +Parameter \N_SLOTS = 4 +Parameter \ADDR_WIDTH = 23 +Parameter \MAX_TILES = 16 +Found cached RTLIL representation for module `$paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3'. +Parameter \DATA_WIDTH = 8 +Parameter \P_IN = 8 +Parameter \N_SLOTS = 4 +Parameter \MAX_TILES = 16 +Found cached RTLIL representation for module `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated'. +Parameter \ADDR_WIDTH = 23 +Parameter \N_SLOTS = 4 +Parameter \QUEUE_DEPTH = 8 +Found cached RTLIL representation for module `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director'. +Parameter \N_NODES = 16 +Parameter \MAX_DEPS = 4 +Parameter \ADDR_WIDTH = 23 +Found cached RTLIL representation for module `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager'. + +19.3.20. Analyzing design hierarchy.. +Top module: \fpga_neural_v2_top +Used module: $paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend +Used module: $paramod$d1bf252c98cb2b8284c90cfb859e00756f939daa\sdram_controller +Used module: $paramod$8ef509dd8065f2599f8ea3948e2930abb5d7b7b0\slot_mem_arbiter_wide +Used module: $paramod$13018cccabdf3dac026b50531aeca2ed1853451d\slot_mem_arbiter +Used module: $paramod$8ec81e5664842acf17791930d1f62ccccc9cf0b8\slot_mem_arbiter +Used module: $paramod$5eff1de9335b9030234048498b6a1d64bf783cb3\nms_dataflow_core_sdram +Used module: $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor +Used module: $paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide +Used module: \weight_prefetch_engine_wide +Used module: $paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed +Used module: $paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3 +Used module: \prefetch_engine +Used module: $paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated +Used module: $paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director +Used module: $paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager +Used module: $paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge +Used module: \reset_sync +Used module: \ecp5_pll_sys_clk +Parameter \DATA_WIDTH = 8 +Parameter \P_IN = 8 +Parameter \ADDR_WIDTH = 23 +Parameter \MAX_TILES = 16 +Parameter \PREFETCH_DISTANCE = 8 +Parameter \MEM_DATA_WIDTH = 64 +Found cached RTLIL representation for module `$paramod$a83886fe79b03d603caba252b5389bc5341a5c19\weight_prefetch_engine_wide'. +Parameter \DATA_WIDTH = 8 +Parameter \P_IN = 8 +Parameter \ADDR_WIDTH = 23 +Found cached RTLIL representation for module `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine'. + +19.3.21. Analyzing design hierarchy.. +Top module: \fpga_neural_v2_top +Used module: $paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend +Used module: $paramod$d1bf252c98cb2b8284c90cfb859e00756f939daa\sdram_controller +Used module: $paramod$8ef509dd8065f2599f8ea3948e2930abb5d7b7b0\slot_mem_arbiter_wide +Used module: $paramod$13018cccabdf3dac026b50531aeca2ed1853451d\slot_mem_arbiter +Used module: $paramod$8ec81e5664842acf17791930d1f62ccccc9cf0b8\slot_mem_arbiter +Used module: $paramod$5eff1de9335b9030234048498b6a1d64bf783cb3\nms_dataflow_core_sdram +Used module: $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor +Used module: $paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide +Used module: $paramod$a83886fe79b03d603caba252b5389bc5341a5c19\weight_prefetch_engine_wide +Used module: $paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed +Used module: $paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3 +Used module: $paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine +Used module: $paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated +Used module: $paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director +Used module: $paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager +Used module: $paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge +Used module: \reset_sync +Used module: \ecp5_pll_sys_clk + +19.3.22. Analyzing design hierarchy.. +Top module: \fpga_neural_v2_top +Used module: $paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend +Used module: $paramod$d1bf252c98cb2b8284c90cfb859e00756f939daa\sdram_controller +Used module: $paramod$8ef509dd8065f2599f8ea3948e2930abb5d7b7b0\slot_mem_arbiter_wide +Used module: $paramod$13018cccabdf3dac026b50531aeca2ed1853451d\slot_mem_arbiter +Used module: $paramod$8ec81e5664842acf17791930d1f62ccccc9cf0b8\slot_mem_arbiter +Used module: $paramod$5eff1de9335b9030234048498b6a1d64bf783cb3\nms_dataflow_core_sdram +Used module: $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor +Used module: $paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide +Used module: $paramod$a83886fe79b03d603caba252b5389bc5341a5c19\weight_prefetch_engine_wide +Used module: $paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed +Used module: $paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3 +Used module: $paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine +Used module: $paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated +Used module: $paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director +Used module: $paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager +Used module: $paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge +Used module: \reset_sync +Used module: \ecp5_pll_sys_clk +Removing unused module `$paramod$5e41e2f2469e9e5942dab766e736710259c3f58c\sdram_controller'. +Removing unused module `\nms_dataflow_core_sdram'. +Removing unused module `\sdram_controller'. +Removing unused module `\sdram_unified_backend'. +Removing unused module `\weight_prefetch_engine_wide'. +Removing unused module `\nms_memory_manager_stream_wide'. +Removing unused module `\nms_weight_packed'. +Removing unused module `\nms_activation_fill_ctrl_v3'. +Removing unused module `\nms_activation_replicated'. +Removing unused module `\spi_host_bridge'. +Removing unused module `\prefetch_engine'. +Removing unused module `\slot_mem_arbiter_wide'. +Removing unused module `\slot_mem_arbiter'. +Removing unused module `\neural_processor'. +Removing unused module `\neural_director'. +Removing unused module `\dependency_manager'. +Removed 16 unused modules. + +19.4. Executing PROC pass (convert processes to netlists). + +19.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Found and cleaned up 1 empty switch in `$paramod$d1bf252c98cb2b8284c90cfb859e00756f939daa\sdram_controller.$proc$hardware/v2/nms/rtl/sdram_controller.v:196$7417'. +Cleaned up 1 empty switch. + +19.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Marked 1 switch rules as full_case in process $proc$hardware/v2/rtl/neural_processor.v:181$3731 in module $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor. +Marked 1 switch rules as full_case in process $proc$hardware/v2/rtl/neural_processor.v:181$3726 in module $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor. +Marked 1 switch rules as full_case in process $proc$hardware/v2/rtl/neural_processor.v:181$3717 in module $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor. +Marked 2 switch rules as full_case in process $proc$hardware/v2/rtl/neural_processor.v:305$3712 in module $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor. +Marked 2 switch rules as full_case in process $proc$hardware/v2/rtl/neural_processor.v:278$3702 in module $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor. +Marked 1 switch rules as full_case in process $proc$hardware/v2/rtl/neural_processor.v:245$3689 in module $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor. +Marked 2 switch rules as full_case in process $proc$hardware/v2/rtl/neural_processor.v:215$3686 in module $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor. +Marked 1 switch rules as full_case in process $proc$hardware/v2/rtl/neural_processor.v:143$3685 in module $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor. +Marked 2 switch rules as full_case in process $proc$hardware/v2/rtl/neural_processor.v:104$3680 in module $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor. +Marked 9 switch rules as full_case in process $proc$hardware/v2/rtl/slot_mem_arbiter.v:115$7147 in module $paramod$8ec81e5664842acf17791930d1f62ccccc9cf0b8\slot_mem_arbiter. +Marked 5 switch rules as full_case in process $proc$hardware/v2/rtl/slot_mem_arbiter.v:102$7145 in module $paramod$8ec81e5664842acf17791930d1f62ccccc9cf0b8\slot_mem_arbiter. +Marked 6 switch rules as full_case in process $proc$hardware/v2/rtl/slot_mem_arbiter.v:115$7113 in module $paramod$13018cccabdf3dac026b50531aeca2ed1853451d\slot_mem_arbiter. +Marked 2 switch rules as full_case in process $proc$hardware/v2/rtl/slot_mem_arbiter.v:102$7111 in module $paramod$13018cccabdf3dac026b50531aeca2ed1853451d\slot_mem_arbiter. +Marked 8 switch rules as full_case in process $proc$hardware/v2/rtl/slot_mem_arbiter_wide.v:116$7075 in module $paramod$8ef509dd8065f2599f8ea3948e2930abb5d7b7b0\slot_mem_arbiter_wide. +Marked 4 switch rules as full_case in process $proc$hardware/v2/rtl/slot_mem_arbiter_wide.v:103$7073 in module $paramod$8ef509dd8065f2599f8ea3948e2930abb5d7b7b0\slot_mem_arbiter_wide. +Marked 7 switch rules as full_case in process $proc$hardware/v2/nms/rtl/sdram_unified_backend.v:200$6968 in module $paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend. +Marked 4 switch rules as full_case in process $proc$hardware/v2/nms/rtl/sdram_unified_backend.v:115$6942 in module $paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend. +Marked 15 switch rules as full_case in process $proc$hardware/v2/nms/rtl/sdram_controller.v:196$7417 in module $paramod$d1bf252c98cb2b8284c90cfb859e00756f939daa\sdram_controller. +Marked 4 switch rules as full_case in process $proc$hardware/v2/rtl/prefetch_engine.v:82$6839 in module $paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine. +Marked 4 switch rules as full_case in process $proc$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:108$6796 in module $paramod$a83886fe79b03d603caba252b5389bc5341a5c19\weight_prefetch_engine_wide. +Marked 148 switch rules as full_case in process $proc$hardware/v2/rtl/dependency_manager.v:116$4677 in module $paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager. +Marked 16 switch rules as full_case in process $proc$hardware/v2/rtl/dependency_manager.v:103$4644 in module $paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager. +Marked 1 switch rules as full_case in process $proc$hardware/v2/rtl/reset_sync.v:27$2673 in module reset_sync. +Marked 2 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_dataflow_core_sdram.v:281$7317 in module $paramod$5eff1de9335b9030234048498b6a1d64bf783cb3\nms_dataflow_core_sdram. +Marked 2 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_dataflow_core_sdram.v:281$7314 in module $paramod$5eff1de9335b9030234048498b6a1d64bf783cb3\nms_dataflow_core_sdram. +Marked 2 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_dataflow_core_sdram.v:281$7311 in module $paramod$5eff1de9335b9030234048498b6a1d64bf783cb3\nms_dataflow_core_sdram. +Marked 2 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_dataflow_core_sdram.v:281$7308 in module $paramod$5eff1de9335b9030234048498b6a1d64bf783cb3\nms_dataflow_core_sdram. +Marked 9 switch rules as full_case in process $proc$hardware/v2/rtl/spi_host_bridge.v:259$7345 in module $paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge. +Marked 2 switch rules as full_case in process $proc$hardware/v2/rtl/spi_host_bridge.v:250$7338 in module $paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge. +Marked 4 switch rules as full_case in process $proc$hardware/v2/rtl/spi_host_bridge.v:192$7331 in module $paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge. +Marked 1 switch rules as full_case in process $proc$hardware/v2/rtl/spi_host_bridge.v:132$7320 in module $paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge. +Marked 1 switch rules as full_case in process $proc$hardware/v2/rtl/spi_host_bridge.v:118$7319 in module $paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge. +Marked 4 switch rules as full_case in process $proc$hardware/v2/rtl/neural_director.v:138$4283 in module $paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director. +Marked 4 switch rules as full_case in process $proc$hardware/v2/rtl/neural_director.v:131$4275 in module $paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director. +Marked 4 switch rules as full_case in process $proc$hardware/v2/rtl/neural_director.v:117$4274 in module $paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director. +Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_activation_replicated.v:42$4246 in module $paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated. +Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_activation_replicated.v:42$4235 in module $paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated. +Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_activation_replicated.v:42$4224 in module $paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated. +Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_activation_replicated.v:42$4213 in module $paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated. +Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:116$4207 in module $paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3. +Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:116$4203 in module $paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3. +Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:116$4199 in module $paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3. +Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:116$4195 in module $paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3. +Removed 1 dead cases from process $proc$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:164$4175 in module $paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3. +Marked 2 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:164$4175 in module $paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3. +Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:132$4174 in module $paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3. +Marked 4 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:126$4169 in module $paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3. +Marked 4 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:76$4168 in module $paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3. +Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4157 in module $paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed. +Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4146 in module $paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed. +Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4135 in module $paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed. +Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4124 in module $paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed. +Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4113 in module $paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed. +Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4102 in module $paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed. +Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4091 in module $paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed. +Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4080 in module $paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed. +Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4069 in module $paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed. +Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4058 in module $paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed. +Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4047 in module $paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed. +Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4036 in module $paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed. +Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4025 in module $paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed. +Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4014 in module $paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed. +Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4003 in module $paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed. +Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3992 in module $paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed. +Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3981 in module $paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed. +Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3970 in module $paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed. +Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3959 in module $paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed. +Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3948 in module $paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed. +Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3937 in module $paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed. +Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3926 in module $paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed. +Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3915 in module $paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed. +Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3904 in module $paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed. +Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3893 in module $paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed. +Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3882 in module $paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed. +Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3871 in module $paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed. +Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3860 in module $paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed. +Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3849 in module $paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed. +Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3838 in module $paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed. +Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3827 in module $paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed. +Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3816 in module $paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed. +Marked 5 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:194$3771 in module $paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide. +Removed a total of 1 dead cases. + +19.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 58 redundant assignments. +Promoted 512 assignments to connections. + +19.4.4. Executing PROC_INIT pass (extract init attributes). + +19.4.5. Executing PROC_ARST pass (detect async resets in processes). +Found async reset \async_rst_n in `\reset_sync.$proc$hardware/v2/rtl/reset_sync.v:27$2673'. + +19.4.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + + +19.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). +Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$3757'. +Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$3756'. +Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$3755'. +Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$3754'. +Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$3753'. +Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$3752'. +Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$3751'. +Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$3750'. +Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$3748'. +Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$3746'. +Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$3744'. +Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$3742'. +Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$3740'. +Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$3738'. +Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$3736'. +Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$3734'. +Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:196$3732'. +Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$3731'. + 1/2: $0\last_tree[2:2] + 2/2: $0\valid_tree[2:2] +Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:196$3729'. +Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:196$3727'. +Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$3726'. + 1/2: $0\last_tree[1:1] + 2/2: $0\valid_tree[1:1] +Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:192$3724'. +Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:192$3722'. +Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:192$3720'. +Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:192$3718'. +Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$3717'. + 1/2: $0\last_tree[0:0] + 2/2: $0\valid_tree[0:0] +Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:305$3712'. + 1/8: $0\node_id_reg[15:0] + 2/8: $0\activation_reg[1:0] + 3/8: $0\bias_reg[7:0] + 4/8: $0\np_error[0:0] + 5/8: $0\np_state[3:0] + 6/8: $0\result_node_id[15:0] + 7/8: $0\result_data[7:0] + 8/8: $0\result_valid[0:0] +Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:278$3702'. + 1/2: $0\valid7[0:0] + 2/2: $0\y7[7:0] +Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:245$3689'. + 1/3: $0\last6[0:0] + 2/3: $0\valid6[0:0] + 3/3: $0\final_acc_reg[31:0] +Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:215$3686'. + 1/3: $0\last5[0:0] + 2/3: $0\valid5[0:0] + 3/3: $0\acc_reg[31:0] +Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$3685'. + 1/11: $0\last1[0:0] + 2/11: $0\valid1[0:0] + 3/11: $4\gi[31:0] + 4/11: $0\prod1[7][31:0] + 5/11: $0\prod1[6][31:0] + 6/11: $0\prod1[5][31:0] + 7/11: $0\prod1[4][31:0] + 8/11: $0\prod1[3][31:0] + 9/11: $0\prod1[2][31:0] + 10/11: $0\prod1[1][31:0] + 11/11: $0\prod1[0][31:0] +Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$3680'. + 1/20: $2\gi[31:0] + 2/20: $0\last0[0:0] + 3/20: $0\valid0[0:0] + 4/20: $1\gi[31:0] + 5/20: $0\w0[7][7:0] + 6/20: $0\w0[6][7:0] + 7/20: $0\w0[5][7:0] + 8/20: $0\w0[4][7:0] + 9/20: $0\w0[3][7:0] + 10/20: $0\w0[2][7:0] + 11/20: $0\w0[1][7:0] + 12/20: $0\w0[0][7:0] + 13/20: $0\x0[7][7:0] + 14/20: $0\x0[6][7:0] + 15/20: $0\x0[5][7:0] + 16/20: $0\x0[4][7:0] + 17/20: $0\x0[3][7:0] + 18/20: $0\x0[2][7:0] + 19/20: $0\x0[1][7:0] + 20/20: $0\x0[0][7:0] +Creating decoders for process `$paramod$8ec81e5664842acf17791930d1f62ccccc9cf0b8\slot_mem_arbiter.$proc$hardware/v2/rtl/slot_mem_arbiter.v:115$7147'. + 1/56: $0\s_ready[4:0] [4] + 2/56: $0\s_ready[4:0] [3] + 3/56: $0\s_rdata[79:0] [63:48] + 4/56: $0\s_ready[4:0] [2] + 5/56: $0\s_rdata[79:0] [47:32] + 6/56: $0\s_ready[4:0] [1] + 7/56: $0\s_rdata[79:0] [31:16] + 8/56: $0\s_ready[4:0] [0] + 9/56: $0\s_rdata[79:0] [15:0] + 10/56: $8$lookahead\pending$7146[4:0]$7161 + 11/56: $3$bitselwrite$pos$hardware/v2/rtl/slot_mem_arbiter.v:164$7144[2:0]$7160 + 12/56: $7$lookahead\pending$7146[4:0]$7159 + 13/56: $2$bitselwrite$pos$hardware/v2/rtl/slot_mem_arbiter.v:164$7144[2:0]$7158 + 14/56: $2\pi[31:0] + 15/56: $6$lookahead\pending$7146[4:4]$7156 + 16/56: $0\pending_wdata[79:0] [79:64] + 17/56: $0\pending_wdata[79:0] [63:48] + 18/56: $0\pending_addr[114:0] [91:69] + 19/56: $0\pending_ub_n[4:0] [3] + 20/56: $0\pending_lb_n[4:0] [3] + 21/56: $0\pending_wr[4:0] [3] + 22/56: $0\pending_addr[114:0] [114:92] + 23/56: $0\pending_wdata[79:0] [47:32] + 24/56: $0\pending_addr[114:0] [68:46] + 25/56: $0\pending_ub_n[4:0] [2] + 26/56: $0\pending_lb_n[4:0] [2] + 27/56: $0\pending_wr[4:0] [2] + 28/56: $0\pending_ub_n[4:0] [4] + 29/56: $0\pending_wdata[79:0] [31:16] + 30/56: $0\pending_addr[114:0] [45:23] + 31/56: $0\pending_ub_n[4:0] [1] + 32/56: $0\pending_lb_n[4:0] [1] + 33/56: $0\pending_wr[4:0] [1] + 34/56: $0\pending_lb_n[4:0] [4] + 35/56: $0\pending_wdata[79:0] [15:0] + 36/56: $0\pending_addr[114:0] [22:0] + 37/56: $0\pending_ub_n[4:0] [0] + 38/56: $0\pending_lb_n[4:0] [0] + 39/56: $0\pending_wr[4:0] [0] + 40/56: $0\s_rdata[79:0] [79:64] + 41/56: $0\m_req[0:0] + 42/56: $1$lookahead\pending$7146[4:0]$7151 + 43/56: $1$bitselwrite$pos$hardware/v2/rtl/slot_mem_arbiter.v:164$7144[2:0]$7150 + 44/56: $1\pi[31:0] + 45/56: $4$lookahead\pending$7146[2:2]$7154 + 46/56: $3$lookahead\pending$7146[1:1]$7153 + 47/56: $2$lookahead\pending$7146[0:0]$7152 + 48/56: $0\pending_wr[4:0] [4] + 49/56: $5$lookahead\pending$7146[3:3]$7155 + 50/56: $0\owner[2:0] + 51/56: $0\m_ub_n[0:0] + 52/56: $0\m_lb_n[0:0] + 53/56: $0\m_wdata[15:0] + 54/56: $0\m_addr[22:0] + 55/56: $0\m_wr[0:0] + 56/56: $3\pi[31:0] +Creating decoders for process `$paramod$8ec81e5664842acf17791930d1f62ccccc9cf0b8\slot_mem_arbiter.$proc$hardware/v2/rtl/slot_mem_arbiter.v:102$7145'. + 1/10: $5\any_pending[0:0] + 2/10: $5\grant_idx[2:0] + 3/10: $4\any_pending[0:0] + 4/10: $4\grant_idx[2:0] + 5/10: $3\any_pending[0:0] + 6/10: $3\grant_idx[2:0] + 7/10: $2\any_pending[0:0] + 8/10: $2\grant_idx[2:0] + 9/10: $1\any_pending[0:0] + 10/10: $1\grant_idx[2:0] +Creating decoders for process `$paramod$13018cccabdf3dac026b50531aeca2ed1853451d\slot_mem_arbiter.$proc$hardware/v2/rtl/slot_mem_arbiter.v:115$7113'. + 1/32: $0\s_ready[1:0] [1] + 2/32: $0\s_ready[1:0] [0] + 3/32: $0\s_rdata[31:0] [15:0] + 4/32: $5$lookahead\pending$7112[1:0]$7124 + 5/32: $3$bitselwrite$pos$hardware/v2/rtl/slot_mem_arbiter.v:164$7110[1:0]$7123 + 6/32: $4$lookahead\pending$7112[1:0]$7122 + 7/32: $2$bitselwrite$pos$hardware/v2/rtl/slot_mem_arbiter.v:164$7110[1:0]$7121 + 8/32: $2\pi[31:0] + 9/32: $3$lookahead\pending$7112[1:1]$7119 + 10/32: $0\pending_wdata[31:0] [31:16] + 11/32: $0\pending_wdata[31:0] [15:0] + 12/32: $0\pending_addr[45:0] [22:0] + 13/32: $0\pending_ub_n[1:0] [0] + 14/32: $0\pending_lb_n[1:0] [0] + 15/32: $0\pending_wr[1:0] [0] + 16/32: $0\s_rdata[31:0] [31:16] + 17/32: $0\m_req[0:0] + 18/32: $1$lookahead\pending$7112[1:0]$7117 + 19/32: $1$bitselwrite$pos$hardware/v2/rtl/slot_mem_arbiter.v:164$7110[1:0]$7116 + 20/32: $1\pi[31:0] + 21/32: $0\pending_lb_n[1:0] [1] + 22/32: $0\pending_wr[1:0] [1] + 23/32: $2$lookahead\pending$7112[0:0]$7118 + 24/32: $0\pending_addr[45:0] [45:23] + 25/32: $0\pending_ub_n[1:0] [1] + 26/32: $0\owner[1:0] + 27/32: $0\m_ub_n[0:0] + 28/32: $0\m_lb_n[0:0] + 29/32: $0\m_wdata[15:0] + 30/32: $0\m_addr[22:0] + 31/32: $0\m_wr[0:0] + 32/32: $3\pi[31:0] +Creating decoders for process `$paramod$13018cccabdf3dac026b50531aeca2ed1853451d\slot_mem_arbiter.$proc$hardware/v2/rtl/slot_mem_arbiter.v:102$7111'. + 1/4: $2\any_pending[0:0] + 2/4: $2\grant_idx[1:0] + 3/4: $1\any_pending[0:0] + 4/4: $1\grant_idx[1:0] +Creating decoders for process `$paramod$8ef509dd8065f2599f8ea3948e2930abb5d7b7b0\slot_mem_arbiter_wide.$proc$hardware/v2/rtl/slot_mem_arbiter_wide.v:116$7075'. + 1/48: $0\s_ready[3:0] [3] + 2/48: $0\s_ready[3:0] [2] + 3/48: $0\s_rdata[255:0] [191:128] + 4/48: $0\s_ready[3:0] [1] + 5/48: $0\s_rdata[255:0] [127:64] + 6/48: $0\s_ready[3:0] [0] + 7/48: $0\s_rdata[255:0] [63:0] + 8/48: $7$lookahead\pending$7074[3:0]$7088 + 9/48: $3$bitselwrite$pos$hardware/v2/rtl/slot_mem_arbiter_wide.v:165$7072[2:0]$7087 + 10/48: $6$lookahead\pending$7074[3:0]$7086 + 11/48: $2$bitselwrite$pos$hardware/v2/rtl/slot_mem_arbiter_wide.v:165$7072[2:0]$7085 + 12/48: $2\pi[31:0] + 13/48: $5$lookahead\pending$7074[3:3]$7083 + 14/48: $0\pending_wdata[255:0] [255:192] + 15/48: $0\pending_wdata[255:0] [191:128] + 16/48: $0\pending_addr[91:0] [68:46] + 17/48: $0\pending_ub_n[3:0] [2] + 18/48: $0\pending_lb_n[3:0] [2] + 19/48: $0\pending_wr[3:0] [2] + 20/48: $0\pending_addr[91:0] [91:69] + 21/48: $0\pending_wdata[255:0] [127:64] + 22/48: $0\pending_addr[91:0] [45:23] + 23/48: $0\pending_ub_n[3:0] [1] + 24/48: $0\pending_lb_n[3:0] [1] + 25/48: $0\pending_wr[3:0] [1] + 26/48: $0\pending_ub_n[3:0] [3] + 27/48: $0\pending_wdata[255:0] [63:0] + 28/48: $0\pending_addr[91:0] [22:0] + 29/48: $0\pending_ub_n[3:0] [0] + 30/48: $0\pending_lb_n[3:0] [0] + 31/48: $0\pending_wr[3:0] [0] + 32/48: $0\s_rdata[255:0] [255:192] + 33/48: $0\m_req[0:0] + 34/48: $1$lookahead\pending$7074[3:0]$7079 + 35/48: $1$bitselwrite$pos$hardware/v2/rtl/slot_mem_arbiter_wide.v:165$7072[2:0]$7078 + 36/48: $1\pi[31:0] + 37/48: $4$lookahead\pending$7074[2:2]$7082 + 38/48: $3$lookahead\pending$7074[1:1]$7081 + 39/48: $2$lookahead\pending$7074[0:0]$7080 + 40/48: $0\pending_lb_n[3:0] [3] + 41/48: $0\pending_wr[3:0] [3] + 42/48: $0\owner[2:0] + 43/48: $0\m_ub_n[0:0] + 44/48: $0\m_lb_n[0:0] + 45/48: $0\m_wdata[63:0] + 46/48: $0\m_addr[22:0] + 47/48: $0\m_wr[0:0] + 48/48: $3\pi[31:0] +Creating decoders for process `$paramod$8ef509dd8065f2599f8ea3948e2930abb5d7b7b0\slot_mem_arbiter_wide.$proc$hardware/v2/rtl/slot_mem_arbiter_wide.v:103$7073'. + 1/8: $4\any_pending[0:0] + 2/8: $4\grant_idx[2:0] + 3/8: $3\any_pending[0:0] + 4/8: $3\grant_idx[2:0] + 5/8: $2\any_pending[0:0] + 6/8: $2\grant_idx[2:0] + 7/8: $1\any_pending[0:0] + 8/8: $1\grant_idx[2:0] +Creating decoders for process `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$proc$hardware/v2/nms/rtl/sdram_unified_backend.v:200$6968'. + 1/87: $4$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:292$6938_EN[22:0]$7057 + 2/87: $4$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:292$6938_DATA[22:0]$7056 + 3/87: $4$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:292$6938_ADDR[1:0]$7055 + 4/87: $4$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$7054 + 5/87: $4$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_DATA[63:0]$7053 + 6/87: $4$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_ADDR[1:0]$7052 + 7/87: $4$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:296$6940_EN[22:0]$7063 + 8/87: $4$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:296$6940_DATA[22:0]$7062 + 9/87: $4$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:296$6940_ADDR[1:0]$7061 + 10/87: $4$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$7060 + 11/87: $4$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_DATA[63:0]$7059 + 12/87: $4$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_ADDR[1:0]$7058 + 13/87: $3$memwr$\w_cache_valid$hardware/v2/nms/rtl/sdram_unified_backend.v:298$6941_EN[0:0]$7051 + 14/87: $3$memwr$\w_cache_valid$hardware/v2/nms/rtl/sdram_unified_backend.v:298$6941_ADDR[1:0]$7050 + 15/87: $3$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:296$6940_EN[22:0]$7049 + 16/87: $3$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:296$6940_DATA[22:0]$7048 + 17/87: $3$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:296$6940_ADDR[1:0]$7047 + 18/87: $3$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$7046 + 19/87: $3$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_DATA[63:0]$7045 + 20/87: $3$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_ADDR[1:0]$7044 + 21/87: $3$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:292$6938_EN[22:0]$7043 + 22/87: $3$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:292$6938_DATA[22:0]$7042 + 23/87: $3$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:292$6938_ADDR[1:0]$7041 + 24/87: $3$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$7040 + 25/87: $3$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_DATA[63:0]$7039 + 26/87: $3$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_ADDR[1:0]$7038 + 27/87: $3$memwr$\w_cache_valid$hardware/v2/nms/rtl/sdram_unified_backend.v:253$6936_EN[0:0]$7026 + 28/87: $3$memwr$\w_cache_valid$hardware/v2/nms/rtl/sdram_unified_backend.v:253$6936_ADDR[1:0]$7025 + 29/87: $2$memwr$\w_cache_valid$hardware/v2/nms/rtl/sdram_unified_backend.v:253$6936_EN[0:0]$7010 + 30/87: $2$memwr$\w_cache_valid$hardware/v2/nms/rtl/sdram_unified_backend.v:253$6936_ADDR[1:0]$7009 + 31/87: $2$memwr$\w_cache_valid$hardware/v2/nms/rtl/sdram_unified_backend.v:298$6941_EN[0:0]$7024 + 32/87: $2$memwr$\w_cache_valid$hardware/v2/nms/rtl/sdram_unified_backend.v:298$6941_ADDR[1:0]$7023 + 33/87: $2$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:296$6940_EN[22:0]$7022 + 34/87: $2$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:296$6940_DATA[22:0]$7021 + 35/87: $2$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:296$6940_ADDR[1:0]$7020 + 36/87: $2$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$7019 + 37/87: $2$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_DATA[63:0]$7018 + 38/87: $2$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_ADDR[1:0]$7017 + 39/87: $2$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:292$6938_EN[22:0]$7016 + 40/87: $2$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:292$6938_DATA[22:0]$7015 + 41/87: $2$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:292$6938_ADDR[1:0]$7014 + 42/87: $2$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$7013 + 43/87: $2$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_DATA[63:0]$7012 + 44/87: $2$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_ADDR[1:0]$7011 + 45/87: $0\ar_ready[0:0] + 46/87: $0\w_ready[0:0] + 47/87: $0\ctrl_req[0:0] + 48/87: $1\ri[31:0] + 49/87: $1$memwr$\w_cache_valid$hardware/v2/nms/rtl/sdram_unified_backend.v:203$6935_EN[0:0]$6992 + 50/87: $1$memwr$\w_cache_valid$hardware/v2/nms/rtl/sdram_unified_backend.v:203$6934_EN[0:0]$6991 + 51/87: $1$memwr$\w_cache_valid$hardware/v2/nms/rtl/sdram_unified_backend.v:203$6933_EN[0:0]$6990 + 52/87: $1$memwr$\w_cache_valid$hardware/v2/nms/rtl/sdram_unified_backend.v:203$6932_EN[0:0]$6989 + 53/87: $1$memwr$\w_cache_valid$hardware/v2/nms/rtl/sdram_unified_backend.v:298$6941_EN[0:0]$7008 + 54/87: $1$memwr$\w_cache_valid$hardware/v2/nms/rtl/sdram_unified_backend.v:298$6941_ADDR[1:0]$7007 + 55/87: $1$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:296$6940_EN[22:0]$7006 + 56/87: $1$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:296$6940_DATA[22:0]$7005 + 57/87: $1$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:296$6940_ADDR[1:0]$7004 + 58/87: $1$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$7003 + 59/87: $1$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_DATA[63:0]$7002 + 60/87: $1$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_ADDR[1:0]$7001 + 61/87: $1$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:292$6938_EN[22:0]$7000 + 62/87: $1$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:292$6938_DATA[22:0]$6999 + 63/87: $1$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:292$6938_ADDR[1:0]$6998 + 64/87: $1$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$6997 + 65/87: $1$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_DATA[63:0]$6996 + 66/87: $1$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_ADDR[1:0]$6995 + 67/87: $1$memwr$\w_cache_valid$hardware/v2/nms/rtl/sdram_unified_backend.v:253$6936_EN[0:0]$6994 + 68/87: $1$memwr$\w_cache_valid$hardware/v2/nms/rtl/sdram_unified_backend.v:253$6936_ADDR[1:0]$6993 + 69/87: $0\ar_req_ubn_lat[0:0] + 70/87: $0\ar_req_lbn_lat[0:0] + 71/87: $0\ar_req_wdata_lat[15:0] + 72/87: $0\ar_req_addr_lat[22:0] + 73/87: $0\ar_req_wr_lat[0:0] + 74/87: $0\ar_req_pending[0:0] + 75/87: $0\w_req_addr_lat[22:0] + 76/87: $0\w_req_pending[0:0] + 77/87: $0\ar_pending_word[2:0] + 78/87: $0\w_pending_addr[22:0] + 79/87: $0\w_pending_upper_half[0:0] + 80/87: $0\ctrl_wmask[15:0] + 81/87: $0\ctrl_wdata[127:0] + 82/87: $0\ctrl_addr[21:0] + 83/87: $0\ctrl_wr[0:0] + 84/87: $0\w_alloc_ptr[1:0] + 85/87: $0\ar_rdata[15:0] + 86/87: $0\w_rdata[63:0] + 87/87: $0\state[2:0] +Creating decoders for process `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$proc$hardware/v2/nms/rtl/sdram_unified_backend.v:115$6942'. + 1/8: $4\w_hit_idx_c[1:0] + 2/8: $4\w_hit_found_c[0:0] + 3/8: $3\w_hit_idx_c[1:0] + 4/8: $3\w_hit_found_c[0:0] + 5/8: $2\w_hit_idx_c[1:0] + 6/8: $2\w_hit_found_c[0:0] + 7/8: $1\w_hit_idx_c[1:0] + 8/8: $1\w_hit_found_c[0:0] +Creating decoders for process `$paramod$d1bf252c98cb2b8284c90cfb859e00756f939daa\sdram_controller.$proc$hardware/v2/nms/rtl/sdram_controller.v:196$7417'. + 1/32: $2$lookahead\rdata$7416[127:0]$7425 [127:16] + 2/32: $2$lookahead\rdata$7416[127:0]$7425 [15:0] + 3/32: $3$lookahead\rdata$7416[15:0]$7444 + 4/32: $0\sdram_a[11:0] [9:0] + 5/32: $0\sdram_a[11:0] [10] + 6/32: $2$bitselwrite$pos$hardware/v2/nms/rtl/sdram_controller.v:410$7408[31:0]$7424 + 7/32: $0\ready[0:0] + 8/32: $0\dq_out_en[0:0] + 9/32: $0\sdram_dqm[1:0] + 10/32: $0\sdram_we_n[0:0] + 11/32: $0\sdram_cas_n[0:0] + 12/32: $0\sdram_ras_n[0:0] + 13/32: $0\sdram_cs_n[0:0] + 14/32: $1$lookahead\rdata$7416[127:0]$7421 + 15/32: $1$bitselwrite$pos$hardware/v2/nms/rtl/sdram_controller.v:410$7408[31:0]$7420 + 16/32: $0\dq_out[15:0] + 17/32: $0\req_pending[0:0] + 18/32: $0\wmask_reg[15:0] + 19/32: $0\wdata_reg[127:0] + 20/32: $0\req_col_reg[7:0] + 21/32: $0\req_row_reg[11:0] + 22/32: $0\req_bank_reg[1:0] + 23/32: $0\req_wr_reg[0:0] + 24/32: $0\burst_idx[2:0] + 25/32: $0\refresh_timer[13:0] + 26/32: $0\init_ref_cnt[3:0] + 27/32: $0\wait_cnt[13:0] + 28/32: $0\busy[0:0] + 29/32: $0\sdram_a[11:0] [11] + 30/32: $0\sdram_ba[1:0] + 31/32: $0\sdram_cke[0:0] + 32/32: $0\state[4:0] +Creating decoders for process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:82$6839'. + 1/16: $3$lookahead\tile_w$6838[63:0]$6847 + 2/16: $3$bitselwrite$pos$hardware/v2/rtl/prefetch_engine.v:115$6837[31:0]$6846 + 3/16: $2$lookahead\tile_w$6838[63:0]$6845 + 4/16: $2$bitselwrite$pos$hardware/v2/rtl/prefetch_engine.v:115$6837[31:0]$6844 + 5/16: $0\mem_req[0:0] + 6/16: $0\fetch_done[0:0] + 7/16: $1$lookahead\tile_w$6838[63:0]$6843 + 8/16: $1$bitselwrite$pos$hardware/v2/rtl/prefetch_engine.v:115$6837[31:0]$6842 + 9/16: $0\word_idx[2:0] + 10/16: $0\state[1:0] + 11/16: $0\mem_ub_n[0:0] + 12/16: $0\mem_lb_n[0:0] + 13/16: $0\mem_wdata[15:0] + 14/16: $0\mem_addr[22:0] + 15/16: $0\mem_wr[0:0] + 16/16: $0\fetch_busy[0:0] +Creating decoders for process `$paramod$a83886fe79b03d603caba252b5389bc5341a5c19\weight_prefetch_engine_wide.$proc$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:108$6796'. + 1/15: $3$lookahead\tile_buf$6795[63:0]$6806 + 2/15: $3$bitselwrite$pos$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:127$6789[31:0]$6805 + 3/15: $2$lookahead\tile_buf$6795[63:0]$6803 + 4/15: $2$bitselwrite$pos$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:127$6789[31:0]$6802 + 5/15: $0\wgt_fill_we[0:0] + 6/15: $0\mem_req[0:0] + 7/15: $1$lookahead\tile_buf$6795[63:0]$6800 + 8/15: $1$bitselwrite$pos$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:127$6789[31:0]$6799 + 9/15: $0\req_outstanding[0:0] + 10/15: $0\fetch_word[0:0] + 11/15: $0\fetch_tile[4:0] + 12/15: $0\ready_count[4:0] + 13/15: $0\wgt_fill_data[63:0] + 14/15: $0\wgt_fill_addr[3:0] + 15/15: $0\mem_addr[22:0] +Creating decoders for process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + 1/975: $2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:164$4641_EN[1:0]$6647 + 2/975: $2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:164$4641_ADDR[3:0]$6646 + 3/975: $5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4639_EN[1:0]$6642 + 4/975: $4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4640_EN[2:0]$6637 + 5/975: $4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4640_DATA[2:0]$6636 + 6/975: $4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4639_EN[1:0]$6635 + 7/975: $5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4637_EN[1:0]$6627 + 8/975: $4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4638_EN[2:0]$6622 + 9/975: $4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4638_DATA[2:0]$6621 + 10/975: $4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4637_EN[1:0]$6620 + 11/975: $5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4635_EN[1:0]$6612 + 12/975: $4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4636_EN[2:0]$6607 + 13/975: $4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4636_DATA[2:0]$6606 + 14/975: $4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4635_EN[1:0]$6605 + 15/975: $5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4633_EN[1:0]$6597 + 16/975: $4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4634_EN[2:0]$6592 + 17/975: $4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4634_DATA[2:0]$6591 + 18/975: $4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4633_EN[1:0]$6590 + 19/975: $19\di[31:0] + 20/975: $3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4640_EN[2:0]$6584 + 21/975: $3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4640_DATA[2:0]$6583 + 22/975: $3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4639_EN[1:0]$6582 + 23/975: $3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4638_EN[2:0]$6581 + 24/975: $3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4638_DATA[2:0]$6580 + 25/975: $3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4637_EN[1:0]$6579 + 26/975: $3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4636_EN[2:0]$6578 + 27/975: $3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4636_DATA[2:0]$6577 + 28/975: $3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4635_EN[1:0]$6576 + 29/975: $3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4634_EN[2:0]$6575 + 30/975: $3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4634_DATA[2:0]$6574 + 31/975: $3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4633_EN[1:0]$6573 + 32/975: $5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4631_EN[1:0]$6568 + 33/975: $4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4632_EN[2:0]$6563 + 34/975: $4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4632_DATA[2:0]$6562 + 35/975: $4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4631_EN[1:0]$6561 + 36/975: $5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4629_EN[1:0]$6553 + 37/975: $4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4630_EN[2:0]$6548 + 38/975: $4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4630_DATA[2:0]$6547 + 39/975: $4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4629_EN[1:0]$6546 + 40/975: $5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4627_EN[1:0]$6538 + 41/975: $4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4628_EN[2:0]$6533 + 42/975: $4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4628_DATA[2:0]$6532 + 43/975: $4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4627_EN[1:0]$6531 + 44/975: $5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4625_EN[1:0]$6523 + 45/975: $4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4626_EN[2:0]$6518 + 46/975: $4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4626_DATA[2:0]$6517 + 47/975: $4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4625_EN[1:0]$6516 + 48/975: $18\di[31:0] + 49/975: $3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4632_EN[2:0]$6510 + 50/975: $3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4632_DATA[2:0]$6509 + 51/975: $3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4631_EN[1:0]$6508 + 52/975: $3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4630_EN[2:0]$6507 + 53/975: $3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4630_DATA[2:0]$6506 + 54/975: $3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4629_EN[1:0]$6505 + 55/975: $3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4628_EN[2:0]$6504 + 56/975: $3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4628_DATA[2:0]$6503 + 57/975: $3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4627_EN[1:0]$6502 + 58/975: $3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4626_EN[2:0]$6501 + 59/975: $3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4626_DATA[2:0]$6500 + 60/975: $3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4625_EN[1:0]$6499 + 61/975: $5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4623_EN[1:0]$6494 + 62/975: $4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4624_EN[2:0]$6489 + 63/975: $4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4624_DATA[2:0]$6488 + 64/975: $4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4623_EN[1:0]$6487 + 65/975: $5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4621_EN[1:0]$6479 + 66/975: $4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4622_EN[2:0]$6474 + 67/975: $4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4622_DATA[2:0]$6473 + 68/975: $4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4621_EN[1:0]$6472 + 69/975: $5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4619_EN[1:0]$6464 + 70/975: $4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4620_EN[2:0]$6459 + 71/975: $4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4620_DATA[2:0]$6458 + 72/975: $4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4619_EN[1:0]$6457 + 73/975: $5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4617_EN[1:0]$6449 + 74/975: $4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4618_EN[2:0]$6444 + 75/975: $4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4618_DATA[2:0]$6443 + 76/975: $4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4617_EN[1:0]$6442 + 77/975: $17\di[31:0] + 78/975: $3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4624_EN[2:0]$6436 + 79/975: $3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4624_DATA[2:0]$6435 + 80/975: $3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4623_EN[1:0]$6434 + 81/975: $3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4622_EN[2:0]$6433 + 82/975: $3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4622_DATA[2:0]$6432 + 83/975: $3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4621_EN[1:0]$6431 + 84/975: $3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4620_EN[2:0]$6430 + 85/975: $3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4620_DATA[2:0]$6429 + 86/975: $3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4619_EN[1:0]$6428 + 87/975: $3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4618_EN[2:0]$6427 + 88/975: $3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4618_DATA[2:0]$6426 + 89/975: $3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4617_EN[1:0]$6425 + 90/975: $5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4615_EN[1:0]$6420 + 91/975: $4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4616_EN[2:0]$6415 + 92/975: $4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4616_DATA[2:0]$6414 + 93/975: $4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4615_EN[1:0]$6413 + 94/975: $5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4613_EN[1:0]$6405 + 95/975: $4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4614_EN[2:0]$6400 + 96/975: $4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4614_DATA[2:0]$6399 + 97/975: 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$1$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4514_EN[2:0]$5034 + 935/975: $1$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4514_DATA[2:0]$5033 + 936/975: $1$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4513_EN[1:0]$5032 + 937/975: $1$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:137$4512_EN[1:0]$5031 + 938/975: $1$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:137$4512_DATA[1:0]$5030 + 939/975: $1$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:137$4512_ADDR[3:0]$5029 + 940/975: $1$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$4511_EN[3:0]$5028 + 941/975: $1$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$4511_DATA[3:0]$5027 + 942/975: $1$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$4511_ADDR[31:0]$5026 + 943/975: $1$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$4510_EN[3:0]$5025 + 944/975: $1$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$4510_DATA[3:0]$5024 + 945/975: $1$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$4510_ADDR[31:0]$5023 + 946/975: $1$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$4509_EN[3:0]$5022 + 947/975: $1$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$4509_DATA[3:0]$5021 + 948/975: $1$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$4509_ADDR[31:0]$5020 + 949/975: $1$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$4508_EN[3:0]$5019 + 950/975: $1$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$4508_DATA[3:0]$5018 + 951/975: $1$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$4508_ADDR[31:0]$5017 + 952/975: $1$memwr$\node_result_addr$hardware/v2/rtl/dependency_manager.v:134$4507_EN[22:0]$5016 + 953/975: $1$memwr$\node_result_addr$hardware/v2/rtl/dependency_manager.v:134$4507_DATA[22:0]$5015 + 954/975: $1$memwr$\node_result_addr$hardware/v2/rtl/dependency_manager.v:134$4507_ADDR[3:0]$5014 + 955/975: $1$memwr$\node_n_tiles$hardware/v2/rtl/dependency_manager.v:133$4506_EN[15:0]$5013 + 956/975: $1$memwr$\node_n_tiles$hardware/v2/rtl/dependency_manager.v:133$4506_DATA[15:0]$5012 + 957/975: $1$memwr$\node_n_tiles$hardware/v2/rtl/dependency_manager.v:133$4506_ADDR[3:0]$5011 + 958/975: $1$memwr$\node_w_base$hardware/v2/rtl/dependency_manager.v:132$4505_EN[22:0]$5010 + 959/975: $1$memwr$\node_w_base$hardware/v2/rtl/dependency_manager.v:132$4505_DATA[22:0]$5009 + 960/975: $1$memwr$\node_w_base$hardware/v2/rtl/dependency_manager.v:132$4505_ADDR[3:0]$5008 + 961/975: $1$memwr$\node_x_base$hardware/v2/rtl/dependency_manager.v:131$4504_EN[22:0]$5007 + 962/975: $1$memwr$\node_x_base$hardware/v2/rtl/dependency_manager.v:131$4504_DATA[22:0]$5006 + 963/975: $1$memwr$\node_x_base$hardware/v2/rtl/dependency_manager.v:131$4504_ADDR[3:0]$5005 + 964/975: $1$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:130$4503_EN[2:0]$5004 + 965/975: $1$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:130$4503_ADDR[3:0]$5003 + 966/975: $1$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:129$4502_EN[2:0]$5002 + 967/975: $1$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:129$4502_DATA[2:0]$5001 + 968/975: $1$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:129$4502_ADDR[3:0]$5000 + 969/975: $1\di[31:0] + 970/975: $0\ready_result_addr[22:0] + 971/975: $0\ready_n_tiles[15:0] + 972/975: $0\ready_w_base[22:0] + 973/975: $0\ready_x_base[22:0] + 974/975: $0\ready_node_id[3:0] + 975/975: $0\ready_valid[0:0] +Creating decoders for process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:103$4644'. + 1/32: $16\any_ready[0:0] + 2/32: $16\first_ready_idx[3:0] + 3/32: $15\any_ready[0:0] + 4/32: $15\first_ready_idx[3:0] + 5/32: $14\any_ready[0:0] + 6/32: $14\first_ready_idx[3:0] + 7/32: $13\any_ready[0:0] + 8/32: $13\first_ready_idx[3:0] + 9/32: $12\any_ready[0:0] + 10/32: $12\first_ready_idx[3:0] + 11/32: $11\any_ready[0:0] + 12/32: $11\first_ready_idx[3:0] + 13/32: $10\any_ready[0:0] + 14/32: $10\first_ready_idx[3:0] + 15/32: $9\any_ready[0:0] + 16/32: $9\first_ready_idx[3:0] + 17/32: $8\any_ready[0:0] + 18/32: $8\first_ready_idx[3:0] + 19/32: $7\any_ready[0:0] + 20/32: $7\first_ready_idx[3:0] + 21/32: $6\any_ready[0:0] + 22/32: $6\first_ready_idx[3:0] + 23/32: $5\any_ready[0:0] + 24/32: $5\first_ready_idx[3:0] + 25/32: $4\any_ready[0:0] + 26/32: $4\first_ready_idx[3:0] + 27/32: $3\any_ready[0:0] + 28/32: $3\first_ready_idx[3:0] + 29/32: $2\any_ready[0:0] + 30/32: $2\first_ready_idx[3:0] + 31/32: $1\any_ready[0:0] + 32/32: $1\first_ready_idx[3:0] +Creating decoders for process `\reset_sync.$proc$hardware/v2/rtl/reset_sync.v:27$2673'. + 1/1: $0\sync_ff[1:0] +Creating decoders for process `$paramod$5eff1de9335b9030234048498b6a1d64bf783cb3\nms_dataflow_core_sdram.$proc$hardware/v2/nms/rtl/nms_dataflow_core_sdram.v:281$7317'. + 1/1: $0\GEN_SLOT[3].job_valid_np[0:0] +Creating decoders for process `$paramod$5eff1de9335b9030234048498b6a1d64bf783cb3\nms_dataflow_core_sdram.$proc$hardware/v2/nms/rtl/nms_dataflow_core_sdram.v:281$7314'. + 1/1: $0\GEN_SLOT[2].job_valid_np[0:0] +Creating decoders for process `$paramod$5eff1de9335b9030234048498b6a1d64bf783cb3\nms_dataflow_core_sdram.$proc$hardware/v2/nms/rtl/nms_dataflow_core_sdram.v:281$7311'. + 1/1: $0\GEN_SLOT[1].job_valid_np[0:0] +Creating decoders for process `$paramod$5eff1de9335b9030234048498b6a1d64bf783cb3\nms_dataflow_core_sdram.$proc$hardware/v2/nms/rtl/nms_dataflow_core_sdram.v:281$7308'. + 1/1: $0\GEN_SLOT[0].job_valid_np[0:0] +Creating decoders for process `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.$proc$hardware/v2/rtl/spi_host_bridge.v:259$7345'. + 1/36: $0\mem_addr[22:0] [22:16] + 2/36: $0\mem_addr[22:0] [15:8] + 3/36: $0\len_words[15:0] [7:0] + 4/36: $0\cur_word[15:0] [7:0] + 5/36: $0\mem_addr[22:0] [7:0] + 6/36: $0\reg_result_addr[22:0] [7:0] + 7/36: $0\reg_result_addr[22:0] [22:16] + 8/36: $0\reg_n_tiles[15:0] [7:0] + 9/36: $0\reg_w_base[22:0] [7:0] + 10/36: $0\reg_w_base[22:0] [22:16] + 11/36: $0\reg_x_base[22:0] [7:0] + 12/36: $0\reg_x_base[22:0] [22:16] + 13/36: $0\reg_producer_ids[15:0] [7:0] + 14/36: $0\soft_rst_pulse[0:0] + 15/36: $0\mem_req[0:0] + 16/36: $0\last_job_accepted_r[0:0] + 17/36: $0\mem_busy_r[0:0] + 18/36: $0\len_words[15:0] [15:8] + 19/36: $0\word_cnt[15:0] + 20/36: $0\cur_word[15:0] [15:8] + 21/36: $0\byte_idx[3:0] + 22/36: $0\opcode[7:0] + 23/36: $0\state[3:0] + 24/36: $0\mem_ub_n[0:0] + 25/36: $0\mem_lb_n[0:0] + 26/36: $0\mem_wdata[15:0] + 27/36: $0\reg_result_addr[22:0] [15:8] + 28/36: $0\mem_wr[0:0] + 29/36: $0\reg_n_tiles[15:0] [15:8] + 30/36: $0\reg_w_base[22:0] [15:8] + 31/36: $0\reg_x_base[22:0] [15:8] + 32/36: $0\reg_producer_ids[15:0] [15:8] + 33/36: $0\job_busy_r[0:0] + 34/36: $0\reg_required[2:0] + 35/36: $0\reg_node_id[3:0] + 36/36: $0\reg_valid[0:0] +Creating decoders for process `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.$proc$hardware/v2/rtl/spi_host_bridge.v:250$7338'. + 1/2: $2\tx_mux[7:0] + 2/2: $1\tx_mux[7:0] +Creating decoders for process `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.$proc$hardware/v2/rtl/spi_host_bridge.v:192$7331'. + 1/5: $0\rx_valid[0:0] + 2/5: $0\miso_shift_bit[0:0] + 3/5: $0\rx_byte[7:0] + 4/5: $0\rx_shift[7:0] + 5/5: $0\bit_count[2:0] +Creating decoders for process `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.$proc$hardware/v2/rtl/spi_host_bridge.v:132$7320'. + 1/2: $0\cs_n_prev[0:0] + 2/2: $0\sclk_prev[0:0] +Creating decoders for process `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.$proc$hardware/v2/rtl/spi_host_bridge.v:118$7319'. + 1/3: $0\cs_n_sync[2:0] + 2/3: $0\mosi_sync[2:0] + 3/3: $0\sclk_sync[2:0] +Creating decoders for process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:138$4283'. + 1/65: $2$lookahead\slot_busy$4282[3:0]$4377 + 2/65: $2$lookahead\slot_node_id$4281[63:0]$4376 + 3/65: $2$lookahead\slot_result_addr$4280[91:0]$4375 + 4/65: $2$lookahead\slot_n_tiles$4279[63:0]$4374 + 5/65: $2$lookahead\slot_w_base$4278[91:0]$4373 + 6/65: $2$lookahead\slot_x_base$4277[91:0]$4372 + 7/65: $2$lookahead\slot_job_start$4276[3:0]$4371 + 8/65: $2$bitselwrite$pos$hardware/v2/rtl/neural_director.v:212$4263[1:0]$4370 + 9/65: $2$bitselwrite$pos$hardware/v2/rtl/neural_director.v:211$4262[31:0]$4369 + 10/65: $2$bitselwrite$pos$hardware/v2/rtl/neural_director.v:210$4261[31:0]$4368 + 11/65: $2$bitselwrite$pos$hardware/v2/rtl/neural_director.v:209$4260[31:0]$4367 + 12/65: $2$bitselwrite$pos$hardware/v2/rtl/neural_director.v:208$4259[31:0]$4366 + 13/65: $2$bitselwrite$pos$hardware/v2/rtl/neural_director.v:207$4258[31:0]$4365 + 14/65: $2$bitselwrite$pos$hardware/v2/rtl/neural_director.v:206$4257[1:0]$4364 + 15/65: $2$memwr$\q_node_id$hardware/v2/rtl/neural_director.v:167$4268_EN[15:0]$4357 + 16/65: $2$memwr$\q_node_id$hardware/v2/rtl/neural_director.v:167$4268_DATA[15:0]$4356 + 17/65: $2$memwr$\q_node_id$hardware/v2/rtl/neural_director.v:167$4268_ADDR[2:0]$4355 + 18/65: $2$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:166$4267_EN[22:0]$4354 + 19/65: $2$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:166$4267_DATA[22:0]$4353 + 20/65: $2$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:166$4267_ADDR[2:0]$4352 + 21/65: $2$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:165$4266_EN[15:0]$4351 + 22/65: $2$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:165$4266_DATA[15:0]$4350 + 23/65: $2$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:165$4266_ADDR[2:0]$4349 + 24/65: $2$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:164$4265_EN[22:0]$4348 + 25/65: $2$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:164$4265_DATA[22:0]$4347 + 26/65: $2$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:164$4265_ADDR[2:0]$4346 + 27/65: $2$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:163$4264_EN[22:0]$4345 + 28/65: $2$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:163$4264_DATA[22:0]$4344 + 29/65: $2$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:163$4264_ADDR[2:0]$4343 + 30/65: $0\job_out_done[0:0] + 31/65: $1$lookahead\slot_node_id$4281[63:0]$4340 + 32/65: $1$lookahead\slot_result_addr$4280[91:0]$4339 + 33/65: $1$lookahead\slot_n_tiles$4279[63:0]$4338 + 34/65: $1$lookahead\slot_w_base$4278[91:0]$4337 + 35/65: $1$lookahead\slot_x_base$4277[91:0]$4336 + 36/65: $1$lookahead\slot_job_start$4276[3:0]$4335 + 37/65: $1$lookahead\slot_busy$4282[3:0]$4341 + 38/65: $0\q_count[3:0] + 39/65: $1$memwr$\q_node_id$hardware/v2/rtl/neural_director.v:167$4268_EN[15:0]$4334 + 40/65: $1$memwr$\q_node_id$hardware/v2/rtl/neural_director.v:167$4268_DATA[15:0]$4333 + 41/65: $1$memwr$\q_node_id$hardware/v2/rtl/neural_director.v:167$4268_ADDR[2:0]$4332 + 42/65: $1$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:166$4267_EN[22:0]$4331 + 43/65: $1$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:166$4267_DATA[22:0]$4330 + 44/65: $1$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:166$4267_ADDR[2:0]$4329 + 45/65: $1$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:165$4266_EN[15:0]$4328 + 46/65: $1$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:165$4266_DATA[15:0]$4327 + 47/65: $1$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:165$4266_ADDR[2:0]$4326 + 48/65: $1$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:164$4265_EN[22:0]$4325 + 49/65: $1$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:164$4265_DATA[22:0]$4324 + 50/65: $1$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:164$4265_ADDR[2:0]$4323 + 51/65: $1$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:163$4264_EN[22:0]$4322 + 52/65: $1$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:163$4264_DATA[22:0]$4321 + 53/65: $1$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:163$4264_ADDR[2:0]$4320 + 54/65: $1$bitselwrite$pos$hardware/v2/rtl/neural_director.v:212$4263[1:0]$4319 + 55/65: $1$bitselwrite$pos$hardware/v2/rtl/neural_director.v:211$4262[31:0]$4318 + 56/65: $1$bitselwrite$pos$hardware/v2/rtl/neural_director.v:210$4261[31:0]$4317 + 57/65: $1$bitselwrite$pos$hardware/v2/rtl/neural_director.v:209$4260[31:0]$4316 + 58/65: $1$bitselwrite$pos$hardware/v2/rtl/neural_director.v:208$4259[31:0]$4315 + 59/65: $1$bitselwrite$pos$hardware/v2/rtl/neural_director.v:207$4258[31:0]$4314 + 60/65: $1$bitselwrite$pos$hardware/v2/rtl/neural_director.v:206$4257[1:0]$4313 + 61/65: $0\q_tail[2:0] + 62/65: $0\q_head[2:0] + 63/65: $0\dir_error[0:0] + 64/65: $0\dir_state[3:0] + 65/65: $0\job_out_slot[1:0] +Creating decoders for process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:131$4275'. + 1/4: $4\done_slot_idx[1:0] + 2/4: $3\done_slot_idx[1:0] + 3/4: $2\done_slot_idx[1:0] + 4/4: $1\done_slot_idx[1:0] +Creating decoders for process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:117$4274'. + 1/4: $4\free_slot_idx[1:0] + 2/4: $3\free_slot_idx[1:0] + 3/4: $2\free_slot_idx[1:0] + 4/4: $1\free_slot_idx[1:0] +Creating decoders for process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$proc$hardware/v2/nms/rtl/nms_activation_replicated.v:42$4246'. + 1/3: $1$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_EN[63:0]$4252 + 2/3: $1$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_DATA[63:0]$4251 + 3/3: $1$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_ADDR[3:0]$4250 +Creating decoders for process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$proc$hardware/v2/nms/rtl/nms_activation_replicated.v:42$4235'. + 1/3: $1$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_EN[63:0]$4241 + 2/3: $1$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_DATA[63:0]$4240 + 3/3: $1$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_ADDR[3:0]$4239 +Creating decoders for process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$proc$hardware/v2/nms/rtl/nms_activation_replicated.v:42$4224'. + 1/3: $1$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_EN[63:0]$4230 + 2/3: $1$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_DATA[63:0]$4229 + 3/3: $1$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_ADDR[3:0]$4228 +Creating decoders for process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$proc$hardware/v2/nms/rtl/nms_activation_replicated.v:42$4213'. + 1/3: $1$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_EN[63:0]$4219 + 2/3: $1$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_DATA[63:0]$4218 + 3/3: $1$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_ADDR[3:0]$4217 +Creating decoders for process `$paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3.$proc$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:116$4207'. + 1/1: $0\n_tiles_masked[3][15:0] +Creating decoders for process `$paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3.$proc$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:116$4203'. + 1/1: $0\n_tiles_masked[2][15:0] +Creating decoders for process `$paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3.$proc$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:116$4199'. + 1/1: $0\n_tiles_masked[1][15:0] +Creating decoders for process `$paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3.$proc$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:116$4195'. + 1/1: $0\n_tiles_masked[0][15:0] +Creating decoders for process `$paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3.$proc$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:164$4175'. + 1/8: $0\fill_we_reg[0:0] + 2/8: $0\pf_start[0:0] + 3/8: $0\fill_data_reg[63:0] + 4/8: $0\fill_addr_reg[3:0] + 5/8: $0\pf_addr[22:0] + 6/8: $0\resident_count[4:0] + 7/8: $0\resident_tag[22:0] + 8/8: $0\state[0:0] +Creating decoders for process `$paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3.$proc$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:132$4174'. + 1/1: $0\max_n_tiles_reg[15:0] +Creating decoders for process `$paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3.$proc$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:126$4169'. + 1/4: $4\max_n_tiles_comb[15:0] + 2/4: $3\max_n_tiles_comb[15:0] + 3/4: $2\max_n_tiles_comb[15:0] + 4/4: $1\max_n_tiles_comb[15:0] +Creating decoders for process `$paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3.$proc$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:76$4168'. + 1/8: $4\desired_x_base[22:0] + 2/8: $4\desired_valid[0:0] + 3/8: $3\desired_x_base[22:0] + 4/8: $3\desired_valid[0:0] + 5/8: $2\desired_x_base[22:0] + 6/8: $2\desired_valid[0:0] + 7/8: $1\desired_x_base[22:0] + 8/8: $1\desired_valid[0:0] +Creating decoders for process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4157'. + 1/3: $1$memwr$\GEN_SLOT[3].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3815_EN[7:0]$4163 + 2/3: $1$memwr$\GEN_SLOT[3].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3815_DATA[7:0]$4162 + 3/3: $1$memwr$\GEN_SLOT[3].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3815_ADDR[3:0]$4161 +Creating decoders for process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4146'. + 1/3: $1$memwr$\GEN_SLOT[3].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3814_EN[7:0]$4152 + 2/3: $1$memwr$\GEN_SLOT[3].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3814_DATA[7:0]$4151 + 3/3: $1$memwr$\GEN_SLOT[3].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3814_ADDR[3:0]$4150 +Creating decoders for process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4135'. + 1/3: $1$memwr$\GEN_SLOT[3].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3813_EN[7:0]$4141 + 2/3: $1$memwr$\GEN_SLOT[3].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3813_DATA[7:0]$4140 + 3/3: $1$memwr$\GEN_SLOT[3].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3813_ADDR[3:0]$4139 +Creating decoders for process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4124'. + 1/3: $1$memwr$\GEN_SLOT[3].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3812_EN[7:0]$4130 + 2/3: $1$memwr$\GEN_SLOT[3].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3812_DATA[7:0]$4129 + 3/3: $1$memwr$\GEN_SLOT[3].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3812_ADDR[3:0]$4128 +Creating decoders for process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4113'. + 1/3: $1$memwr$\GEN_SLOT[3].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3811_EN[7:0]$4119 + 2/3: $1$memwr$\GEN_SLOT[3].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3811_DATA[7:0]$4118 + 3/3: $1$memwr$\GEN_SLOT[3].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3811_ADDR[3:0]$4117 +Creating decoders for process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4102'. + 1/3: $1$memwr$\GEN_SLOT[3].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3810_EN[7:0]$4108 + 2/3: $1$memwr$\GEN_SLOT[3].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3810_DATA[7:0]$4107 + 3/3: $1$memwr$\GEN_SLOT[3].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3810_ADDR[3:0]$4106 +Creating decoders for process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4091'. + 1/3: $1$memwr$\GEN_SLOT[3].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3809_EN[7:0]$4097 + 2/3: $1$memwr$\GEN_SLOT[3].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3809_DATA[7:0]$4096 + 3/3: $1$memwr$\GEN_SLOT[3].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3809_ADDR[3:0]$4095 +Creating decoders for process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4080'. + 1/3: $1$memwr$\GEN_SLOT[3].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3808_EN[7:0]$4086 + 2/3: $1$memwr$\GEN_SLOT[3].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3808_DATA[7:0]$4085 + 3/3: $1$memwr$\GEN_SLOT[3].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3808_ADDR[3:0]$4084 +Creating decoders for process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4069'. + 1/3: $1$memwr$\GEN_SLOT[2].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3807_EN[7:0]$4075 + 2/3: $1$memwr$\GEN_SLOT[2].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3807_DATA[7:0]$4074 + 3/3: $1$memwr$\GEN_SLOT[2].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3807_ADDR[3:0]$4073 +Creating decoders for process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4058'. + 1/3: $1$memwr$\GEN_SLOT[2].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3806_EN[7:0]$4064 + 2/3: $1$memwr$\GEN_SLOT[2].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3806_DATA[7:0]$4063 + 3/3: $1$memwr$\GEN_SLOT[2].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3806_ADDR[3:0]$4062 +Creating decoders for process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4047'. + 1/3: $1$memwr$\GEN_SLOT[2].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3805_EN[7:0]$4053 + 2/3: $1$memwr$\GEN_SLOT[2].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3805_DATA[7:0]$4052 + 3/3: $1$memwr$\GEN_SLOT[2].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3805_ADDR[3:0]$4051 +Creating decoders for process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4036'. + 1/3: $1$memwr$\GEN_SLOT[2].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3804_EN[7:0]$4042 + 2/3: $1$memwr$\GEN_SLOT[2].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3804_DATA[7:0]$4041 + 3/3: $1$memwr$\GEN_SLOT[2].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3804_ADDR[3:0]$4040 +Creating decoders for process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4025'. + 1/3: $1$memwr$\GEN_SLOT[2].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3803_EN[7:0]$4031 + 2/3: $1$memwr$\GEN_SLOT[2].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3803_DATA[7:0]$4030 + 3/3: $1$memwr$\GEN_SLOT[2].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3803_ADDR[3:0]$4029 +Creating decoders for process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4014'. + 1/3: $1$memwr$\GEN_SLOT[2].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3802_EN[7:0]$4020 + 2/3: $1$memwr$\GEN_SLOT[2].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3802_DATA[7:0]$4019 + 3/3: $1$memwr$\GEN_SLOT[2].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3802_ADDR[3:0]$4018 +Creating decoders for process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4003'. + 1/3: $1$memwr$\GEN_SLOT[2].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3801_EN[7:0]$4009 + 2/3: $1$memwr$\GEN_SLOT[2].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3801_DATA[7:0]$4008 + 3/3: $1$memwr$\GEN_SLOT[2].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3801_ADDR[3:0]$4007 +Creating decoders for process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3992'. + 1/3: $1$memwr$\GEN_SLOT[2].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3800_EN[7:0]$3998 + 2/3: $1$memwr$\GEN_SLOT[2].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3800_DATA[7:0]$3997 + 3/3: $1$memwr$\GEN_SLOT[2].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3800_ADDR[3:0]$3996 +Creating decoders for process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3981'. + 1/3: $1$memwr$\GEN_SLOT[1].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3799_EN[7:0]$3987 + 2/3: $1$memwr$\GEN_SLOT[1].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3799_DATA[7:0]$3986 + 3/3: $1$memwr$\GEN_SLOT[1].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3799_ADDR[3:0]$3985 +Creating decoders for process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3970'. + 1/3: $1$memwr$\GEN_SLOT[1].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3798_EN[7:0]$3976 + 2/3: $1$memwr$\GEN_SLOT[1].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3798_DATA[7:0]$3975 + 3/3: $1$memwr$\GEN_SLOT[1].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3798_ADDR[3:0]$3974 +Creating decoders for process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3959'. + 1/3: $1$memwr$\GEN_SLOT[1].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3797_EN[7:0]$3965 + 2/3: $1$memwr$\GEN_SLOT[1].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3797_DATA[7:0]$3964 + 3/3: $1$memwr$\GEN_SLOT[1].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3797_ADDR[3:0]$3963 +Creating decoders for process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3948'. + 1/3: $1$memwr$\GEN_SLOT[1].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3796_EN[7:0]$3954 + 2/3: $1$memwr$\GEN_SLOT[1].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3796_DATA[7:0]$3953 + 3/3: $1$memwr$\GEN_SLOT[1].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3796_ADDR[3:0]$3952 +Creating decoders for process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3937'. + 1/3: $1$memwr$\GEN_SLOT[1].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3795_EN[7:0]$3943 + 2/3: $1$memwr$\GEN_SLOT[1].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3795_DATA[7:0]$3942 + 3/3: $1$memwr$\GEN_SLOT[1].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3795_ADDR[3:0]$3941 +Creating decoders for process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3926'. + 1/3: $1$memwr$\GEN_SLOT[1].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3794_EN[7:0]$3932 + 2/3: $1$memwr$\GEN_SLOT[1].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3794_DATA[7:0]$3931 + 3/3: $1$memwr$\GEN_SLOT[1].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3794_ADDR[3:0]$3930 +Creating decoders for process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3915'. + 1/3: $1$memwr$\GEN_SLOT[1].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3793_EN[7:0]$3921 + 2/3: $1$memwr$\GEN_SLOT[1].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3793_DATA[7:0]$3920 + 3/3: $1$memwr$\GEN_SLOT[1].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3793_ADDR[3:0]$3919 +Creating decoders for process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3904'. + 1/3: $1$memwr$\GEN_SLOT[1].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3792_EN[7:0]$3910 + 2/3: $1$memwr$\GEN_SLOT[1].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3792_DATA[7:0]$3909 + 3/3: $1$memwr$\GEN_SLOT[1].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3792_ADDR[3:0]$3908 +Creating decoders for process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3893'. + 1/3: $1$memwr$\GEN_SLOT[0].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3791_EN[7:0]$3899 + 2/3: $1$memwr$\GEN_SLOT[0].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3791_DATA[7:0]$3898 + 3/3: $1$memwr$\GEN_SLOT[0].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3791_ADDR[3:0]$3897 +Creating decoders for process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3882'. + 1/3: $1$memwr$\GEN_SLOT[0].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3790_EN[7:0]$3888 + 2/3: $1$memwr$\GEN_SLOT[0].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3790_DATA[7:0]$3887 + 3/3: $1$memwr$\GEN_SLOT[0].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3790_ADDR[3:0]$3886 +Creating decoders for process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3871'. + 1/3: $1$memwr$\GEN_SLOT[0].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3789_EN[7:0]$3877 + 2/3: $1$memwr$\GEN_SLOT[0].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3789_DATA[7:0]$3876 + 3/3: $1$memwr$\GEN_SLOT[0].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3789_ADDR[3:0]$3875 +Creating decoders for process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3860'. + 1/3: $1$memwr$\GEN_SLOT[0].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3788_EN[7:0]$3866 + 2/3: $1$memwr$\GEN_SLOT[0].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3788_DATA[7:0]$3865 + 3/3: $1$memwr$\GEN_SLOT[0].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3788_ADDR[3:0]$3864 +Creating decoders for process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3849'. + 1/3: $1$memwr$\GEN_SLOT[0].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3787_EN[7:0]$3855 + 2/3: $1$memwr$\GEN_SLOT[0].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3787_DATA[7:0]$3854 + 3/3: $1$memwr$\GEN_SLOT[0].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3787_ADDR[3:0]$3853 +Creating decoders for process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3838'. + 1/3: $1$memwr$\GEN_SLOT[0].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3786_EN[7:0]$3844 + 2/3: $1$memwr$\GEN_SLOT[0].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3786_DATA[7:0]$3843 + 3/3: $1$memwr$\GEN_SLOT[0].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3786_ADDR[3:0]$3842 +Creating decoders for process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3827'. + 1/3: $1$memwr$\GEN_SLOT[0].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3785_EN[7:0]$3833 + 2/3: $1$memwr$\GEN_SLOT[0].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3785_DATA[7:0]$3832 + 3/3: $1$memwr$\GEN_SLOT[0].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3785_ADDR[3:0]$3831 +Creating decoders for process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3816'. + 1/3: $1$memwr$\GEN_SLOT[0].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3784_EN[7:0]$3822 + 2/3: $1$memwr$\GEN_SLOT[0].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3784_DATA[7:0]$3821 + 3/3: $1$memwr$\GEN_SLOT[0].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3784_ADDR[3:0]$3820 +Creating decoders for process `$paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide.$proc$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:194$3771'. + 1/26: $0\wgt_rd_en[0:0] + 2/26: $0\act_rd_en[0:0] + 3/26: $0\result_ready[0:0] + 4/26: $0\job_done[0:0] + 5/26: $0\buf_last[0:0] + 6/26: $0\buf_weight[63:0] + 7/26: $0\buf_input[63:0] + 8/26: $0\buf_valid[0:0] + 9/26: $0\rd_pending_last[0:0] + 10/26: $0\rd_pending_tile[4:0] + 11/26: $0\rd_pending[0:0] + 12/26: $0\wr_mem_ub_n[0:0] + 13/26: $0\wr_mem_lb_n[0:0] + 14/26: $0\wr_mem_wdata[15:0] + 15/26: $0\wr_mem_addr[22:0] + 16/26: $0\wr_mem_req[0:0] + 17/26: $0\rd_ptr[4:0] + 18/26: $0\tile_idx[4:0] + 19/26: $0\n_tiles_reg[15:0] + 20/26: $0\result_addr_reg[22:0] + 21/26: $0\w_base_reg[22:0] + 22/26: $0\x_base_reg[22:0] + 23/26: $0\job_active_reg[0:0] + 24/26: $0\wgt_rd_addr[3:0] + 25/26: $0\act_rd_addr[3:0] + 26/26: $0\state[2:0] + +19.4.8. Executing PROC_DLATCH pass (convert process syncs to latches). +No latch inferred for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\level0[7]' from process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$3757'. +No latch inferred for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\level0[6]' from process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$3756'. +No latch inferred for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\level0[5]' from process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$3755'. +No latch inferred for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\level0[4]' from process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$3754'. +No latch inferred for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\level0[3]' from process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$3753'. +No latch inferred for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\level0[2]' from process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$3752'. +No latch inferred for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\level0[1]' from process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$3751'. +No latch inferred for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\level0[0]' from process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$3750'. +No latch inferred for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\product_comb[7]' from process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$3748'. +No latch inferred for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\product_comb[6]' from process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$3746'. +No latch inferred for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\product_comb[5]' from process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$3744'. +No latch inferred for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\product_comb[4]' from process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$3742'. +No latch inferred for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\product_comb[3]' from process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$3740'. +No latch inferred for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\product_comb[2]' from process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$3738'. +No latch inferred for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\product_comb[1]' from process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$3736'. +No latch inferred for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\product_comb[0]' from process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$3734'. +No latch inferred for signal `$paramod$8ec81e5664842acf17791930d1f62ccccc9cf0b8\slot_mem_arbiter.\ri' from process `$paramod$8ec81e5664842acf17791930d1f62ccccc9cf0b8\slot_mem_arbiter.$proc$hardware/v2/rtl/slot_mem_arbiter.v:102$7145'. +No latch inferred for signal `$paramod$8ec81e5664842acf17791930d1f62ccccc9cf0b8\slot_mem_arbiter.\grant_idx' from process `$paramod$8ec81e5664842acf17791930d1f62ccccc9cf0b8\slot_mem_arbiter.$proc$hardware/v2/rtl/slot_mem_arbiter.v:102$7145'. +No latch inferred for signal `$paramod$8ec81e5664842acf17791930d1f62ccccc9cf0b8\slot_mem_arbiter.\any_pending' from process `$paramod$8ec81e5664842acf17791930d1f62ccccc9cf0b8\slot_mem_arbiter.$proc$hardware/v2/rtl/slot_mem_arbiter.v:102$7145'. +No latch inferred for signal `$paramod$13018cccabdf3dac026b50531aeca2ed1853451d\slot_mem_arbiter.\ri' from process `$paramod$13018cccabdf3dac026b50531aeca2ed1853451d\slot_mem_arbiter.$proc$hardware/v2/rtl/slot_mem_arbiter.v:102$7111'. +No latch inferred for signal `$paramod$13018cccabdf3dac026b50531aeca2ed1853451d\slot_mem_arbiter.\grant_idx' from process `$paramod$13018cccabdf3dac026b50531aeca2ed1853451d\slot_mem_arbiter.$proc$hardware/v2/rtl/slot_mem_arbiter.v:102$7111'. +No latch inferred for signal `$paramod$13018cccabdf3dac026b50531aeca2ed1853451d\slot_mem_arbiter.\any_pending' from process `$paramod$13018cccabdf3dac026b50531aeca2ed1853451d\slot_mem_arbiter.$proc$hardware/v2/rtl/slot_mem_arbiter.v:102$7111'. +No latch inferred for signal `$paramod$8ef509dd8065f2599f8ea3948e2930abb5d7b7b0\slot_mem_arbiter_wide.\ri' from process `$paramod$8ef509dd8065f2599f8ea3948e2930abb5d7b7b0\slot_mem_arbiter_wide.$proc$hardware/v2/rtl/slot_mem_arbiter_wide.v:103$7073'. +No latch inferred for signal `$paramod$8ef509dd8065f2599f8ea3948e2930abb5d7b7b0\slot_mem_arbiter_wide.\grant_idx' from process `$paramod$8ef509dd8065f2599f8ea3948e2930abb5d7b7b0\slot_mem_arbiter_wide.$proc$hardware/v2/rtl/slot_mem_arbiter_wide.v:103$7073'. +No latch inferred for signal `$paramod$8ef509dd8065f2599f8ea3948e2930abb5d7b7b0\slot_mem_arbiter_wide.\any_pending' from process `$paramod$8ef509dd8065f2599f8ea3948e2930abb5d7b7b0\slot_mem_arbiter_wide.$proc$hardware/v2/rtl/slot_mem_arbiter_wide.v:103$7073'. +No latch inferred for signal `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.\w_hit_found_c' from process `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$proc$hardware/v2/nms/rtl/sdram_unified_backend.v:115$6942'. +No latch inferred for signal `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.\w_hit_idx_c' from process `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$proc$hardware/v2/nms/rtl/sdram_unified_backend.v:115$6942'. +No latch inferred for signal `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.\ei' from process `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$proc$hardware/v2/nms/rtl/sdram_unified_backend.v:115$6942'. +No latch inferred for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.\first_ready_idx' from process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:103$4644'. +No latch inferred for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.\any_ready' from process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:103$4644'. +No latch inferred for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.\ri' from process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:103$4644'. +No latch inferred for signal `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.\tx_mux' from process `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.$proc$hardware/v2/rtl/spi_host_bridge.v:250$7338'. +No latch inferred for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.\di' from process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:131$4275'. +No latch inferred for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.\done_slot_idx' from process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:131$4275'. +No latch inferred for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.\free_slot_idx' from process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:117$4274'. +No latch inferred for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.\fi' from process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:117$4274'. +No latch inferred for signal `$paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3.\j' from process `$paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3.$proc$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:126$4169'. +No latch inferred for signal `$paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3.\max_n_tiles_comb' from process `$paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3.$proc$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:126$4169'. +No latch inferred for signal `$paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3.\i' from process `$paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3.$proc$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:76$4168'. +No latch inferred for signal `$paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3.\desired_valid' from process `$paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3.$proc$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:76$4168'. +No latch inferred for signal `$paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3.\desired_x_base' from process `$paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3.$proc$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:76$4168'. + +19.4.9. Executing PROC_DFF pass (convert process syncs to FFs). +Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\tree[16]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:196$3732'. + created $dff cell `$procdff$20041' with positive edge clock. +Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\valid_tree [2]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$3731'. + created $dff cell `$procdff$20042' with positive edge clock. +Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\last_tree [2]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$3731'. + created $dff cell `$procdff$20043' with positive edge clock. +Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\tree[9]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:196$3729'. + created $dff cell `$procdff$20044' with positive edge clock. +Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\tree[8]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:196$3727'. + created $dff cell `$procdff$20045' with positive edge clock. +Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\valid_tree [1]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$3726'. + created $dff cell `$procdff$20046' with positive edge clock. +Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\last_tree [1]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$3726'. + created $dff cell `$procdff$20047' with positive edge clock. +Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\tree[3]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:192$3724'. + created $dff cell `$procdff$20048' with positive edge clock. +Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\tree[2]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:192$3722'. + created $dff cell `$procdff$20049' with positive edge clock. +Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\tree[1]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:192$3720'. + created $dff cell `$procdff$20050' with positive edge clock. +Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\tree[0]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:192$3718'. + created $dff cell `$procdff$20051' with positive edge clock. +Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\valid_tree [0]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$3717'. + created $dff cell `$procdff$20052' with positive edge clock. +Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\last_tree [0]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$3717'. + created $dff cell `$procdff$20053' with positive edge clock. +Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\result_valid' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:305$3712'. + created $dff cell `$procdff$20054' with positive edge clock. +Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\result_data' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:305$3712'. + created $dff cell `$procdff$20055' with positive edge clock. +Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\result_node_id' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:305$3712'. + created $dff cell `$procdff$20056' with positive edge clock. +Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\np_state' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:305$3712'. + created $dff cell `$procdff$20057' with positive edge clock. +Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\np_error' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:305$3712'. + created $dff cell `$procdff$20058' with positive edge clock. +Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\bias_reg' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:305$3712'. + created $dff cell `$procdff$20059' with positive edge clock. +Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\activation_reg' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:305$3712'. + created $dff cell `$procdff$20060' with positive edge clock. +Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\node_id_reg' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:305$3712'. + created $dff cell `$procdff$20061' with positive edge clock. +Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\valid7' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:278$3702'. + created $dff cell `$procdff$20062' with positive edge clock. +Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\y7' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:278$3702'. + created $dff cell `$procdff$20063' with positive edge clock. +Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\valid6' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:245$3689'. + created $dff cell `$procdff$20064' with positive edge clock. +Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\last6' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:245$3689'. + created $dff cell `$procdff$20065' with positive edge clock. +Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\final_acc_reg' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:245$3689'. + created $dff cell `$procdff$20066' with positive edge clock. +Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\acc_reg' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:215$3686'. + created $dff cell `$procdff$20067' with positive edge clock. +Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\valid5' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:215$3686'. + created $dff cell `$procdff$20068' with positive edge clock. +Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\last5' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:215$3686'. + created $dff cell `$procdff$20069' with positive edge clock. +Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$3685'. + created $dff cell `$procdff$20070' with positive edge clock. +Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\valid1' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$3685'. + created $dff cell `$procdff$20071' with positive edge clock. +Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\last1' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$3685'. + created $dff cell `$procdff$20072' with positive edge clock. +Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\prod1[0]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$3685'. + created $dff cell `$procdff$20073' with positive edge clock. +Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\prod1[1]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$3685'. + created $dff cell `$procdff$20074' with positive edge clock. +Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\prod1[2]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$3685'. + created $dff cell `$procdff$20075' with positive edge clock. +Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\prod1[3]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$3685'. + created $dff cell `$procdff$20076' with positive edge clock. +Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\prod1[4]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$3685'. + created $dff cell `$procdff$20077' with positive edge clock. +Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\prod1[5]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$3685'. + created $dff cell `$procdff$20078' with positive edge clock. +Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\prod1[6]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$3685'. + created $dff cell `$procdff$20079' with positive edge clock. +Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\prod1[7]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$3685'. + created $dff cell `$procdff$20080' with positive edge clock. +Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\valid0' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$3680'. + created $dff cell `$procdff$20081' with positive edge clock. +Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\last0' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$3680'. + created $dff cell `$procdff$20082' with positive edge clock. +Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$3680'. + created $dff cell `$procdff$20083' with positive edge clock. +Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\x0[0]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$3680'. + created $dff cell `$procdff$20084' with positive edge clock. +Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\x0[1]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$3680'. + created $dff cell `$procdff$20085' with positive edge clock. +Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\x0[2]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$3680'. + created $dff cell `$procdff$20086' with positive edge clock. +Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\x0[3]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$3680'. + created $dff cell `$procdff$20087' with positive edge clock. +Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\x0[4]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$3680'. + created $dff cell `$procdff$20088' with positive edge clock. +Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\x0[5]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$3680'. + created $dff cell `$procdff$20089' with positive edge clock. +Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\x0[6]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$3680'. + created $dff cell `$procdff$20090' with positive edge clock. +Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\x0[7]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$3680'. + created $dff cell `$procdff$20091' with positive edge clock. +Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\w0[0]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$3680'. + created $dff cell `$procdff$20092' with positive edge clock. +Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\w0[1]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$3680'. + created $dff cell `$procdff$20093' with positive edge clock. +Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\w0[2]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$3680'. + created $dff cell `$procdff$20094' with positive edge clock. +Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\w0[3]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$3680'. + created $dff cell `$procdff$20095' with positive edge clock. +Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\w0[4]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$3680'. + created $dff cell `$procdff$20096' with positive edge clock. +Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\w0[5]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$3680'. + created $dff cell `$procdff$20097' with positive edge clock. +Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\w0[6]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$3680'. + created $dff cell `$procdff$20098' with positive edge clock. +Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\w0[7]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$3680'. + created $dff cell `$procdff$20099' with positive edge clock. +Creating register for signal `$paramod$8ec81e5664842acf17791930d1f62ccccc9cf0b8\slot_mem_arbiter.\s_rdata' using process `$paramod$8ec81e5664842acf17791930d1f62ccccc9cf0b8\slot_mem_arbiter.$proc$hardware/v2/rtl/slot_mem_arbiter.v:115$7147'. + created $dff cell `$procdff$20100' with positive edge clock. +Creating register for signal `$paramod$8ec81e5664842acf17791930d1f62ccccc9cf0b8\slot_mem_arbiter.\s_ready' using process `$paramod$8ec81e5664842acf17791930d1f62ccccc9cf0b8\slot_mem_arbiter.$proc$hardware/v2/rtl/slot_mem_arbiter.v:115$7147'. + created $dff cell `$procdff$20101' with positive edge clock. +Creating register for signal `$paramod$8ec81e5664842acf17791930d1f62ccccc9cf0b8\slot_mem_arbiter.\m_req' using process `$paramod$8ec81e5664842acf17791930d1f62ccccc9cf0b8\slot_mem_arbiter.$proc$hardware/v2/rtl/slot_mem_arbiter.v:115$7147'. + created $dff cell `$procdff$20102' with positive edge clock. +Creating register for signal `$paramod$8ec81e5664842acf17791930d1f62ccccc9cf0b8\slot_mem_arbiter.\m_wr' using process `$paramod$8ec81e5664842acf17791930d1f62ccccc9cf0b8\slot_mem_arbiter.$proc$hardware/v2/rtl/slot_mem_arbiter.v:115$7147'. + created $dff cell `$procdff$20103' with positive edge clock. +Creating register for signal `$paramod$8ec81e5664842acf17791930d1f62ccccc9cf0b8\slot_mem_arbiter.\m_addr' using process `$paramod$8ec81e5664842acf17791930d1f62ccccc9cf0b8\slot_mem_arbiter.$proc$hardware/v2/rtl/slot_mem_arbiter.v:115$7147'. + created $dff cell `$procdff$20104' with positive edge clock. +Creating register for signal `$paramod$8ec81e5664842acf17791930d1f62ccccc9cf0b8\slot_mem_arbiter.\m_wdata' using process `$paramod$8ec81e5664842acf17791930d1f62ccccc9cf0b8\slot_mem_arbiter.$proc$hardware/v2/rtl/slot_mem_arbiter.v:115$7147'. + created $dff cell `$procdff$20105' with positive edge clock. +Creating register for signal `$paramod$8ec81e5664842acf17791930d1f62ccccc9cf0b8\slot_mem_arbiter.\m_lb_n' using process `$paramod$8ec81e5664842acf17791930d1f62ccccc9cf0b8\slot_mem_arbiter.$proc$hardware/v2/rtl/slot_mem_arbiter.v:115$7147'. + created $dff cell `$procdff$20106' with positive edge clock. +Creating register for signal `$paramod$8ec81e5664842acf17791930d1f62ccccc9cf0b8\slot_mem_arbiter.\m_ub_n' using process `$paramod$8ec81e5664842acf17791930d1f62ccccc9cf0b8\slot_mem_arbiter.$proc$hardware/v2/rtl/slot_mem_arbiter.v:115$7147'. + created $dff cell `$procdff$20107' with positive edge clock. +Creating register for signal `$paramod$8ec81e5664842acf17791930d1f62ccccc9cf0b8\slot_mem_arbiter.\owner' using process `$paramod$8ec81e5664842acf17791930d1f62ccccc9cf0b8\slot_mem_arbiter.$proc$hardware/v2/rtl/slot_mem_arbiter.v:115$7147'. + created $dff cell `$procdff$20108' with positive edge clock. +Creating register for signal `$paramod$8ec81e5664842acf17791930d1f62ccccc9cf0b8\slot_mem_arbiter.\pending' using process `$paramod$8ec81e5664842acf17791930d1f62ccccc9cf0b8\slot_mem_arbiter.$proc$hardware/v2/rtl/slot_mem_arbiter.v:115$7147'. + created $dff cell `$procdff$20109' with positive edge clock. +Creating register for signal `$paramod$8ec81e5664842acf17791930d1f62ccccc9cf0b8\slot_mem_arbiter.\pending_addr' using process `$paramod$8ec81e5664842acf17791930d1f62ccccc9cf0b8\slot_mem_arbiter.$proc$hardware/v2/rtl/slot_mem_arbiter.v:115$7147'. + created $dff cell `$procdff$20110' with positive edge clock. +Creating register for signal `$paramod$8ec81e5664842acf17791930d1f62ccccc9cf0b8\slot_mem_arbiter.\pending_wdata' using process `$paramod$8ec81e5664842acf17791930d1f62ccccc9cf0b8\slot_mem_arbiter.$proc$hardware/v2/rtl/slot_mem_arbiter.v:115$7147'. + created $dff cell `$procdff$20111' with positive edge clock. +Creating register for signal `$paramod$8ec81e5664842acf17791930d1f62ccccc9cf0b8\slot_mem_arbiter.\pending_wr' using process `$paramod$8ec81e5664842acf17791930d1f62ccccc9cf0b8\slot_mem_arbiter.$proc$hardware/v2/rtl/slot_mem_arbiter.v:115$7147'. + created $dff cell `$procdff$20112' with positive edge clock. +Creating register for signal `$paramod$8ec81e5664842acf17791930d1f62ccccc9cf0b8\slot_mem_arbiter.\pending_lb_n' using process `$paramod$8ec81e5664842acf17791930d1f62ccccc9cf0b8\slot_mem_arbiter.$proc$hardware/v2/rtl/slot_mem_arbiter.v:115$7147'. + created $dff cell `$procdff$20113' with positive edge clock. +Creating register for signal `$paramod$8ec81e5664842acf17791930d1f62ccccc9cf0b8\slot_mem_arbiter.\pending_ub_n' using process `$paramod$8ec81e5664842acf17791930d1f62ccccc9cf0b8\slot_mem_arbiter.$proc$hardware/v2/rtl/slot_mem_arbiter.v:115$7147'. + created $dff cell `$procdff$20114' with positive edge clock. +Creating register for signal `$paramod$8ec81e5664842acf17791930d1f62ccccc9cf0b8\slot_mem_arbiter.\pi' using process `$paramod$8ec81e5664842acf17791930d1f62ccccc9cf0b8\slot_mem_arbiter.$proc$hardware/v2/rtl/slot_mem_arbiter.v:115$7147'. + created $dff cell `$procdff$20115' with positive edge clock. +Creating register for signal `$paramod$8ec81e5664842acf17791930d1f62ccccc9cf0b8\slot_mem_arbiter.$bitselwrite$pos$hardware/v2/rtl/slot_mem_arbiter.v:164$7144' using process `$paramod$8ec81e5664842acf17791930d1f62ccccc9cf0b8\slot_mem_arbiter.$proc$hardware/v2/rtl/slot_mem_arbiter.v:115$7147'. + created $dff cell `$procdff$20116' with positive edge clock. +Creating register for signal `$paramod$8ec81e5664842acf17791930d1f62ccccc9cf0b8\slot_mem_arbiter.$lookahead\pending$7146' using process `$paramod$8ec81e5664842acf17791930d1f62ccccc9cf0b8\slot_mem_arbiter.$proc$hardware/v2/rtl/slot_mem_arbiter.v:115$7147'. + created $dff cell `$procdff$20117' with positive edge clock. +Creating register for signal `$paramod$13018cccabdf3dac026b50531aeca2ed1853451d\slot_mem_arbiter.\s_rdata' using process `$paramod$13018cccabdf3dac026b50531aeca2ed1853451d\slot_mem_arbiter.$proc$hardware/v2/rtl/slot_mem_arbiter.v:115$7113'. + created $dff cell `$procdff$20118' with positive edge clock. +Creating register for signal `$paramod$13018cccabdf3dac026b50531aeca2ed1853451d\slot_mem_arbiter.\s_ready' using process `$paramod$13018cccabdf3dac026b50531aeca2ed1853451d\slot_mem_arbiter.$proc$hardware/v2/rtl/slot_mem_arbiter.v:115$7113'. + created $dff cell `$procdff$20119' with positive edge clock. +Creating register for signal `$paramod$13018cccabdf3dac026b50531aeca2ed1853451d\slot_mem_arbiter.\m_req' using process `$paramod$13018cccabdf3dac026b50531aeca2ed1853451d\slot_mem_arbiter.$proc$hardware/v2/rtl/slot_mem_arbiter.v:115$7113'. + created $dff cell `$procdff$20120' with positive edge clock. +Creating register for signal `$paramod$13018cccabdf3dac026b50531aeca2ed1853451d\slot_mem_arbiter.\m_wr' using process `$paramod$13018cccabdf3dac026b50531aeca2ed1853451d\slot_mem_arbiter.$proc$hardware/v2/rtl/slot_mem_arbiter.v:115$7113'. + created $dff cell `$procdff$20121' with positive edge clock. +Creating register for signal `$paramod$13018cccabdf3dac026b50531aeca2ed1853451d\slot_mem_arbiter.\m_addr' using process `$paramod$13018cccabdf3dac026b50531aeca2ed1853451d\slot_mem_arbiter.$proc$hardware/v2/rtl/slot_mem_arbiter.v:115$7113'. + created $dff cell `$procdff$20122' with positive edge clock. +Creating register for signal `$paramod$13018cccabdf3dac026b50531aeca2ed1853451d\slot_mem_arbiter.\m_wdata' using process `$paramod$13018cccabdf3dac026b50531aeca2ed1853451d\slot_mem_arbiter.$proc$hardware/v2/rtl/slot_mem_arbiter.v:115$7113'. + created $dff cell `$procdff$20123' with positive edge clock. +Creating register for signal `$paramod$13018cccabdf3dac026b50531aeca2ed1853451d\slot_mem_arbiter.\m_lb_n' using process `$paramod$13018cccabdf3dac026b50531aeca2ed1853451d\slot_mem_arbiter.$proc$hardware/v2/rtl/slot_mem_arbiter.v:115$7113'. + created $dff cell `$procdff$20124' with positive edge clock. +Creating register for signal `$paramod$13018cccabdf3dac026b50531aeca2ed1853451d\slot_mem_arbiter.\m_ub_n' using process `$paramod$13018cccabdf3dac026b50531aeca2ed1853451d\slot_mem_arbiter.$proc$hardware/v2/rtl/slot_mem_arbiter.v:115$7113'. + created $dff cell `$procdff$20125' with positive edge clock. +Creating register for signal `$paramod$13018cccabdf3dac026b50531aeca2ed1853451d\slot_mem_arbiter.\owner' using process `$paramod$13018cccabdf3dac026b50531aeca2ed1853451d\slot_mem_arbiter.$proc$hardware/v2/rtl/slot_mem_arbiter.v:115$7113'. + created $dff cell `$procdff$20126' with positive edge clock. +Creating register for signal `$paramod$13018cccabdf3dac026b50531aeca2ed1853451d\slot_mem_arbiter.\pending' using process `$paramod$13018cccabdf3dac026b50531aeca2ed1853451d\slot_mem_arbiter.$proc$hardware/v2/rtl/slot_mem_arbiter.v:115$7113'. + created $dff cell `$procdff$20127' with positive edge clock. +Creating register for signal `$paramod$13018cccabdf3dac026b50531aeca2ed1853451d\slot_mem_arbiter.\pending_addr' using process `$paramod$13018cccabdf3dac026b50531aeca2ed1853451d\slot_mem_arbiter.$proc$hardware/v2/rtl/slot_mem_arbiter.v:115$7113'. + created $dff cell `$procdff$20128' with positive edge clock. +Creating register for signal `$paramod$13018cccabdf3dac026b50531aeca2ed1853451d\slot_mem_arbiter.\pending_wdata' using process `$paramod$13018cccabdf3dac026b50531aeca2ed1853451d\slot_mem_arbiter.$proc$hardware/v2/rtl/slot_mem_arbiter.v:115$7113'. + created $dff cell `$procdff$20129' with positive edge clock. +Creating register for signal `$paramod$13018cccabdf3dac026b50531aeca2ed1853451d\slot_mem_arbiter.\pending_wr' using process `$paramod$13018cccabdf3dac026b50531aeca2ed1853451d\slot_mem_arbiter.$proc$hardware/v2/rtl/slot_mem_arbiter.v:115$7113'. + created $dff cell `$procdff$20130' with positive edge clock. +Creating register for signal `$paramod$13018cccabdf3dac026b50531aeca2ed1853451d\slot_mem_arbiter.\pending_lb_n' using process `$paramod$13018cccabdf3dac026b50531aeca2ed1853451d\slot_mem_arbiter.$proc$hardware/v2/rtl/slot_mem_arbiter.v:115$7113'. + created $dff cell `$procdff$20131' with positive edge clock. +Creating register for signal `$paramod$13018cccabdf3dac026b50531aeca2ed1853451d\slot_mem_arbiter.\pending_ub_n' using process `$paramod$13018cccabdf3dac026b50531aeca2ed1853451d\slot_mem_arbiter.$proc$hardware/v2/rtl/slot_mem_arbiter.v:115$7113'. + created $dff cell `$procdff$20132' with positive edge clock. +Creating register for signal `$paramod$13018cccabdf3dac026b50531aeca2ed1853451d\slot_mem_arbiter.\pi' using process `$paramod$13018cccabdf3dac026b50531aeca2ed1853451d\slot_mem_arbiter.$proc$hardware/v2/rtl/slot_mem_arbiter.v:115$7113'. + created $dff cell `$procdff$20133' with positive edge clock. +Creating register for signal `$paramod$13018cccabdf3dac026b50531aeca2ed1853451d\slot_mem_arbiter.$bitselwrite$pos$hardware/v2/rtl/slot_mem_arbiter.v:164$7110' using process `$paramod$13018cccabdf3dac026b50531aeca2ed1853451d\slot_mem_arbiter.$proc$hardware/v2/rtl/slot_mem_arbiter.v:115$7113'. + created $dff cell `$procdff$20134' with positive edge clock. +Creating register for signal `$paramod$13018cccabdf3dac026b50531aeca2ed1853451d\slot_mem_arbiter.$lookahead\pending$7112' using process `$paramod$13018cccabdf3dac026b50531aeca2ed1853451d\slot_mem_arbiter.$proc$hardware/v2/rtl/slot_mem_arbiter.v:115$7113'. + created $dff cell `$procdff$20135' with positive edge clock. +Creating register for signal `$paramod$8ef509dd8065f2599f8ea3948e2930abb5d7b7b0\slot_mem_arbiter_wide.\s_rdata' using process `$paramod$8ef509dd8065f2599f8ea3948e2930abb5d7b7b0\slot_mem_arbiter_wide.$proc$hardware/v2/rtl/slot_mem_arbiter_wide.v:116$7075'. + created $dff cell `$procdff$20136' with positive edge clock. +Creating register for signal `$paramod$8ef509dd8065f2599f8ea3948e2930abb5d7b7b0\slot_mem_arbiter_wide.\s_ready' using process `$paramod$8ef509dd8065f2599f8ea3948e2930abb5d7b7b0\slot_mem_arbiter_wide.$proc$hardware/v2/rtl/slot_mem_arbiter_wide.v:116$7075'. + created $dff cell `$procdff$20137' with positive edge clock. +Creating register for signal `$paramod$8ef509dd8065f2599f8ea3948e2930abb5d7b7b0\slot_mem_arbiter_wide.\m_req' using process `$paramod$8ef509dd8065f2599f8ea3948e2930abb5d7b7b0\slot_mem_arbiter_wide.$proc$hardware/v2/rtl/slot_mem_arbiter_wide.v:116$7075'. + created $dff cell `$procdff$20138' with positive edge clock. +Creating register for signal `$paramod$8ef509dd8065f2599f8ea3948e2930abb5d7b7b0\slot_mem_arbiter_wide.\m_wr' using process `$paramod$8ef509dd8065f2599f8ea3948e2930abb5d7b7b0\slot_mem_arbiter_wide.$proc$hardware/v2/rtl/slot_mem_arbiter_wide.v:116$7075'. + created $dff cell `$procdff$20139' with positive edge clock. +Creating register for signal `$paramod$8ef509dd8065f2599f8ea3948e2930abb5d7b7b0\slot_mem_arbiter_wide.\m_addr' using process `$paramod$8ef509dd8065f2599f8ea3948e2930abb5d7b7b0\slot_mem_arbiter_wide.$proc$hardware/v2/rtl/slot_mem_arbiter_wide.v:116$7075'. + created $dff cell `$procdff$20140' with positive edge clock. +Creating register for signal `$paramod$8ef509dd8065f2599f8ea3948e2930abb5d7b7b0\slot_mem_arbiter_wide.\m_wdata' using process `$paramod$8ef509dd8065f2599f8ea3948e2930abb5d7b7b0\slot_mem_arbiter_wide.$proc$hardware/v2/rtl/slot_mem_arbiter_wide.v:116$7075'. + created $dff cell `$procdff$20141' with positive edge clock. +Creating register for signal `$paramod$8ef509dd8065f2599f8ea3948e2930abb5d7b7b0\slot_mem_arbiter_wide.\m_lb_n' using process `$paramod$8ef509dd8065f2599f8ea3948e2930abb5d7b7b0\slot_mem_arbiter_wide.$proc$hardware/v2/rtl/slot_mem_arbiter_wide.v:116$7075'. + created $dff cell `$procdff$20142' with positive edge clock. +Creating register for signal `$paramod$8ef509dd8065f2599f8ea3948e2930abb5d7b7b0\slot_mem_arbiter_wide.\m_ub_n' using process `$paramod$8ef509dd8065f2599f8ea3948e2930abb5d7b7b0\slot_mem_arbiter_wide.$proc$hardware/v2/rtl/slot_mem_arbiter_wide.v:116$7075'. + created $dff cell `$procdff$20143' with positive edge clock. +Creating register for signal `$paramod$8ef509dd8065f2599f8ea3948e2930abb5d7b7b0\slot_mem_arbiter_wide.\owner' using process `$paramod$8ef509dd8065f2599f8ea3948e2930abb5d7b7b0\slot_mem_arbiter_wide.$proc$hardware/v2/rtl/slot_mem_arbiter_wide.v:116$7075'. + created $dff cell `$procdff$20144' with positive edge clock. +Creating register for signal `$paramod$8ef509dd8065f2599f8ea3948e2930abb5d7b7b0\slot_mem_arbiter_wide.\pending' using process `$paramod$8ef509dd8065f2599f8ea3948e2930abb5d7b7b0\slot_mem_arbiter_wide.$proc$hardware/v2/rtl/slot_mem_arbiter_wide.v:116$7075'. + created $dff cell `$procdff$20145' with positive edge clock. +Creating register for signal `$paramod$8ef509dd8065f2599f8ea3948e2930abb5d7b7b0\slot_mem_arbiter_wide.\pending_addr' using process `$paramod$8ef509dd8065f2599f8ea3948e2930abb5d7b7b0\slot_mem_arbiter_wide.$proc$hardware/v2/rtl/slot_mem_arbiter_wide.v:116$7075'. + created $dff cell `$procdff$20146' with positive edge clock. +Creating register for signal `$paramod$8ef509dd8065f2599f8ea3948e2930abb5d7b7b0\slot_mem_arbiter_wide.\pending_wdata' using process `$paramod$8ef509dd8065f2599f8ea3948e2930abb5d7b7b0\slot_mem_arbiter_wide.$proc$hardware/v2/rtl/slot_mem_arbiter_wide.v:116$7075'. + created $dff cell `$procdff$20147' with positive edge clock. +Creating register for signal `$paramod$8ef509dd8065f2599f8ea3948e2930abb5d7b7b0\slot_mem_arbiter_wide.\pending_wr' using process `$paramod$8ef509dd8065f2599f8ea3948e2930abb5d7b7b0\slot_mem_arbiter_wide.$proc$hardware/v2/rtl/slot_mem_arbiter_wide.v:116$7075'. + created $dff cell `$procdff$20148' with positive edge clock. +Creating register for signal `$paramod$8ef509dd8065f2599f8ea3948e2930abb5d7b7b0\slot_mem_arbiter_wide.\pending_lb_n' using process `$paramod$8ef509dd8065f2599f8ea3948e2930abb5d7b7b0\slot_mem_arbiter_wide.$proc$hardware/v2/rtl/slot_mem_arbiter_wide.v:116$7075'. + created $dff cell `$procdff$20149' with positive edge clock. +Creating register for signal `$paramod$8ef509dd8065f2599f8ea3948e2930abb5d7b7b0\slot_mem_arbiter_wide.\pending_ub_n' using process `$paramod$8ef509dd8065f2599f8ea3948e2930abb5d7b7b0\slot_mem_arbiter_wide.$proc$hardware/v2/rtl/slot_mem_arbiter_wide.v:116$7075'. + created $dff cell `$procdff$20150' with positive edge clock. +Creating register for signal `$paramod$8ef509dd8065f2599f8ea3948e2930abb5d7b7b0\slot_mem_arbiter_wide.\pi' using process `$paramod$8ef509dd8065f2599f8ea3948e2930abb5d7b7b0\slot_mem_arbiter_wide.$proc$hardware/v2/rtl/slot_mem_arbiter_wide.v:116$7075'. + created $dff cell `$procdff$20151' with positive edge clock. +Creating register for signal `$paramod$8ef509dd8065f2599f8ea3948e2930abb5d7b7b0\slot_mem_arbiter_wide.$bitselwrite$pos$hardware/v2/rtl/slot_mem_arbiter_wide.v:165$7072' using process `$paramod$8ef509dd8065f2599f8ea3948e2930abb5d7b7b0\slot_mem_arbiter_wide.$proc$hardware/v2/rtl/slot_mem_arbiter_wide.v:116$7075'. + created $dff cell `$procdff$20152' with positive edge clock. +Creating register for signal `$paramod$8ef509dd8065f2599f8ea3948e2930abb5d7b7b0\slot_mem_arbiter_wide.$lookahead\pending$7074' using process `$paramod$8ef509dd8065f2599f8ea3948e2930abb5d7b7b0\slot_mem_arbiter_wide.$proc$hardware/v2/rtl/slot_mem_arbiter_wide.v:116$7075'. + created $dff cell `$procdff$20153' with positive edge clock. +Creating register for signal `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.\ri' using process `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$proc$hardware/v2/nms/rtl/sdram_unified_backend.v:200$6968'. + created $dff cell `$procdff$20154' with positive edge clock. +Creating register for signal `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.\state' using process `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$proc$hardware/v2/nms/rtl/sdram_unified_backend.v:200$6968'. + created $dff cell `$procdff$20155' with positive edge clock. +Creating register for signal `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.\w_rdata' using process `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$proc$hardware/v2/nms/rtl/sdram_unified_backend.v:200$6968'. + created $dff cell `$procdff$20156' with positive edge clock. +Creating register for signal `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.\w_ready' using process `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$proc$hardware/v2/nms/rtl/sdram_unified_backend.v:200$6968'. + created $dff cell `$procdff$20157' with positive edge clock. +Creating register for signal `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.\ar_rdata' using process `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$proc$hardware/v2/nms/rtl/sdram_unified_backend.v:200$6968'. + created $dff cell `$procdff$20158' with positive edge clock. +Creating register for signal `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.\ar_ready' using process `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$proc$hardware/v2/nms/rtl/sdram_unified_backend.v:200$6968'. + created $dff cell `$procdff$20159' with positive edge clock. +Creating register for signal `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.\w_alloc_ptr' using process `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$proc$hardware/v2/nms/rtl/sdram_unified_backend.v:200$6968'. + created $dff cell `$procdff$20160' with positive edge clock. +Creating register for signal `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.\ctrl_req' using process `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$proc$hardware/v2/nms/rtl/sdram_unified_backend.v:200$6968'. + created $dff cell `$procdff$20161' with positive edge clock. +Creating register for signal `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.\ctrl_wr' using process `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$proc$hardware/v2/nms/rtl/sdram_unified_backend.v:200$6968'. + created $dff cell `$procdff$20162' with positive edge clock. +Creating register for signal `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.\ctrl_addr' using process `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$proc$hardware/v2/nms/rtl/sdram_unified_backend.v:200$6968'. + created $dff cell `$procdff$20163' with positive edge clock. +Creating register for signal `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.\ctrl_wdata' using process `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$proc$hardware/v2/nms/rtl/sdram_unified_backend.v:200$6968'. + created $dff cell `$procdff$20164' with positive edge clock. +Creating register for signal `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.\ctrl_wmask' using process `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$proc$hardware/v2/nms/rtl/sdram_unified_backend.v:200$6968'. + created $dff cell `$procdff$20165' with positive edge clock. +Creating register for signal `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.\w_pending_upper_half' using process `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$proc$hardware/v2/nms/rtl/sdram_unified_backend.v:200$6968'. + created $dff cell `$procdff$20166' with positive edge clock. +Creating register for signal `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.\w_pending_addr' using process `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$proc$hardware/v2/nms/rtl/sdram_unified_backend.v:200$6968'. + created $dff cell `$procdff$20167' with positive edge clock. +Creating register for signal `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.\ar_pending_word' using process `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$proc$hardware/v2/nms/rtl/sdram_unified_backend.v:200$6968'. + created $dff cell `$procdff$20168' with positive edge clock. +Creating register for signal `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.\w_req_pending' using process `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$proc$hardware/v2/nms/rtl/sdram_unified_backend.v:200$6968'. + created $dff cell `$procdff$20169' with positive edge clock. +Creating register for signal `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.\w_req_addr_lat' using process `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$proc$hardware/v2/nms/rtl/sdram_unified_backend.v:200$6968'. + created $dff cell `$procdff$20170' with positive edge clock. +Creating register for signal `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.\ar_req_pending' using process `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$proc$hardware/v2/nms/rtl/sdram_unified_backend.v:200$6968'. + created $dff cell `$procdff$20171' with positive edge clock. +Creating register for signal `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.\ar_req_wr_lat' using process `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$proc$hardware/v2/nms/rtl/sdram_unified_backend.v:200$6968'. + created $dff cell `$procdff$20172' with positive edge clock. +Creating register for signal `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.\ar_req_addr_lat' using process `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$proc$hardware/v2/nms/rtl/sdram_unified_backend.v:200$6968'. + created $dff cell `$procdff$20173' with positive edge clock. +Creating register for signal `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.\ar_req_wdata_lat' using process `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$proc$hardware/v2/nms/rtl/sdram_unified_backend.v:200$6968'. + created $dff cell `$procdff$20174' with positive edge clock. +Creating register for signal `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.\ar_req_lbn_lat' using process `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$proc$hardware/v2/nms/rtl/sdram_unified_backend.v:200$6968'. + created $dff cell `$procdff$20175' with positive edge clock. +Creating register for signal `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.\ar_req_ubn_lat' using process `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$proc$hardware/v2/nms/rtl/sdram_unified_backend.v:200$6968'. + created $dff cell `$procdff$20176' with positive edge clock. +Creating register for signal `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$memwr$\w_cache_valid$hardware/v2/nms/rtl/sdram_unified_backend.v:203$6932_EN' using process `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$proc$hardware/v2/nms/rtl/sdram_unified_backend.v:200$6968'. + created $dff cell `$procdff$20177' with positive edge clock. +Creating register for signal `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$memwr$\w_cache_valid$hardware/v2/nms/rtl/sdram_unified_backend.v:203$6933_EN' using process `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$proc$hardware/v2/nms/rtl/sdram_unified_backend.v:200$6968'. + created $dff cell `$procdff$20178' with positive edge clock. +Creating register for signal `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$memwr$\w_cache_valid$hardware/v2/nms/rtl/sdram_unified_backend.v:203$6934_EN' using process `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$proc$hardware/v2/nms/rtl/sdram_unified_backend.v:200$6968'. + created $dff cell `$procdff$20179' with positive edge clock. +Creating register for signal `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$memwr$\w_cache_valid$hardware/v2/nms/rtl/sdram_unified_backend.v:203$6935_EN' using process `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$proc$hardware/v2/nms/rtl/sdram_unified_backend.v:200$6968'. + created $dff cell `$procdff$20180' with positive edge clock. +Creating register for signal `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$memwr$\w_cache_valid$hardware/v2/nms/rtl/sdram_unified_backend.v:253$6936_ADDR' using process `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$proc$hardware/v2/nms/rtl/sdram_unified_backend.v:200$6968'. + created $dff cell `$procdff$20181' with positive edge clock. +Creating register for signal `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$memwr$\w_cache_valid$hardware/v2/nms/rtl/sdram_unified_backend.v:253$6936_EN' using process `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$proc$hardware/v2/nms/rtl/sdram_unified_backend.v:200$6968'. + created $dff cell `$procdff$20182' with positive edge clock. +Creating register for signal `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_ADDR' using process `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$proc$hardware/v2/nms/rtl/sdram_unified_backend.v:200$6968'. + created $dff cell `$procdff$20183' with positive edge clock. +Creating register for signal `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_DATA' using process `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$proc$hardware/v2/nms/rtl/sdram_unified_backend.v:200$6968'. + created $dff cell `$procdff$20184' with positive edge clock. +Creating register for signal `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN' using process `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$proc$hardware/v2/nms/rtl/sdram_unified_backend.v:200$6968'. + created $dff cell `$procdff$20185' with positive edge clock. +Creating register for signal `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:292$6938_ADDR' using process `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$proc$hardware/v2/nms/rtl/sdram_unified_backend.v:200$6968'. + created $dff cell `$procdff$20186' with positive edge clock. +Creating register for signal `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:292$6938_DATA' using process `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$proc$hardware/v2/nms/rtl/sdram_unified_backend.v:200$6968'. + created $dff cell `$procdff$20187' with positive edge clock. +Creating register for signal `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:292$6938_EN' using process `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$proc$hardware/v2/nms/rtl/sdram_unified_backend.v:200$6968'. + created $dff cell `$procdff$20188' with positive edge clock. +Creating register for signal `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_ADDR' using process `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$proc$hardware/v2/nms/rtl/sdram_unified_backend.v:200$6968'. + created $dff cell `$procdff$20189' with positive edge clock. +Creating register for signal `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_DATA' using process `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$proc$hardware/v2/nms/rtl/sdram_unified_backend.v:200$6968'. + created $dff cell `$procdff$20190' with positive edge clock. +Creating register for signal `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN' using process `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$proc$hardware/v2/nms/rtl/sdram_unified_backend.v:200$6968'. + created $dff cell `$procdff$20191' with positive edge clock. +Creating register for signal `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:296$6940_ADDR' using process `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$proc$hardware/v2/nms/rtl/sdram_unified_backend.v:200$6968'. + created $dff cell `$procdff$20192' with positive edge clock. +Creating register for signal `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:296$6940_DATA' using process `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$proc$hardware/v2/nms/rtl/sdram_unified_backend.v:200$6968'. + created $dff cell `$procdff$20193' with positive edge clock. +Creating register for signal `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:296$6940_EN' using process `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$proc$hardware/v2/nms/rtl/sdram_unified_backend.v:200$6968'. + created $dff cell `$procdff$20194' with positive edge clock. +Creating register for signal `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$memwr$\w_cache_valid$hardware/v2/nms/rtl/sdram_unified_backend.v:298$6941_ADDR' using process `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$proc$hardware/v2/nms/rtl/sdram_unified_backend.v:200$6968'. + created $dff cell `$procdff$20195' with positive edge clock. +Creating register for signal `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$memwr$\w_cache_valid$hardware/v2/nms/rtl/sdram_unified_backend.v:298$6941_EN' using process `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$proc$hardware/v2/nms/rtl/sdram_unified_backend.v:200$6968'. + created $dff cell `$procdff$20196' with positive edge clock. +Creating register for signal `$paramod$d1bf252c98cb2b8284c90cfb859e00756f939daa\sdram_controller.\state' using process `$paramod$d1bf252c98cb2b8284c90cfb859e00756f939daa\sdram_controller.$proc$hardware/v2/nms/rtl/sdram_controller.v:196$7417'. + created $dff cell `$procdff$20197' with positive edge clock. +Creating register for signal `$paramod$d1bf252c98cb2b8284c90cfb859e00756f939daa\sdram_controller.\sdram_cke' using process `$paramod$d1bf252c98cb2b8284c90cfb859e00756f939daa\sdram_controller.$proc$hardware/v2/nms/rtl/sdram_controller.v:196$7417'. + created $dff cell `$procdff$20198' with positive edge clock. +Creating register for signal `$paramod$d1bf252c98cb2b8284c90cfb859e00756f939daa\sdram_controller.\sdram_cs_n' using process `$paramod$d1bf252c98cb2b8284c90cfb859e00756f939daa\sdram_controller.$proc$hardware/v2/nms/rtl/sdram_controller.v:196$7417'. + created $dff cell `$procdff$20199' with positive edge clock. +Creating register for signal `$paramod$d1bf252c98cb2b8284c90cfb859e00756f939daa\sdram_controller.\sdram_ras_n' using process `$paramod$d1bf252c98cb2b8284c90cfb859e00756f939daa\sdram_controller.$proc$hardware/v2/nms/rtl/sdram_controller.v:196$7417'. + created $dff cell `$procdff$20200' with positive edge clock. +Creating register for signal `$paramod$d1bf252c98cb2b8284c90cfb859e00756f939daa\sdram_controller.\sdram_cas_n' using process `$paramod$d1bf252c98cb2b8284c90cfb859e00756f939daa\sdram_controller.$proc$hardware/v2/nms/rtl/sdram_controller.v:196$7417'. + created $dff cell `$procdff$20201' with positive edge clock. +Creating register for signal `$paramod$d1bf252c98cb2b8284c90cfb859e00756f939daa\sdram_controller.\sdram_we_n' using process `$paramod$d1bf252c98cb2b8284c90cfb859e00756f939daa\sdram_controller.$proc$hardware/v2/nms/rtl/sdram_controller.v:196$7417'. + created $dff cell `$procdff$20202' with positive edge clock. +Creating register for signal `$paramod$d1bf252c98cb2b8284c90cfb859e00756f939daa\sdram_controller.\sdram_ba' using process `$paramod$d1bf252c98cb2b8284c90cfb859e00756f939daa\sdram_controller.$proc$hardware/v2/nms/rtl/sdram_controller.v:196$7417'. + created $dff cell `$procdff$20203' with positive edge clock. +Creating register for signal `$paramod$d1bf252c98cb2b8284c90cfb859e00756f939daa\sdram_controller.\sdram_a' using process `$paramod$d1bf252c98cb2b8284c90cfb859e00756f939daa\sdram_controller.$proc$hardware/v2/nms/rtl/sdram_controller.v:196$7417'. + created $dff cell `$procdff$20204' with positive edge clock. +Creating register for signal `$paramod$d1bf252c98cb2b8284c90cfb859e00756f939daa\sdram_controller.\sdram_dqm' using process `$paramod$d1bf252c98cb2b8284c90cfb859e00756f939daa\sdram_controller.$proc$hardware/v2/nms/rtl/sdram_controller.v:196$7417'. + created $dff cell `$procdff$20205' with positive edge clock. +Creating register for signal `$paramod$d1bf252c98cb2b8284c90cfb859e00756f939daa\sdram_controller.\rdata' using process `$paramod$d1bf252c98cb2b8284c90cfb859e00756f939daa\sdram_controller.$proc$hardware/v2/nms/rtl/sdram_controller.v:196$7417'. + created $dff cell `$procdff$20206' with positive edge clock. +Creating register for signal `$paramod$d1bf252c98cb2b8284c90cfb859e00756f939daa\sdram_controller.\ready' using process `$paramod$d1bf252c98cb2b8284c90cfb859e00756f939daa\sdram_controller.$proc$hardware/v2/nms/rtl/sdram_controller.v:196$7417'. + created $dff cell `$procdff$20207' with positive edge clock. +Creating register for signal `$paramod$d1bf252c98cb2b8284c90cfb859e00756f939daa\sdram_controller.\busy' using process `$paramod$d1bf252c98cb2b8284c90cfb859e00756f939daa\sdram_controller.$proc$hardware/v2/nms/rtl/sdram_controller.v:196$7417'. + created $dff cell `$procdff$20208' with positive edge clock. +Creating register for signal `$paramod$d1bf252c98cb2b8284c90cfb859e00756f939daa\sdram_controller.\wait_cnt' using process `$paramod$d1bf252c98cb2b8284c90cfb859e00756f939daa\sdram_controller.$proc$hardware/v2/nms/rtl/sdram_controller.v:196$7417'. + created $dff cell `$procdff$20209' with positive edge clock. +Creating register for signal `$paramod$d1bf252c98cb2b8284c90cfb859e00756f939daa\sdram_controller.\init_ref_cnt' using process `$paramod$d1bf252c98cb2b8284c90cfb859e00756f939daa\sdram_controller.$proc$hardware/v2/nms/rtl/sdram_controller.v:196$7417'. + created $dff cell `$procdff$20210' with positive edge clock. +Creating register for signal `$paramod$d1bf252c98cb2b8284c90cfb859e00756f939daa\sdram_controller.\refresh_timer' using process `$paramod$d1bf252c98cb2b8284c90cfb859e00756f939daa\sdram_controller.$proc$hardware/v2/nms/rtl/sdram_controller.v:196$7417'. + created $dff cell `$procdff$20211' with positive edge clock. +Creating register for signal `$paramod$d1bf252c98cb2b8284c90cfb859e00756f939daa\sdram_controller.\burst_idx' using process `$paramod$d1bf252c98cb2b8284c90cfb859e00756f939daa\sdram_controller.$proc$hardware/v2/nms/rtl/sdram_controller.v:196$7417'. + created $dff cell `$procdff$20212' with positive edge clock. +Creating register for signal `$paramod$d1bf252c98cb2b8284c90cfb859e00756f939daa\sdram_controller.\req_wr_reg' using process `$paramod$d1bf252c98cb2b8284c90cfb859e00756f939daa\sdram_controller.$proc$hardware/v2/nms/rtl/sdram_controller.v:196$7417'. + created $dff cell `$procdff$20213' with positive edge clock. +Creating register for signal `$paramod$d1bf252c98cb2b8284c90cfb859e00756f939daa\sdram_controller.\req_bank_reg' using process `$paramod$d1bf252c98cb2b8284c90cfb859e00756f939daa\sdram_controller.$proc$hardware/v2/nms/rtl/sdram_controller.v:196$7417'. + created $dff cell `$procdff$20214' with positive edge clock. +Creating register for signal `$paramod$d1bf252c98cb2b8284c90cfb859e00756f939daa\sdram_controller.\req_row_reg' using process `$paramod$d1bf252c98cb2b8284c90cfb859e00756f939daa\sdram_controller.$proc$hardware/v2/nms/rtl/sdram_controller.v:196$7417'. + created $dff cell `$procdff$20215' with positive edge clock. +Creating register for signal `$paramod$d1bf252c98cb2b8284c90cfb859e00756f939daa\sdram_controller.\req_col_reg' using process `$paramod$d1bf252c98cb2b8284c90cfb859e00756f939daa\sdram_controller.$proc$hardware/v2/nms/rtl/sdram_controller.v:196$7417'. + created $dff cell `$procdff$20216' with positive edge clock. +Creating register for signal `$paramod$d1bf252c98cb2b8284c90cfb859e00756f939daa\sdram_controller.\wdata_reg' using process `$paramod$d1bf252c98cb2b8284c90cfb859e00756f939daa\sdram_controller.$proc$hardware/v2/nms/rtl/sdram_controller.v:196$7417'. + created $dff cell `$procdff$20217' with positive edge clock. +Creating register for signal `$paramod$d1bf252c98cb2b8284c90cfb859e00756f939daa\sdram_controller.\wmask_reg' using process `$paramod$d1bf252c98cb2b8284c90cfb859e00756f939daa\sdram_controller.$proc$hardware/v2/nms/rtl/sdram_controller.v:196$7417'. + created $dff cell `$procdff$20218' with positive edge clock. +Creating register for signal `$paramod$d1bf252c98cb2b8284c90cfb859e00756f939daa\sdram_controller.\req_pending' using process `$paramod$d1bf252c98cb2b8284c90cfb859e00756f939daa\sdram_controller.$proc$hardware/v2/nms/rtl/sdram_controller.v:196$7417'. + created $dff cell `$procdff$20219' with positive edge clock. +Creating register for signal `$paramod$d1bf252c98cb2b8284c90cfb859e00756f939daa\sdram_controller.\dq_out_en' using process `$paramod$d1bf252c98cb2b8284c90cfb859e00756f939daa\sdram_controller.$proc$hardware/v2/nms/rtl/sdram_controller.v:196$7417'. + created $dff cell `$procdff$20220' with positive edge clock. +Creating register for signal `$paramod$d1bf252c98cb2b8284c90cfb859e00756f939daa\sdram_controller.\dq_out' using process `$paramod$d1bf252c98cb2b8284c90cfb859e00756f939daa\sdram_controller.$proc$hardware/v2/nms/rtl/sdram_controller.v:196$7417'. + created $dff cell `$procdff$20221' with positive edge clock. +Creating register for signal `$paramod$d1bf252c98cb2b8284c90cfb859e00756f939daa\sdram_controller.$bitselwrite$pos$hardware/v2/nms/rtl/sdram_controller.v:410$7408' using process `$paramod$d1bf252c98cb2b8284c90cfb859e00756f939daa\sdram_controller.$proc$hardware/v2/nms/rtl/sdram_controller.v:196$7417'. + created $dff cell `$procdff$20222' with positive edge clock. +Creating register for signal `$paramod$d1bf252c98cb2b8284c90cfb859e00756f939daa\sdram_controller.$lookahead\rdata$7416' using process `$paramod$d1bf252c98cb2b8284c90cfb859e00756f939daa\sdram_controller.$proc$hardware/v2/nms/rtl/sdram_controller.v:196$7417'. + created $dff cell `$procdff$20223' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.\fetch_busy' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:82$6839'. + created $dff cell `$procdff$20224' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.\fetch_done' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:82$6839'. + created $dff cell `$procdff$20225' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.\tile_w' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:82$6839'. + created $dff cell `$procdff$20226' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.\mem_req' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:82$6839'. + created $dff cell `$procdff$20227' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.\mem_wr' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:82$6839'. + created $dff cell `$procdff$20228' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.\mem_addr' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:82$6839'. + created $dff cell `$procdff$20229' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.\mem_wdata' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:82$6839'. + created $dff cell `$procdff$20230' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.\mem_lb_n' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:82$6839'. + created $dff cell `$procdff$20231' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.\mem_ub_n' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:82$6839'. + created $dff cell `$procdff$20232' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.\state' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:82$6839'. + created $dff cell `$procdff$20233' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.\word_idx' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:82$6839'. + created $dff cell `$procdff$20234' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$bitselwrite$pos$hardware/v2/rtl/prefetch_engine.v:115$6837' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:82$6839'. + created $dff cell `$procdff$20235' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$lookahead\tile_w$6838' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:82$6839'. + created $dff cell `$procdff$20236' with positive edge clock. +Creating register for signal `$paramod$a83886fe79b03d603caba252b5389bc5341a5c19\weight_prefetch_engine_wide.\mem_req' using process `$paramod$a83886fe79b03d603caba252b5389bc5341a5c19\weight_prefetch_engine_wide.$proc$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:108$6796'. + created $dff cell `$procdff$20237' with positive edge clock. +Creating register for signal `$paramod$a83886fe79b03d603caba252b5389bc5341a5c19\weight_prefetch_engine_wide.\mem_addr' using process `$paramod$a83886fe79b03d603caba252b5389bc5341a5c19\weight_prefetch_engine_wide.$proc$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:108$6796'. + created $dff cell `$procdff$20238' with positive edge clock. +Creating register for signal `$paramod$a83886fe79b03d603caba252b5389bc5341a5c19\weight_prefetch_engine_wide.\wgt_fill_we' using process `$paramod$a83886fe79b03d603caba252b5389bc5341a5c19\weight_prefetch_engine_wide.$proc$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:108$6796'. + created $dff cell `$procdff$20239' with positive edge clock. +Creating register for signal `$paramod$a83886fe79b03d603caba252b5389bc5341a5c19\weight_prefetch_engine_wide.\wgt_fill_addr' using process `$paramod$a83886fe79b03d603caba252b5389bc5341a5c19\weight_prefetch_engine_wide.$proc$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:108$6796'. + created $dff cell `$procdff$20240' with positive edge clock. +Creating register for signal `$paramod$a83886fe79b03d603caba252b5389bc5341a5c19\weight_prefetch_engine_wide.\wgt_fill_data' using process `$paramod$a83886fe79b03d603caba252b5389bc5341a5c19\weight_prefetch_engine_wide.$proc$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:108$6796'. + created $dff cell `$procdff$20241' with positive edge clock. +Creating register for signal `$paramod$a83886fe79b03d603caba252b5389bc5341a5c19\weight_prefetch_engine_wide.\ready_count' using process `$paramod$a83886fe79b03d603caba252b5389bc5341a5c19\weight_prefetch_engine_wide.$proc$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:108$6796'. + created $dff cell `$procdff$20242' with positive edge clock. +Creating register for signal `$paramod$a83886fe79b03d603caba252b5389bc5341a5c19\weight_prefetch_engine_wide.\fetch_tile' using process `$paramod$a83886fe79b03d603caba252b5389bc5341a5c19\weight_prefetch_engine_wide.$proc$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:108$6796'. + created $dff cell `$procdff$20243' with positive edge clock. +Creating register for signal `$paramod$a83886fe79b03d603caba252b5389bc5341a5c19\weight_prefetch_engine_wide.\fetch_word' using process `$paramod$a83886fe79b03d603caba252b5389bc5341a5c19\weight_prefetch_engine_wide.$proc$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:108$6796'. + created $dff cell `$procdff$20244' with positive edge clock. +Creating register for signal `$paramod$a83886fe79b03d603caba252b5389bc5341a5c19\weight_prefetch_engine_wide.\req_outstanding' using process `$paramod$a83886fe79b03d603caba252b5389bc5341a5c19\weight_prefetch_engine_wide.$proc$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:108$6796'. + created $dff cell `$procdff$20245' with positive edge clock. +Creating register for signal `$paramod$a83886fe79b03d603caba252b5389bc5341a5c19\weight_prefetch_engine_wide.\tile_buf' using process `$paramod$a83886fe79b03d603caba252b5389bc5341a5c19\weight_prefetch_engine_wide.$proc$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:108$6796'. + created $dff cell `$procdff$20246' with positive edge clock. +Creating register for signal `$paramod$a83886fe79b03d603caba252b5389bc5341a5c19\weight_prefetch_engine_wide.$bitselwrite$pos$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:127$6789' using process `$paramod$a83886fe79b03d603caba252b5389bc5341a5c19\weight_prefetch_engine_wide.$proc$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:108$6796'. + created $dff cell `$procdff$20247' with positive edge clock. +Creating register for signal `$paramod$a83886fe79b03d603caba252b5389bc5341a5c19\weight_prefetch_engine_wide.$lookahead\tile_buf$6795' using process `$paramod$a83886fe79b03d603caba252b5389bc5341a5c19\weight_prefetch_engine_wide.$proc$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:108$6796'. + created $dff cell `$procdff$20248' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.\ready_valid' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20249' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.\ready_node_id' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20250' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.\ready_x_base' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20251' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.\ready_w_base' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20252' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.\ready_n_tiles' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20253' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.\ready_result_addr' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20254' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.\ni' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20255' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.\di' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20256' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4454_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20257' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4455_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20258' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4456_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20259' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4457_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20260' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4458_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20261' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4459_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20262' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4460_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20263' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4461_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20264' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4462_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20265' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4463_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20266' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4464_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20267' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4465_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20268' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4466_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20269' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4467_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20270' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4468_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20271' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4469_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20272' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4470_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20273' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4471_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20274' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4472_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20275' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4473_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20276' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4474_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20277' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4475_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20278' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4476_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20279' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4477_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20280' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4478_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20281' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4479_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20282' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4480_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20283' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4481_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20284' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4482_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20285' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4483_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20286' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4484_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20287' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4485_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20288' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4486_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20289' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4487_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20290' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4488_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20291' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4489_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20292' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4490_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20293' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4491_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20294' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4492_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20295' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4493_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20296' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4494_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20297' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4495_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20298' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4496_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20299' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4497_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20300' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4498_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20301' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4499_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20302' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4500_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20303' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4501_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20304' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:129$4502_ADDR' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20305' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:129$4502_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20306' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:129$4502_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20307' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:130$4503_ADDR' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20308' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:130$4503_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20309' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_x_base$hardware/v2/rtl/dependency_manager.v:131$4504_ADDR' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20310' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_x_base$hardware/v2/rtl/dependency_manager.v:131$4504_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20311' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_x_base$hardware/v2/rtl/dependency_manager.v:131$4504_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20312' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_w_base$hardware/v2/rtl/dependency_manager.v:132$4505_ADDR' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20313' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_w_base$hardware/v2/rtl/dependency_manager.v:132$4505_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20314' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_w_base$hardware/v2/rtl/dependency_manager.v:132$4505_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20315' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_n_tiles$hardware/v2/rtl/dependency_manager.v:133$4506_ADDR' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20316' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_n_tiles$hardware/v2/rtl/dependency_manager.v:133$4506_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20317' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_n_tiles$hardware/v2/rtl/dependency_manager.v:133$4506_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20318' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_result_addr$hardware/v2/rtl/dependency_manager.v:134$4507_ADDR' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20319' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_result_addr$hardware/v2/rtl/dependency_manager.v:134$4507_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20320' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_result_addr$hardware/v2/rtl/dependency_manager.v:134$4507_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20321' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$4508_ADDR' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20322' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$4508_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20323' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$4508_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20324' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$4509_ADDR' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20325' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$4509_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20326' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$4509_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20327' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$4510_ADDR' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20328' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$4510_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20329' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$4510_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20330' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$4511_ADDR' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20331' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$4511_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20332' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$4511_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20333' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:137$4512_ADDR' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20334' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:137$4512_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20335' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:137$4512_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20336' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4513_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20337' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4514_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20338' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4514_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20339' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4515_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20340' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4516_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20341' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4516_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20342' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4517_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20343' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4518_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20344' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4518_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20345' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4519_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20346' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4520_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20347' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4520_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20348' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4521_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20349' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4522_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20350' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4522_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20351' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4523_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20352' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4524_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20353' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4524_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20354' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4525_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20355' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4526_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20356' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4526_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20357' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4527_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20358' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4528_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20359' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4528_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20360' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4529_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20361' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4530_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20362' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4530_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20363' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4531_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20364' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4532_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20365' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4532_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20366' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4533_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20367' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4534_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20368' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4534_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20369' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4535_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20370' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4536_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20371' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4536_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20372' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4537_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20373' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4538_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20374' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4538_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20375' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4539_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20376' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4540_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20377' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4540_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20378' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4541_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20379' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4542_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20380' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4542_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20381' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4543_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20382' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4544_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20383' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4544_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20384' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4545_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20385' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4546_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20386' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4546_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20387' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4547_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20388' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4548_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20389' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4548_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20390' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4549_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20391' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4550_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20392' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4550_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20393' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4551_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20394' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4552_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20395' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4552_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20396' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4553_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20397' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4554_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20398' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4554_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20399' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4555_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20400' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4556_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20401' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4556_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20402' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4557_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20403' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4558_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20404' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4558_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20405' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4559_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20406' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4560_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20407' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4560_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20408' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4561_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20409' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4562_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20410' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4562_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20411' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4563_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20412' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4564_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20413' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4564_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20414' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4565_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20415' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4566_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20416' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4566_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20417' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4567_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20418' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4568_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20419' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4568_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20420' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4569_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20421' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4570_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20422' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4570_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20423' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4571_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20424' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4572_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20425' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4572_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20426' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4573_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20427' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4574_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20428' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4574_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20429' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4575_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20430' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4576_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20431' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4576_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20432' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4577_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20433' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4578_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20434' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4578_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20435' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4579_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20436' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4580_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20437' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4580_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20438' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4581_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20439' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4582_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20440' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4582_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20441' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4583_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20442' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4584_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20443' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4584_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20444' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4585_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20445' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4586_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20446' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4586_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20447' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4587_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20448' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4588_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20449' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4588_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20450' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4589_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20451' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4590_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20452' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4590_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20453' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4591_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20454' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4592_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20455' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4592_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20456' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4593_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20457' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4594_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20458' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4594_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20459' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4595_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20460' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4596_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20461' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4596_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20462' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4597_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20463' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4598_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20464' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4598_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20465' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4599_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20466' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4600_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20467' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4600_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20468' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4601_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20469' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4602_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20470' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4602_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20471' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4603_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20472' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4604_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20473' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4604_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20474' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4605_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20475' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4606_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20476' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4606_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20477' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4607_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20478' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4608_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20479' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4608_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20480' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4609_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20481' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4610_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20482' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4610_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20483' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4611_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20484' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4612_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20485' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4612_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20486' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4613_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20487' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4614_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20488' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4614_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20489' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4615_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20490' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4616_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20491' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4616_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20492' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4617_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20493' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4618_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20494' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4618_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20495' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4619_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20496' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4620_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20497' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4620_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20498' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4621_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20499' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4622_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20500' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4622_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20501' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4623_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20502' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4624_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20503' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4624_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20504' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4625_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20505' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4626_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20506' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4626_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20507' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4627_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20508' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4628_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20509' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4628_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20510' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4629_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20511' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4630_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20512' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4630_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20513' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4631_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20514' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4632_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20515' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4632_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20516' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4633_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20517' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4634_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20518' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4634_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20519' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4635_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20520' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4636_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20521' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4636_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20522' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4637_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20523' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4638_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20524' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4638_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20525' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4639_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20526' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4640_DATA' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20527' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4640_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20528' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:164$4641_ADDR' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20529' with positive edge clock. +Creating register for signal `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:164$4641_EN' using process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. + created $dff cell `$procdff$20530' with positive edge clock. +Creating register for signal `\reset_sync.\sync_ff' using process `\reset_sync.$proc$hardware/v2/rtl/reset_sync.v:27$2673'. + created $adff cell `$procdff$20535' with positive edge clock and positive level reset. +Creating register for signal `$paramod$5eff1de9335b9030234048498b6a1d64bf783cb3\nms_dataflow_core_sdram.\GEN_SLOT[3].job_valid_np' using process `$paramod$5eff1de9335b9030234048498b6a1d64bf783cb3\nms_dataflow_core_sdram.$proc$hardware/v2/nms/rtl/nms_dataflow_core_sdram.v:281$7317'. + created $dff cell `$procdff$20536' with positive edge clock. +Creating register for signal `$paramod$5eff1de9335b9030234048498b6a1d64bf783cb3\nms_dataflow_core_sdram.\GEN_SLOT[2].job_valid_np' using process `$paramod$5eff1de9335b9030234048498b6a1d64bf783cb3\nms_dataflow_core_sdram.$proc$hardware/v2/nms/rtl/nms_dataflow_core_sdram.v:281$7314'. + created $dff cell `$procdff$20537' with positive edge clock. +Creating register for signal `$paramod$5eff1de9335b9030234048498b6a1d64bf783cb3\nms_dataflow_core_sdram.\GEN_SLOT[1].job_valid_np' using process `$paramod$5eff1de9335b9030234048498b6a1d64bf783cb3\nms_dataflow_core_sdram.$proc$hardware/v2/nms/rtl/nms_dataflow_core_sdram.v:281$7311'. + created $dff cell `$procdff$20538' with positive edge clock. +Creating register for signal `$paramod$5eff1de9335b9030234048498b6a1d64bf783cb3\nms_dataflow_core_sdram.\GEN_SLOT[0].job_valid_np' using process `$paramod$5eff1de9335b9030234048498b6a1d64bf783cb3\nms_dataflow_core_sdram.$proc$hardware/v2/nms/rtl/nms_dataflow_core_sdram.v:281$7308'. + created $dff cell `$procdff$20539' with positive edge clock. +Creating register for signal `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.\reg_valid' using process `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.$proc$hardware/v2/rtl/spi_host_bridge.v:259$7345'. + created $dff cell `$procdff$20540' with positive edge clock. +Creating register for signal `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.\reg_node_id' using process `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.$proc$hardware/v2/rtl/spi_host_bridge.v:259$7345'. + created $dff cell `$procdff$20541' with positive edge clock. +Creating register for signal `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.\reg_required' using process `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.$proc$hardware/v2/rtl/spi_host_bridge.v:259$7345'. + created $dff cell `$procdff$20542' with positive edge clock. +Creating register for signal `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.\reg_producer_ids' using process `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.$proc$hardware/v2/rtl/spi_host_bridge.v:259$7345'. + created $dff cell `$procdff$20543' with positive edge clock. +Creating register for signal `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.\reg_x_base' using process `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.$proc$hardware/v2/rtl/spi_host_bridge.v:259$7345'. + created $dff cell `$procdff$20544' with positive edge clock. +Creating register for signal `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.\reg_w_base' using process `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.$proc$hardware/v2/rtl/spi_host_bridge.v:259$7345'. + created $dff cell `$procdff$20545' with positive edge clock. +Creating register for signal `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.\reg_n_tiles' using process `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.$proc$hardware/v2/rtl/spi_host_bridge.v:259$7345'. + created $dff cell `$procdff$20546' with positive edge clock. +Creating register for signal `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.\reg_result_addr' using process `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.$proc$hardware/v2/rtl/spi_host_bridge.v:259$7345'. + created $dff cell `$procdff$20547' with positive edge clock. +Creating register for signal `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.\mem_req' using process `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.$proc$hardware/v2/rtl/spi_host_bridge.v:259$7345'. + created $dff cell `$procdff$20548' with positive edge clock. +Creating register for signal `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.\mem_wr' using process `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.$proc$hardware/v2/rtl/spi_host_bridge.v:259$7345'. + created $dff cell `$procdff$20549' with positive edge clock. +Creating register for signal `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.\mem_addr' using process `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.$proc$hardware/v2/rtl/spi_host_bridge.v:259$7345'. + created $dff cell `$procdff$20550' with positive edge clock. +Creating register for signal `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.\mem_wdata' using process `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.$proc$hardware/v2/rtl/spi_host_bridge.v:259$7345'. + created $dff cell `$procdff$20551' with positive edge clock. +Creating register for signal `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.\mem_lb_n' using process `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.$proc$hardware/v2/rtl/spi_host_bridge.v:259$7345'. + created $dff cell `$procdff$20552' with positive edge clock. +Creating register for signal `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.\mem_ub_n' using process `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.$proc$hardware/v2/rtl/spi_host_bridge.v:259$7345'. + created $dff cell `$procdff$20553' with positive edge clock. +Creating register for signal `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.\state' using process `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.$proc$hardware/v2/rtl/spi_host_bridge.v:259$7345'. + created $dff cell `$procdff$20554' with positive edge clock. +Creating register for signal `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.\soft_rst_pulse' using process `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.$proc$hardware/v2/rtl/spi_host_bridge.v:259$7345'. + created $dff cell `$procdff$20555' with positive edge clock. +Creating register for signal `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.\opcode' using process `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.$proc$hardware/v2/rtl/spi_host_bridge.v:259$7345'. + created $dff cell `$procdff$20556' with positive edge clock. +Creating register for signal `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.\byte_idx' using process `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.$proc$hardware/v2/rtl/spi_host_bridge.v:259$7345'. + created $dff cell `$procdff$20557' with positive edge clock. +Creating register for signal `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.\len_words' using process `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.$proc$hardware/v2/rtl/spi_host_bridge.v:259$7345'. + created $dff cell `$procdff$20558' with positive edge clock. +Creating register for signal `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.\word_cnt' using process `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.$proc$hardware/v2/rtl/spi_host_bridge.v:259$7345'. + created $dff cell `$procdff$20559' with positive edge clock. +Creating register for signal `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.\cur_word' using process `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.$proc$hardware/v2/rtl/spi_host_bridge.v:259$7345'. + created $dff cell `$procdff$20560' with positive edge clock. +Creating register for signal `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.\job_busy_r' using process `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.$proc$hardware/v2/rtl/spi_host_bridge.v:259$7345'. + created $dff cell `$procdff$20561' with positive edge clock. +Creating register for signal `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.\mem_busy_r' using process `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.$proc$hardware/v2/rtl/spi_host_bridge.v:259$7345'. + created $dff cell `$procdff$20562' with positive edge clock. +Creating register for signal `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.\last_job_accepted_r' using process `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.$proc$hardware/v2/rtl/spi_host_bridge.v:259$7345'. + created $dff cell `$procdff$20563' with positive edge clock. +Creating register for signal `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.\bit_count' using process `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.$proc$hardware/v2/rtl/spi_host_bridge.v:192$7331'. + created $dff cell `$procdff$20564' with positive edge clock. +Creating register for signal `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.\rx_shift' using process `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.$proc$hardware/v2/rtl/spi_host_bridge.v:192$7331'. + created $dff cell `$procdff$20565' with positive edge clock. +Creating register for signal `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.\rx_byte' using process `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.$proc$hardware/v2/rtl/spi_host_bridge.v:192$7331'. + created $dff cell `$procdff$20566' with positive edge clock. +Creating register for signal `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.\rx_valid' using process `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.$proc$hardware/v2/rtl/spi_host_bridge.v:192$7331'. + created $dff cell `$procdff$20567' with positive edge clock. +Creating register for signal `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.\miso_shift_bit' using process `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.$proc$hardware/v2/rtl/spi_host_bridge.v:192$7331'. + created $dff cell `$procdff$20568' with positive edge clock. +Creating register for signal `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.\sclk_prev' using process `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.$proc$hardware/v2/rtl/spi_host_bridge.v:132$7320'. + created $dff cell `$procdff$20569' with positive edge clock. +Creating register for signal `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.\cs_n_prev' using process `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.$proc$hardware/v2/rtl/spi_host_bridge.v:132$7320'. + created $dff cell `$procdff$20570' with positive edge clock. +Creating register for signal `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.\sclk_sync' using process `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.$proc$hardware/v2/rtl/spi_host_bridge.v:118$7319'. + created $dff cell `$procdff$20571' with positive edge clock. +Creating register for signal `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.\mosi_sync' using process `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.$proc$hardware/v2/rtl/spi_host_bridge.v:118$7319'. + created $dff cell `$procdff$20572' with positive edge clock. +Creating register for signal `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.\cs_n_sync' using process `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.$proc$hardware/v2/rtl/spi_host_bridge.v:118$7319'. + created $dff cell `$procdff$20573' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.\slot_job_start' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:138$4283'. + created $dff cell `$procdff$20574' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.\slot_x_base' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:138$4283'. + created $dff cell `$procdff$20575' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.\slot_w_base' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:138$4283'. + created $dff cell `$procdff$20576' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.\slot_n_tiles' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:138$4283'. + created $dff cell `$procdff$20577' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.\slot_result_addr' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:138$4283'. + created $dff cell `$procdff$20578' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.\slot_node_id' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:138$4283'. + created $dff cell `$procdff$20579' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.\job_out_done' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:138$4283'. + created $dff cell `$procdff$20580' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.\job_out_slot' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:138$4283'. + created $dff cell `$procdff$20581' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.\dir_state' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:138$4283'. + created $dff cell `$procdff$20582' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.\dir_error' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:138$4283'. + created $dff cell `$procdff$20583' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.\q_head' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:138$4283'. + created $dff cell `$procdff$20584' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.\q_tail' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:138$4283'. + created $dff cell `$procdff$20585' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.\q_count' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:138$4283'. + created $dff cell `$procdff$20586' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.\slot_busy' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:138$4283'. + created $dff cell `$procdff$20587' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$bitselwrite$pos$hardware/v2/rtl/neural_director.v:206$4257' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:138$4283'. + created $dff cell `$procdff$20588' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$bitselwrite$pos$hardware/v2/rtl/neural_director.v:207$4258' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:138$4283'. + created $dff cell `$procdff$20589' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$bitselwrite$pos$hardware/v2/rtl/neural_director.v:208$4259' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:138$4283'. + created $dff cell `$procdff$20590' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$bitselwrite$pos$hardware/v2/rtl/neural_director.v:209$4260' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:138$4283'. + created $dff cell `$procdff$20591' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$bitselwrite$pos$hardware/v2/rtl/neural_director.v:210$4261' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:138$4283'. + created $dff cell `$procdff$20592' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$bitselwrite$pos$hardware/v2/rtl/neural_director.v:211$4262' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:138$4283'. + created $dff cell `$procdff$20593' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$bitselwrite$pos$hardware/v2/rtl/neural_director.v:212$4263' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:138$4283'. + created $dff cell `$procdff$20594' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:163$4264_ADDR' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:138$4283'. + created $dff cell `$procdff$20595' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:163$4264_DATA' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:138$4283'. + created $dff cell `$procdff$20596' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:163$4264_EN' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:138$4283'. + created $dff cell `$procdff$20597' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:164$4265_ADDR' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:138$4283'. + created $dff cell `$procdff$20598' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:164$4265_DATA' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:138$4283'. + created $dff cell `$procdff$20599' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:164$4265_EN' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:138$4283'. + created $dff cell `$procdff$20600' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:165$4266_ADDR' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:138$4283'. + created $dff cell `$procdff$20601' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:165$4266_DATA' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:138$4283'. + created $dff cell `$procdff$20602' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:165$4266_EN' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:138$4283'. + created $dff cell `$procdff$20603' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:166$4267_ADDR' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:138$4283'. + created $dff cell `$procdff$20604' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:166$4267_DATA' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:138$4283'. + created $dff cell `$procdff$20605' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:166$4267_EN' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:138$4283'. + created $dff cell `$procdff$20606' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$memwr$\q_node_id$hardware/v2/rtl/neural_director.v:167$4268_ADDR' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:138$4283'. + created $dff cell `$procdff$20607' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$memwr$\q_node_id$hardware/v2/rtl/neural_director.v:167$4268_DATA' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:138$4283'. + created $dff cell `$procdff$20608' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$memwr$\q_node_id$hardware/v2/rtl/neural_director.v:167$4268_EN' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:138$4283'. + created $dff cell `$procdff$20609' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$lookahead\slot_job_start$4276' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:138$4283'. + created $dff cell `$procdff$20610' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$lookahead\slot_x_base$4277' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:138$4283'. + created $dff cell `$procdff$20611' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$lookahead\slot_w_base$4278' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:138$4283'. + created $dff cell `$procdff$20612' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$lookahead\slot_n_tiles$4279' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:138$4283'. + created $dff cell `$procdff$20613' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$lookahead\slot_result_addr$4280' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:138$4283'. + created $dff cell `$procdff$20614' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$lookahead\slot_node_id$4281' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:138$4283'. + created $dff cell `$procdff$20615' with positive edge clock. +Creating register for signal `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$lookahead\slot_busy$4282' using process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:138$4283'. + created $dff cell `$procdff$20616' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_ADDR' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$proc$hardware/v2/nms/rtl/nms_activation_replicated.v:42$4246'. + created $dff cell `$procdff$20617' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_DATA' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$proc$hardware/v2/nms/rtl/nms_activation_replicated.v:42$4246'. + created $dff cell `$procdff$20618' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_EN' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$proc$hardware/v2/nms/rtl/nms_activation_replicated.v:42$4246'. + created $dff cell `$procdff$20619' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_ADDR' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$proc$hardware/v2/nms/rtl/nms_activation_replicated.v:42$4235'. + created $dff cell `$procdff$20620' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_DATA' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$proc$hardware/v2/nms/rtl/nms_activation_replicated.v:42$4235'. + created $dff cell `$procdff$20621' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_EN' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$proc$hardware/v2/nms/rtl/nms_activation_replicated.v:42$4235'. + created $dff cell `$procdff$20622' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_ADDR' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$proc$hardware/v2/nms/rtl/nms_activation_replicated.v:42$4224'. + created $dff cell `$procdff$20623' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_DATA' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$proc$hardware/v2/nms/rtl/nms_activation_replicated.v:42$4224'. + created $dff cell `$procdff$20624' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_EN' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$proc$hardware/v2/nms/rtl/nms_activation_replicated.v:42$4224'. + created $dff cell `$procdff$20625' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_ADDR' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$proc$hardware/v2/nms/rtl/nms_activation_replicated.v:42$4213'. + created $dff cell `$procdff$20626' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_DATA' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$proc$hardware/v2/nms/rtl/nms_activation_replicated.v:42$4213'. + created $dff cell `$procdff$20627' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_EN' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$proc$hardware/v2/nms/rtl/nms_activation_replicated.v:42$4213'. + created $dff cell `$procdff$20628' with positive edge clock. +Creating register for signal `$paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3.\n_tiles_masked[3]' using process `$paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3.$proc$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:116$4207'. + created $dff cell `$procdff$20629' with positive edge clock. +Creating register for signal `$paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3.\n_tiles_masked[2]' using process `$paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3.$proc$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:116$4203'. + created $dff cell `$procdff$20630' with positive edge clock. +Creating register for signal `$paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3.\n_tiles_masked[1]' using process `$paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3.$proc$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:116$4199'. + created $dff cell `$procdff$20631' with positive edge clock. +Creating register for signal `$paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3.\n_tiles_masked[0]' using process `$paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3.$proc$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:116$4195'. + created $dff cell `$procdff$20632' with positive edge clock. +Creating register for signal `$paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3.\state' using process `$paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3.$proc$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:164$4175'. + created $dff cell `$procdff$20633' with positive edge clock. +Creating register for signal `$paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3.\resident_tag' using process `$paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3.$proc$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:164$4175'. + created $dff cell `$procdff$20634' with positive edge clock. +Creating register for signal `$paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3.\resident_count' using process `$paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3.$proc$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:164$4175'. + created $dff cell `$procdff$20635' with positive edge clock. +Creating register for signal `$paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3.\pf_start' using process `$paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3.$proc$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:164$4175'. + created $dff cell `$procdff$20636' with positive edge clock. +Creating register for signal `$paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3.\pf_addr' using process `$paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3.$proc$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:164$4175'. + created $dff cell `$procdff$20637' with positive edge clock. +Creating register for signal `$paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3.\fill_we_reg' using process `$paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3.$proc$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:164$4175'. + created $dff cell `$procdff$20638' with positive edge clock. +Creating register for signal `$paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3.\fill_addr_reg' using process `$paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3.$proc$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:164$4175'. + created $dff cell `$procdff$20639' with positive edge clock. +Creating register for signal `$paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3.\fill_data_reg' using process `$paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3.$proc$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:164$4175'. + created $dff cell `$procdff$20640' with positive edge clock. +Creating register for signal `$paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3.\max_n_tiles_reg' using process `$paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3.$proc$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:132$4174'. + created $dff cell `$procdff$20641' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[3].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3815_ADDR' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4157'. + created $dff cell `$procdff$20642' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[3].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3815_DATA' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4157'. + created $dff cell `$procdff$20643' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[3].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3815_EN' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4157'. + created $dff cell `$procdff$20644' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[3].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3814_ADDR' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4146'. + created $dff cell `$procdff$20645' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[3].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3814_DATA' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4146'. + created $dff cell `$procdff$20646' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[3].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3814_EN' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4146'. + created $dff cell `$procdff$20647' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[3].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3813_ADDR' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4135'. + created $dff cell `$procdff$20648' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[3].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3813_DATA' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4135'. + created $dff cell `$procdff$20649' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[3].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3813_EN' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4135'. + created $dff cell `$procdff$20650' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[3].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3812_ADDR' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4124'. + created $dff cell `$procdff$20651' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[3].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3812_DATA' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4124'. + created $dff cell `$procdff$20652' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[3].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3812_EN' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4124'. + created $dff cell `$procdff$20653' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[3].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3811_ADDR' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4113'. + created $dff cell `$procdff$20654' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[3].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3811_DATA' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4113'. + created $dff cell `$procdff$20655' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[3].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3811_EN' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4113'. + created $dff cell `$procdff$20656' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[3].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3810_ADDR' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4102'. + created $dff cell `$procdff$20657' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[3].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3810_DATA' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4102'. + created $dff cell `$procdff$20658' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[3].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3810_EN' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4102'. + created $dff cell `$procdff$20659' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[3].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3809_ADDR' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4091'. + created $dff cell `$procdff$20660' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[3].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3809_DATA' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4091'. + created $dff cell `$procdff$20661' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[3].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3809_EN' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4091'. + created $dff cell `$procdff$20662' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[3].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3808_ADDR' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4080'. + created $dff cell `$procdff$20663' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[3].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3808_DATA' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4080'. + created $dff cell `$procdff$20664' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[3].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3808_EN' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4080'. + created $dff cell `$procdff$20665' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[2].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3807_ADDR' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4069'. + created $dff cell `$procdff$20666' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[2].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3807_DATA' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4069'. + created $dff cell `$procdff$20667' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[2].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3807_EN' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4069'. + created $dff cell `$procdff$20668' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[2].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3806_ADDR' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4058'. + created $dff cell `$procdff$20669' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[2].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3806_DATA' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4058'. + created $dff cell `$procdff$20670' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[2].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3806_EN' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4058'. + created $dff cell `$procdff$20671' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[2].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3805_ADDR' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4047'. + created $dff cell `$procdff$20672' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[2].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3805_DATA' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4047'. + created $dff cell `$procdff$20673' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[2].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3805_EN' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4047'. + created $dff cell `$procdff$20674' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[2].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3804_ADDR' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4036'. + created $dff cell `$procdff$20675' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[2].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3804_DATA' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4036'. + created $dff cell `$procdff$20676' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[2].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3804_EN' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4036'. + created $dff cell `$procdff$20677' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[2].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3803_ADDR' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4025'. + created $dff cell `$procdff$20678' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[2].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3803_DATA' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4025'. + created $dff cell `$procdff$20679' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[2].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3803_EN' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4025'. + created $dff cell `$procdff$20680' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[2].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3802_ADDR' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4014'. + created $dff cell `$procdff$20681' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[2].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3802_DATA' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4014'. + created $dff cell `$procdff$20682' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[2].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3802_EN' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4014'. + created $dff cell `$procdff$20683' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[2].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3801_ADDR' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4003'. + created $dff cell `$procdff$20684' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[2].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3801_DATA' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4003'. + created $dff cell `$procdff$20685' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[2].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3801_EN' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4003'. + created $dff cell `$procdff$20686' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[2].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3800_ADDR' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3992'. + created $dff cell `$procdff$20687' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[2].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3800_DATA' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3992'. + created $dff cell `$procdff$20688' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[2].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3800_EN' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3992'. + created $dff cell `$procdff$20689' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3799_ADDR' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3981'. + created $dff cell `$procdff$20690' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3799_DATA' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3981'. + created $dff cell `$procdff$20691' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3799_EN' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3981'. + created $dff cell `$procdff$20692' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3798_ADDR' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3970'. + created $dff cell `$procdff$20693' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3798_DATA' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3970'. + created $dff cell `$procdff$20694' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3798_EN' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3970'. + created $dff cell `$procdff$20695' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3797_ADDR' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3959'. + created $dff cell `$procdff$20696' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3797_DATA' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3959'. + created $dff cell `$procdff$20697' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3797_EN' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3959'. + created $dff cell `$procdff$20698' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3796_ADDR' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3948'. + created $dff cell `$procdff$20699' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3796_DATA' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3948'. + created $dff cell `$procdff$20700' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3796_EN' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3948'. + created $dff cell `$procdff$20701' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3795_ADDR' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3937'. + created $dff cell `$procdff$20702' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3795_DATA' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3937'. + created $dff cell `$procdff$20703' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3795_EN' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3937'. + created $dff cell `$procdff$20704' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3794_ADDR' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3926'. + created $dff cell `$procdff$20705' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3794_DATA' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3926'. + created $dff cell `$procdff$20706' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3794_EN' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3926'. + created $dff cell `$procdff$20707' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3793_ADDR' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3915'. + created $dff cell `$procdff$20708' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3793_DATA' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3915'. + created $dff cell `$procdff$20709' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3793_EN' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3915'. + created $dff cell `$procdff$20710' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3792_ADDR' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3904'. + created $dff cell `$procdff$20711' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3792_DATA' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3904'. + created $dff cell `$procdff$20712' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3792_EN' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3904'. + created $dff cell `$procdff$20713' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3791_ADDR' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3893'. + created $dff cell `$procdff$20714' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3791_DATA' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3893'. + created $dff cell `$procdff$20715' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3791_EN' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3893'. + created $dff cell `$procdff$20716' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3790_ADDR' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3882'. + created $dff cell `$procdff$20717' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3790_DATA' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3882'. + created $dff cell `$procdff$20718' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3790_EN' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3882'. + created $dff cell `$procdff$20719' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3789_ADDR' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3871'. + created $dff cell `$procdff$20720' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3789_DATA' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3871'. + created $dff cell `$procdff$20721' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3789_EN' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3871'. + created $dff cell `$procdff$20722' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3788_ADDR' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3860'. + created $dff cell `$procdff$20723' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3788_DATA' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3860'. + created $dff cell `$procdff$20724' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3788_EN' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3860'. + created $dff cell `$procdff$20725' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3787_ADDR' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3849'. + created $dff cell `$procdff$20726' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3787_DATA' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3849'. + created $dff cell `$procdff$20727' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3787_EN' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3849'. + created $dff cell `$procdff$20728' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3786_ADDR' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3838'. + created $dff cell `$procdff$20729' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3786_DATA' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3838'. + created $dff cell `$procdff$20730' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3786_EN' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3838'. + created $dff cell `$procdff$20731' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3785_ADDR' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3827'. + created $dff cell `$procdff$20732' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3785_DATA' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3827'. + created $dff cell `$procdff$20733' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3785_EN' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3827'. + created $dff cell `$procdff$20734' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3784_ADDR' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3816'. + created $dff cell `$procdff$20735' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3784_DATA' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3816'. + created $dff cell `$procdff$20736' with positive edge clock. +Creating register for signal `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3784_EN' using process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3816'. + created $dff cell `$procdff$20737' with positive edge clock. +Creating register for signal `$paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide.\result_ready' using process `$paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide.$proc$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:194$3771'. + created $dff cell `$procdff$20738' with positive edge clock. +Creating register for signal `$paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide.\state' using process `$paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide.$proc$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:194$3771'. + created $dff cell `$procdff$20739' with positive edge clock. +Creating register for signal `$paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide.\act_rd_en' using process `$paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide.$proc$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:194$3771'. + created $dff cell `$procdff$20740' with positive edge clock. +Creating register for signal `$paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide.\wgt_rd_en' using process `$paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide.$proc$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:194$3771'. + created $dff cell `$procdff$20741' with positive edge clock. +Creating register for signal `$paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide.\job_done' using process `$paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide.$proc$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:194$3771'. + created $dff cell `$procdff$20742' with positive edge clock. +Creating register for signal `$paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide.\act_rd_addr' using process `$paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide.$proc$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:194$3771'. + created $dff cell `$procdff$20743' with positive edge clock. +Creating register for signal `$paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide.\wgt_rd_addr' using process `$paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide.$proc$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:194$3771'. + created $dff cell `$procdff$20744' with positive edge clock. +Creating register for signal `$paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide.\job_active_reg' using process `$paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide.$proc$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:194$3771'. + created $dff cell `$procdff$20745' with positive edge clock. +Creating register for signal `$paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide.\x_base_reg' using process `$paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide.$proc$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:194$3771'. + created $dff cell `$procdff$20746' with positive edge clock. +Creating register for signal `$paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide.\w_base_reg' using process `$paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide.$proc$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:194$3771'. + created $dff cell `$procdff$20747' with positive edge clock. +Creating register for signal `$paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide.\result_addr_reg' using process `$paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide.$proc$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:194$3771'. + created $dff cell `$procdff$20748' with positive edge clock. +Creating register for signal `$paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide.\n_tiles_reg' using process `$paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide.$proc$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:194$3771'. + created $dff cell `$procdff$20749' with positive edge clock. +Creating register for signal `$paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide.\tile_idx' using process `$paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide.$proc$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:194$3771'. + created $dff cell `$procdff$20750' with positive edge clock. +Creating register for signal `$paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide.\rd_ptr' using process `$paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide.$proc$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:194$3771'. + created $dff cell `$procdff$20751' with positive edge clock. +Creating register for signal `$paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide.\wr_mem_req' using process `$paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide.$proc$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:194$3771'. + created $dff cell `$procdff$20752' with positive edge clock. +Creating register for signal `$paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide.\wr_mem_addr' using process `$paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide.$proc$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:194$3771'. + created $dff cell `$procdff$20753' with positive edge clock. +Creating register for signal `$paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide.\wr_mem_wdata' using process `$paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide.$proc$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:194$3771'. + created $dff cell `$procdff$20754' with positive edge clock. +Creating register for signal `$paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide.\wr_mem_lb_n' using process `$paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide.$proc$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:194$3771'. + created $dff cell `$procdff$20755' with positive edge clock. +Creating register for signal `$paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide.\wr_mem_ub_n' using process `$paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide.$proc$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:194$3771'. + created $dff cell `$procdff$20756' with positive edge clock. +Creating register for signal `$paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide.\rd_pending' using process `$paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide.$proc$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:194$3771'. + created $dff cell `$procdff$20757' with positive edge clock. +Creating register for signal `$paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide.\rd_pending_tile' using process `$paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide.$proc$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:194$3771'. + created $dff cell `$procdff$20758' with positive edge clock. +Creating register for signal `$paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide.\rd_pending_last' using process `$paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide.$proc$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:194$3771'. + created $dff cell `$procdff$20759' with positive edge clock. +Creating register for signal `$paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide.\buf_valid' using process `$paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide.$proc$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:194$3771'. + created $dff cell `$procdff$20760' with positive edge clock. +Creating register for signal `$paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide.\buf_input' using process `$paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide.$proc$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:194$3771'. + created $dff cell `$procdff$20761' with positive edge clock. +Creating register for signal `$paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide.\buf_weight' using process `$paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide.$proc$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:194$3771'. + created $dff cell `$procdff$20762' with positive edge clock. +Creating register for signal `$paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide.\buf_last' using process `$paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide.$proc$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:194$3771'. + created $dff cell `$procdff$20763' with positive edge clock. + +19.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +19.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$3757'. +Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$3756'. +Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$3755'. +Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$3754'. +Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$3753'. +Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$3752'. +Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$3751'. +Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$3750'. +Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$3748'. +Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$3746'. +Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$3744'. +Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$3742'. +Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$3740'. +Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$3738'. +Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$3736'. +Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$3734'. +Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:196$3732'. +Found and cleaned up 1 empty switch in `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$3731'. +Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$3731'. +Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:196$3729'. +Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:196$3727'. +Found and cleaned up 1 empty switch in `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$3726'. +Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$3726'. +Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:192$3724'. +Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:192$3722'. +Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:192$3720'. +Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:192$3718'. +Found and cleaned up 1 empty switch in `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$3717'. +Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$3717'. +Found and cleaned up 6 empty switches in `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:305$3712'. +Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:305$3712'. +Found and cleaned up 2 empty switches in `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:278$3702'. +Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:278$3702'. +Found and cleaned up 1 empty switch in `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:245$3689'. +Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:245$3689'. +Found and cleaned up 3 empty switches in `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:215$3686'. +Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:215$3686'. +Found and cleaned up 1 empty switch in `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$3685'. +Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$3685'. +Found and cleaned up 2 empty switches in `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$3680'. +Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$3680'. +Found and cleaned up 14 empty switches in `$paramod$8ec81e5664842acf17791930d1f62ccccc9cf0b8\slot_mem_arbiter.$proc$hardware/v2/rtl/slot_mem_arbiter.v:115$7147'. +Removing empty process `$paramod$8ec81e5664842acf17791930d1f62ccccc9cf0b8\slot_mem_arbiter.$proc$hardware/v2/rtl/slot_mem_arbiter.v:115$7147'. +Found and cleaned up 5 empty switches in `$paramod$8ec81e5664842acf17791930d1f62ccccc9cf0b8\slot_mem_arbiter.$proc$hardware/v2/rtl/slot_mem_arbiter.v:102$7145'. +Removing empty process `$paramod$8ec81e5664842acf17791930d1f62ccccc9cf0b8\slot_mem_arbiter.$proc$hardware/v2/rtl/slot_mem_arbiter.v:102$7145'. +Found and cleaned up 8 empty switches in `$paramod$13018cccabdf3dac026b50531aeca2ed1853451d\slot_mem_arbiter.$proc$hardware/v2/rtl/slot_mem_arbiter.v:115$7113'. +Removing empty process `$paramod$13018cccabdf3dac026b50531aeca2ed1853451d\slot_mem_arbiter.$proc$hardware/v2/rtl/slot_mem_arbiter.v:115$7113'. +Found and cleaned up 2 empty switches in `$paramod$13018cccabdf3dac026b50531aeca2ed1853451d\slot_mem_arbiter.$proc$hardware/v2/rtl/slot_mem_arbiter.v:102$7111'. +Removing empty process `$paramod$13018cccabdf3dac026b50531aeca2ed1853451d\slot_mem_arbiter.$proc$hardware/v2/rtl/slot_mem_arbiter.v:102$7111'. +Found and cleaned up 12 empty switches in `$paramod$8ef509dd8065f2599f8ea3948e2930abb5d7b7b0\slot_mem_arbiter_wide.$proc$hardware/v2/rtl/slot_mem_arbiter_wide.v:116$7075'. +Removing empty process `$paramod$8ef509dd8065f2599f8ea3948e2930abb5d7b7b0\slot_mem_arbiter_wide.$proc$hardware/v2/rtl/slot_mem_arbiter_wide.v:116$7075'. +Found and cleaned up 4 empty switches in `$paramod$8ef509dd8065f2599f8ea3948e2930abb5d7b7b0\slot_mem_arbiter_wide.$proc$hardware/v2/rtl/slot_mem_arbiter_wide.v:103$7073'. +Removing empty process `$paramod$8ef509dd8065f2599f8ea3948e2930abb5d7b7b0\slot_mem_arbiter_wide.$proc$hardware/v2/rtl/slot_mem_arbiter_wide.v:103$7073'. +Found and cleaned up 12 empty switches in `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$proc$hardware/v2/nms/rtl/sdram_unified_backend.v:200$6968'. +Removing empty process `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$proc$hardware/v2/nms/rtl/sdram_unified_backend.v:200$6968'. +Found and cleaned up 4 empty switches in `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$proc$hardware/v2/nms/rtl/sdram_unified_backend.v:115$6942'. +Removing empty process `$paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend.$proc$hardware/v2/nms/rtl/sdram_unified_backend.v:115$6942'. +Found and cleaned up 18 empty switches in `$paramod$d1bf252c98cb2b8284c90cfb859e00756f939daa\sdram_controller.$proc$hardware/v2/nms/rtl/sdram_controller.v:196$7417'. +Removing empty process `$paramod$d1bf252c98cb2b8284c90cfb859e00756f939daa\sdram_controller.$proc$hardware/v2/nms/rtl/sdram_controller.v:196$7417'. +Found and cleaned up 5 empty switches in `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:82$6839'. +Removing empty process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:82$6839'. +Found and cleaned up 6 empty switches in `$paramod$a83886fe79b03d603caba252b5389bc5341a5c19\weight_prefetch_engine_wide.$proc$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:108$6796'. +Removing empty process `$paramod$a83886fe79b03d603caba252b5389bc5341a5c19\weight_prefetch_engine_wide.$proc$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:108$6796'. +Found and cleaned up 149 empty switches in `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. +Removing empty process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:116$4677'. +Found and cleaned up 16 empty switches in `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:103$4644'. +Removing empty process `$paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager.$proc$hardware/v2/rtl/dependency_manager.v:103$4644'. +Removing empty process `reset_sync.$proc$hardware/v2/rtl/reset_sync.v:27$2673'. +Found and cleaned up 3 empty switches in `$paramod$5eff1de9335b9030234048498b6a1d64bf783cb3\nms_dataflow_core_sdram.$proc$hardware/v2/nms/rtl/nms_dataflow_core_sdram.v:281$7317'. +Removing empty process `$paramod$5eff1de9335b9030234048498b6a1d64bf783cb3\nms_dataflow_core_sdram.$proc$hardware/v2/nms/rtl/nms_dataflow_core_sdram.v:281$7317'. +Found and cleaned up 3 empty switches in `$paramod$5eff1de9335b9030234048498b6a1d64bf783cb3\nms_dataflow_core_sdram.$proc$hardware/v2/nms/rtl/nms_dataflow_core_sdram.v:281$7314'. +Removing empty process `$paramod$5eff1de9335b9030234048498b6a1d64bf783cb3\nms_dataflow_core_sdram.$proc$hardware/v2/nms/rtl/nms_dataflow_core_sdram.v:281$7314'. +Found and cleaned up 3 empty switches in `$paramod$5eff1de9335b9030234048498b6a1d64bf783cb3\nms_dataflow_core_sdram.$proc$hardware/v2/nms/rtl/nms_dataflow_core_sdram.v:281$7311'. +Removing empty process `$paramod$5eff1de9335b9030234048498b6a1d64bf783cb3\nms_dataflow_core_sdram.$proc$hardware/v2/nms/rtl/nms_dataflow_core_sdram.v:281$7311'. +Found and cleaned up 3 empty switches in `$paramod$5eff1de9335b9030234048498b6a1d64bf783cb3\nms_dataflow_core_sdram.$proc$hardware/v2/nms/rtl/nms_dataflow_core_sdram.v:281$7308'. +Removing empty process `$paramod$5eff1de9335b9030234048498b6a1d64bf783cb3\nms_dataflow_core_sdram.$proc$hardware/v2/nms/rtl/nms_dataflow_core_sdram.v:281$7308'. +Found and cleaned up 21 empty switches in `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.$proc$hardware/v2/rtl/spi_host_bridge.v:259$7345'. +Removing empty process `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.$proc$hardware/v2/rtl/spi_host_bridge.v:259$7345'. +Found and cleaned up 2 empty switches in `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.$proc$hardware/v2/rtl/spi_host_bridge.v:250$7338'. +Removing empty process `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.$proc$hardware/v2/rtl/spi_host_bridge.v:250$7338'. +Found and cleaned up 6 empty switches in `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.$proc$hardware/v2/rtl/spi_host_bridge.v:192$7331'. +Removing empty process `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.$proc$hardware/v2/rtl/spi_host_bridge.v:192$7331'. +Found and cleaned up 1 empty switch in `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.$proc$hardware/v2/rtl/spi_host_bridge.v:132$7320'. +Removing empty process `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.$proc$hardware/v2/rtl/spi_host_bridge.v:132$7320'. +Found and cleaned up 1 empty switch in `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.$proc$hardware/v2/rtl/spi_host_bridge.v:118$7319'. +Removing empty process `$paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge.$proc$hardware/v2/rtl/spi_host_bridge.v:118$7319'. +Found and cleaned up 6 empty switches in `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:138$4283'. +Removing empty process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:138$4283'. +Found and cleaned up 4 empty switches in `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:131$4275'. +Removing empty process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:131$4275'. +Found and cleaned up 4 empty switches in `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:117$4274'. +Removing empty process `$paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director.$proc$hardware/v2/rtl/neural_director.v:117$4274'. +Found and cleaned up 1 empty switch in `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$proc$hardware/v2/nms/rtl/nms_activation_replicated.v:42$4246'. +Removing empty process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$proc$hardware/v2/nms/rtl/nms_activation_replicated.v:42$4246'. +Found and cleaned up 1 empty switch in `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$proc$hardware/v2/nms/rtl/nms_activation_replicated.v:42$4235'. +Removing empty process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$proc$hardware/v2/nms/rtl/nms_activation_replicated.v:42$4235'. +Found and cleaned up 1 empty switch in `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$proc$hardware/v2/nms/rtl/nms_activation_replicated.v:42$4224'. +Removing empty process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$proc$hardware/v2/nms/rtl/nms_activation_replicated.v:42$4224'. +Found and cleaned up 1 empty switch in `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$proc$hardware/v2/nms/rtl/nms_activation_replicated.v:42$4213'. +Removing empty process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated.$proc$hardware/v2/nms/rtl/nms_activation_replicated.v:42$4213'. +Found and cleaned up 1 empty switch in `$paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3.$proc$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:116$4207'. +Removing empty process `$paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3.$proc$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:116$4207'. +Found and cleaned up 1 empty switch in `$paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3.$proc$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:116$4203'. +Removing empty process `$paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3.$proc$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:116$4203'. +Found and cleaned up 1 empty switch in `$paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3.$proc$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:116$4199'. +Removing empty process `$paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3.$proc$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:116$4199'. +Found and cleaned up 1 empty switch in `$paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3.$proc$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:116$4195'. +Removing empty process `$paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3.$proc$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:116$4195'. +Found and cleaned up 6 empty switches in `$paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3.$proc$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:164$4175'. +Removing empty process `$paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3.$proc$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:164$4175'. +Found and cleaned up 1 empty switch in `$paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3.$proc$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:132$4174'. +Removing empty process `$paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3.$proc$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:132$4174'. +Found and cleaned up 4 empty switches in `$paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3.$proc$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:126$4169'. +Removing empty process `$paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3.$proc$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:126$4169'. +Found and cleaned up 4 empty switches in `$paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3.$proc$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:76$4168'. +Removing empty process `$paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3.$proc$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:76$4168'. +Found and cleaned up 1 empty switch in `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4157'. +Removing empty process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4157'. +Found and cleaned up 1 empty switch in `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4146'. +Removing empty process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4146'. +Found and cleaned up 1 empty switch in `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4135'. +Removing empty process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4135'. +Found and cleaned up 1 empty switch in `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4124'. +Removing empty process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4124'. +Found and cleaned up 1 empty switch in `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4113'. +Removing empty process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4113'. +Found and cleaned up 1 empty switch in `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4102'. +Removing empty process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4102'. +Found and cleaned up 1 empty switch in `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4091'. +Removing empty process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4091'. +Found and cleaned up 1 empty switch in `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4080'. +Removing empty process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4080'. +Found and cleaned up 1 empty switch in `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4069'. +Removing empty process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4069'. +Found and cleaned up 1 empty switch in `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4058'. +Removing empty process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4058'. +Found and cleaned up 1 empty switch in `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4047'. +Removing empty process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4047'. +Found and cleaned up 1 empty switch in `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4036'. +Removing empty process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4036'. +Found and cleaned up 1 empty switch in `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4025'. +Removing empty process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4025'. +Found and cleaned up 1 empty switch in `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4014'. +Removing empty process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4014'. +Found and cleaned up 1 empty switch in `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4003'. +Removing empty process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$4003'. +Found and cleaned up 1 empty switch in `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3992'. +Removing empty process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3992'. +Found and cleaned up 1 empty switch in `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3981'. +Removing empty process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3981'. +Found and cleaned up 1 empty switch in `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3970'. +Removing empty process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3970'. +Found and cleaned up 1 empty switch in `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3959'. +Removing empty process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3959'. +Found and cleaned up 1 empty switch in `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3948'. +Removing empty process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3948'. +Found and cleaned up 1 empty switch in `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3937'. +Removing empty process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3937'. +Found and cleaned up 1 empty switch in `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3926'. +Removing empty process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3926'. +Found and cleaned up 1 empty switch in `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3915'. +Removing empty process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3915'. +Found and cleaned up 1 empty switch in `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3904'. +Removing empty process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3904'. +Found and cleaned up 1 empty switch in `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3893'. +Removing empty process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3893'. +Found and cleaned up 1 empty switch in `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3882'. +Removing empty process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3882'. +Found and cleaned up 1 empty switch in `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3871'. +Removing empty process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3871'. +Found and cleaned up 1 empty switch in `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3860'. +Removing empty process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3860'. +Found and cleaned up 1 empty switch in `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3849'. +Removing empty process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3849'. +Found and cleaned up 1 empty switch in `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3838'. +Removing empty process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3838'. +Found and cleaned up 1 empty switch in `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3827'. +Removing empty process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3827'. +Found and cleaned up 1 empty switch in `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3816'. +Removing empty process `$paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:39$3816'. +Found and cleaned up 10 empty switches in `$paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide.$proc$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:194$3771'. +Removing empty process `$paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide.$proc$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:194$3771'. +Cleaned up 395 empty switches. + +19.4.12. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor. + +Optimizing module fpga_neural_v2_top. +Optimizing module $paramod$8ec81e5664842acf17791930d1f62ccccc9cf0b8\slot_mem_arbiter. + +Optimizing module $paramod$13018cccabdf3dac026b50531aeca2ed1853451d\slot_mem_arbiter. + +Optimizing module $paramod$8ef509dd8065f2599f8ea3948e2930abb5d7b7b0\slot_mem_arbiter_wide. + +Optimizing module $paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend. + +Optimizing module $paramod$d1bf252c98cb2b8284c90cfb859e00756f939daa\sdram_controller. + +Optimizing module $paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine. + +Optimizing module $paramod$a83886fe79b03d603caba252b5389bc5341a5c19\weight_prefetch_engine_wide. + +Optimizing module $paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager. + +Optimizing module reset_sync. + +Optimizing module ecp5_pll_sys_clk. +Optimizing module $paramod$5eff1de9335b9030234048498b6a1d64bf783cb3\nms_dataflow_core_sdram. +Optimizing module $paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge. + +Optimizing module $paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director. + +Optimizing module $paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated. +Optimizing module $paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3. + +Optimizing module $paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed. +Optimizing module $paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide. + + +19.5. Executing CHECK pass (checking for obvious problems). +Checking module $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor... +Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [31]: + port Q[31] of cell $procdff$20083 ($dff) + port Q[31] of cell $procdff$20070 ($dff) +Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [30]: + port Q[30] of cell $procdff$20083 ($dff) + port Q[30] of cell $procdff$20070 ($dff) +Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [29]: + port Q[29] of cell $procdff$20083 ($dff) + port Q[29] of cell $procdff$20070 ($dff) +Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [28]: + port Q[28] of cell $procdff$20083 ($dff) + port Q[28] of cell $procdff$20070 ($dff) +Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [27]: + port Q[27] of cell $procdff$20083 ($dff) + port Q[27] of cell $procdff$20070 ($dff) +Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [26]: + port Q[26] of cell $procdff$20083 ($dff) + port Q[26] of cell $procdff$20070 ($dff) +Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [25]: + port Q[25] of cell $procdff$20083 ($dff) + port Q[25] of cell $procdff$20070 ($dff) +Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [24]: + port Q[24] of cell $procdff$20083 ($dff) + port Q[24] of cell $procdff$20070 ($dff) +Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [23]: + port Q[23] of cell $procdff$20083 ($dff) + port Q[23] of cell $procdff$20070 ($dff) +Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [22]: + port Q[22] of cell $procdff$20083 ($dff) + port Q[22] of cell $procdff$20070 ($dff) +Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [21]: + port Q[21] of cell $procdff$20083 ($dff) + port Q[21] of cell $procdff$20070 ($dff) +Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [20]: + port Q[20] of cell $procdff$20083 ($dff) + port Q[20] of cell $procdff$20070 ($dff) +Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [19]: + port Q[19] of cell $procdff$20083 ($dff) + port Q[19] of cell $procdff$20070 ($dff) +Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [18]: + port Q[18] of cell $procdff$20083 ($dff) + port Q[18] of cell $procdff$20070 ($dff) +Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [17]: + port Q[17] of cell $procdff$20083 ($dff) + port Q[17] of cell $procdff$20070 ($dff) +Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [16]: + port Q[16] of cell $procdff$20083 ($dff) + port Q[16] of cell $procdff$20070 ($dff) +Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [15]: + port Q[15] of cell $procdff$20083 ($dff) + port Q[15] of cell $procdff$20070 ($dff) +Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [14]: + port Q[14] of cell $procdff$20083 ($dff) + port Q[14] of cell $procdff$20070 ($dff) +Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [13]: + port Q[13] of cell $procdff$20083 ($dff) + port Q[13] of cell $procdff$20070 ($dff) +Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [12]: + port Q[12] of cell $procdff$20083 ($dff) + port Q[12] of cell $procdff$20070 ($dff) +Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [11]: + port Q[11] of cell $procdff$20083 ($dff) + port Q[11] of cell $procdff$20070 ($dff) +Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [10]: + port Q[10] of cell $procdff$20083 ($dff) + port Q[10] of cell $procdff$20070 ($dff) +Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [9]: + port Q[9] of cell $procdff$20083 ($dff) + port Q[9] of cell $procdff$20070 ($dff) +Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [8]: + port Q[8] of cell $procdff$20083 ($dff) + port Q[8] of cell $procdff$20070 ($dff) +Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [7]: + port Q[7] of cell $procdff$20083 ($dff) + port Q[7] of cell $procdff$20070 ($dff) +Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [6]: + port Q[6] of cell $procdff$20083 ($dff) + port Q[6] of cell $procdff$20070 ($dff) +Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [5]: + port Q[5] of cell $procdff$20083 ($dff) + port Q[5] of cell $procdff$20070 ($dff) +Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [4]: + port Q[4] of cell $procdff$20083 ($dff) + port Q[4] of cell $procdff$20070 ($dff) +Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [3]: + port Q[3] of cell $procdff$20083 ($dff) + port Q[3] of cell $procdff$20070 ($dff) +Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [2]: + port Q[2] of cell $procdff$20083 ($dff) + port Q[2] of cell $procdff$20070 ($dff) +Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [1]: + port Q[1] of cell $procdff$20083 ($dff) + port Q[1] of cell $procdff$20070 ($dff) +Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [0]: + port Q[0] of cell $procdff$20083 ($dff) + port Q[0] of cell $procdff$20070 ($dff) +Checking module fpga_neural_v2_top... +Checking module $paramod$8ec81e5664842acf17791930d1f62ccccc9cf0b8\slot_mem_arbiter... +Checking module $paramod$13018cccabdf3dac026b50531aeca2ed1853451d\slot_mem_arbiter... +Checking module $paramod$8ef509dd8065f2599f8ea3948e2930abb5d7b7b0\slot_mem_arbiter_wide... +Checking module $paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend... +Checking module $paramod$d1bf252c98cb2b8284c90cfb859e00756f939daa\sdram_controller... +Checking module $paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine... +Checking module $paramod$a83886fe79b03d603caba252b5389bc5341a5c19\weight_prefetch_engine_wide... +Checking module $paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager... +Checking module reset_sync... +Checking module ecp5_pll_sys_clk... +Checking module $paramod$5eff1de9335b9030234048498b6a1d64bf783cb3\nms_dataflow_core_sdram... +Checking module $paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge... +Checking module $paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director... +Checking module $paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated... +Checking module $paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3... +Checking module $paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed... +Checking module $paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide... +Found and reported 32 problems. + +19.6. Executing FLATTEN pass (flatten design). +Deleting now unused module $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor. +Deleting now unused module $paramod$8ec81e5664842acf17791930d1f62ccccc9cf0b8\slot_mem_arbiter. +Deleting now unused module $paramod$13018cccabdf3dac026b50531aeca2ed1853451d\slot_mem_arbiter. +Deleting now unused module $paramod$8ef509dd8065f2599f8ea3948e2930abb5d7b7b0\slot_mem_arbiter_wide. +Deleting now unused module $paramod$af7e8776671c0b0c6599ccc377f866917bf4bc16\sdram_unified_backend. +Deleting now unused module $paramod$d1bf252c98cb2b8284c90cfb859e00756f939daa\sdram_controller. +Deleting now unused module $paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine. +Deleting now unused module $paramod$a83886fe79b03d603caba252b5389bc5341a5c19\weight_prefetch_engine_wide. +Deleting now unused module $paramod$ebc8d58b17cd65fc71126a46baec4de95ef0327b\dependency_manager. +Deleting now unused module reset_sync. +Deleting now unused module ecp5_pll_sys_clk. +Deleting now unused module $paramod$5eff1de9335b9030234048498b6a1d64bf783cb3\nms_dataflow_core_sdram. +Deleting now unused module $paramod$4782e0d3d6eb7cc81046b85118d3a22f8e9e9a62\spi_host_bridge. +Deleting now unused module $paramod$97f0d57663bedcc06ca700dc61528c90ee913395\neural_director. +Deleting now unused module $paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_activation_replicated. +Deleting now unused module $paramod$cb31cf5ee5dc6c0703facb962c769b7c89554668\nms_activation_fill_ctrl_v3. +Deleting now unused module $paramod$bc03d0b13e512c4f96743320e28b429af13c6c8e\nms_weight_packed. +Deleting now unused module $paramod$4188adb81b560d669b896bdf53af1e3ae5c5ab00\nms_memory_manager_stream_wide. + + +19.7. Executing TRIBUF pass. + +19.8. Executing DEMINOUT pass (demote inout ports to input or output). + +19.9. Executing OPT_EXPR pass (perform const folding). +Optimizing module fpga_neural_v2_top. + + +19.10. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \fpga_neural_v2_top.. +Removed 879 unused cells and 8342 unused wires. + + +19.11. Executing CHECK pass (checking for obvious problems). +Checking module fpga_neural_v2_top... +Found and reported 0 problems. + +19.12. Executing OPT pass (performing simple optimizations). + +19.12.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module fpga_neural_v2_top. + +19.12.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\fpga_neural_v2_top'. +Computing hashes of 7296 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. +Computing hashes of 6595 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. +Computing hashes of 6450 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. +Computing hashes of 6399 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. +Computing hashes of 6397 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. + +Removed a total of 899 cells. + +19.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \fpga_neural_v2_top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Replacing known input bits on port A of cell $flatten\u_dataflow_core.\u_act_fill.$procmux$19388: \u_dataflow_core.u_act_fill.state -> 1'0 + Replacing known input bits on port A of cell $flatten\u_dataflow_core.\u_act_fill.$procmux$19386: \u_dataflow_core.u_act_fill.state -> 1'1 + Replacing known input bits on port A of cell $flatten\u_dataflow_core.\u_act_fill.$procmux$19390: \u_dataflow_core.u_act_fill.state -> 1'0 + Analyzing evaluation results. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17159. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17153. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17147. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17141. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17135. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17129. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17123. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17117. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17111. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17105. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17099. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17093. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17087. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17081. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17075. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17069. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17063. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17057. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17051. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17045. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17039. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17033. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17027. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17021. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17015. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17009. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17003. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16997. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16991. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16979. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16973. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16967. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16961. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16955. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16949. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16943. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16937. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16931. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16925. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16919. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16913. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16907. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16901. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16895. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16889. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16883. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16877. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16871. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16865. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16859. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16853. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16847. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16841. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16835. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16829. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16823. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16817. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16811. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16805. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16799. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16793. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16787. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16781. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16775. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16769. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16763. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16757. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16751. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16745. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16739. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16733. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16727. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16721. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16715. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16709. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16703. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16697. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16691. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16685. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16679. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16673. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16667. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16661. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16655. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16649. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16643. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16637. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16631. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16625. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16619. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16613. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16607. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16601. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16595. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16589. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16583. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16577. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16571. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16565. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16559. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16553. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16547. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16541. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16535. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16529. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16523. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16517. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16511. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16505. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16499. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16493. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16487. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16481. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16475. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16469. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16463. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16457. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16451. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16445. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16439. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16433. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16427. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16421. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16415. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16409. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16403. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16397. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16391. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16385. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16379. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16373. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16367. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16361. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16355. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16349. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16343. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16337. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16331. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16325. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16319. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16313. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16307. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16301. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16295. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16289. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16283. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16277. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16271. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16265. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16259. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16253. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16247. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16241. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16235. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16229. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16223. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16217. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16211. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16205. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16199. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16193. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16187. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16181. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16175. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16169. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16163. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16157. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16151. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16145. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16139. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16133. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16127. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16121. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16115. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16109. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16103. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16097. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16091. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16085. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16079. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16073. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16067. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16061. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16055. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16049. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16043. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16037. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16031. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16025. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16019. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16013. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16007. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16001. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15995. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15989. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15983. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15977. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15971. + dead port 1/2 on $mux $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15965. + dead port 1/2 on $mux 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dead port 1/2 on $mux $flatten\u_sdram_backend.$procmux$9134. + dead port 2/2 on $mux $flatten\u_sdram_backend.$procmux$9131. + dead port 1/2 on $mux $flatten\u_sdram_backend.$procmux$9123. + dead port 2/2 on $mux $flatten\u_sdram_backend.$procmux$9120. + dead port 1/2 on $mux $flatten\u_sdram_backend.$procmux$9112. + dead port 2/2 on $mux $flatten\u_sdram_backend.$procmux$9109. + dead port 1/2 on $mux $flatten\u_sdram_backend.$procmux$9101. + dead port 2/2 on $mux $flatten\u_sdram_backend.$procmux$9098. + dead port 1/2 on $mux $flatten\u_sdram_backend.$procmux$9090. + dead port 2/2 on $mux $flatten\u_sdram_backend.$procmux$9087. + dead port 1/2 on $mux $flatten\u_sdram_backend.$procmux$9079. + dead port 2/2 on $mux $flatten\u_sdram_backend.$procmux$9076. + dead port 1/2 on $mux $flatten\u_sdram_backend.$procmux$9068. + dead port 2/2 on $mux $flatten\u_sdram_backend.$procmux$9065. + dead port 1/2 on $mux $flatten\u_sdram_backend.$procmux$9057. + dead port 2/2 on $mux $flatten\u_sdram_backend.$procmux$9054. + dead port 1/2 on $mux $flatten\u_sdram_backend.$procmux$9046. + dead port 2/2 on $mux $flatten\u_sdram_backend.$procmux$9043. + dead port 1/2 on $mux $flatten\u_sdram_backend.$procmux$9035. + dead port 2/2 on $mux $flatten\u_sdram_backend.$procmux$9032. + dead port 1/2 on $mux $flatten\u_host_arb.$procmux$8258. + dead port 1/2 on $mux $flatten\u_sdram_backend.$procmux$8865. + dead port 1/2 on $mux $flatten\u_sdram_backend.$procmux$9024. + dead port 2/2 on $mux $flatten\u_sdram_backend.$procmux$9021. + dead port 1/2 on $mux $flatten\u_sdram_backend.$procmux$9013. + dead port 2/2 on $mux $flatten\u_sdram_backend.$procmux$9010. + dead port 1/2 on $mux $flatten\u_sdram_backend.$procmux$9002. + dead port 2/2 on $mux $flatten\u_sdram_backend.$procmux$8999. + dead port 1/2 on $mux $flatten\u_sdram_backend.$procmux$8991. + dead port 2/2 on $mux $flatten\u_sdram_backend.$procmux$8988. + dead port 2/2 on $mux $flatten\u_sdram_backend.$procmux$8986. + dead port 1/2 on $mux $flatten\u_sdram_backend.$procmux$8977. + dead port 2/2 on $mux $flatten\u_sdram_backend.$procmux$8974. + dead port 2/2 on $mux $flatten\u_sdram_backend.$procmux$8972. + dead port 1/2 on $mux $flatten\u_sdram_backend.$procmux$8963. + dead port 2/2 on $mux $flatten\u_sdram_backend.$procmux$8960. + dead port 2/2 on $mux $flatten\u_sdram_backend.$procmux$8958. + dead port 1/2 on $mux $flatten\u_sdram_backend.$procmux$8949. + dead port 2/2 on $mux $flatten\u_sdram_backend.$procmux$8946. + dead port 1/2 on $mux $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$9701. + dead port 2/2 on $mux $flatten\u_sdram_backend.$procmux$8944. + dead port 1/2 on $mux $flatten\u_sdram_backend.$procmux$8935. + dead port 2/2 on $mux $flatten\u_sdram_backend.$procmux$8932. + dead port 2/2 on $mux $flatten\u_sdram_backend.$procmux$8930. + dead port 1/2 on $mux $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$9710. + dead port 1/2 on $mux $flatten\u_sdram_backend.$procmux$8921. + dead port 2/2 on $mux $flatten\u_sdram_backend.$procmux$8918. + dead port 2/2 on $mux $flatten\u_sdram_backend.$procmux$8916. + dead port 1/2 on $mux $flatten\u_sdram_backend.$procmux$8907. + dead port 2/2 on $mux $flatten\u_sdram_backend.$procmux$8904. + dead port 2/2 on $mux $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$9719. + dead port 2/2 on $mux $flatten\u_sdram_backend.$procmux$8902. + dead port 1/2 on $mux $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$9722. + dead port 1/2 on $mux $flatten\u_sdram_backend.$procmux$8893. + dead port 2/2 on $mux $flatten\u_sdram_backend.$procmux$8890. + dead port 2/2 on $mux $flatten\u_sdram_backend.$procmux$8888. + dead port 1/2 on $mux $flatten\u_sdram_backend.$procmux$8879. + dead port 2/2 on $mux $flatten\u_sdram_backend.$procmux$8876. + dead port 1/2 on $mux $flatten\u_spi_bridge.$procmux$18866. + dead port 2/2 on $mux $flatten\u_sdram_backend.$procmux$8874. +Removed 1565 multiplexer ports. + + +19.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \fpga_neural_v2_top. + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13081: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13081_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13081_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13081_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13081_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13081_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13067: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13067_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13067_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13067_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13067_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15175: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15175_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15175_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15175_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15175_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15175_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15161: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15161_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15161_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15161_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15161_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13030: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13030_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13030_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13030_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13030_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13030_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13016: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13016_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13016_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13016_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13016_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12979: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12979_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12979_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12979_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12979_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12979_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12965: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12965_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12965_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12965_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12965_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12928: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12928_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12928_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12928_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12928_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12928_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12914: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12914_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12914_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12914_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12914_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15007: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15007_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15007_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15007_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15007_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15007_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14993: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14993_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14993_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14993_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14993_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_sdram_backend.$procmux$8830: + Old ports: A=23'00000000000000000000000, B=23'11111111111111111111111, Y=$flatten\u_sdram_backend.$procmux$8830_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_sdram_backend.$procmux$8830_Y [0] + New connections: $flatten\u_sdram_backend.$procmux$8830_Y [22:1] = { $flatten\u_sdram_backend.$procmux$8830_Y [0] $flatten\u_sdram_backend.$procmux$8830_Y [0] $flatten\u_sdram_backend.$procmux$8830_Y [0] $flatten\u_sdram_backend.$procmux$8830_Y [0] $flatten\u_sdram_backend.$procmux$8830_Y [0] $flatten\u_sdram_backend.$procmux$8830_Y [0] $flatten\u_sdram_backend.$procmux$8830_Y [0] $flatten\u_sdram_backend.$procmux$8830_Y [0] $flatten\u_sdram_backend.$procmux$8830_Y [0] $flatten\u_sdram_backend.$procmux$8830_Y [0] $flatten\u_sdram_backend.$procmux$8830_Y [0] $flatten\u_sdram_backend.$procmux$8830_Y [0] $flatten\u_sdram_backend.$procmux$8830_Y [0] $flatten\u_sdram_backend.$procmux$8830_Y [0] $flatten\u_sdram_backend.$procmux$8830_Y [0] $flatten\u_sdram_backend.$procmux$8830_Y [0] $flatten\u_sdram_backend.$procmux$8830_Y [0] $flatten\u_sdram_backend.$procmux$8830_Y [0] $flatten\u_sdram_backend.$procmux$8830_Y [0] $flatten\u_sdram_backend.$procmux$8830_Y [0] $flatten\u_sdram_backend.$procmux$8830_Y [0] $flatten\u_sdram_backend.$procmux$8830_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12760: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12760_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12760_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12760_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12760_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12760_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14956: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14956_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14956_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14956_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14956_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14956_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12746: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12746_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12746_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12746_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12746_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14942: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14942_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14942_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14942_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14942_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12709: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12709_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12709_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12709_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12709_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12709_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12695: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12695_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12695_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12695_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12695_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14905: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14905_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14905_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14905_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14905_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14905_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14891: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14891_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14891_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14891_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14891_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12658: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12658_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12658_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12658_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12658_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12658_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12644: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12644_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12644_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12644_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12644_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14854: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14854_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14854_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14854_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14854_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14854_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12607: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12607_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12607_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12607_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12607_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12607_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14840: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14840_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14840_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14840_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14840_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12593: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12593_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12593_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12593_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12593_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12439: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12439_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12439_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12439_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12439_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12439_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12425: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12425_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12425_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12425_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12425_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12388: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12388_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12388_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12388_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12388_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12388_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14686: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14686_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14686_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14686_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14686_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14686_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12374: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12374_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12374_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12374_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12374_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14672: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14672_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14672_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14672_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14672_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12337: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12337_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12337_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12337_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12337_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12337_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12323: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12323_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12323_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12323_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12323_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14635: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14635_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14635_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14635_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14635_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14635_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14621: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14621_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14621_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14621_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14621_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12286: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12286_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12286_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12286_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12286_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12286_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12272: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12272_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12272_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12272_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12272_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14584: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14584_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14584_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14584_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14584_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14584_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14570: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14570_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14570_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14570_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14570_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14533: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14533_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14533_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14533_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14533_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14533_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14519: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14519_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14519_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14519_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14519_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17306: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4454_EN[1:0]$4678 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4454_EN[1:0]$4678 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4454_EN[1:0]$4678 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4454_EN[1:0]$4678 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12118: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12118_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12118_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12118_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12118_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12118_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17303: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4455_EN[2:0]$4679 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4455_EN[2:0]$4679 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4455_EN[2:0]$4679 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4455_EN[2:0]$4679 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4455_EN[2:0]$4679 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17300: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4456_EN[2:0]$4680 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4456_EN[2:0]$4680 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4456_EN[2:0]$4680 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4456_EN[2:0]$4680 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4456_EN[2:0]$4680 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12104: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12104_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12104_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12104_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12104_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17297: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4457_EN[1:0]$4681 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4457_EN[1:0]$4681 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4457_EN[1:0]$4681 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4457_EN[1:0]$4681 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17294: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4458_EN[2:0]$4682 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4458_EN[2:0]$4682 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4458_EN[2:0]$4682 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4458_EN[2:0]$4682 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4458_EN[2:0]$4682 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17291: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4459_EN[2:0]$4683 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4459_EN[2:0]$4683 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4459_EN[2:0]$4683 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4459_EN[2:0]$4683 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4459_EN[2:0]$4683 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12067: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12067_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12067_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12067_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12067_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12067_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17288: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4460_EN[1:0]$4684 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4460_EN[1:0]$4684 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4460_EN[1:0]$4684 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4460_EN[1:0]$4684 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12053: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12053_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12053_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12053_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12053_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17285: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4461_EN[2:0]$4685 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4461_EN[2:0]$4685 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4461_EN[2:0]$4685 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4461_EN[2:0]$4685 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4461_EN[2:0]$4685 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17282: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4462_EN[2:0]$4686 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4462_EN[2:0]$4686 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4462_EN[2:0]$4686 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4462_EN[2:0]$4686 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4462_EN[2:0]$4686 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17279: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4463_EN[1:0]$4687 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4463_EN[1:0]$4687 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4463_EN[1:0]$4687 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4463_EN[1:0]$4687 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12016: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12016_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12016_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12016_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12016_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12016_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17276: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4464_EN[2:0]$4688 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4464_EN[2:0]$4688 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4464_EN[2:0]$4688 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4464_EN[2:0]$4688 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4464_EN[2:0]$4688 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12002: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12002_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12002_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12002_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12002_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17273: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4465_EN[2:0]$4689 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4465_EN[2:0]$4689 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4465_EN[2:0]$4689 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4465_EN[2:0]$4689 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4465_EN[2:0]$4689 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17270: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4466_EN[1:0]$4690 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4466_EN[1:0]$4690 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4466_EN[1:0]$4690 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4466_EN[1:0]$4690 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17267: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4467_EN[2:0]$4691 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4467_EN[2:0]$4691 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4467_EN[2:0]$4691 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4467_EN[2:0]$4691 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4467_EN[2:0]$4691 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11965: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11965_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11965_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11965_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11965_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11965_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17264: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4468_EN[2:0]$4692 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4468_EN[2:0]$4692 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4468_EN[2:0]$4692 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4468_EN[2:0]$4692 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4468_EN[2:0]$4692 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11951: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11951_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11951_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11951_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11951_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17261: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4469_EN[1:0]$4693 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4469_EN[1:0]$4693 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4469_EN[1:0]$4693 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4469_EN[1:0]$4693 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17258: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4470_EN[2:0]$4694 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4470_EN[2:0]$4694 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4470_EN[2:0]$4694 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4470_EN[2:0]$4694 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4470_EN[2:0]$4694 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14365: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14365_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14365_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14365_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14365_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14365_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17255: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4471_EN[2:0]$4695 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4471_EN[2:0]$4695 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4471_EN[2:0]$4695 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4471_EN[2:0]$4695 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4471_EN[2:0]$4695 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17252: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4472_EN[1:0]$4696 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4472_EN[1:0]$4696 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4472_EN[1:0]$4696 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4472_EN[1:0]$4696 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14351: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14351_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14351_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14351_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14351_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17249: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4473_EN[2:0]$4697 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4473_EN[2:0]$4697 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4473_EN[2:0]$4697 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4473_EN[2:0]$4697 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4473_EN[2:0]$4697 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17246: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4474_EN[2:0]$4698 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4474_EN[2:0]$4698 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4474_EN[2:0]$4698 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4474_EN[2:0]$4698 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4474_EN[2:0]$4698 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17243: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4475_EN[1:0]$4699 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4475_EN[1:0]$4699 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4475_EN[1:0]$4699 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4475_EN[1:0]$4699 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17240: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4476_EN[2:0]$4700 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4476_EN[2:0]$4700 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4476_EN[2:0]$4700 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4476_EN[2:0]$4700 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4476_EN[2:0]$4700 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14314: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14314_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14314_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14314_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14314_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14314_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17237: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4477_EN[2:0]$4701 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4477_EN[2:0]$4701 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4477_EN[2:0]$4701 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4477_EN[2:0]$4701 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4477_EN[2:0]$4701 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17234: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4478_EN[1:0]$4702 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4478_EN[1:0]$4702 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4478_EN[1:0]$4702 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4478_EN[1:0]$4702 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14300: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14300_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14300_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14300_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14300_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17231: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4479_EN[2:0]$4703 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4479_EN[2:0]$4703 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4479_EN[2:0]$4703 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4479_EN[2:0]$4703 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4479_EN[2:0]$4703 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17228: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4480_EN[2:0]$4704 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4480_EN[2:0]$4704 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4480_EN[2:0]$4704 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4480_EN[2:0]$4704 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4480_EN[2:0]$4704 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17225: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4481_EN[1:0]$4705 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4481_EN[1:0]$4705 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4481_EN[1:0]$4705 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4481_EN[1:0]$4705 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11797: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11797_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11797_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11797_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11797_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11797_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17222: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4482_EN[2:0]$4706 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4482_EN[2:0]$4706 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4482_EN[2:0]$4706 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4482_EN[2:0]$4706 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4482_EN[2:0]$4706 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11783: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11783_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11783_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11783_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11783_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17219: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4483_EN[2:0]$4707 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4483_EN[2:0]$4707 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4483_EN[2:0]$4707 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4483_EN[2:0]$4707 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4483_EN[2:0]$4707 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14263: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14263_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14263_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14263_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14263_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14263_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17216: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4484_EN[1:0]$4708 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4484_EN[1:0]$4708 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4484_EN[1:0]$4708 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4484_EN[1:0]$4708 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17213: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4485_EN[2:0]$4709 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4485_EN[2:0]$4709 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4485_EN[2:0]$4709 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4485_EN[2:0]$4709 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4485_EN[2:0]$4709 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14249: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14249_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14249_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14249_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14249_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17210: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4486_EN[2:0]$4710 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4486_EN[2:0]$4710 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4486_EN[2:0]$4710 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4486_EN[2:0]$4710 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4486_EN[2:0]$4710 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11746: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11746_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11746_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11746_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11746_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11746_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17207: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4487_EN[1:0]$4711 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4487_EN[1:0]$4711 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4487_EN[1:0]$4711 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4487_EN[1:0]$4711 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11732: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11732_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11732_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11732_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11732_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17204: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4488_EN[2:0]$4712 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4488_EN[2:0]$4712 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4488_EN[2:0]$4712 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4488_EN[2:0]$4712 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4488_EN[2:0]$4712 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17201: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4489_EN[2:0]$4713 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4489_EN[2:0]$4713 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4489_EN[2:0]$4713 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4489_EN[2:0]$4713 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4489_EN[2:0]$4713 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14212: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14212_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14212_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14212_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14212_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14212_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17198: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4490_EN[1:0]$4714 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4490_EN[1:0]$4714 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4490_EN[1:0]$4714 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4490_EN[1:0]$4714 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17195: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4491_EN[2:0]$4715 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4491_EN[2:0]$4715 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4491_EN[2:0]$4715 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4491_EN[2:0]$4715 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4491_EN[2:0]$4715 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11695: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11695_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11695_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11695_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11695_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11695_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14198: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14198_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14198_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14198_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14198_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17192: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4492_EN[2:0]$4716 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4492_EN[2:0]$4716 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4492_EN[2:0]$4716 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4492_EN[2:0]$4716 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4492_EN[2:0]$4716 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11681: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11681_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11681_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11681_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11681_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17189: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4493_EN[1:0]$4717 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4493_EN[1:0]$4717 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4493_EN[1:0]$4717 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4493_EN[1:0]$4717 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17186: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4494_EN[2:0]$4718 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4494_EN[2:0]$4718 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4494_EN[2:0]$4718 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4494_EN[2:0]$4718 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4494_EN[2:0]$4718 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17183: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4495_EN[2:0]$4719 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4495_EN[2:0]$4719 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4495_EN[2:0]$4719 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4495_EN[2:0]$4719 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4495_EN[2:0]$4719 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11644: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11644_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11644_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11644_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11644_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11644_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17180: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4496_EN[1:0]$4720 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4496_EN[1:0]$4720 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4496_EN[1:0]$4720 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4496_EN[1:0]$4720 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11630: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11630_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11630_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11630_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11630_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17177: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4497_EN[2:0]$4721 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4497_EN[2:0]$4721 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4497_EN[2:0]$4721 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4497_EN[2:0]$4721 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4497_EN[2:0]$4721 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17174: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4498_EN[2:0]$4722 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4498_EN[2:0]$4722 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4498_EN[2:0]$4722 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4498_EN[2:0]$4722 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4498_EN[2:0]$4722 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17171: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4499_EN[1:0]$4723 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4499_EN[1:0]$4723 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4499_EN[1:0]$4723 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:119$4499_EN[1:0]$4723 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17168: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4500_EN[2:0]$4724 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4500_EN[2:0]$4724 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4500_EN[2:0]$4724 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4500_EN[2:0]$4724 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:120$4500_EN[2:0]$4724 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17165: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4501_EN[2:0]$4725 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4501_EN[2:0]$4725 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4501_EN[2:0]$4725 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4501_EN[2:0]$4725 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:121$4501_EN[2:0]$4725 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11476: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11476_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11476_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11476_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11476_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11476_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14044: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14044_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14044_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14044_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14044_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14044_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11462: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11462_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11462_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11462_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11462_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17144: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$17144_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$17144_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17144_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17144_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17144_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14030: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14030_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14030_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14030_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14030_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11425: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11425_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11425_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11425_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11425_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11425_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17132: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$17132_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$17132_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17132_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17132_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17132_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11411: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11411_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11411_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11411_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11411_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13993: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13993_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13993_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13993_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13993_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13993_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13979: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13979_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13979_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13979_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13979_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11374: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11374_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11374_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11374_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11374_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11374_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11360: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11360_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11360_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11360_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11360_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17114: + Old ports: A=23'00000000000000000000000, B=23'11111111111111111111111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$17114_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$17114_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17114_Y [22:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17114_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17114_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17114_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17114_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17114_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17114_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17114_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17114_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17114_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17114_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17114_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17114_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17114_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17114_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17114_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17114_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17114_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17114_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17114_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17114_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17114_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17114_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13942: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13942_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13942_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13942_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13942_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13942_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11323: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11323_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11323_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11323_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11323_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11323_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13928: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13928_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13928_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13928_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13928_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11309: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11309_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11309_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11309_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11309_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17096: + Old ports: A=23'00000000000000000000000, B=23'11111111111111111111111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$17096_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$17096_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17096_Y [22:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17096_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17096_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17096_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17096_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17096_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17096_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17096_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17096_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17096_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17096_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17096_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17096_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17096_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17096_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17096_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17096_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17096_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17096_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17096_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17096_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17096_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17096_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13891: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13891_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13891_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13891_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13891_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13891_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17078: + Old ports: A=16'0000000000000000, B=16'1111111111111111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$17078_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$17078_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17078_Y [15:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17078_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17078_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17078_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17078_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17078_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17078_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17078_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17078_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17078_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17078_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17078_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17078_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17078_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17078_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17078_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13877: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13877_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13877_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13877_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13877_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17060: + Old ports: A=23'00000000000000000000000, B=23'11111111111111111111111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$17060_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$17060_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17060_Y [22:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17060_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17060_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17060_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17060_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17060_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17060_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17060_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17060_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17060_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17060_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17060_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17060_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17060_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17060_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17060_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17060_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17060_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17060_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17060_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17060_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17060_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17060_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11155: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11155_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11155_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11155_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11155_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11155_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11141: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11141_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11141_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11141_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11141_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17042: + Old ports: A=4'0000, B=4'1111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$17042_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$17042_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17042_Y [3:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17042_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17042_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17042_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11104: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11104_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11104_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11104_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11104_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11104_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11090: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11090_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11090_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11090_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11090_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11053: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11053_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11053_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11053_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11053_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11053_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17024: + Old ports: A=4'0000, B=4'1111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$17024_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$17024_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17024_Y [3:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17024_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17024_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17024_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11039: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11039_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11039_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11039_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11039_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15649: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15649_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15649_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15649_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15649_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15649_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13723: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13723_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13723_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13723_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13723_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13723_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17006: + Old ports: A=4'0000, B=4'1111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$17006_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$17006_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17006_Y [3:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17006_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17006_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17006_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13709: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13709_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13709_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13709_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13709_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11002: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11002_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11002_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11002_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11002_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11002_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15635: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15635_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15635_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15635_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15635_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10988: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$10988_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$10988_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10988_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10988_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16988: + Old ports: A=4'0000, B=4'1111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16988_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16988_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16988_Y [3:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16988_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16988_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16988_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13672: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13672_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13672_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13672_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13672_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13672_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15598: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15598_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15598_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15598_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15598_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15598_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13658: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13658_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13658_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13658_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13658_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16964: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16964_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16964_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16964_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16964_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15584: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15584_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15584_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15584_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15584_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13621: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13621_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13621_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13621_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13621_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13621_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13607: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13607_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13607_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13607_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13607_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10834: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$10834_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$10834_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10834_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10834_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10834_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15547: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15547_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15547_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15547_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15547_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15547_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10820: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$10820_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$10820_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10820_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10820_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15533: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15533_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15533_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15533_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15533_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13570: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13570_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13570_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13570_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13570_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13570_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10783: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$10783_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$10783_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10783_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10783_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10783_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13556: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13556_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13556_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13556_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13556_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10769: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$10769_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$10769_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10769_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10769_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15496: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15496_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15496_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15496_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15496_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15496_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10732: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$10732_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$10732_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10732_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10732_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10732_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10718: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$10718_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$10718_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10718_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10718_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15482: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15482_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15482_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15482_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15482_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10681: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$10681_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$10681_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10681_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10681_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10681_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10667: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$10667_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$10667_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10667_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10667_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10652: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$10652_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$10652_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10652_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10652_Y [0] + New ctrl vector for $pmux cell $flatten\u_dataflow_core.\u_director.$procmux$19256: { $flatten\u_dataflow_core.\u_director.$procmux$19257_CMP $auto$opt_reduce.cc:137:opt_pmux$21028 $flatten\u_dataflow_core.\u_director.$procmux$19261_CMP } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_director.$procmux$19123: + Old ports: A=23'00000000000000000000000, B=23'11111111111111111111111, Y=$flatten\u_dataflow_core.\u_director.$procmux$19123_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_director.$procmux$19123_Y [0] + New connections: $flatten\u_dataflow_core.\u_director.$procmux$19123_Y [22:1] = { $flatten\u_dataflow_core.\u_director.$procmux$19123_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19123_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19123_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19123_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19123_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19123_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19123_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19123_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19123_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19123_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19123_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19123_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19123_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19123_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19123_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19123_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19123_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19123_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19123_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19123_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19123_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19123_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_director.$procmux$19105: + Old ports: A=23'00000000000000000000000, B=23'11111111111111111111111, Y=$flatten\u_dataflow_core.\u_director.$procmux$19105_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_director.$procmux$19105_Y [0] + New connections: $flatten\u_dataflow_core.\u_director.$procmux$19105_Y [22:1] = { $flatten\u_dataflow_core.\u_director.$procmux$19105_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19105_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19105_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19105_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19105_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19105_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19105_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19105_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19105_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19105_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19105_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19105_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19105_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19105_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19105_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19105_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19105_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19105_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19105_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19105_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19105_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19105_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_director.$procmux$19087: + Old ports: A=16'0000000000000000, B=16'1111111111111111, Y=$flatten\u_dataflow_core.\u_director.$procmux$19087_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_director.$procmux$19087_Y [0] + New connections: $flatten\u_dataflow_core.\u_director.$procmux$19087_Y [15:1] = { $flatten\u_dataflow_core.\u_director.$procmux$19087_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19087_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19087_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19087_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19087_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19087_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19087_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19087_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19087_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19087_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19087_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19087_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19087_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19087_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19087_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_director.$procmux$19069: + Old ports: A=23'00000000000000000000000, B=23'11111111111111111111111, Y=$flatten\u_dataflow_core.\u_director.$procmux$19069_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_director.$procmux$19069_Y [0] + New connections: $flatten\u_dataflow_core.\u_director.$procmux$19069_Y [22:1] = { $flatten\u_dataflow_core.\u_director.$procmux$19069_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19069_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19069_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19069_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19069_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19069_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19069_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19069_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19069_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19069_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19069_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19069_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19069_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19069_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19069_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19069_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19069_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19069_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19069_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19069_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19069_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19069_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13402: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13402_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13402_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13402_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13402_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13402_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_director.$procmux$19051: + Old ports: A=16'0000000000000000, B=16'1111111111111111, Y=$flatten\u_dataflow_core.\u_director.$procmux$19051_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_director.$procmux$19051_Y [0] + New connections: $flatten\u_dataflow_core.\u_director.$procmux$19051_Y [15:1] = { $flatten\u_dataflow_core.\u_director.$procmux$19051_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19051_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19051_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19051_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19051_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19051_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19051_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19051_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19051_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19051_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19051_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19051_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19051_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19051_Y [0] $flatten\u_dataflow_core.\u_director.$procmux$19051_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13388: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13388_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13388_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13388_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13388_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_act_mem.$procmux$19323: + Old ports: A=64'0000000000000000000000000000000000000000000000000000000000000000, B=64'1111111111111111111111111111111111111111111111111111111111111111, Y=$flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_EN[63:0]$4216 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_EN[63:0]$4216 [0] + New connections: $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_EN[63:0]$4216 [63:1] = { $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_EN[63:0]$4216 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_EN[63:0]$4216 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_EN[63:0]$4216 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_EN[63:0]$4216 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_EN[63:0]$4216 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_EN[63:0]$4216 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_EN[63:0]$4216 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_EN[63:0]$4216 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_EN[63:0]$4216 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_EN[63:0]$4216 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_EN[63:0]$4216 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_EN[63:0]$4216 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_EN[63:0]$4216 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_EN[63:0]$4216 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_EN[63:0]$4216 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_EN[63:0]$4216 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_EN[63:0]$4216 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_EN[63:0]$4216 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_EN[63:0]$4216 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_EN[63:0]$4216 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_EN[63:0]$4216 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_EN[63:0]$4216 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_EN[63:0]$4216 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_EN[63:0]$4216 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_EN[63:0]$4216 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_EN[63:0]$4216 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_EN[63:0]$4216 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_EN[63:0]$4216 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_EN[63:0]$4216 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_EN[63:0]$4216 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_EN[63:0]$4216 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_EN[63:0]$4216 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_EN[63:0]$4216 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_EN[63:0]$4216 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_EN[63:0]$4216 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_EN[63:0]$4216 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_EN[63:0]$4216 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_EN[63:0]$4216 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_EN[63:0]$4216 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_EN[63:0]$4216 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_EN[63:0]$4216 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_EN[63:0]$4216 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_EN[63:0]$4216 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_EN[63:0]$4216 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_EN[63:0]$4216 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_EN[63:0]$4216 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_EN[63:0]$4216 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_EN[63:0]$4216 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_EN[63:0]$4216 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_EN[63:0]$4216 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_EN[63:0]$4216 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_EN[63:0]$4216 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_EN[63:0]$4216 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_EN[63:0]$4216 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_EN[63:0]$4216 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_EN[63:0]$4216 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_EN[63:0]$4216 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_EN[63:0]$4216 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_EN[63:0]$4216 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_EN[63:0]$4216 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_EN[63:0]$4216 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_EN[63:0]$4216 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4209_EN[63:0]$4216 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_act_mem.$procmux$19314: + Old ports: A=64'0000000000000000000000000000000000000000000000000000000000000000, B=64'1111111111111111111111111111111111111111111111111111111111111111, Y=$flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_EN[63:0]$4227 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_EN[63:0]$4227 [0] + New connections: $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_EN[63:0]$4227 [63:1] = { $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_EN[63:0]$4227 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_EN[63:0]$4227 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_EN[63:0]$4227 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_EN[63:0]$4227 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_EN[63:0]$4227 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_EN[63:0]$4227 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_EN[63:0]$4227 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_EN[63:0]$4227 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_EN[63:0]$4227 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_EN[63:0]$4227 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_EN[63:0]$4227 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_EN[63:0]$4227 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_EN[63:0]$4227 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_EN[63:0]$4227 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_EN[63:0]$4227 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_EN[63:0]$4227 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_EN[63:0]$4227 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_EN[63:0]$4227 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_EN[63:0]$4227 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_EN[63:0]$4227 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_EN[63:0]$4227 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_EN[63:0]$4227 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_EN[63:0]$4227 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_EN[63:0]$4227 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_EN[63:0]$4227 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_EN[63:0]$4227 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_EN[63:0]$4227 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_EN[63:0]$4227 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_EN[63:0]$4227 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_EN[63:0]$4227 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_EN[63:0]$4227 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_EN[63:0]$4227 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_EN[63:0]$4227 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_EN[63:0]$4227 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_EN[63:0]$4227 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_EN[63:0]$4227 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_EN[63:0]$4227 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_EN[63:0]$4227 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_EN[63:0]$4227 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_EN[63:0]$4227 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_EN[63:0]$4227 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_EN[63:0]$4227 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_EN[63:0]$4227 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_EN[63:0]$4227 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_EN[63:0]$4227 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_EN[63:0]$4227 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_EN[63:0]$4227 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_EN[63:0]$4227 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_EN[63:0]$4227 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_EN[63:0]$4227 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_EN[63:0]$4227 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_EN[63:0]$4227 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_EN[63:0]$4227 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_EN[63:0]$4227 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_EN[63:0]$4227 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_EN[63:0]$4227 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_EN[63:0]$4227 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_EN[63:0]$4227 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_EN[63:0]$4227 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_EN[63:0]$4227 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_EN[63:0]$4227 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_EN[63:0]$4227 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4210_EN[63:0]$4227 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_act_mem.$procmux$19305: + Old ports: A=64'0000000000000000000000000000000000000000000000000000000000000000, B=64'1111111111111111111111111111111111111111111111111111111111111111, Y=$flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_EN[63:0]$4238 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_EN[63:0]$4238 [0] + New connections: $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_EN[63:0]$4238 [63:1] = { $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_EN[63:0]$4238 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_EN[63:0]$4238 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_EN[63:0]$4238 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_EN[63:0]$4238 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_EN[63:0]$4238 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_EN[63:0]$4238 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_EN[63:0]$4238 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_EN[63:0]$4238 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_EN[63:0]$4238 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_EN[63:0]$4238 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_EN[63:0]$4238 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_EN[63:0]$4238 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_EN[63:0]$4238 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_EN[63:0]$4238 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_EN[63:0]$4238 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_EN[63:0]$4238 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_EN[63:0]$4238 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_EN[63:0]$4238 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_EN[63:0]$4238 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_EN[63:0]$4238 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_EN[63:0]$4238 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_EN[63:0]$4238 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_EN[63:0]$4238 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_EN[63:0]$4238 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_EN[63:0]$4238 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_EN[63:0]$4238 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_EN[63:0]$4238 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_EN[63:0]$4238 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_EN[63:0]$4238 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_EN[63:0]$4238 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_EN[63:0]$4238 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_EN[63:0]$4238 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_EN[63:0]$4238 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_EN[63:0]$4238 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_EN[63:0]$4238 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_EN[63:0]$4238 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_EN[63:0]$4238 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_EN[63:0]$4238 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_EN[63:0]$4238 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_EN[63:0]$4238 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_EN[63:0]$4238 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_EN[63:0]$4238 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_EN[63:0]$4238 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_EN[63:0]$4238 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_EN[63:0]$4238 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_EN[63:0]$4238 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_EN[63:0]$4238 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_EN[63:0]$4238 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_EN[63:0]$4238 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_EN[63:0]$4238 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_EN[63:0]$4238 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_EN[63:0]$4238 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_EN[63:0]$4238 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_EN[63:0]$4238 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_EN[63:0]$4238 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_EN[63:0]$4238 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_EN[63:0]$4238 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_EN[63:0]$4238 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_EN[63:0]$4238 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_EN[63:0]$4238 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_EN[63:0]$4238 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_EN[63:0]$4238 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4211_EN[63:0]$4238 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_act_mem.$procmux$19296: + Old ports: A=64'0000000000000000000000000000000000000000000000000000000000000000, B=64'1111111111111111111111111111111111111111111111111111111111111111, Y=$flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_EN[63:0]$4249 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_EN[63:0]$4249 [0] + New connections: $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_EN[63:0]$4249 [63:1] = { $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_EN[63:0]$4249 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_EN[63:0]$4249 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_EN[63:0]$4249 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_EN[63:0]$4249 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_EN[63:0]$4249 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_EN[63:0]$4249 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_EN[63:0]$4249 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_EN[63:0]$4249 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_EN[63:0]$4249 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_EN[63:0]$4249 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_EN[63:0]$4249 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_EN[63:0]$4249 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_EN[63:0]$4249 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_EN[63:0]$4249 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_EN[63:0]$4249 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_EN[63:0]$4249 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_EN[63:0]$4249 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_EN[63:0]$4249 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_EN[63:0]$4249 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_EN[63:0]$4249 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_EN[63:0]$4249 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_EN[63:0]$4249 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_EN[63:0]$4249 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_EN[63:0]$4249 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_EN[63:0]$4249 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_EN[63:0]$4249 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_EN[63:0]$4249 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_EN[63:0]$4249 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_EN[63:0]$4249 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_EN[63:0]$4249 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_EN[63:0]$4249 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_EN[63:0]$4249 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_EN[63:0]$4249 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_EN[63:0]$4249 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_EN[63:0]$4249 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_EN[63:0]$4249 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_EN[63:0]$4249 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_EN[63:0]$4249 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_EN[63:0]$4249 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_EN[63:0]$4249 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_EN[63:0]$4249 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_EN[63:0]$4249 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_EN[63:0]$4249 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_EN[63:0]$4249 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_EN[63:0]$4249 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_EN[63:0]$4249 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_EN[63:0]$4249 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_EN[63:0]$4249 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_EN[63:0]$4249 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_EN[63:0]$4249 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_EN[63:0]$4249 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_EN[63:0]$4249 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_EN[63:0]$4249 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_EN[63:0]$4249 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_EN[63:0]$4249 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_EN[63:0]$4249 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_EN[63:0]$4249 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_EN[63:0]$4249 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_EN[63:0]$4249 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_EN[63:0]$4249 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_EN[63:0]$4249 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_EN[63:0]$4249 [0] $flatten\u_dataflow_core.\u_act_mem.$0$memwr$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:44$4212_EN[63:0]$4249 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_wgt_mem.$procmux$19715: + Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3784_EN[7:0]$3819 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3784_EN[7:0]$3819 [0] + New connections: $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3784_EN[7:0]$3819 [7:1] = { $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3784_EN[7:0]$3819 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3784_EN[7:0]$3819 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3784_EN[7:0]$3819 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3784_EN[7:0]$3819 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3784_EN[7:0]$3819 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3784_EN[7:0]$3819 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3784_EN[7:0]$3819 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_wgt_mem.$procmux$19706: + Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3785_EN[7:0]$3830 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3785_EN[7:0]$3830 [0] + New connections: $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3785_EN[7:0]$3830 [7:1] = { $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3785_EN[7:0]$3830 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3785_EN[7:0]$3830 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3785_EN[7:0]$3830 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3785_EN[7:0]$3830 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3785_EN[7:0]$3830 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3785_EN[7:0]$3830 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3785_EN[7:0]$3830 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_wgt_mem.$procmux$19697: + Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3786_EN[7:0]$3841 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3786_EN[7:0]$3841 [0] + New connections: $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3786_EN[7:0]$3841 [7:1] = { $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3786_EN[7:0]$3841 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3786_EN[7:0]$3841 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3786_EN[7:0]$3841 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3786_EN[7:0]$3841 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3786_EN[7:0]$3841 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3786_EN[7:0]$3841 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3786_EN[7:0]$3841 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_wgt_mem.$procmux$19688: + Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3787_EN[7:0]$3852 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3787_EN[7:0]$3852 [0] + New connections: $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3787_EN[7:0]$3852 [7:1] = { $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3787_EN[7:0]$3852 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3787_EN[7:0]$3852 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3787_EN[7:0]$3852 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3787_EN[7:0]$3852 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3787_EN[7:0]$3852 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3787_EN[7:0]$3852 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3787_EN[7:0]$3852 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_wgt_mem.$procmux$19679: + Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3788_EN[7:0]$3863 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3788_EN[7:0]$3863 [0] + New connections: $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3788_EN[7:0]$3863 [7:1] = { $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3788_EN[7:0]$3863 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3788_EN[7:0]$3863 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3788_EN[7:0]$3863 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3788_EN[7:0]$3863 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3788_EN[7:0]$3863 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3788_EN[7:0]$3863 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3788_EN[7:0]$3863 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_wgt_mem.$procmux$19670: + Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3789_EN[7:0]$3874 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3789_EN[7:0]$3874 [0] + New connections: $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3789_EN[7:0]$3874 [7:1] = { $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3789_EN[7:0]$3874 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3789_EN[7:0]$3874 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3789_EN[7:0]$3874 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3789_EN[7:0]$3874 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3789_EN[7:0]$3874 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3789_EN[7:0]$3874 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3789_EN[7:0]$3874 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_wgt_mem.$procmux$19661: + Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3790_EN[7:0]$3885 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3790_EN[7:0]$3885 [0] + New connections: $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3790_EN[7:0]$3885 [7:1] = { $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3790_EN[7:0]$3885 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3790_EN[7:0]$3885 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3790_EN[7:0]$3885 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3790_EN[7:0]$3885 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3790_EN[7:0]$3885 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3790_EN[7:0]$3885 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3790_EN[7:0]$3885 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_wgt_mem.$procmux$19652: + Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3791_EN[7:0]$3896 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3791_EN[7:0]$3896 [0] + New connections: $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3791_EN[7:0]$3896 [7:1] = { $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3791_EN[7:0]$3896 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3791_EN[7:0]$3896 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3791_EN[7:0]$3896 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3791_EN[7:0]$3896 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3791_EN[7:0]$3896 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3791_EN[7:0]$3896 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[0].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3791_EN[7:0]$3896 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_wgt_mem.$procmux$19643: + Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3792_EN[7:0]$3907 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3792_EN[7:0]$3907 [0] + New connections: $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3792_EN[7:0]$3907 [7:1] = { $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3792_EN[7:0]$3907 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3792_EN[7:0]$3907 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3792_EN[7:0]$3907 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3792_EN[7:0]$3907 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3792_EN[7:0]$3907 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3792_EN[7:0]$3907 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3792_EN[7:0]$3907 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_wgt_mem.$procmux$19634: + Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3793_EN[7:0]$3918 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3793_EN[7:0]$3918 [0] + New connections: $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3793_EN[7:0]$3918 [7:1] = { $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3793_EN[7:0]$3918 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3793_EN[7:0]$3918 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3793_EN[7:0]$3918 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3793_EN[7:0]$3918 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3793_EN[7:0]$3918 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3793_EN[7:0]$3918 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3793_EN[7:0]$3918 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_wgt_mem.$procmux$19625: + Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3794_EN[7:0]$3929 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3794_EN[7:0]$3929 [0] + New connections: $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3794_EN[7:0]$3929 [7:1] = { $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3794_EN[7:0]$3929 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3794_EN[7:0]$3929 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3794_EN[7:0]$3929 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3794_EN[7:0]$3929 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3794_EN[7:0]$3929 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3794_EN[7:0]$3929 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3794_EN[7:0]$3929 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_wgt_mem.$procmux$19616: + Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3795_EN[7:0]$3940 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3795_EN[7:0]$3940 [0] + New connections: $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3795_EN[7:0]$3940 [7:1] = { $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3795_EN[7:0]$3940 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3795_EN[7:0]$3940 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3795_EN[7:0]$3940 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3795_EN[7:0]$3940 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3795_EN[7:0]$3940 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3795_EN[7:0]$3940 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3795_EN[7:0]$3940 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_wgt_mem.$procmux$19607: + Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3796_EN[7:0]$3951 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3796_EN[7:0]$3951 [0] + New connections: $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3796_EN[7:0]$3951 [7:1] = { $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3796_EN[7:0]$3951 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3796_EN[7:0]$3951 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3796_EN[7:0]$3951 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3796_EN[7:0]$3951 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3796_EN[7:0]$3951 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3796_EN[7:0]$3951 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3796_EN[7:0]$3951 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_wgt_mem.$procmux$19598: + Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3797_EN[7:0]$3962 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3797_EN[7:0]$3962 [0] + New connections: $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3797_EN[7:0]$3962 [7:1] = { $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3797_EN[7:0]$3962 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3797_EN[7:0]$3962 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3797_EN[7:0]$3962 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3797_EN[7:0]$3962 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3797_EN[7:0]$3962 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3797_EN[7:0]$3962 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3797_EN[7:0]$3962 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_wgt_mem.$procmux$19589: + Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3798_EN[7:0]$3973 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3798_EN[7:0]$3973 [0] + New connections: $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3798_EN[7:0]$3973 [7:1] = { $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3798_EN[7:0]$3973 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3798_EN[7:0]$3973 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3798_EN[7:0]$3973 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3798_EN[7:0]$3973 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3798_EN[7:0]$3973 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3798_EN[7:0]$3973 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3798_EN[7:0]$3973 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_wgt_mem.$procmux$19580: + Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3799_EN[7:0]$3984 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3799_EN[7:0]$3984 [0] + New connections: $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3799_EN[7:0]$3984 [7:1] = { $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3799_EN[7:0]$3984 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3799_EN[7:0]$3984 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3799_EN[7:0]$3984 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3799_EN[7:0]$3984 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3799_EN[7:0]$3984 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3799_EN[7:0]$3984 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[1].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3799_EN[7:0]$3984 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_wgt_mem.$procmux$19571: + Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3800_EN[7:0]$3995 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3800_EN[7:0]$3995 [0] + New connections: $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3800_EN[7:0]$3995 [7:1] = { $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3800_EN[7:0]$3995 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3800_EN[7:0]$3995 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3800_EN[7:0]$3995 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3800_EN[7:0]$3995 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3800_EN[7:0]$3995 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3800_EN[7:0]$3995 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3800_EN[7:0]$3995 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_wgt_mem.$procmux$19562: + Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3801_EN[7:0]$4006 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3801_EN[7:0]$4006 [0] + New connections: $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3801_EN[7:0]$4006 [7:1] = { $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3801_EN[7:0]$4006 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3801_EN[7:0]$4006 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3801_EN[7:0]$4006 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3801_EN[7:0]$4006 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3801_EN[7:0]$4006 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3801_EN[7:0]$4006 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3801_EN[7:0]$4006 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_wgt_mem.$procmux$19553: + Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3802_EN[7:0]$4017 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3802_EN[7:0]$4017 [0] + New connections: $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3802_EN[7:0]$4017 [7:1] = { $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3802_EN[7:0]$4017 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3802_EN[7:0]$4017 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3802_EN[7:0]$4017 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3802_EN[7:0]$4017 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3802_EN[7:0]$4017 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3802_EN[7:0]$4017 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3802_EN[7:0]$4017 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_wgt_mem.$procmux$19544: + Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3803_EN[7:0]$4028 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3803_EN[7:0]$4028 [0] + New connections: $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3803_EN[7:0]$4028 [7:1] = { $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3803_EN[7:0]$4028 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3803_EN[7:0]$4028 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3803_EN[7:0]$4028 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3803_EN[7:0]$4028 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3803_EN[7:0]$4028 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3803_EN[7:0]$4028 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3803_EN[7:0]$4028 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_wgt_mem.$procmux$19535: + Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3804_EN[7:0]$4039 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3804_EN[7:0]$4039 [0] + New connections: $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3804_EN[7:0]$4039 [7:1] = { $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3804_EN[7:0]$4039 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3804_EN[7:0]$4039 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3804_EN[7:0]$4039 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3804_EN[7:0]$4039 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3804_EN[7:0]$4039 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3804_EN[7:0]$4039 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3804_EN[7:0]$4039 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_wgt_mem.$procmux$19526: + Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3805_EN[7:0]$4050 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3805_EN[7:0]$4050 [0] + New connections: $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3805_EN[7:0]$4050 [7:1] = { $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3805_EN[7:0]$4050 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3805_EN[7:0]$4050 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3805_EN[7:0]$4050 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3805_EN[7:0]$4050 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3805_EN[7:0]$4050 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3805_EN[7:0]$4050 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3805_EN[7:0]$4050 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_wgt_mem.$procmux$19517: + Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3806_EN[7:0]$4061 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3806_EN[7:0]$4061 [0] + New connections: $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3806_EN[7:0]$4061 [7:1] = { $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3806_EN[7:0]$4061 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3806_EN[7:0]$4061 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3806_EN[7:0]$4061 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3806_EN[7:0]$4061 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3806_EN[7:0]$4061 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3806_EN[7:0]$4061 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3806_EN[7:0]$4061 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_wgt_mem.$procmux$19508: + Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3807_EN[7:0]$4072 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3807_EN[7:0]$4072 [0] + New connections: $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3807_EN[7:0]$4072 [7:1] = { $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3807_EN[7:0]$4072 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3807_EN[7:0]$4072 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3807_EN[7:0]$4072 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3807_EN[7:0]$4072 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3807_EN[7:0]$4072 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3807_EN[7:0]$4072 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[2].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3807_EN[7:0]$4072 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_wgt_mem.$procmux$19499: + Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3808_EN[7:0]$4083 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3808_EN[7:0]$4083 [0] + New connections: $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3808_EN[7:0]$4083 [7:1] = { $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3808_EN[7:0]$4083 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3808_EN[7:0]$4083 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3808_EN[7:0]$4083 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3808_EN[7:0]$4083 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3808_EN[7:0]$4083 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3808_EN[7:0]$4083 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3808_EN[7:0]$4083 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_wgt_mem.$procmux$19490: + Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3809_EN[7:0]$4094 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3809_EN[7:0]$4094 [0] + New connections: $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3809_EN[7:0]$4094 [7:1] = { $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3809_EN[7:0]$4094 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3809_EN[7:0]$4094 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3809_EN[7:0]$4094 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3809_EN[7:0]$4094 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3809_EN[7:0]$4094 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3809_EN[7:0]$4094 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3809_EN[7:0]$4094 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_wgt_mem.$procmux$19481: + Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3810_EN[7:0]$4105 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3810_EN[7:0]$4105 [0] + New connections: $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3810_EN[7:0]$4105 [7:1] = { $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3810_EN[7:0]$4105 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3810_EN[7:0]$4105 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3810_EN[7:0]$4105 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3810_EN[7:0]$4105 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3810_EN[7:0]$4105 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3810_EN[7:0]$4105 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3810_EN[7:0]$4105 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_wgt_mem.$procmux$19472: + Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3811_EN[7:0]$4116 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3811_EN[7:0]$4116 [0] + New connections: $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3811_EN[7:0]$4116 [7:1] = { $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3811_EN[7:0]$4116 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3811_EN[7:0]$4116 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3811_EN[7:0]$4116 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3811_EN[7:0]$4116 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3811_EN[7:0]$4116 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3811_EN[7:0]$4116 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3811_EN[7:0]$4116 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_wgt_mem.$procmux$19463: + Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3812_EN[7:0]$4127 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3812_EN[7:0]$4127 [0] + New connections: $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3812_EN[7:0]$4127 [7:1] = { $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3812_EN[7:0]$4127 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3812_EN[7:0]$4127 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3812_EN[7:0]$4127 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3812_EN[7:0]$4127 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3812_EN[7:0]$4127 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3812_EN[7:0]$4127 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3812_EN[7:0]$4127 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_wgt_mem.$procmux$19454: + Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3813_EN[7:0]$4138 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3813_EN[7:0]$4138 [0] + New connections: $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3813_EN[7:0]$4138 [7:1] = { $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3813_EN[7:0]$4138 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3813_EN[7:0]$4138 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3813_EN[7:0]$4138 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3813_EN[7:0]$4138 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3813_EN[7:0]$4138 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3813_EN[7:0]$4138 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3813_EN[7:0]$4138 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_wgt_mem.$procmux$19445: + Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3814_EN[7:0]$4149 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3814_EN[7:0]$4149 [0] + New connections: $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3814_EN[7:0]$4149 [7:1] = { $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3814_EN[7:0]$4149 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3814_EN[7:0]$4149 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3814_EN[7:0]$4149 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3814_EN[7:0]$4149 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3814_EN[7:0]$4149 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3814_EN[7:0]$4149 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3814_EN[7:0]$4149 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_wgt_mem.$procmux$19436: + Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3815_EN[7:0]$4160 + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3815_EN[7:0]$4160 [0] + New connections: $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3815_EN[7:0]$4160 [7:1] = { $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3815_EN[7:0]$4160 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3815_EN[7:0]$4160 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3815_EN[7:0]$4160 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3815_EN[7:0]$4160 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3815_EN[7:0]$4160 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3815_EN[7:0]$4160 [0] $flatten\u_dataflow_core.\u_wgt_mem.$0$memwr$\GEN_SLOT[3].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:41$3815_EN[7:0]$4160 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13351: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13351_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13351_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13351_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13351_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13351_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13337: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13337_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13337_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13337_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13337_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13300: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13300_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13300_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13300_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13300_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13300_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13286: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13286_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13286_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13286_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13286_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15328: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15328_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15328_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15328_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15328_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15328_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15314: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15314_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15314_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15314_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15314_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13249: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13249_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13249_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13249_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13249_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13249_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13235: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13235_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13235_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13235_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13235_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15277: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15277_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15277_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15277_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15277_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15277_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15263: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15263_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15263_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15263_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15263_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_sdram_backend.$procmux$8956: + Old ports: A=64'1111111111111111111111111111111111111111111111111111111111111111, B=64'0000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\u_sdram_backend.$procmux$8956_Y + New ports: A=1'1, B=1'0, Y=$flatten\u_sdram_backend.$procmux$8956_Y [0] + New connections: $flatten\u_sdram_backend.$procmux$8956_Y [63:1] = { $flatten\u_sdram_backend.$procmux$8956_Y [0] $flatten\u_sdram_backend.$procmux$8956_Y [0] $flatten\u_sdram_backend.$procmux$8956_Y [0] $flatten\u_sdram_backend.$procmux$8956_Y [0] $flatten\u_sdram_backend.$procmux$8956_Y [0] $flatten\u_sdram_backend.$procmux$8956_Y [0] $flatten\u_sdram_backend.$procmux$8956_Y [0] $flatten\u_sdram_backend.$procmux$8956_Y [0] $flatten\u_sdram_backend.$procmux$8956_Y [0] $flatten\u_sdram_backend.$procmux$8956_Y [0] $flatten\u_sdram_backend.$procmux$8956_Y [0] $flatten\u_sdram_backend.$procmux$8956_Y [0] $flatten\u_sdram_backend.$procmux$8956_Y [0] $flatten\u_sdram_backend.$procmux$8956_Y [0] $flatten\u_sdram_backend.$procmux$8956_Y [0] $flatten\u_sdram_backend.$procmux$8956_Y [0] $flatten\u_sdram_backend.$procmux$8956_Y [0] $flatten\u_sdram_backend.$procmux$8956_Y [0] $flatten\u_sdram_backend.$procmux$8956_Y [0] $flatten\u_sdram_backend.$procmux$8956_Y [0] $flatten\u_sdram_backend.$procmux$8956_Y [0] $flatten\u_sdram_backend.$procmux$8956_Y [0] $flatten\u_sdram_backend.$procmux$8956_Y [0] $flatten\u_sdram_backend.$procmux$8956_Y [0] $flatten\u_sdram_backend.$procmux$8956_Y [0] $flatten\u_sdram_backend.$procmux$8956_Y [0] $flatten\u_sdram_backend.$procmux$8956_Y [0] $flatten\u_sdram_backend.$procmux$8956_Y [0] $flatten\u_sdram_backend.$procmux$8956_Y [0] $flatten\u_sdram_backend.$procmux$8956_Y [0] $flatten\u_sdram_backend.$procmux$8956_Y [0] $flatten\u_sdram_backend.$procmux$8956_Y [0] $flatten\u_sdram_backend.$procmux$8956_Y [0] $flatten\u_sdram_backend.$procmux$8956_Y [0] $flatten\u_sdram_backend.$procmux$8956_Y [0] $flatten\u_sdram_backend.$procmux$8956_Y [0] $flatten\u_sdram_backend.$procmux$8956_Y [0] $flatten\u_sdram_backend.$procmux$8956_Y [0] $flatten\u_sdram_backend.$procmux$8956_Y [0] $flatten\u_sdram_backend.$procmux$8956_Y [0] $flatten\u_sdram_backend.$procmux$8956_Y [0] $flatten\u_sdram_backend.$procmux$8956_Y [0] $flatten\u_sdram_backend.$procmux$8956_Y [0] $flatten\u_sdram_backend.$procmux$8956_Y [0] $flatten\u_sdram_backend.$procmux$8956_Y [0] $flatten\u_sdram_backend.$procmux$8956_Y [0] $flatten\u_sdram_backend.$procmux$8956_Y [0] $flatten\u_sdram_backend.$procmux$8956_Y [0] $flatten\u_sdram_backend.$procmux$8956_Y [0] $flatten\u_sdram_backend.$procmux$8956_Y [0] $flatten\u_sdram_backend.$procmux$8956_Y [0] $flatten\u_sdram_backend.$procmux$8956_Y [0] $flatten\u_sdram_backend.$procmux$8956_Y [0] $flatten\u_sdram_backend.$procmux$8956_Y [0] $flatten\u_sdram_backend.$procmux$8956_Y [0] $flatten\u_sdram_backend.$procmux$8956_Y [0] $flatten\u_sdram_backend.$procmux$8956_Y [0] $flatten\u_sdram_backend.$procmux$8956_Y [0] $flatten\u_sdram_backend.$procmux$8956_Y [0] $flatten\u_sdram_backend.$procmux$8956_Y [0] $flatten\u_sdram_backend.$procmux$8956_Y [0] $flatten\u_sdram_backend.$procmux$8956_Y [0] $flatten\u_sdram_backend.$procmux$8956_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15226: + Old ports: A=3'000, B=3'111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15226_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15226_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15226_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15226_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15226_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_sdram_backend.$procmux$8914: + Old ports: A=23'11111111111111111111111, B=23'00000000000000000000000, Y=$flatten\u_sdram_backend.$procmux$8914_Y + New ports: A=1'1, B=1'0, Y=$flatten\u_sdram_backend.$procmux$8914_Y [0] + New connections: $flatten\u_sdram_backend.$procmux$8914_Y [22:1] = { $flatten\u_sdram_backend.$procmux$8914_Y [0] $flatten\u_sdram_backend.$procmux$8914_Y [0] $flatten\u_sdram_backend.$procmux$8914_Y [0] $flatten\u_sdram_backend.$procmux$8914_Y [0] $flatten\u_sdram_backend.$procmux$8914_Y [0] $flatten\u_sdram_backend.$procmux$8914_Y [0] $flatten\u_sdram_backend.$procmux$8914_Y [0] $flatten\u_sdram_backend.$procmux$8914_Y [0] $flatten\u_sdram_backend.$procmux$8914_Y [0] $flatten\u_sdram_backend.$procmux$8914_Y [0] $flatten\u_sdram_backend.$procmux$8914_Y [0] $flatten\u_sdram_backend.$procmux$8914_Y [0] $flatten\u_sdram_backend.$procmux$8914_Y [0] $flatten\u_sdram_backend.$procmux$8914_Y [0] $flatten\u_sdram_backend.$procmux$8914_Y [0] $flatten\u_sdram_backend.$procmux$8914_Y [0] $flatten\u_sdram_backend.$procmux$8914_Y [0] $flatten\u_sdram_backend.$procmux$8914_Y [0] $flatten\u_sdram_backend.$procmux$8914_Y [0] $flatten\u_sdram_backend.$procmux$8914_Y [0] $flatten\u_sdram_backend.$procmux$8914_Y [0] $flatten\u_sdram_backend.$procmux$8914_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15212: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15212_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15212_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15212_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15212_Y [0] + New ctrl vector for $pmux cell $flatten\u_spi_bridge.$procmux$18611: { $auto$opt_reduce.cc:137:opt_pmux$21030 $flatten\u_spi_bridge.$procmux$18614_CMP } + Consolidated identical input bits for $mux cell $flatten\u_sdram_backend.$procmux$8872: + Old ports: A=64'0000000000000000000000000000000000000000000000000000000000000000, B=64'1111111111111111111111111111111111111111111111111111111111111111, Y=$flatten\u_sdram_backend.$procmux$8872_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_sdram_backend.$procmux$8872_Y [0] + New connections: $flatten\u_sdram_backend.$procmux$8872_Y [63:1] = { $flatten\u_sdram_backend.$procmux$8872_Y [0] $flatten\u_sdram_backend.$procmux$8872_Y [0] $flatten\u_sdram_backend.$procmux$8872_Y [0] $flatten\u_sdram_backend.$procmux$8872_Y [0] $flatten\u_sdram_backend.$procmux$8872_Y [0] $flatten\u_sdram_backend.$procmux$8872_Y [0] $flatten\u_sdram_backend.$procmux$8872_Y [0] $flatten\u_sdram_backend.$procmux$8872_Y [0] $flatten\u_sdram_backend.$procmux$8872_Y [0] $flatten\u_sdram_backend.$procmux$8872_Y [0] $flatten\u_sdram_backend.$procmux$8872_Y [0] $flatten\u_sdram_backend.$procmux$8872_Y [0] $flatten\u_sdram_backend.$procmux$8872_Y [0] $flatten\u_sdram_backend.$procmux$8872_Y [0] $flatten\u_sdram_backend.$procmux$8872_Y [0] $flatten\u_sdram_backend.$procmux$8872_Y [0] $flatten\u_sdram_backend.$procmux$8872_Y [0] $flatten\u_sdram_backend.$procmux$8872_Y [0] $flatten\u_sdram_backend.$procmux$8872_Y [0] $flatten\u_sdram_backend.$procmux$8872_Y [0] $flatten\u_sdram_backend.$procmux$8872_Y [0] $flatten\u_sdram_backend.$procmux$8872_Y [0] $flatten\u_sdram_backend.$procmux$8872_Y [0] $flatten\u_sdram_backend.$procmux$8872_Y [0] $flatten\u_sdram_backend.$procmux$8872_Y [0] $flatten\u_sdram_backend.$procmux$8872_Y [0] $flatten\u_sdram_backend.$procmux$8872_Y [0] $flatten\u_sdram_backend.$procmux$8872_Y [0] $flatten\u_sdram_backend.$procmux$8872_Y [0] $flatten\u_sdram_backend.$procmux$8872_Y [0] $flatten\u_sdram_backend.$procmux$8872_Y [0] $flatten\u_sdram_backend.$procmux$8872_Y [0] $flatten\u_sdram_backend.$procmux$8872_Y [0] $flatten\u_sdram_backend.$procmux$8872_Y [0] $flatten\u_sdram_backend.$procmux$8872_Y [0] $flatten\u_sdram_backend.$procmux$8872_Y [0] $flatten\u_sdram_backend.$procmux$8872_Y [0] $flatten\u_sdram_backend.$procmux$8872_Y [0] $flatten\u_sdram_backend.$procmux$8872_Y [0] $flatten\u_sdram_backend.$procmux$8872_Y [0] $flatten\u_sdram_backend.$procmux$8872_Y [0] $flatten\u_sdram_backend.$procmux$8872_Y [0] $flatten\u_sdram_backend.$procmux$8872_Y [0] $flatten\u_sdram_backend.$procmux$8872_Y [0] $flatten\u_sdram_backend.$procmux$8872_Y [0] $flatten\u_sdram_backend.$procmux$8872_Y [0] $flatten\u_sdram_backend.$procmux$8872_Y [0] $flatten\u_sdram_backend.$procmux$8872_Y [0] $flatten\u_sdram_backend.$procmux$8872_Y [0] $flatten\u_sdram_backend.$procmux$8872_Y [0] $flatten\u_sdram_backend.$procmux$8872_Y [0] $flatten\u_sdram_backend.$procmux$8872_Y [0] $flatten\u_sdram_backend.$procmux$8872_Y [0] $flatten\u_sdram_backend.$procmux$8872_Y [0] $flatten\u_sdram_backend.$procmux$8872_Y [0] $flatten\u_sdram_backend.$procmux$8872_Y [0] $flatten\u_sdram_backend.$procmux$8872_Y [0] $flatten\u_sdram_backend.$procmux$8872_Y [0] $flatten\u_sdram_backend.$procmux$8872_Y [0] $flatten\u_sdram_backend.$procmux$8872_Y [0] $flatten\u_sdram_backend.$procmux$8872_Y [0] $flatten\u_sdram_backend.$procmux$8872_Y [0] $flatten\u_sdram_backend.$procmux$8872_Y [0] } + Optimizing cells in module \fpga_neural_v2_top. + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15199: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4527_EN[1:0]$5606, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15199_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15161_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15199_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15199_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15199_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13054: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4579_EN[1:0]$6094, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13054_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13016_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13054_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13054_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13054_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15132: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4530_EN[2:0]$5630, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15132_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15007_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15132_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15132_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15132_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15132_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13003: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4581_EN[1:0]$6109, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13003_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12965_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13003_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13003_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13003_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15105: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4532_EN[2:0]$5645, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15105_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14956_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15105_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15105_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15105_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15105_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12952: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4583_EN[1:0]$6124, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12952_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12914_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12952_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12952_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12952_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15078: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4534_EN[2:0]$5660, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15078_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14905_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15078_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15078_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15078_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15078_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15051: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4536_EN[2:0]$5675, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15051_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14854_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15051_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15051_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15051_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15051_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12885: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4586_EN[2:0]$6148, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12885_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12760_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12885_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12885_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12885_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12885_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15031: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4529_EN[1:0]$5635, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15031_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14993_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15031_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15031_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15031_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12858: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4588_EN[2:0]$6163, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12858_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12709_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12858_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12858_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12858_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12858_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12831: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4590_EN[2:0]$6178, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12831_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12658_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12831_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12831_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12831_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12831_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12804: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4592_EN[2:0]$6193, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12804_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12607_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12804_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12804_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12804_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12804_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12784: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4585_EN[1:0]$6153, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12784_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12746_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12784_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12784_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12784_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14980: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4531_EN[1:0]$5650, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14980_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14942_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14980_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14980_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14980_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12733: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4587_EN[1:0]$6168, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12733_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12695_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12733_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12733_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12733_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14929: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4533_EN[1:0]$5665, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14929_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14891_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14929_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14929_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14929_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12682: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4589_EN[1:0]$6183, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12682_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12644_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12682_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12682_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12682_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14878: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4535_EN[1:0]$5680, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14878_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14840_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14878_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14878_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14878_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12631: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4591_EN[1:0]$6198, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12631_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12593_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12631_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12631_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12631_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12564: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4594_EN[2:0]$6222, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12564_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12439_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12564_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12564_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12564_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12564_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14811: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4538_EN[2:0]$5704, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14811_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14686_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14811_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14811_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14811_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14811_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12537: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4596_EN[2:0]$6237, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12537_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12388_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12537_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12537_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12537_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12537_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14784: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4540_EN[2:0]$5719, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14784_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14635_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14784_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14784_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14784_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14784_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12510: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4598_EN[2:0]$6252, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12510_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12337_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12510_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12510_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12510_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12510_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12483: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4600_EN[2:0]$6267, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12483_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12286_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12483_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12483_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12483_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12483_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14757: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4542_EN[2:0]$5734, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14757_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14584_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14757_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14757_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14757_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14757_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12463: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4593_EN[1:0]$6227, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12463_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12425_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12463_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12463_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12463_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14730: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4544_EN[2:0]$5749, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14730_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14533_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14730_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14730_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14730_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14730_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12412: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4595_EN[1:0]$6242, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12412_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12374_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12412_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12412_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12412_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14710: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4537_EN[1:0]$5709, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14710_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14672_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14710_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14710_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14710_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12361: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4597_EN[1:0]$6257, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12361_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12323_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12361_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12361_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12361_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14659: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4539_EN[1:0]$5724, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14659_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14621_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14659_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14659_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14659_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12310: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4599_EN[1:0]$6272, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12310_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12272_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12310_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12310_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12310_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14608: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4541_EN[1:0]$5739, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14608_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14570_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14608_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14608_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14608_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12243: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4602_EN[2:0]$6296, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12243_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12118_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12243_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12243_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12243_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12243_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12216: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4604_EN[2:0]$6311, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12216_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12067_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12216_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12216_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12216_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12216_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14557: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4543_EN[1:0]$5754, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14557_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14519_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14557_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14557_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14557_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12189: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4606_EN[2:0]$6326, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12189_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12016_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12189_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12189_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12189_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12189_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12162: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4608_EN[2:0]$6341, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12162_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11965_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12162_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12162_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12162_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12162_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12142: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4601_EN[1:0]$6301, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12142_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12104_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12142_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12142_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12142_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17309: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:164$4641_EN[1:0]$6647, B=2'00, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:164$4641_EN[1:0]$4951 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$10652_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:164$4641_EN[1:0]$4951 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:164$4641_EN[1:0]$4951 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:164$4641_EN[1:0]$4951 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14490: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4546_EN[2:0]$5778, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14490_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14365_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14490_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14490_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14490_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14490_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12091: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4603_EN[1:0]$6316, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12091_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12053_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12091_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12091_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12091_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14463: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4548_EN[2:0]$5793, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14463_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14314_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14463_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14463_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14463_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14463_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12040: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4605_EN[1:0]$6331, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12040_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12002_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12040_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12040_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12040_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14436: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4550_EN[2:0]$5808, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14436_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14263_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14436_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14436_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14436_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14436_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14409: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4552_EN[2:0]$5823, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14409_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14212_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14409_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14409_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14409_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14409_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11989: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4607_EN[1:0]$6346, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11989_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11951_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11989_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11989_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11989_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14389: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4545_EN[1:0]$5783, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14389_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14351_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14389_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14389_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14389_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11922: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4610_EN[2:0]$6370, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11922_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11797_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11922_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11922_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11922_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11922_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11895: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4612_EN[2:0]$6385, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11895_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11746_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11895_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11895_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11895_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11895_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14338: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4547_EN[1:0]$5798, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14338_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14300_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14338_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14338_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14338_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11868: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4614_EN[2:0]$6400, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11868_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11695_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11868_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11868_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11868_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11868_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11841: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4616_EN[2:0]$6415, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11841_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11644_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11841_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11841_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11841_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11841_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11821: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4609_EN[1:0]$6375, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11821_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11783_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11821_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11821_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11821_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14287: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4549_EN[1:0]$5813, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14287_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14249_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14287_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14287_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14287_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11770: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4611_EN[1:0]$6390, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11770_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11732_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11770_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11770_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11770_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14236: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4551_EN[1:0]$5828, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14236_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14198_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14236_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14236_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14236_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11719: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4613_EN[1:0]$6405, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11719_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11681_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11719_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11719_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11719_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11668: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4615_EN[1:0]$6420, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11668_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11630_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11668_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11668_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11668_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14169: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4554_EN[2:0]$5852, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14169_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14044_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14169_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14169_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14169_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14169_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14142: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4556_EN[2:0]$5867, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14142_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13993_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14142_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14142_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14142_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14142_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11601: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4618_EN[2:0]$6444, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11601_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11476_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11601_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11601_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11601_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11601_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14115: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4558_EN[2:0]$5882, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14115_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13942_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14115_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14115_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14115_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14115_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11574: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4620_EN[2:0]$6459, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11574_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11425_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11574_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11574_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11574_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11574_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11547: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4622_EN[2:0]$6474, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11547_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11374_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11547_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11547_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11547_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11547_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14088: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4560_EN[2:0]$5897, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14088_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13891_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14088_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14088_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14088_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14088_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11520: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4624_EN[2:0]$6489, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11520_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11323_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11520_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11520_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11520_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11520_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11500: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4617_EN[1:0]$6449, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11500_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11462_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11500_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11500_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11500_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14068: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4553_EN[1:0]$5857, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14068_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14030_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14068_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14068_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14068_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11449: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4619_EN[1:0]$6464, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11449_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11411_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11449_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11449_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11449_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14017: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4555_EN[1:0]$5872, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14017_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13979_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14017_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14017_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14017_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11398: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4621_EN[1:0]$6479, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11398_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11360_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11398_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11398_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11398_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13966: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4557_EN[1:0]$5887, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13966_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13928_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13966_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13966_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13966_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11347: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4623_EN[1:0]$6494, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11347_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11309_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11347_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11347_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11347_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13915: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4559_EN[1:0]$5902, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13915_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13877_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13915_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13915_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13915_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15774: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4514_EN[2:0]$5482, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15774_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15649_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15774_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15774_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15774_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15774_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11280: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4626_EN[2:0]$6518, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11280_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11155_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11280_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11280_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11280_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11280_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11253: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4628_EN[2:0]$6533, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11253_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11104_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11253_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11253_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11253_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11253_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15747: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4516_EN[2:0]$5497, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15747_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15598_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15747_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15747_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15747_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15747_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11226: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4630_EN[2:0]$6548, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11226_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11053_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11226_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11226_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11226_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11226_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11199: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4632_EN[2:0]$6563, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11199_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11002_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11199_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11199_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11199_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11199_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13848: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4562_EN[2:0]$5926, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13848_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13723_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13848_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13848_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13848_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13848_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11179: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4625_EN[1:0]$6523, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11179_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11141_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11179_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11179_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11179_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15720: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4518_EN[2:0]$5512, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15720_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15547_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15720_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15720_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15720_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15720_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13821: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4564_EN[2:0]$5941, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13821_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13672_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13821_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13821_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13821_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13821_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11128: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4627_EN[1:0]$6538, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11128_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11090_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11128_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11128_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11128_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15693: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4520_EN[2:0]$5527, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15693_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15496_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15693_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15693_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15693_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15693_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13794: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4566_EN[2:0]$5956, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13794_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13621_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13794_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13794_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13794_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13794_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13767: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4568_EN[2:0]$5971, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13767_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13570_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13767_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13767_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13767_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13767_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11077: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4629_EN[1:0]$6553, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11077_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11039_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11077_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11077_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11077_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15673: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4513_EN[1:0]$5487, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15673_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15635_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15673_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15673_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15673_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13747: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4561_EN[1:0]$5931, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13747_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13709_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13747_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13747_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13747_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11026: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4631_EN[1:0]$6568, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11026_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$10988_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11026_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11026_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11026_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13696: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4563_EN[1:0]$5946, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13696_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13658_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13696_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13696_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13696_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15622: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4515_EN[1:0]$5502, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15622_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15584_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15622_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15622_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15622_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10959: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4634_EN[2:0]$6592, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$10959_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$10834_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$10959_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10959_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10959_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10959_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10932: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4636_EN[2:0]$6607, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$10932_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$10783_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$10932_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10932_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10932_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10932_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13645: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4565_EN[1:0]$5961, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13645_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13607_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13645_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13645_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13645_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10905: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4638_EN[2:0]$6622, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$10905_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$10732_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$10905_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10905_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10905_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10905_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15571: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4517_EN[1:0]$5517, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15571_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15533_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15571_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15571_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15571_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10878: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4640_EN[2:0]$6637, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$10878_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$10681_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$10878_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10878_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10878_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10878_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10858: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4633_EN[1:0]$6597, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$10858_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$10820_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$10858_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10858_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10858_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13594: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4567_EN[1:0]$5976, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13594_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13556_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13594_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13594_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13594_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10807: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4635_EN[1:0]$6612, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$10807_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$10769_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$10807_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10807_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10807_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15520: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4519_EN[1:0]$5532, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15520_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15482_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15520_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15520_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15520_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10756: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4637_EN[1:0]$6627, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$10756_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$10718_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$10756_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10756_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10756_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13527: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4570_EN[2:0]$6000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13527_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13402_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13527_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13527_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13527_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13527_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13500: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4572_EN[2:0]$6015, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13500_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13351_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13500_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13500_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13500_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13500_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10705: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4639_EN[1:0]$6642, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$10705_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$10667_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$10705_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10705_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10705_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13473: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4574_EN[2:0]$6030, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13473_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13300_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13473_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13473_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13473_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13473_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17936: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_result_addr$hardware/v2/rtl/dependency_manager.v:134$4507_EN[22:0]$5243, B=23'00000000000000000000000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_result_addr$hardware/v2/rtl/dependency_manager.v:134$4507_EN[22:0]$4742 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$17060_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_result_addr$hardware/v2/rtl/dependency_manager.v:134$4507_EN[22:0]$4742 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_result_addr$hardware/v2/rtl/dependency_manager.v:134$4507_EN[22:0]$4742 [22:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_result_addr$hardware/v2/rtl/dependency_manager.v:134$4507_EN[22:0]$4742 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_result_addr$hardware/v2/rtl/dependency_manager.v:134$4507_EN[22:0]$4742 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_result_addr$hardware/v2/rtl/dependency_manager.v:134$4507_EN[22:0]$4742 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_result_addr$hardware/v2/rtl/dependency_manager.v:134$4507_EN[22:0]$4742 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_result_addr$hardware/v2/rtl/dependency_manager.v:134$4507_EN[22:0]$4742 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_result_addr$hardware/v2/rtl/dependency_manager.v:134$4507_EN[22:0]$4742 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_result_addr$hardware/v2/rtl/dependency_manager.v:134$4507_EN[22:0]$4742 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_result_addr$hardware/v2/rtl/dependency_manager.v:134$4507_EN[22:0]$4742 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_result_addr$hardware/v2/rtl/dependency_manager.v:134$4507_EN[22:0]$4742 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_result_addr$hardware/v2/rtl/dependency_manager.v:134$4507_EN[22:0]$4742 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_result_addr$hardware/v2/rtl/dependency_manager.v:134$4507_EN[22:0]$4742 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_result_addr$hardware/v2/rtl/dependency_manager.v:134$4507_EN[22:0]$4742 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_result_addr$hardware/v2/rtl/dependency_manager.v:134$4507_EN[22:0]$4742 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_result_addr$hardware/v2/rtl/dependency_manager.v:134$4507_EN[22:0]$4742 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_result_addr$hardware/v2/rtl/dependency_manager.v:134$4507_EN[22:0]$4742 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_result_addr$hardware/v2/rtl/dependency_manager.v:134$4507_EN[22:0]$4742 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_result_addr$hardware/v2/rtl/dependency_manager.v:134$4507_EN[22:0]$4742 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_result_addr$hardware/v2/rtl/dependency_manager.v:134$4507_EN[22:0]$4742 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_result_addr$hardware/v2/rtl/dependency_manager.v:134$4507_EN[22:0]$4742 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_result_addr$hardware/v2/rtl/dependency_manager.v:134$4507_EN[22:0]$4742 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_result_addr$hardware/v2/rtl/dependency_manager.v:134$4507_EN[22:0]$4742 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_result_addr$hardware/v2/rtl/dependency_manager.v:134$4507_EN[22:0]$4742 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15453: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4522_EN[2:0]$5556, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15453_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15328_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15453_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15453_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15453_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15453_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17927: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$4508_EN[3:0]$5246, B=4'0000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$4508_EN[3:0]$4745 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$17042_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$4508_EN[3:0]$4745 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$4508_EN[3:0]$4745 [3:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$4508_EN[3:0]$4745 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$4508_EN[3:0]$4745 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$4508_EN[3:0]$4745 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17918: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$4509_EN[3:0]$5249, B=4'0000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$4509_EN[3:0]$4748 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$17024_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$4509_EN[3:0]$4748 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$4509_EN[3:0]$4748 [3:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$4509_EN[3:0]$4748 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$4509_EN[3:0]$4748 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$4509_EN[3:0]$4748 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17909: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$4510_EN[3:0]$5252, B=4'0000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$4510_EN[3:0]$4751 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$17006_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$4510_EN[3:0]$4751 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$4510_EN[3:0]$4751 [3:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$4510_EN[3:0]$4751 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$4510_EN[3:0]$4751 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$4510_EN[3:0]$4751 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17900: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$4511_EN[3:0]$5255, B=4'0000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$4511_EN[3:0]$4754 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16988_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$4511_EN[3:0]$4754 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$4511_EN[3:0]$4754 [3:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$4511_EN[3:0]$4754 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$4511_EN[3:0]$4754 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$4511_EN[3:0]$4754 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17891: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:137$4512_EN[1:0]$5258, B=2'00, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:137$4512_EN[1:0]$4757 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16964_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:137$4512_EN[1:0]$4757 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:137$4512_EN[1:0]$4757 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:137$4512_EN[1:0]$4757 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13446: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4576_EN[2:0]$6045, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13446_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13249_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13446_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13446_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13446_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13446_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_director.$procmux$19210: + Old ports: A=$flatten\u_dataflow_core.\u_director.$2$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:163$4264_EN[22:0]$4345, B=23'00000000000000000000000, Y=$flatten\u_dataflow_core.\u_director.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:163$4264_EN[22:0]$4293 + New ports: A=$flatten\u_dataflow_core.\u_director.$procmux$19123_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_director.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:163$4264_EN[22:0]$4293 [0] + New connections: $flatten\u_dataflow_core.\u_director.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:163$4264_EN[22:0]$4293 [22:1] = { $flatten\u_dataflow_core.\u_director.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:163$4264_EN[22:0]$4293 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:163$4264_EN[22:0]$4293 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:163$4264_EN[22:0]$4293 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:163$4264_EN[22:0]$4293 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:163$4264_EN[22:0]$4293 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:163$4264_EN[22:0]$4293 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:163$4264_EN[22:0]$4293 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:163$4264_EN[22:0]$4293 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:163$4264_EN[22:0]$4293 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:163$4264_EN[22:0]$4293 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:163$4264_EN[22:0]$4293 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:163$4264_EN[22:0]$4293 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:163$4264_EN[22:0]$4293 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:163$4264_EN[22:0]$4293 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:163$4264_EN[22:0]$4293 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:163$4264_EN[22:0]$4293 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:163$4264_EN[22:0]$4293 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:163$4264_EN[22:0]$4293 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:163$4264_EN[22:0]$4293 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:163$4264_EN[22:0]$4293 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:163$4264_EN[22:0]$4293 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_x_base$hardware/v2/rtl/neural_director.v:163$4264_EN[22:0]$4293 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_director.$procmux$19201: + Old ports: A=$flatten\u_dataflow_core.\u_director.$2$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:164$4265_EN[22:0]$4348, B=23'00000000000000000000000, Y=$flatten\u_dataflow_core.\u_director.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:164$4265_EN[22:0]$4296 + New ports: A=$flatten\u_dataflow_core.\u_director.$procmux$19105_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_director.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:164$4265_EN[22:0]$4296 [0] + New connections: $flatten\u_dataflow_core.\u_director.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:164$4265_EN[22:0]$4296 [22:1] = { $flatten\u_dataflow_core.\u_director.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:164$4265_EN[22:0]$4296 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:164$4265_EN[22:0]$4296 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:164$4265_EN[22:0]$4296 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:164$4265_EN[22:0]$4296 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:164$4265_EN[22:0]$4296 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:164$4265_EN[22:0]$4296 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:164$4265_EN[22:0]$4296 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:164$4265_EN[22:0]$4296 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:164$4265_EN[22:0]$4296 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:164$4265_EN[22:0]$4296 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:164$4265_EN[22:0]$4296 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:164$4265_EN[22:0]$4296 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:164$4265_EN[22:0]$4296 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:164$4265_EN[22:0]$4296 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:164$4265_EN[22:0]$4296 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:164$4265_EN[22:0]$4296 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:164$4265_EN[22:0]$4296 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:164$4265_EN[22:0]$4296 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:164$4265_EN[22:0]$4296 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:164$4265_EN[22:0]$4296 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:164$4265_EN[22:0]$4296 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_w_base$hardware/v2/rtl/neural_director.v:164$4265_EN[22:0]$4296 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_director.$procmux$19192: + Old ports: A=$flatten\u_dataflow_core.\u_director.$2$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:165$4266_EN[15:0]$4351, B=16'0000000000000000, Y=$flatten\u_dataflow_core.\u_director.$0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:165$4266_EN[15:0]$4299 + New ports: A=$flatten\u_dataflow_core.\u_director.$procmux$19087_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_director.$0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:165$4266_EN[15:0]$4299 [0] + New connections: $flatten\u_dataflow_core.\u_director.$0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:165$4266_EN[15:0]$4299 [15:1] = { $flatten\u_dataflow_core.\u_director.$0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:165$4266_EN[15:0]$4299 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:165$4266_EN[15:0]$4299 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:165$4266_EN[15:0]$4299 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:165$4266_EN[15:0]$4299 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:165$4266_EN[15:0]$4299 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:165$4266_EN[15:0]$4299 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:165$4266_EN[15:0]$4299 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:165$4266_EN[15:0]$4299 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:165$4266_EN[15:0]$4299 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:165$4266_EN[15:0]$4299 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:165$4266_EN[15:0]$4299 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:165$4266_EN[15:0]$4299 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:165$4266_EN[15:0]$4299 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:165$4266_EN[15:0]$4299 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_n_tiles$hardware/v2/rtl/neural_director.v:165$4266_EN[15:0]$4299 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_director.$procmux$19183: + Old ports: A=$flatten\u_dataflow_core.\u_director.$2$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:166$4267_EN[22:0]$4354, B=23'00000000000000000000000, Y=$flatten\u_dataflow_core.\u_director.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:166$4267_EN[22:0]$4302 + New ports: A=$flatten\u_dataflow_core.\u_director.$procmux$19069_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_director.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:166$4267_EN[22:0]$4302 [0] + New connections: $flatten\u_dataflow_core.\u_director.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:166$4267_EN[22:0]$4302 [22:1] = { $flatten\u_dataflow_core.\u_director.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:166$4267_EN[22:0]$4302 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:166$4267_EN[22:0]$4302 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:166$4267_EN[22:0]$4302 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:166$4267_EN[22:0]$4302 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:166$4267_EN[22:0]$4302 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:166$4267_EN[22:0]$4302 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:166$4267_EN[22:0]$4302 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:166$4267_EN[22:0]$4302 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:166$4267_EN[22:0]$4302 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:166$4267_EN[22:0]$4302 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:166$4267_EN[22:0]$4302 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:166$4267_EN[22:0]$4302 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:166$4267_EN[22:0]$4302 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:166$4267_EN[22:0]$4302 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:166$4267_EN[22:0]$4302 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:166$4267_EN[22:0]$4302 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:166$4267_EN[22:0]$4302 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:166$4267_EN[22:0]$4302 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:166$4267_EN[22:0]$4302 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:166$4267_EN[22:0]$4302 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:166$4267_EN[22:0]$4302 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_result_addr$hardware/v2/rtl/neural_director.v:166$4267_EN[22:0]$4302 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_director.$procmux$19174: + Old ports: A=$flatten\u_dataflow_core.\u_director.$2$memwr$\q_node_id$hardware/v2/rtl/neural_director.v:167$4268_EN[15:0]$4357, B=16'0000000000000000, Y=$flatten\u_dataflow_core.\u_director.$0$memwr$\q_node_id$hardware/v2/rtl/neural_director.v:167$4268_EN[15:0]$4305 + New ports: A=$flatten\u_dataflow_core.\u_director.$procmux$19051_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_director.$0$memwr$\q_node_id$hardware/v2/rtl/neural_director.v:167$4268_EN[15:0]$4305 [0] + New connections: $flatten\u_dataflow_core.\u_director.$0$memwr$\q_node_id$hardware/v2/rtl/neural_director.v:167$4268_EN[15:0]$4305 [15:1] = { $flatten\u_dataflow_core.\u_director.$0$memwr$\q_node_id$hardware/v2/rtl/neural_director.v:167$4268_EN[15:0]$4305 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_node_id$hardware/v2/rtl/neural_director.v:167$4268_EN[15:0]$4305 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_node_id$hardware/v2/rtl/neural_director.v:167$4268_EN[15:0]$4305 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_node_id$hardware/v2/rtl/neural_director.v:167$4268_EN[15:0]$4305 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_node_id$hardware/v2/rtl/neural_director.v:167$4268_EN[15:0]$4305 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_node_id$hardware/v2/rtl/neural_director.v:167$4268_EN[15:0]$4305 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_node_id$hardware/v2/rtl/neural_director.v:167$4268_EN[15:0]$4305 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_node_id$hardware/v2/rtl/neural_director.v:167$4268_EN[15:0]$4305 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_node_id$hardware/v2/rtl/neural_director.v:167$4268_EN[15:0]$4305 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_node_id$hardware/v2/rtl/neural_director.v:167$4268_EN[15:0]$4305 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_node_id$hardware/v2/rtl/neural_director.v:167$4268_EN[15:0]$4305 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_node_id$hardware/v2/rtl/neural_director.v:167$4268_EN[15:0]$4305 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_node_id$hardware/v2/rtl/neural_director.v:167$4268_EN[15:0]$4305 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_node_id$hardware/v2/rtl/neural_director.v:167$4268_EN[15:0]$4305 [0] $flatten\u_dataflow_core.\u_director.$0$memwr$\q_node_id$hardware/v2/rtl/neural_director.v:167$4268_EN[15:0]$4305 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13426: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4569_EN[1:0]$6005, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13426_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13388_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13426_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13426_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13426_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15426: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4524_EN[2:0]$5571, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15426_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15277_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15426_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15426_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15426_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15426_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15399: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4526_EN[2:0]$5586, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15399_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15226_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15399_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15399_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15399_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15399_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13375: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4571_EN[1:0]$6020, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13375_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13337_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13375_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13375_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13375_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17978: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:129$4502_EN[2:0]$5229, B=3'000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:129$4502_EN[2:0]$4728 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$17144_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:129$4502_EN[2:0]$4728 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:129$4502_EN[2:0]$4728 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:129$4502_EN[2:0]$4728 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_required$hardware/v2/rtl/dependency_manager.v:129$4502_EN[2:0]$4728 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17972: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:130$4503_EN[2:0]$5231, B=3'000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:130$4503_EN[2:0]$4730 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$17132_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:130$4503_EN[2:0]$4730 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:130$4503_EN[2:0]$4730 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:130$4503_EN[2:0]$4730 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:130$4503_EN[2:0]$4730 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17963: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_x_base$hardware/v2/rtl/dependency_manager.v:131$4504_EN[22:0]$5234, B=23'00000000000000000000000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_x_base$hardware/v2/rtl/dependency_manager.v:131$4504_EN[22:0]$4733 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$17114_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_x_base$hardware/v2/rtl/dependency_manager.v:131$4504_EN[22:0]$4733 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_x_base$hardware/v2/rtl/dependency_manager.v:131$4504_EN[22:0]$4733 [22:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_x_base$hardware/v2/rtl/dependency_manager.v:131$4504_EN[22:0]$4733 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_x_base$hardware/v2/rtl/dependency_manager.v:131$4504_EN[22:0]$4733 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_x_base$hardware/v2/rtl/dependency_manager.v:131$4504_EN[22:0]$4733 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_x_base$hardware/v2/rtl/dependency_manager.v:131$4504_EN[22:0]$4733 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_x_base$hardware/v2/rtl/dependency_manager.v:131$4504_EN[22:0]$4733 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_x_base$hardware/v2/rtl/dependency_manager.v:131$4504_EN[22:0]$4733 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_x_base$hardware/v2/rtl/dependency_manager.v:131$4504_EN[22:0]$4733 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_x_base$hardware/v2/rtl/dependency_manager.v:131$4504_EN[22:0]$4733 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_x_base$hardware/v2/rtl/dependency_manager.v:131$4504_EN[22:0]$4733 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_x_base$hardware/v2/rtl/dependency_manager.v:131$4504_EN[22:0]$4733 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_x_base$hardware/v2/rtl/dependency_manager.v:131$4504_EN[22:0]$4733 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_x_base$hardware/v2/rtl/dependency_manager.v:131$4504_EN[22:0]$4733 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_x_base$hardware/v2/rtl/dependency_manager.v:131$4504_EN[22:0]$4733 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_x_base$hardware/v2/rtl/dependency_manager.v:131$4504_EN[22:0]$4733 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_x_base$hardware/v2/rtl/dependency_manager.v:131$4504_EN[22:0]$4733 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_x_base$hardware/v2/rtl/dependency_manager.v:131$4504_EN[22:0]$4733 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_x_base$hardware/v2/rtl/dependency_manager.v:131$4504_EN[22:0]$4733 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_x_base$hardware/v2/rtl/dependency_manager.v:131$4504_EN[22:0]$4733 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_x_base$hardware/v2/rtl/dependency_manager.v:131$4504_EN[22:0]$4733 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_x_base$hardware/v2/rtl/dependency_manager.v:131$4504_EN[22:0]$4733 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_x_base$hardware/v2/rtl/dependency_manager.v:131$4504_EN[22:0]$4733 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_x_base$hardware/v2/rtl/dependency_manager.v:131$4504_EN[22:0]$4733 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17954: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_w_base$hardware/v2/rtl/dependency_manager.v:132$4505_EN[22:0]$5237, B=23'00000000000000000000000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_w_base$hardware/v2/rtl/dependency_manager.v:132$4505_EN[22:0]$4736 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$17096_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_w_base$hardware/v2/rtl/dependency_manager.v:132$4505_EN[22:0]$4736 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_w_base$hardware/v2/rtl/dependency_manager.v:132$4505_EN[22:0]$4736 [22:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_w_base$hardware/v2/rtl/dependency_manager.v:132$4505_EN[22:0]$4736 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_w_base$hardware/v2/rtl/dependency_manager.v:132$4505_EN[22:0]$4736 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_w_base$hardware/v2/rtl/dependency_manager.v:132$4505_EN[22:0]$4736 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_w_base$hardware/v2/rtl/dependency_manager.v:132$4505_EN[22:0]$4736 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_w_base$hardware/v2/rtl/dependency_manager.v:132$4505_EN[22:0]$4736 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_w_base$hardware/v2/rtl/dependency_manager.v:132$4505_EN[22:0]$4736 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_w_base$hardware/v2/rtl/dependency_manager.v:132$4505_EN[22:0]$4736 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_w_base$hardware/v2/rtl/dependency_manager.v:132$4505_EN[22:0]$4736 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_w_base$hardware/v2/rtl/dependency_manager.v:132$4505_EN[22:0]$4736 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_w_base$hardware/v2/rtl/dependency_manager.v:132$4505_EN[22:0]$4736 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_w_base$hardware/v2/rtl/dependency_manager.v:132$4505_EN[22:0]$4736 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_w_base$hardware/v2/rtl/dependency_manager.v:132$4505_EN[22:0]$4736 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_w_base$hardware/v2/rtl/dependency_manager.v:132$4505_EN[22:0]$4736 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_w_base$hardware/v2/rtl/dependency_manager.v:132$4505_EN[22:0]$4736 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_w_base$hardware/v2/rtl/dependency_manager.v:132$4505_EN[22:0]$4736 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_w_base$hardware/v2/rtl/dependency_manager.v:132$4505_EN[22:0]$4736 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_w_base$hardware/v2/rtl/dependency_manager.v:132$4505_EN[22:0]$4736 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_w_base$hardware/v2/rtl/dependency_manager.v:132$4505_EN[22:0]$4736 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_w_base$hardware/v2/rtl/dependency_manager.v:132$4505_EN[22:0]$4736 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_w_base$hardware/v2/rtl/dependency_manager.v:132$4505_EN[22:0]$4736 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_w_base$hardware/v2/rtl/dependency_manager.v:132$4505_EN[22:0]$4736 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_w_base$hardware/v2/rtl/dependency_manager.v:132$4505_EN[22:0]$4736 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17945: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_n_tiles$hardware/v2/rtl/dependency_manager.v:133$4506_EN[15:0]$5240, B=16'0000000000000000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_n_tiles$hardware/v2/rtl/dependency_manager.v:133$4506_EN[15:0]$4739 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$17078_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_n_tiles$hardware/v2/rtl/dependency_manager.v:133$4506_EN[15:0]$4739 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_n_tiles$hardware/v2/rtl/dependency_manager.v:133$4506_EN[15:0]$4739 [15:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_n_tiles$hardware/v2/rtl/dependency_manager.v:133$4506_EN[15:0]$4739 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_n_tiles$hardware/v2/rtl/dependency_manager.v:133$4506_EN[15:0]$4739 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_n_tiles$hardware/v2/rtl/dependency_manager.v:133$4506_EN[15:0]$4739 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_n_tiles$hardware/v2/rtl/dependency_manager.v:133$4506_EN[15:0]$4739 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_n_tiles$hardware/v2/rtl/dependency_manager.v:133$4506_EN[15:0]$4739 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_n_tiles$hardware/v2/rtl/dependency_manager.v:133$4506_EN[15:0]$4739 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_n_tiles$hardware/v2/rtl/dependency_manager.v:133$4506_EN[15:0]$4739 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_n_tiles$hardware/v2/rtl/dependency_manager.v:133$4506_EN[15:0]$4739 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_n_tiles$hardware/v2/rtl/dependency_manager.v:133$4506_EN[15:0]$4739 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_n_tiles$hardware/v2/rtl/dependency_manager.v:133$4506_EN[15:0]$4739 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_n_tiles$hardware/v2/rtl/dependency_manager.v:133$4506_EN[15:0]$4739 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_n_tiles$hardware/v2/rtl/dependency_manager.v:133$4506_EN[15:0]$4739 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_n_tiles$hardware/v2/rtl/dependency_manager.v:133$4506_EN[15:0]$4739 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_n_tiles$hardware/v2/rtl/dependency_manager.v:133$4506_EN[15:0]$4739 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_n_tiles$hardware/v2/rtl/dependency_manager.v:133$4506_EN[15:0]$4739 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15372: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4528_EN[2:0]$5601, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15372_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15175_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15372_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15372_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15372_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15372_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13324: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4573_EN[1:0]$6035, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13324_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13286_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13324_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13324_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13324_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15352: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4521_EN[1:0]$5561, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15352_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15314_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15352_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15352_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15352_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13273: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4575_EN[1:0]$6050, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13273_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13235_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13273_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13273_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13273_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_sdram_backend.$procmux$9118: + Old ports: A=64'0000000000000000000000000000000000000000000000000000000000000000, B=$flatten\u_sdram_backend.$4$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$7054, Y=$flatten\u_sdram_backend.$procmux$9118_Y + New ports: A=1'0, B=$flatten\u_sdram_backend.$procmux$8872_Y [0], Y=$flatten\u_sdram_backend.$procmux$9118_Y [0] + New connections: $flatten\u_sdram_backend.$procmux$9118_Y [63:1] = { $flatten\u_sdram_backend.$procmux$9118_Y [0] $flatten\u_sdram_backend.$procmux$9118_Y [0] $flatten\u_sdram_backend.$procmux$9118_Y [0] $flatten\u_sdram_backend.$procmux$9118_Y [0] $flatten\u_sdram_backend.$procmux$9118_Y [0] $flatten\u_sdram_backend.$procmux$9118_Y [0] $flatten\u_sdram_backend.$procmux$9118_Y [0] $flatten\u_sdram_backend.$procmux$9118_Y [0] $flatten\u_sdram_backend.$procmux$9118_Y [0] $flatten\u_sdram_backend.$procmux$9118_Y [0] $flatten\u_sdram_backend.$procmux$9118_Y [0] $flatten\u_sdram_backend.$procmux$9118_Y [0] $flatten\u_sdram_backend.$procmux$9118_Y [0] $flatten\u_sdram_backend.$procmux$9118_Y [0] $flatten\u_sdram_backend.$procmux$9118_Y [0] $flatten\u_sdram_backend.$procmux$9118_Y [0] $flatten\u_sdram_backend.$procmux$9118_Y [0] $flatten\u_sdram_backend.$procmux$9118_Y [0] $flatten\u_sdram_backend.$procmux$9118_Y [0] $flatten\u_sdram_backend.$procmux$9118_Y [0] $flatten\u_sdram_backend.$procmux$9118_Y [0] $flatten\u_sdram_backend.$procmux$9118_Y [0] $flatten\u_sdram_backend.$procmux$9118_Y [0] $flatten\u_sdram_backend.$procmux$9118_Y [0] $flatten\u_sdram_backend.$procmux$9118_Y [0] $flatten\u_sdram_backend.$procmux$9118_Y [0] $flatten\u_sdram_backend.$procmux$9118_Y [0] $flatten\u_sdram_backend.$procmux$9118_Y [0] $flatten\u_sdram_backend.$procmux$9118_Y [0] $flatten\u_sdram_backend.$procmux$9118_Y [0] $flatten\u_sdram_backend.$procmux$9118_Y [0] $flatten\u_sdram_backend.$procmux$9118_Y [0] $flatten\u_sdram_backend.$procmux$9118_Y [0] $flatten\u_sdram_backend.$procmux$9118_Y [0] $flatten\u_sdram_backend.$procmux$9118_Y [0] $flatten\u_sdram_backend.$procmux$9118_Y [0] $flatten\u_sdram_backend.$procmux$9118_Y [0] $flatten\u_sdram_backend.$procmux$9118_Y [0] $flatten\u_sdram_backend.$procmux$9118_Y [0] $flatten\u_sdram_backend.$procmux$9118_Y [0] $flatten\u_sdram_backend.$procmux$9118_Y [0] $flatten\u_sdram_backend.$procmux$9118_Y [0] $flatten\u_sdram_backend.$procmux$9118_Y [0] $flatten\u_sdram_backend.$procmux$9118_Y [0] $flatten\u_sdram_backend.$procmux$9118_Y [0] $flatten\u_sdram_backend.$procmux$9118_Y [0] $flatten\u_sdram_backend.$procmux$9118_Y [0] $flatten\u_sdram_backend.$procmux$9118_Y [0] $flatten\u_sdram_backend.$procmux$9118_Y [0] $flatten\u_sdram_backend.$procmux$9118_Y [0] $flatten\u_sdram_backend.$procmux$9118_Y [0] $flatten\u_sdram_backend.$procmux$9118_Y [0] $flatten\u_sdram_backend.$procmux$9118_Y [0] $flatten\u_sdram_backend.$procmux$9118_Y [0] $flatten\u_sdram_backend.$procmux$9118_Y [0] $flatten\u_sdram_backend.$procmux$9118_Y [0] $flatten\u_sdram_backend.$procmux$9118_Y [0] $flatten\u_sdram_backend.$procmux$9118_Y [0] $flatten\u_sdram_backend.$procmux$9118_Y [0] $flatten\u_sdram_backend.$procmux$9118_Y [0] $flatten\u_sdram_backend.$procmux$9118_Y [0] $flatten\u_sdram_backend.$procmux$9118_Y [0] $flatten\u_sdram_backend.$procmux$9118_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15301: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4523_EN[1:0]$5576, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15301_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15263_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15301_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15301_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15301_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_sdram_backend.$procmux$9085: + Old ports: A=23'00000000000000000000000, B=$flatten\u_sdram_backend.$4$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:292$6938_EN[22:0]$7057, Y=$flatten\u_sdram_backend.$procmux$9085_Y + New ports: A=1'0, B=$flatten\u_sdram_backend.$procmux$8830_Y [0], Y=$flatten\u_sdram_backend.$procmux$9085_Y [0] + New connections: $flatten\u_sdram_backend.$procmux$9085_Y [22:1] = { $flatten\u_sdram_backend.$procmux$9085_Y [0] $flatten\u_sdram_backend.$procmux$9085_Y [0] $flatten\u_sdram_backend.$procmux$9085_Y [0] $flatten\u_sdram_backend.$procmux$9085_Y [0] $flatten\u_sdram_backend.$procmux$9085_Y [0] $flatten\u_sdram_backend.$procmux$9085_Y [0] $flatten\u_sdram_backend.$procmux$9085_Y [0] $flatten\u_sdram_backend.$procmux$9085_Y [0] $flatten\u_sdram_backend.$procmux$9085_Y [0] $flatten\u_sdram_backend.$procmux$9085_Y [0] $flatten\u_sdram_backend.$procmux$9085_Y [0] $flatten\u_sdram_backend.$procmux$9085_Y [0] $flatten\u_sdram_backend.$procmux$9085_Y [0] $flatten\u_sdram_backend.$procmux$9085_Y [0] $flatten\u_sdram_backend.$procmux$9085_Y [0] $flatten\u_sdram_backend.$procmux$9085_Y [0] $flatten\u_sdram_backend.$procmux$9085_Y [0] $flatten\u_sdram_backend.$procmux$9085_Y [0] $flatten\u_sdram_backend.$procmux$9085_Y [0] $flatten\u_sdram_backend.$procmux$9085_Y [0] $flatten\u_sdram_backend.$procmux$9085_Y [0] $flatten\u_sdram_backend.$procmux$9085_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_sdram_backend.$procmux$9052: + Old ports: A=64'0000000000000000000000000000000000000000000000000000000000000000, B=$flatten\u_sdram_backend.$4$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$7060, Y=$flatten\u_sdram_backend.$procmux$9052_Y + New ports: A=1'0, B=$flatten\u_sdram_backend.$procmux$8956_Y [0], Y=$flatten\u_sdram_backend.$procmux$9052_Y [0] + New connections: $flatten\u_sdram_backend.$procmux$9052_Y [63:1] = { $flatten\u_sdram_backend.$procmux$9052_Y [0] $flatten\u_sdram_backend.$procmux$9052_Y [0] $flatten\u_sdram_backend.$procmux$9052_Y [0] $flatten\u_sdram_backend.$procmux$9052_Y [0] $flatten\u_sdram_backend.$procmux$9052_Y [0] $flatten\u_sdram_backend.$procmux$9052_Y [0] $flatten\u_sdram_backend.$procmux$9052_Y [0] $flatten\u_sdram_backend.$procmux$9052_Y [0] $flatten\u_sdram_backend.$procmux$9052_Y [0] $flatten\u_sdram_backend.$procmux$9052_Y [0] $flatten\u_sdram_backend.$procmux$9052_Y [0] $flatten\u_sdram_backend.$procmux$9052_Y [0] $flatten\u_sdram_backend.$procmux$9052_Y [0] $flatten\u_sdram_backend.$procmux$9052_Y [0] $flatten\u_sdram_backend.$procmux$9052_Y [0] $flatten\u_sdram_backend.$procmux$9052_Y [0] $flatten\u_sdram_backend.$procmux$9052_Y [0] $flatten\u_sdram_backend.$procmux$9052_Y [0] $flatten\u_sdram_backend.$procmux$9052_Y [0] $flatten\u_sdram_backend.$procmux$9052_Y [0] $flatten\u_sdram_backend.$procmux$9052_Y [0] $flatten\u_sdram_backend.$procmux$9052_Y [0] $flatten\u_sdram_backend.$procmux$9052_Y [0] $flatten\u_sdram_backend.$procmux$9052_Y [0] $flatten\u_sdram_backend.$procmux$9052_Y [0] $flatten\u_sdram_backend.$procmux$9052_Y [0] $flatten\u_sdram_backend.$procmux$9052_Y [0] $flatten\u_sdram_backend.$procmux$9052_Y [0] $flatten\u_sdram_backend.$procmux$9052_Y [0] $flatten\u_sdram_backend.$procmux$9052_Y [0] $flatten\u_sdram_backend.$procmux$9052_Y [0] $flatten\u_sdram_backend.$procmux$9052_Y [0] $flatten\u_sdram_backend.$procmux$9052_Y [0] $flatten\u_sdram_backend.$procmux$9052_Y [0] $flatten\u_sdram_backend.$procmux$9052_Y [0] $flatten\u_sdram_backend.$procmux$9052_Y [0] $flatten\u_sdram_backend.$procmux$9052_Y [0] $flatten\u_sdram_backend.$procmux$9052_Y [0] $flatten\u_sdram_backend.$procmux$9052_Y [0] $flatten\u_sdram_backend.$procmux$9052_Y [0] $flatten\u_sdram_backend.$procmux$9052_Y [0] $flatten\u_sdram_backend.$procmux$9052_Y [0] $flatten\u_sdram_backend.$procmux$9052_Y [0] $flatten\u_sdram_backend.$procmux$9052_Y [0] $flatten\u_sdram_backend.$procmux$9052_Y [0] $flatten\u_sdram_backend.$procmux$9052_Y [0] $flatten\u_sdram_backend.$procmux$9052_Y [0] $flatten\u_sdram_backend.$procmux$9052_Y [0] $flatten\u_sdram_backend.$procmux$9052_Y [0] $flatten\u_sdram_backend.$procmux$9052_Y [0] $flatten\u_sdram_backend.$procmux$9052_Y [0] $flatten\u_sdram_backend.$procmux$9052_Y [0] $flatten\u_sdram_backend.$procmux$9052_Y [0] $flatten\u_sdram_backend.$procmux$9052_Y [0] $flatten\u_sdram_backend.$procmux$9052_Y [0] $flatten\u_sdram_backend.$procmux$9052_Y [0] $flatten\u_sdram_backend.$procmux$9052_Y [0] $flatten\u_sdram_backend.$procmux$9052_Y [0] $flatten\u_sdram_backend.$procmux$9052_Y [0] $flatten\u_sdram_backend.$procmux$9052_Y [0] $flatten\u_sdram_backend.$procmux$9052_Y [0] $flatten\u_sdram_backend.$procmux$9052_Y [0] $flatten\u_sdram_backend.$procmux$9052_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13206: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4578_EN[2:0]$6074, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13206_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13081_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13206_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13206_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13206_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13206_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_sdram_backend.$procmux$9019: + Old ports: A=23'00000000000000000000000, B=$flatten\u_sdram_backend.$4$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:296$6940_EN[22:0]$7063, Y=$flatten\u_sdram_backend.$procmux$9019_Y + New ports: A=1'0, B=$flatten\u_sdram_backend.$procmux$8914_Y [0], Y=$flatten\u_sdram_backend.$procmux$9019_Y [0] + New connections: $flatten\u_sdram_backend.$procmux$9019_Y [22:1] = { $flatten\u_sdram_backend.$procmux$9019_Y [0] $flatten\u_sdram_backend.$procmux$9019_Y [0] $flatten\u_sdram_backend.$procmux$9019_Y [0] $flatten\u_sdram_backend.$procmux$9019_Y [0] $flatten\u_sdram_backend.$procmux$9019_Y [0] $flatten\u_sdram_backend.$procmux$9019_Y [0] $flatten\u_sdram_backend.$procmux$9019_Y [0] $flatten\u_sdram_backend.$procmux$9019_Y [0] $flatten\u_sdram_backend.$procmux$9019_Y [0] $flatten\u_sdram_backend.$procmux$9019_Y [0] $flatten\u_sdram_backend.$procmux$9019_Y [0] $flatten\u_sdram_backend.$procmux$9019_Y [0] $flatten\u_sdram_backend.$procmux$9019_Y [0] $flatten\u_sdram_backend.$procmux$9019_Y [0] $flatten\u_sdram_backend.$procmux$9019_Y [0] $flatten\u_sdram_backend.$procmux$9019_Y [0] $flatten\u_sdram_backend.$procmux$9019_Y [0] $flatten\u_sdram_backend.$procmux$9019_Y [0] $flatten\u_sdram_backend.$procmux$9019_Y [0] $flatten\u_sdram_backend.$procmux$9019_Y [0] $flatten\u_sdram_backend.$procmux$9019_Y [0] $flatten\u_sdram_backend.$procmux$9019_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13179: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4580_EN[2:0]$6089, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13179_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13030_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13179_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13179_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13179_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13179_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15250: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4525_EN[1:0]$5591, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15250_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15212_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15250_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15250_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15250_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13152: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4582_EN[2:0]$6104, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13152_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12979_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13152_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13152_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13152_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13152_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13125: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4584_EN[2:0]$6119, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13125_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12928_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13125_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13125_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13125_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13125_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13105: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$5$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4577_EN[1:0]$6079, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13105_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13067_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13105_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13105_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13105_Y [0] + Optimizing cells in module \fpga_neural_v2_top. + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16676: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4544_EN[2:0]$5696, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16676_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14730_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16676_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16676_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16676_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16676_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16658: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4546_EN[2:0]$5761, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16658_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14490_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16658_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16658_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16658_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16658_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15150: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4529_EN[1:0]$5628, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15150_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15031_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15150_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15150_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15150_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16640: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4548_EN[2:0]$5764, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16640_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14463_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16640_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16640_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16640_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16640_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15123: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4531_EN[1:0]$5643, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15123_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14980_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15123_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15123_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15123_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16622: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4550_EN[2:0]$5767, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16622_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14436_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16622_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16622_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16622_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16622_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15096: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4533_EN[1:0]$5658, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15096_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14929_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15096_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15096_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15096_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16604: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4552_EN[2:0]$5770, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16604_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14409_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16604_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16604_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16604_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16604_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15069: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4535_EN[1:0]$5673, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15069_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14878_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15069_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15069_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15069_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12903: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4585_EN[1:0]$6146, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12903_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12784_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12903_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12903_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12903_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16586: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4554_EN[2:0]$5835, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16586_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14169_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16586_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16586_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16586_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16586_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12876: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4587_EN[1:0]$6161, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12876_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12733_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12876_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12876_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12876_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16568: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4556_EN[2:0]$5838, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16568_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14142_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16568_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16568_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16568_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16568_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12849: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4589_EN[1:0]$6176, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12849_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12682_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12849_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12849_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12849_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12822: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4591_EN[1:0]$6191, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12822_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12631_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12822_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12822_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12822_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16550: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4558_EN[2:0]$5841, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16550_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14115_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16550_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16550_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16550_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16550_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16532: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4560_EN[2:0]$5844, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16532_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14088_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16532_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16532_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16532_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16532_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16514: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4562_EN[2:0]$5909, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16514_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13848_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16514_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16514_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16514_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16514_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16496: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4564_EN[2:0]$5912, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16496_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13821_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16496_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16496_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16496_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16496_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16478: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4566_EN[2:0]$5915, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16478_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13794_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16478_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16478_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16478_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16478_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16460: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4568_EN[2:0]$5918, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16460_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13767_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16460_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16460_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16460_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16460_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16442: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4570_EN[2:0]$5983, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16442_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13527_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16442_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16442_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16442_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16442_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16424: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4572_EN[2:0]$5986, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16424_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13500_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16424_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16424_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16424_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16424_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14829: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4537_EN[1:0]$5702, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14829_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14710_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14829_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14829_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14829_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12582: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4593_EN[1:0]$6220, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12582_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12463_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12582_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12582_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12582_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12555: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4595_EN[1:0]$6235, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12555_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12412_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12555_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12555_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12555_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16406: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4574_EN[2:0]$5989, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16406_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13473_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16406_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16406_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16406_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16406_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14802: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4539_EN[1:0]$5717, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14802_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14659_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14802_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14802_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14802_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12528: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4597_EN[1:0]$6250, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12528_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12361_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12528_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12528_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12528_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16388: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4576_EN[2:0]$5992, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16388_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13446_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16388_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16388_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16388_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16388_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14775: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4541_EN[1:0]$5732, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14775_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14608_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14775_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14775_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14775_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12501: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4599_EN[1:0]$6265, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12501_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12310_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12501_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12501_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12501_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16370: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4578_EN[2:0]$6057, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16370_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13206_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16370_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16370_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16370_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16370_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14748: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4543_EN[1:0]$5747, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14748_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14557_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14748_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14748_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14748_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16352: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4580_EN[2:0]$6060, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16352_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13179_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16352_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16352_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16352_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16352_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16334: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4582_EN[2:0]$6063, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16334_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13152_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16334_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16334_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16334_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16334_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16316: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4584_EN[2:0]$6066, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16316_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13125_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16316_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16316_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16316_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16316_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16298: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4586_EN[2:0]$6131, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16298_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12885_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16298_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16298_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16298_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16298_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16280: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4588_EN[2:0]$6134, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16280_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12858_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16280_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16280_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16280_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16280_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12261: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4601_EN[1:0]$6294, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12261_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12142_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12261_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12261_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12261_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16262: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4590_EN[2:0]$6137, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16262_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12831_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16262_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16262_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16262_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16262_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12234: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4603_EN[1:0]$6309, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12234_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12091_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12234_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12234_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12234_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16244: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4592_EN[2:0]$6140, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16244_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12804_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16244_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16244_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16244_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16244_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12207: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4605_EN[1:0]$6324, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12207_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12040_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12207_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12207_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12207_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16226: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4594_EN[2:0]$6205, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16226_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12564_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16226_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16226_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16226_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16226_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12180: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4607_EN[1:0]$6339, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12180_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11989_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12180_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12180_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$12180_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16208: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4596_EN[2:0]$6208, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16208_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12537_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16208_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16208_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16208_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16208_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14508: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4545_EN[1:0]$5776, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14508_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14389_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14508_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14508_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14508_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16190: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4598_EN[2:0]$6211, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16190_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12510_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16190_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16190_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16190_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16190_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14481: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4547_EN[1:0]$5791, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14481_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14338_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14481_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14481_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14481_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16172: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4600_EN[2:0]$6214, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16172_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12483_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16172_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16172_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16172_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16172_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14454: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4549_EN[1:0]$5806, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14454_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14287_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14454_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14454_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14454_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16154: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4602_EN[2:0]$6279, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16154_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12243_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16154_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16154_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16154_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16154_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14427: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4551_EN[1:0]$5821, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14427_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14236_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14427_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14427_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14427_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16136: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4604_EN[2:0]$6282, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16136_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12216_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16136_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16136_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16136_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16136_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16118: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4606_EN[2:0]$6285, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16118_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12189_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16118_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16118_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16118_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16118_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11940: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4609_EN[1:0]$6368, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11940_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11821_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11940_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11940_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11940_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16100: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4608_EN[2:0]$6288, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16100_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12162_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16100_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16100_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16100_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16100_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11913: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4611_EN[1:0]$6383, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11913_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11770_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11913_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11913_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11913_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16082: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4610_EN[2:0]$6353, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16082_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11922_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16082_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16082_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16082_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16082_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11886: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4613_EN[1:0]$6398, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11886_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11719_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11886_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11886_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11886_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11859: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4615_EN[1:0]$6413, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11859_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11668_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11859_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11859_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11859_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16064: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4612_EN[2:0]$6356, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16064_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11895_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16064_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16064_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16064_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16064_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16046: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4614_EN[2:0]$6359, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16046_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11868_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16046_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16046_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16046_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16046_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16028: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4616_EN[2:0]$6362, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16028_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11841_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16028_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16028_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16028_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16028_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16010: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4618_EN[2:0]$6427, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16010_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11601_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16010_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16010_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16010_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16010_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15992: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4620_EN[2:0]$6430, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15992_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11574_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15992_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15992_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15992_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15992_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15974: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4622_EN[2:0]$6433, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15974_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11547_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15974_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15974_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15974_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15974_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14187: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4553_EN[1:0]$5850, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14187_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14068_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14187_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14187_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14187_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15956: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4624_EN[2:0]$6436, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15956_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11520_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15956_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15956_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15956_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15956_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14160: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4555_EN[1:0]$5865, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14160_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14017_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14160_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14160_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14160_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15938: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4626_EN[2:0]$6501, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15938_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11280_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15938_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15938_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15938_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15938_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11619: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4617_EN[1:0]$6442, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11619_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11500_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11619_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11619_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11619_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14133: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4557_EN[1:0]$5880, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14133_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13966_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14133_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14133_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14133_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11592: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4619_EN[1:0]$6457, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11592_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11449_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11592_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11592_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11592_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15920: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4628_EN[2:0]$6504, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15920_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11253_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15920_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15920_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15920_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15920_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11565: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4621_EN[1:0]$6472, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11565_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11398_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11565_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11565_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11565_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14106: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4559_EN[1:0]$5895, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14106_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13915_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14106_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14106_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$14106_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15902: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4630_EN[2:0]$6507, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15902_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11226_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15902_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15902_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15902_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15902_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11538: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4623_EN[1:0]$6487, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11538_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11347_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11538_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11538_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11538_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15884: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4632_EN[2:0]$6510, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15884_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11199_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15884_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15884_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15884_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15884_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15860: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4634_EN[2:0]$6575, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15860_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$10959_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15860_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15860_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15860_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15860_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15842: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4636_EN[2:0]$6578, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15842_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$10932_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15842_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15842_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15842_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15842_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15824: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4638_EN[2:0]$6581, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15824_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$10905_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15824_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15824_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15824_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15824_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15806: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4640_EN[2:0]$6584, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15806_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$10878_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15806_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15806_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15806_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15806_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15792: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4513_EN[1:0]$5480, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15792_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15673_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15792_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15792_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15792_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11298: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4625_EN[1:0]$6516, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11298_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11179_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11298_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11298_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11298_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15765: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4515_EN[1:0]$5495, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15765_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15622_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15765_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15765_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15765_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11271: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4627_EN[1:0]$6531, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11271_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11128_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11271_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11271_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11271_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11244: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4629_EN[1:0]$6546, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11244_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11077_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11244_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11244_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11244_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13866: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4561_EN[1:0]$5924, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13866_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13747_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13866_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13866_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13866_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15738: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4517_EN[1:0]$5510, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15738_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15571_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15738_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15738_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15738_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11217: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4631_EN[1:0]$6561, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11217_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11026_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11217_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11217_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$11217_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13839: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4563_EN[1:0]$5939, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13839_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13696_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13839_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13839_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13839_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15711: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4519_EN[1:0]$5525, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15711_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15520_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15711_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15711_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15711_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13812: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4565_EN[1:0]$5954, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13812_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13645_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13812_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13812_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13812_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13785: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4567_EN[1:0]$5969, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13785_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13594_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13785_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13785_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13785_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10977: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4633_EN[1:0]$6590, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$10977_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$10858_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$10977_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10977_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10977_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10950: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4635_EN[1:0]$6605, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$10950_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$10807_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$10950_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10950_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10950_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10923: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4637_EN[1:0]$6620, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$10923_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$10756_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$10923_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10923_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10923_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10896: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4639_EN[1:0]$6635, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$10896_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$10705_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$10896_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10896_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$10896_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16946: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4514_EN[2:0]$5465, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16946_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15774_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16946_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16946_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16946_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16946_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16928: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4516_EN[2:0]$5468, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16928_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15747_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16928_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16928_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16928_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16928_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16910: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4518_EN[2:0]$5471, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16910_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15720_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16910_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16910_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16910_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16910_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13545: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4569_EN[1:0]$5998, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13545_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13426_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13545_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13545_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13545_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13518: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4571_EN[1:0]$6013, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13518_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13375_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13518_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13518_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13518_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16892: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4520_EN[2:0]$5474, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16892_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15693_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16892_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16892_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16892_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16892_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13491: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4573_EN[1:0]$6028, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13491_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13324_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13491_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13491_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13491_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15471: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4521_EN[1:0]$5554, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15471_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15352_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15471_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15471_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15471_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16874: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4522_EN[2:0]$5539, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16874_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15453_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16874_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16874_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16874_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16874_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13464: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4575_EN[1:0]$6043, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13464_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13273_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13464_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13464_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13464_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15444: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4523_EN[1:0]$5569, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15444_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15301_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15444_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15444_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15444_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16856: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4524_EN[2:0]$5542, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16856_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15426_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16856_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16856_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16856_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16856_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15417: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4525_EN[1:0]$5584, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15417_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15250_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15417_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15417_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15417_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16838: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4526_EN[2:0]$5545, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16838_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15399_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16838_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16838_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16838_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16838_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15390: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4527_EN[1:0]$5599, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15390_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15199_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15390_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15390_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15390_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16820: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4528_EN[2:0]$5548, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16820_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15372_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16820_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16820_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16820_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16820_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_sdram_backend.$procmux$9280: + Old ports: A=64'0000000000000000000000000000000000000000000000000000000000000000, B=$flatten\u_sdram_backend.$3$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$7040, Y=$flatten\u_sdram_backend.$procmux$9280_Y + New ports: A=1'0, B=$flatten\u_sdram_backend.$procmux$9118_Y [0], Y=$flatten\u_sdram_backend.$procmux$9280_Y [0] + New connections: $flatten\u_sdram_backend.$procmux$9280_Y [63:1] = { $flatten\u_sdram_backend.$procmux$9280_Y [0] $flatten\u_sdram_backend.$procmux$9280_Y [0] $flatten\u_sdram_backend.$procmux$9280_Y [0] $flatten\u_sdram_backend.$procmux$9280_Y [0] $flatten\u_sdram_backend.$procmux$9280_Y [0] $flatten\u_sdram_backend.$procmux$9280_Y [0] $flatten\u_sdram_backend.$procmux$9280_Y [0] $flatten\u_sdram_backend.$procmux$9280_Y [0] $flatten\u_sdram_backend.$procmux$9280_Y [0] $flatten\u_sdram_backend.$procmux$9280_Y [0] $flatten\u_sdram_backend.$procmux$9280_Y [0] $flatten\u_sdram_backend.$procmux$9280_Y [0] $flatten\u_sdram_backend.$procmux$9280_Y [0] $flatten\u_sdram_backend.$procmux$9280_Y [0] $flatten\u_sdram_backend.$procmux$9280_Y [0] $flatten\u_sdram_backend.$procmux$9280_Y [0] $flatten\u_sdram_backend.$procmux$9280_Y [0] $flatten\u_sdram_backend.$procmux$9280_Y [0] $flatten\u_sdram_backend.$procmux$9280_Y [0] $flatten\u_sdram_backend.$procmux$9280_Y [0] $flatten\u_sdram_backend.$procmux$9280_Y [0] $flatten\u_sdram_backend.$procmux$9280_Y [0] $flatten\u_sdram_backend.$procmux$9280_Y [0] $flatten\u_sdram_backend.$procmux$9280_Y [0] $flatten\u_sdram_backend.$procmux$9280_Y [0] $flatten\u_sdram_backend.$procmux$9280_Y [0] $flatten\u_sdram_backend.$procmux$9280_Y [0] $flatten\u_sdram_backend.$procmux$9280_Y [0] $flatten\u_sdram_backend.$procmux$9280_Y [0] $flatten\u_sdram_backend.$procmux$9280_Y [0] $flatten\u_sdram_backend.$procmux$9280_Y [0] $flatten\u_sdram_backend.$procmux$9280_Y [0] $flatten\u_sdram_backend.$procmux$9280_Y [0] $flatten\u_sdram_backend.$procmux$9280_Y [0] $flatten\u_sdram_backend.$procmux$9280_Y [0] $flatten\u_sdram_backend.$procmux$9280_Y [0] $flatten\u_sdram_backend.$procmux$9280_Y [0] $flatten\u_sdram_backend.$procmux$9280_Y [0] $flatten\u_sdram_backend.$procmux$9280_Y [0] $flatten\u_sdram_backend.$procmux$9280_Y [0] $flatten\u_sdram_backend.$procmux$9280_Y [0] $flatten\u_sdram_backend.$procmux$9280_Y [0] $flatten\u_sdram_backend.$procmux$9280_Y [0] $flatten\u_sdram_backend.$procmux$9280_Y [0] $flatten\u_sdram_backend.$procmux$9280_Y [0] $flatten\u_sdram_backend.$procmux$9280_Y [0] $flatten\u_sdram_backend.$procmux$9280_Y [0] $flatten\u_sdram_backend.$procmux$9280_Y [0] $flatten\u_sdram_backend.$procmux$9280_Y [0] $flatten\u_sdram_backend.$procmux$9280_Y [0] $flatten\u_sdram_backend.$procmux$9280_Y [0] $flatten\u_sdram_backend.$procmux$9280_Y [0] $flatten\u_sdram_backend.$procmux$9280_Y [0] $flatten\u_sdram_backend.$procmux$9280_Y [0] $flatten\u_sdram_backend.$procmux$9280_Y [0] $flatten\u_sdram_backend.$procmux$9280_Y [0] $flatten\u_sdram_backend.$procmux$9280_Y [0] $flatten\u_sdram_backend.$procmux$9280_Y [0] $flatten\u_sdram_backend.$procmux$9280_Y [0] $flatten\u_sdram_backend.$procmux$9280_Y [0] $flatten\u_sdram_backend.$procmux$9280_Y [0] $flatten\u_sdram_backend.$procmux$9280_Y [0] $flatten\u_sdram_backend.$procmux$9280_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_sdram_backend.$procmux$9256: + Old ports: A=23'00000000000000000000000, B=$flatten\u_sdram_backend.$3$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:292$6938_EN[22:0]$7043, Y=$flatten\u_sdram_backend.$procmux$9256_Y + New ports: A=1'0, B=$flatten\u_sdram_backend.$procmux$9085_Y [0], Y=$flatten\u_sdram_backend.$procmux$9256_Y [0] + New connections: $flatten\u_sdram_backend.$procmux$9256_Y [22:1] = { $flatten\u_sdram_backend.$procmux$9256_Y [0] $flatten\u_sdram_backend.$procmux$9256_Y [0] $flatten\u_sdram_backend.$procmux$9256_Y [0] $flatten\u_sdram_backend.$procmux$9256_Y [0] $flatten\u_sdram_backend.$procmux$9256_Y [0] $flatten\u_sdram_backend.$procmux$9256_Y [0] $flatten\u_sdram_backend.$procmux$9256_Y [0] $flatten\u_sdram_backend.$procmux$9256_Y [0] $flatten\u_sdram_backend.$procmux$9256_Y [0] $flatten\u_sdram_backend.$procmux$9256_Y [0] $flatten\u_sdram_backend.$procmux$9256_Y [0] $flatten\u_sdram_backend.$procmux$9256_Y [0] $flatten\u_sdram_backend.$procmux$9256_Y [0] $flatten\u_sdram_backend.$procmux$9256_Y [0] $flatten\u_sdram_backend.$procmux$9256_Y [0] $flatten\u_sdram_backend.$procmux$9256_Y [0] $flatten\u_sdram_backend.$procmux$9256_Y [0] $flatten\u_sdram_backend.$procmux$9256_Y [0] $flatten\u_sdram_backend.$procmux$9256_Y [0] $flatten\u_sdram_backend.$procmux$9256_Y [0] $flatten\u_sdram_backend.$procmux$9256_Y [0] $flatten\u_sdram_backend.$procmux$9256_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_sdram_backend.$procmux$9232: + Old ports: A=64'0000000000000000000000000000000000000000000000000000000000000000, B=$flatten\u_sdram_backend.$3$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$7046, Y=$flatten\u_sdram_backend.$procmux$9232_Y + New ports: A=1'0, B=$flatten\u_sdram_backend.$procmux$9052_Y [0], Y=$flatten\u_sdram_backend.$procmux$9232_Y [0] + New connections: $flatten\u_sdram_backend.$procmux$9232_Y [63:1] = { $flatten\u_sdram_backend.$procmux$9232_Y [0] $flatten\u_sdram_backend.$procmux$9232_Y [0] $flatten\u_sdram_backend.$procmux$9232_Y [0] $flatten\u_sdram_backend.$procmux$9232_Y [0] $flatten\u_sdram_backend.$procmux$9232_Y [0] $flatten\u_sdram_backend.$procmux$9232_Y [0] $flatten\u_sdram_backend.$procmux$9232_Y [0] $flatten\u_sdram_backend.$procmux$9232_Y [0] $flatten\u_sdram_backend.$procmux$9232_Y [0] $flatten\u_sdram_backend.$procmux$9232_Y [0] $flatten\u_sdram_backend.$procmux$9232_Y [0] $flatten\u_sdram_backend.$procmux$9232_Y [0] $flatten\u_sdram_backend.$procmux$9232_Y [0] $flatten\u_sdram_backend.$procmux$9232_Y [0] $flatten\u_sdram_backend.$procmux$9232_Y [0] $flatten\u_sdram_backend.$procmux$9232_Y [0] $flatten\u_sdram_backend.$procmux$9232_Y [0] $flatten\u_sdram_backend.$procmux$9232_Y [0] $flatten\u_sdram_backend.$procmux$9232_Y [0] $flatten\u_sdram_backend.$procmux$9232_Y [0] $flatten\u_sdram_backend.$procmux$9232_Y [0] $flatten\u_sdram_backend.$procmux$9232_Y [0] $flatten\u_sdram_backend.$procmux$9232_Y [0] $flatten\u_sdram_backend.$procmux$9232_Y [0] $flatten\u_sdram_backend.$procmux$9232_Y [0] $flatten\u_sdram_backend.$procmux$9232_Y [0] $flatten\u_sdram_backend.$procmux$9232_Y [0] $flatten\u_sdram_backend.$procmux$9232_Y [0] $flatten\u_sdram_backend.$procmux$9232_Y [0] $flatten\u_sdram_backend.$procmux$9232_Y [0] $flatten\u_sdram_backend.$procmux$9232_Y [0] $flatten\u_sdram_backend.$procmux$9232_Y [0] $flatten\u_sdram_backend.$procmux$9232_Y [0] $flatten\u_sdram_backend.$procmux$9232_Y [0] $flatten\u_sdram_backend.$procmux$9232_Y [0] $flatten\u_sdram_backend.$procmux$9232_Y [0] $flatten\u_sdram_backend.$procmux$9232_Y [0] $flatten\u_sdram_backend.$procmux$9232_Y [0] $flatten\u_sdram_backend.$procmux$9232_Y [0] $flatten\u_sdram_backend.$procmux$9232_Y [0] $flatten\u_sdram_backend.$procmux$9232_Y [0] $flatten\u_sdram_backend.$procmux$9232_Y [0] $flatten\u_sdram_backend.$procmux$9232_Y [0] $flatten\u_sdram_backend.$procmux$9232_Y [0] $flatten\u_sdram_backend.$procmux$9232_Y [0] $flatten\u_sdram_backend.$procmux$9232_Y [0] $flatten\u_sdram_backend.$procmux$9232_Y [0] $flatten\u_sdram_backend.$procmux$9232_Y [0] $flatten\u_sdram_backend.$procmux$9232_Y [0] $flatten\u_sdram_backend.$procmux$9232_Y [0] $flatten\u_sdram_backend.$procmux$9232_Y [0] $flatten\u_sdram_backend.$procmux$9232_Y [0] $flatten\u_sdram_backend.$procmux$9232_Y [0] $flatten\u_sdram_backend.$procmux$9232_Y [0] $flatten\u_sdram_backend.$procmux$9232_Y [0] $flatten\u_sdram_backend.$procmux$9232_Y [0] $flatten\u_sdram_backend.$procmux$9232_Y [0] $flatten\u_sdram_backend.$procmux$9232_Y [0] $flatten\u_sdram_backend.$procmux$9232_Y [0] $flatten\u_sdram_backend.$procmux$9232_Y [0] $flatten\u_sdram_backend.$procmux$9232_Y [0] $flatten\u_sdram_backend.$procmux$9232_Y [0] $flatten\u_sdram_backend.$procmux$9232_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_sdram_backend.$procmux$9208: + Old ports: A=23'00000000000000000000000, B=$flatten\u_sdram_backend.$3$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:296$6940_EN[22:0]$7049, Y=$flatten\u_sdram_backend.$procmux$9208_Y + New ports: A=1'0, B=$flatten\u_sdram_backend.$procmux$9019_Y [0], Y=$flatten\u_sdram_backend.$procmux$9208_Y [0] + New connections: $flatten\u_sdram_backend.$procmux$9208_Y [22:1] = { $flatten\u_sdram_backend.$procmux$9208_Y [0] $flatten\u_sdram_backend.$procmux$9208_Y [0] $flatten\u_sdram_backend.$procmux$9208_Y [0] $flatten\u_sdram_backend.$procmux$9208_Y [0] $flatten\u_sdram_backend.$procmux$9208_Y [0] $flatten\u_sdram_backend.$procmux$9208_Y [0] $flatten\u_sdram_backend.$procmux$9208_Y [0] $flatten\u_sdram_backend.$procmux$9208_Y [0] $flatten\u_sdram_backend.$procmux$9208_Y [0] $flatten\u_sdram_backend.$procmux$9208_Y [0] $flatten\u_sdram_backend.$procmux$9208_Y [0] $flatten\u_sdram_backend.$procmux$9208_Y [0] $flatten\u_sdram_backend.$procmux$9208_Y [0] $flatten\u_sdram_backend.$procmux$9208_Y [0] $flatten\u_sdram_backend.$procmux$9208_Y [0] $flatten\u_sdram_backend.$procmux$9208_Y [0] $flatten\u_sdram_backend.$procmux$9208_Y [0] $flatten\u_sdram_backend.$procmux$9208_Y [0] $flatten\u_sdram_backend.$procmux$9208_Y [0] $flatten\u_sdram_backend.$procmux$9208_Y [0] $flatten\u_sdram_backend.$procmux$9208_Y [0] $flatten\u_sdram_backend.$procmux$9208_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16802: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4530_EN[2:0]$5613, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16802_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15132_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16802_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16802_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16802_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16802_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16784: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4532_EN[2:0]$5616, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16784_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15105_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16784_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16784_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16784_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16784_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16766: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4534_EN[2:0]$5619, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16766_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15078_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16766_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16766_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16766_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16766_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13224: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4577_EN[1:0]$6072, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13224_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13105_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13224_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13224_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13224_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16748: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4536_EN[2:0]$5622, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16748_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15051_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16748_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16748_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16748_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16748_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13197: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4579_EN[1:0]$6087, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13197_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13054_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13197_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13197_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13197_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16730: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4538_EN[2:0]$5687, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16730_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14811_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16730_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16730_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16730_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16730_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13170: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4581_EN[1:0]$6102, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13170_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13003_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13170_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13170_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13170_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16712: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4540_EN[2:0]$5690, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16712_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14784_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16712_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16712_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16712_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16712_Y [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13143: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$4$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4583_EN[1:0]$6117, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13143_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12952_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13143_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13143_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$13143_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16694: + Old ports: A=3'000, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4542_EN[2:0]$5693, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16694_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14757_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16694_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16694_Y [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16694_Y [0] $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16694_Y [0] } + Optimizing cells in module \fpga_neural_v2_top. + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17549: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4588_EN[2:0]$5382, B=3'000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4588_EN[2:0]$4871 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16280_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4588_EN[2:0]$4871 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4588_EN[2:0]$4871 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4588_EN[2:0]$4871 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4588_EN[2:0]$4871 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16670: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4545_EN[1:0]$5759, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16670_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14508_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16670_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16670_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16670_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17540: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4590_EN[2:0]$5385, B=3'000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4590_EN[2:0]$4874 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16262_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4590_EN[2:0]$4874 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4590_EN[2:0]$4874 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4590_EN[2:0]$4874 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4590_EN[2:0]$4874 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16652: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4547_EN[1:0]$5762, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16652_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14481_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16652_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16652_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16652_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17531: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4592_EN[2:0]$5388, B=3'000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4592_EN[2:0]$4877 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16244_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4592_EN[2:0]$4877 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4592_EN[2:0]$4877 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4592_EN[2:0]$4877 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4592_EN[2:0]$4877 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16634: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4549_EN[1:0]$5765, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16634_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14454_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16634_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16634_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16634_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17522: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4594_EN[2:0]$5391, B=3'000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4594_EN[2:0]$4880 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16226_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4594_EN[2:0]$4880 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4594_EN[2:0]$4880 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4594_EN[2:0]$4880 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4594_EN[2:0]$4880 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16616: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4551_EN[1:0]$5768, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16616_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14427_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16616_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16616_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16616_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17513: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4596_EN[2:0]$5394, B=3'000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4596_EN[2:0]$4883 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16208_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4596_EN[2:0]$4883 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4596_EN[2:0]$4883 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4596_EN[2:0]$4883 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4596_EN[2:0]$4883 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16598: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4553_EN[1:0]$5833, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16598_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14187_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16598_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16598_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16598_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17504: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4598_EN[2:0]$5397, B=3'000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4598_EN[2:0]$4886 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16190_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4598_EN[2:0]$4886 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4598_EN[2:0]$4886 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4598_EN[2:0]$4886 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4598_EN[2:0]$4886 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16580: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4555_EN[1:0]$5836, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16580_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14160_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16580_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16580_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16580_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17495: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4600_EN[2:0]$5400, B=3'000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4600_EN[2:0]$4889 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16172_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4600_EN[2:0]$4889 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4600_EN[2:0]$4889 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4600_EN[2:0]$4889 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4600_EN[2:0]$4889 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16562: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4557_EN[1:0]$5839, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16562_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14133_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16562_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16562_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16562_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17486: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4602_EN[2:0]$5403, B=3'000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4602_EN[2:0]$4892 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16154_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4602_EN[2:0]$4892 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4602_EN[2:0]$4892 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4602_EN[2:0]$4892 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4602_EN[2:0]$4892 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16544: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4559_EN[1:0]$5842, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16544_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14106_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16544_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16544_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16544_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17477: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4604_EN[2:0]$5406, B=3'000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4604_EN[2:0]$4895 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16136_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4604_EN[2:0]$4895 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4604_EN[2:0]$4895 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4604_EN[2:0]$4895 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4604_EN[2:0]$4895 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16526: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4561_EN[1:0]$5907, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16526_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13866_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16526_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16526_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16526_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17468: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4606_EN[2:0]$5409, B=3'000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4606_EN[2:0]$4898 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16118_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4606_EN[2:0]$4898 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4606_EN[2:0]$4898 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4606_EN[2:0]$4898 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4606_EN[2:0]$4898 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16508: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4563_EN[1:0]$5910, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16508_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13839_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16508_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16508_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16508_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17459: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4608_EN[2:0]$5412, B=3'000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4608_EN[2:0]$4901 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16100_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4608_EN[2:0]$4901 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4608_EN[2:0]$4901 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4608_EN[2:0]$4901 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4608_EN[2:0]$4901 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16490: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4565_EN[1:0]$5913, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16490_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13812_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16490_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16490_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16490_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17450: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4610_EN[2:0]$5415, B=3'000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4610_EN[2:0]$4904 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16082_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4610_EN[2:0]$4904 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4610_EN[2:0]$4904 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4610_EN[2:0]$4904 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4610_EN[2:0]$4904 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16472: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4567_EN[1:0]$5916, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16472_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13785_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16472_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16472_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16472_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17441: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4612_EN[2:0]$5418, B=3'000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4612_EN[2:0]$4907 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16064_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4612_EN[2:0]$4907 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4612_EN[2:0]$4907 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4612_EN[2:0]$4907 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4612_EN[2:0]$4907 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16454: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4569_EN[1:0]$5981, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16454_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13545_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16454_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16454_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16454_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17432: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4614_EN[2:0]$5421, B=3'000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4614_EN[2:0]$4910 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16046_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4614_EN[2:0]$4910 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4614_EN[2:0]$4910 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4614_EN[2:0]$4910 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4614_EN[2:0]$4910 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16436: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4571_EN[1:0]$5984, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16436_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13518_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16436_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16436_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16436_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17423: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4616_EN[2:0]$5424, B=3'000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4616_EN[2:0]$4913 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16028_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4616_EN[2:0]$4913 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4616_EN[2:0]$4913 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4616_EN[2:0]$4913 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4616_EN[2:0]$4913 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16418: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4573_EN[1:0]$5987, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16418_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13491_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16418_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16418_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16418_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17414: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4618_EN[2:0]$5427, B=3'000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4618_EN[2:0]$4916 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16010_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4618_EN[2:0]$4916 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4618_EN[2:0]$4916 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4618_EN[2:0]$4916 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4618_EN[2:0]$4916 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16400: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4575_EN[1:0]$5990, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16400_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13464_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16400_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16400_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16400_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17405: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4620_EN[2:0]$5430, B=3'000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4620_EN[2:0]$4919 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15992_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4620_EN[2:0]$4919 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4620_EN[2:0]$4919 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4620_EN[2:0]$4919 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4620_EN[2:0]$4919 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16382: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4577_EN[1:0]$6055, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16382_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13224_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16382_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16382_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16382_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17396: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4622_EN[2:0]$5433, B=3'000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4622_EN[2:0]$4922 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15974_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4622_EN[2:0]$4922 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4622_EN[2:0]$4922 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4622_EN[2:0]$4922 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4622_EN[2:0]$4922 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16364: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4579_EN[1:0]$6058, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16364_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13197_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16364_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16364_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16364_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17387: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4624_EN[2:0]$5436, B=3'000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4624_EN[2:0]$4925 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15956_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4624_EN[2:0]$4925 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4624_EN[2:0]$4925 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4624_EN[2:0]$4925 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4624_EN[2:0]$4925 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16346: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4581_EN[1:0]$6061, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16346_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13170_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16346_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16346_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16346_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17378: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4626_EN[2:0]$5439, B=3'000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4626_EN[2:0]$4928 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15938_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4626_EN[2:0]$4928 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4626_EN[2:0]$4928 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4626_EN[2:0]$4928 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4626_EN[2:0]$4928 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16328: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4583_EN[1:0]$6064, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16328_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$13143_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16328_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16328_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16328_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17369: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4628_EN[2:0]$5442, B=3'000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4628_EN[2:0]$4931 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15920_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4628_EN[2:0]$4931 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4628_EN[2:0]$4931 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4628_EN[2:0]$4931 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4628_EN[2:0]$4931 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16310: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4585_EN[1:0]$6129, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16310_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12903_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16310_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16310_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16310_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17360: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4630_EN[2:0]$5445, B=3'000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4630_EN[2:0]$4934 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15902_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4630_EN[2:0]$4934 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4630_EN[2:0]$4934 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4630_EN[2:0]$4934 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4630_EN[2:0]$4934 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16292: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4587_EN[1:0]$6132, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16292_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12876_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16292_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16292_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16292_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17351: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4632_EN[2:0]$5448, B=3'000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4632_EN[2:0]$4937 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15884_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4632_EN[2:0]$4937 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4632_EN[2:0]$4937 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4632_EN[2:0]$4937 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4632_EN[2:0]$4937 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16274: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4589_EN[1:0]$6135, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16274_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12849_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16274_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16274_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16274_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17342: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4634_EN[2:0]$5451, B=3'000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4634_EN[2:0]$4940 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15860_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4634_EN[2:0]$4940 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4634_EN[2:0]$4940 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4634_EN[2:0]$4940 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4634_EN[2:0]$4940 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16256: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4591_EN[1:0]$6138, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16256_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12822_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16256_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16256_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16256_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17333: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4636_EN[2:0]$5454, B=3'000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4636_EN[2:0]$4943 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15842_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4636_EN[2:0]$4943 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4636_EN[2:0]$4943 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4636_EN[2:0]$4943 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4636_EN[2:0]$4943 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16238: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4593_EN[1:0]$6203, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16238_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12582_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16238_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16238_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16238_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17324: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4638_EN[2:0]$5457, B=3'000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4638_EN[2:0]$4946 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15824_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4638_EN[2:0]$4946 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4638_EN[2:0]$4946 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4638_EN[2:0]$4946 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4638_EN[2:0]$4946 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16220: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4595_EN[1:0]$6206, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16220_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12555_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16220_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16220_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16220_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17315: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4640_EN[2:0]$5460, B=3'000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4640_EN[2:0]$4949 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15806_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4640_EN[2:0]$4949 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4640_EN[2:0]$4949 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4640_EN[2:0]$4949 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4640_EN[2:0]$4949 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16202: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4597_EN[1:0]$6209, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16202_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12528_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16202_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16202_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16202_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16184: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4599_EN[1:0]$6212, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16184_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12501_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16184_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16184_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16184_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16166: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4601_EN[1:0]$6277, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16166_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12261_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16166_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16166_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16166_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16148: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4603_EN[1:0]$6280, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16148_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12234_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16148_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16148_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16148_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16130: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4605_EN[1:0]$6283, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16130_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12207_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16130_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16130_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16130_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16112: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4607_EN[1:0]$6286, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16112_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$12180_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16112_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16112_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16112_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16094: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4609_EN[1:0]$6351, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16094_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11940_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16094_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16094_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16094_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16076: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4611_EN[1:0]$6354, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16076_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11913_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16076_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16076_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16076_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16058: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4613_EN[1:0]$6357, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16058_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11886_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16058_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16058_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16058_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16040: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4615_EN[1:0]$6360, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16040_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11859_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16040_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16040_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16040_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16022: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4617_EN[1:0]$6425, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16022_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11619_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16022_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16022_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16022_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16004: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4619_EN[1:0]$6428, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16004_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11592_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16004_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16004_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16004_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15986: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4621_EN[1:0]$6431, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15986_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11565_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15986_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15986_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15986_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15968: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4623_EN[1:0]$6434, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15968_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11538_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15968_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15968_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15968_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15950: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4625_EN[1:0]$6499, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15950_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11298_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15950_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15950_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15950_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15932: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4627_EN[1:0]$6502, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15932_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11271_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15932_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15932_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15932_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15914: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4629_EN[1:0]$6505, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15914_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11244_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15914_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15914_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15914_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17783: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4536_EN[2:0]$5304, B=3'000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4536_EN[2:0]$4793 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16748_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4536_EN[2:0]$4793 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4536_EN[2:0]$4793 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4536_EN[2:0]$4793 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4536_EN[2:0]$4793 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15896: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4631_EN[1:0]$6508, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15896_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$11217_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15896_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15896_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15896_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15872: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4633_EN[1:0]$6573, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15872_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$10977_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15872_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15872_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15872_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17774: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4538_EN[2:0]$5307, B=3'000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4538_EN[2:0]$4796 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16730_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4538_EN[2:0]$4796 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4538_EN[2:0]$4796 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4538_EN[2:0]$4796 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4538_EN[2:0]$4796 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15854: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4635_EN[1:0]$6576, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15854_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$10950_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15854_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15854_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15854_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15836: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4637_EN[1:0]$6579, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15836_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$10923_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15836_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15836_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15836_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17765: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4540_EN[2:0]$5310, B=3'000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4540_EN[2:0]$4799 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16712_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4540_EN[2:0]$4799 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4540_EN[2:0]$4799 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4540_EN[2:0]$4799 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4540_EN[2:0]$4799 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15818: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4639_EN[1:0]$6582, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15818_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$10896_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15818_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15818_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$15818_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17756: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4542_EN[2:0]$5313, B=3'000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4542_EN[2:0]$4802 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16694_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4542_EN[2:0]$4802 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4542_EN[2:0]$4802 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4542_EN[2:0]$4802 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4542_EN[2:0]$4802 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17747: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4544_EN[2:0]$5316, B=3'000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4544_EN[2:0]$4805 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16676_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4544_EN[2:0]$4805 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4544_EN[2:0]$4805 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4544_EN[2:0]$4805 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4544_EN[2:0]$4805 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17738: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4546_EN[2:0]$5319, B=3'000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4546_EN[2:0]$4808 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16658_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4546_EN[2:0]$4808 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4546_EN[2:0]$4808 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4546_EN[2:0]$4808 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4546_EN[2:0]$4808 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17729: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4548_EN[2:0]$5322, B=3'000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4548_EN[2:0]$4811 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16640_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4548_EN[2:0]$4811 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4548_EN[2:0]$4811 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4548_EN[2:0]$4811 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4548_EN[2:0]$4811 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17720: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4550_EN[2:0]$5325, B=3'000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4550_EN[2:0]$4814 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16622_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4550_EN[2:0]$4814 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4550_EN[2:0]$4814 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4550_EN[2:0]$4814 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4550_EN[2:0]$4814 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17711: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4552_EN[2:0]$5328, B=3'000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4552_EN[2:0]$4817 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16604_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4552_EN[2:0]$4817 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4552_EN[2:0]$4817 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4552_EN[2:0]$4817 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4552_EN[2:0]$4817 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17702: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4554_EN[2:0]$5331, B=3'000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4554_EN[2:0]$4820 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16586_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4554_EN[2:0]$4820 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4554_EN[2:0]$4820 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4554_EN[2:0]$4820 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4554_EN[2:0]$4820 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17693: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4556_EN[2:0]$5334, B=3'000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4556_EN[2:0]$4823 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16568_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4556_EN[2:0]$4823 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4556_EN[2:0]$4823 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4556_EN[2:0]$4823 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4556_EN[2:0]$4823 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16958: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4513_EN[1:0]$5463, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16958_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15792_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16958_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16958_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16958_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17684: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4558_EN[2:0]$5337, B=3'000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4558_EN[2:0]$4826 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16550_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4558_EN[2:0]$4826 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4558_EN[2:0]$4826 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4558_EN[2:0]$4826 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4558_EN[2:0]$4826 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16940: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4515_EN[1:0]$5466, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16940_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15765_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16940_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16940_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16940_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17675: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4560_EN[2:0]$5340, B=3'000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4560_EN[2:0]$4829 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16532_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4560_EN[2:0]$4829 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4560_EN[2:0]$4829 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4560_EN[2:0]$4829 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4560_EN[2:0]$4829 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16922: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4517_EN[1:0]$5469, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16922_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15738_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16922_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16922_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16922_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17666: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4562_EN[2:0]$5343, B=3'000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4562_EN[2:0]$4832 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16514_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4562_EN[2:0]$4832 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4562_EN[2:0]$4832 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4562_EN[2:0]$4832 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4562_EN[2:0]$4832 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16904: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4519_EN[1:0]$5472, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16904_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15711_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16904_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16904_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16904_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17657: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4564_EN[2:0]$5346, B=3'000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4564_EN[2:0]$4835 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16496_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4564_EN[2:0]$4835 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4564_EN[2:0]$4835 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4564_EN[2:0]$4835 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4564_EN[2:0]$4835 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16886: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4521_EN[1:0]$5537, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16886_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15471_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16886_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16886_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16886_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17648: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4566_EN[2:0]$5349, B=3'000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4566_EN[2:0]$4838 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16478_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4566_EN[2:0]$4838 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4566_EN[2:0]$4838 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4566_EN[2:0]$4838 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4566_EN[2:0]$4838 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16868: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4523_EN[1:0]$5540, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16868_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15444_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16868_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16868_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16868_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17639: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4568_EN[2:0]$5352, B=3'000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4568_EN[2:0]$4841 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16460_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4568_EN[2:0]$4841 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4568_EN[2:0]$4841 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4568_EN[2:0]$4841 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4568_EN[2:0]$4841 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17882: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4514_EN[2:0]$5271, B=3'000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4514_EN[2:0]$4760 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16946_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4514_EN[2:0]$4760 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4514_EN[2:0]$4760 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4514_EN[2:0]$4760 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4514_EN[2:0]$4760 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17873: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4516_EN[2:0]$5274, B=3'000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4516_EN[2:0]$4763 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16928_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4516_EN[2:0]$4763 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4516_EN[2:0]$4763 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4516_EN[2:0]$4763 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4516_EN[2:0]$4763 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17864: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4518_EN[2:0]$5277, B=3'000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4518_EN[2:0]$4766 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16910_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4518_EN[2:0]$4766 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4518_EN[2:0]$4766 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4518_EN[2:0]$4766 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4518_EN[2:0]$4766 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17855: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4520_EN[2:0]$5280, B=3'000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4520_EN[2:0]$4769 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16892_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4520_EN[2:0]$4769 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4520_EN[2:0]$4769 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4520_EN[2:0]$4769 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4520_EN[2:0]$4769 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17846: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4522_EN[2:0]$5283, B=3'000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4522_EN[2:0]$4772 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16874_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4522_EN[2:0]$4772 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4522_EN[2:0]$4772 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4522_EN[2:0]$4772 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4522_EN[2:0]$4772 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17837: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4524_EN[2:0]$5286, B=3'000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4524_EN[2:0]$4775 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16856_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4524_EN[2:0]$4775 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4524_EN[2:0]$4775 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4524_EN[2:0]$4775 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4524_EN[2:0]$4775 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17828: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4526_EN[2:0]$5289, B=3'000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4526_EN[2:0]$4778 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16838_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4526_EN[2:0]$4778 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4526_EN[2:0]$4778 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4526_EN[2:0]$4778 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4526_EN[2:0]$4778 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17819: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4528_EN[2:0]$5292, B=3'000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4528_EN[2:0]$4781 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16820_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4528_EN[2:0]$4781 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4528_EN[2:0]$4781 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4528_EN[2:0]$4781 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4528_EN[2:0]$4781 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17810: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4530_EN[2:0]$5295, B=3'000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4530_EN[2:0]$4784 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16802_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4530_EN[2:0]$4784 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4530_EN[2:0]$4784 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4530_EN[2:0]$4784 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4530_EN[2:0]$4784 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17801: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4532_EN[2:0]$5298, B=3'000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4532_EN[2:0]$4787 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16784_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4532_EN[2:0]$4787 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4532_EN[2:0]$4787 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4532_EN[2:0]$4787 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4532_EN[2:0]$4787 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16850: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4525_EN[1:0]$5543, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16850_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15417_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16850_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16850_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16850_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17630: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4570_EN[2:0]$5355, B=3'000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4570_EN[2:0]$4844 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16442_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4570_EN[2:0]$4844 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4570_EN[2:0]$4844 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4570_EN[2:0]$4844 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4570_EN[2:0]$4844 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16832: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4527_EN[1:0]$5546, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16832_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15390_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16832_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16832_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16832_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17621: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4572_EN[2:0]$5358, B=3'000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4572_EN[2:0]$4847 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16424_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4572_EN[2:0]$4847 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4572_EN[2:0]$4847 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4572_EN[2:0]$4847 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4572_EN[2:0]$4847 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17792: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4534_EN[2:0]$5301, B=3'000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4534_EN[2:0]$4790 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16766_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4534_EN[2:0]$4790 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4534_EN[2:0]$4790 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4534_EN[2:0]$4790 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4534_EN[2:0]$4790 [0] } + Consolidated identical input bits for $mux cell $flatten\u_sdram_backend.$procmux$9396: + Old ports: A=$flatten\u_sdram_backend.$2$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$7013, B=64'0000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$6977 + New ports: A=$flatten\u_sdram_backend.$procmux$9280_Y [0], B=1'0, Y=$flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$6977 [0] + New connections: $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$6977 [63:1] = { $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$6977 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$6977 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$6977 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$6977 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$6977 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$6977 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$6977 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$6977 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$6977 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$6977 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$6977 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$6977 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$6977 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$6977 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$6977 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$6977 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$6977 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$6977 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$6977 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$6977 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$6977 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$6977 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$6977 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$6977 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$6977 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$6977 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$6977 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$6977 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$6977 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$6977 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$6977 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$6977 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$6977 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$6977 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$6977 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$6977 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$6977 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$6977 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$6977 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$6977 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$6977 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$6977 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$6977 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$6977 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$6977 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$6977 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$6977 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$6977 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$6977 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$6977 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$6977 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$6977 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$6977 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$6977 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$6977 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$6977 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$6977 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$6977 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$6977 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$6977 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$6977 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$6977 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:291$6937_EN[63:0]$6977 [0] } + Consolidated identical input bits for $mux cell $flatten\u_sdram_backend.$procmux$9387: + Old ports: A=$flatten\u_sdram_backend.$2$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:292$6938_EN[22:0]$7016, B=23'00000000000000000000000, Y=$flatten\u_sdram_backend.$0$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:292$6938_EN[22:0]$6980 + New ports: A=$flatten\u_sdram_backend.$procmux$9256_Y [0], B=1'0, Y=$flatten\u_sdram_backend.$0$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:292$6938_EN[22:0]$6980 [0] + New connections: $flatten\u_sdram_backend.$0$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:292$6938_EN[22:0]$6980 [22:1] = { $flatten\u_sdram_backend.$0$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:292$6938_EN[22:0]$6980 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:292$6938_EN[22:0]$6980 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:292$6938_EN[22:0]$6980 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:292$6938_EN[22:0]$6980 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:292$6938_EN[22:0]$6980 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:292$6938_EN[22:0]$6980 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:292$6938_EN[22:0]$6980 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:292$6938_EN[22:0]$6980 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:292$6938_EN[22:0]$6980 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:292$6938_EN[22:0]$6980 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:292$6938_EN[22:0]$6980 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:292$6938_EN[22:0]$6980 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:292$6938_EN[22:0]$6980 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:292$6938_EN[22:0]$6980 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:292$6938_EN[22:0]$6980 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:292$6938_EN[22:0]$6980 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:292$6938_EN[22:0]$6980 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:292$6938_EN[22:0]$6980 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:292$6938_EN[22:0]$6980 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:292$6938_EN[22:0]$6980 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:292$6938_EN[22:0]$6980 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:292$6938_EN[22:0]$6980 [0] } + Consolidated identical input bits for $mux cell $flatten\u_sdram_backend.$procmux$9378: + Old ports: A=$flatten\u_sdram_backend.$2$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$7019, B=64'0000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$6983 + New ports: A=$flatten\u_sdram_backend.$procmux$9232_Y [0], B=1'0, Y=$flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$6983 [0] + New connections: $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$6983 [63:1] = { $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$6983 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$6983 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$6983 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$6983 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$6983 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$6983 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$6983 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$6983 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$6983 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$6983 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$6983 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$6983 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$6983 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$6983 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$6983 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$6983 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$6983 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$6983 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$6983 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$6983 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$6983 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$6983 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$6983 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$6983 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$6983 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$6983 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$6983 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$6983 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$6983 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$6983 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$6983 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$6983 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$6983 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$6983 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$6983 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$6983 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$6983 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$6983 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$6983 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$6983 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$6983 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$6983 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$6983 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$6983 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$6983 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$6983 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$6983 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$6983 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$6983 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$6983 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$6983 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$6983 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$6983 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$6983 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$6983 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$6983 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$6983 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$6983 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$6983 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$6983 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$6983 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$6983 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:295$6939_EN[63:0]$6983 [0] } + Consolidated identical input bits for $mux cell $flatten\u_sdram_backend.$procmux$9369: + Old ports: A=$flatten\u_sdram_backend.$2$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:296$6940_EN[22:0]$7022, B=23'00000000000000000000000, Y=$flatten\u_sdram_backend.$0$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:296$6940_EN[22:0]$6986 + New ports: A=$flatten\u_sdram_backend.$procmux$9208_Y [0], B=1'0, Y=$flatten\u_sdram_backend.$0$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:296$6940_EN[22:0]$6986 [0] + New connections: $flatten\u_sdram_backend.$0$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:296$6940_EN[22:0]$6986 [22:1] = { $flatten\u_sdram_backend.$0$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:296$6940_EN[22:0]$6986 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:296$6940_EN[22:0]$6986 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:296$6940_EN[22:0]$6986 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:296$6940_EN[22:0]$6986 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:296$6940_EN[22:0]$6986 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:296$6940_EN[22:0]$6986 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:296$6940_EN[22:0]$6986 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:296$6940_EN[22:0]$6986 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:296$6940_EN[22:0]$6986 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:296$6940_EN[22:0]$6986 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:296$6940_EN[22:0]$6986 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:296$6940_EN[22:0]$6986 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:296$6940_EN[22:0]$6986 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:296$6940_EN[22:0]$6986 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:296$6940_EN[22:0]$6986 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:296$6940_EN[22:0]$6986 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:296$6940_EN[22:0]$6986 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:296$6940_EN[22:0]$6986 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:296$6940_EN[22:0]$6986 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:296$6940_EN[22:0]$6986 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:296$6940_EN[22:0]$6986 [0] $flatten\u_sdram_backend.$0$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:296$6940_EN[22:0]$6986 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16814: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4529_EN[1:0]$5611, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16814_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15150_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16814_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16814_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16814_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17612: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4574_EN[2:0]$5361, B=3'000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4574_EN[2:0]$4850 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16406_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4574_EN[2:0]$4850 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4574_EN[2:0]$4850 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4574_EN[2:0]$4850 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4574_EN[2:0]$4850 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16796: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4531_EN[1:0]$5614, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16796_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15123_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16796_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16796_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16796_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17603: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4576_EN[2:0]$5364, B=3'000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4576_EN[2:0]$4853 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16388_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4576_EN[2:0]$4853 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4576_EN[2:0]$4853 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4576_EN[2:0]$4853 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4576_EN[2:0]$4853 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16778: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4533_EN[1:0]$5617, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16778_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15096_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16778_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16778_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16778_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17594: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4578_EN[2:0]$5367, B=3'000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4578_EN[2:0]$4856 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16370_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4578_EN[2:0]$4856 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4578_EN[2:0]$4856 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4578_EN[2:0]$4856 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4578_EN[2:0]$4856 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16760: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4535_EN[1:0]$5620, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16760_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15069_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16760_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16760_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16760_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17585: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4580_EN[2:0]$5370, B=3'000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4580_EN[2:0]$4859 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16352_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4580_EN[2:0]$4859 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4580_EN[2:0]$4859 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4580_EN[2:0]$4859 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4580_EN[2:0]$4859 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16742: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4537_EN[1:0]$5685, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16742_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14829_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16742_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16742_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16742_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17576: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4582_EN[2:0]$5373, B=3'000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4582_EN[2:0]$4862 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16334_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4582_EN[2:0]$4862 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4582_EN[2:0]$4862 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4582_EN[2:0]$4862 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4582_EN[2:0]$4862 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16724: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4539_EN[1:0]$5688, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16724_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14802_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16724_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16724_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16724_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17567: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4584_EN[2:0]$5376, B=3'000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4584_EN[2:0]$4865 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16316_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4584_EN[2:0]$4865 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4584_EN[2:0]$4865 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4584_EN[2:0]$4865 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4584_EN[2:0]$4865 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16706: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4541_EN[1:0]$5691, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16706_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14775_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16706_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16706_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16706_Y [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17558: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4586_EN[2:0]$5379, B=3'000, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4586_EN[2:0]$4868 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16298_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4586_EN[2:0]$4868 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4586_EN[2:0]$4868 [2:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4586_EN[2:0]$4868 [0] $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$4586_EN[2:0]$4868 [0] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16688: + Old ports: A=2'00, B=$flatten\u_dataflow_core.\u_dep_mgr.$3$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4543_EN[1:0]$5694, Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16688_Y + New ports: A=1'0, B=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$14748_Y [0], Y=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16688_Y [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16688_Y [1] = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$16688_Y [0] + Optimizing cells in module \fpga_neural_v2_top. + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17546: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4589_EN[1:0]$5383, B=2'00, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4589_EN[1:0]$4872 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16274_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4589_EN[1:0]$4872 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4589_EN[1:0]$4872 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4589_EN[1:0]$4872 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17537: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4591_EN[1:0]$5386, B=2'00, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4591_EN[1:0]$4875 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16256_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4591_EN[1:0]$4875 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4591_EN[1:0]$4875 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4591_EN[1:0]$4875 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17528: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4593_EN[1:0]$5389, B=2'00, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4593_EN[1:0]$4878 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16238_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4593_EN[1:0]$4878 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4593_EN[1:0]$4878 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4593_EN[1:0]$4878 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17519: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4595_EN[1:0]$5392, B=2'00, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4595_EN[1:0]$4881 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16220_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4595_EN[1:0]$4881 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4595_EN[1:0]$4881 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4595_EN[1:0]$4881 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17510: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4597_EN[1:0]$5395, B=2'00, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4597_EN[1:0]$4884 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16202_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4597_EN[1:0]$4884 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4597_EN[1:0]$4884 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4597_EN[1:0]$4884 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17501: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4599_EN[1:0]$5398, B=2'00, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4599_EN[1:0]$4887 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16184_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4599_EN[1:0]$4887 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4599_EN[1:0]$4887 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4599_EN[1:0]$4887 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17492: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4601_EN[1:0]$5401, B=2'00, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4601_EN[1:0]$4890 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16166_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4601_EN[1:0]$4890 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4601_EN[1:0]$4890 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4601_EN[1:0]$4890 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17483: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4603_EN[1:0]$5404, B=2'00, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4603_EN[1:0]$4893 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16148_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4603_EN[1:0]$4893 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4603_EN[1:0]$4893 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4603_EN[1:0]$4893 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17474: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4605_EN[1:0]$5407, B=2'00, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4605_EN[1:0]$4896 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16130_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4605_EN[1:0]$4896 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4605_EN[1:0]$4896 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4605_EN[1:0]$4896 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17465: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4607_EN[1:0]$5410, B=2'00, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4607_EN[1:0]$4899 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16112_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4607_EN[1:0]$4899 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4607_EN[1:0]$4899 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4607_EN[1:0]$4899 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17456: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4609_EN[1:0]$5413, B=2'00, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4609_EN[1:0]$4902 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16094_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4609_EN[1:0]$4902 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4609_EN[1:0]$4902 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4609_EN[1:0]$4902 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17447: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4611_EN[1:0]$5416, B=2'00, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4611_EN[1:0]$4905 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16076_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4611_EN[1:0]$4905 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4611_EN[1:0]$4905 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4611_EN[1:0]$4905 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17438: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4613_EN[1:0]$5419, B=2'00, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4613_EN[1:0]$4908 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16058_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4613_EN[1:0]$4908 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4613_EN[1:0]$4908 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4613_EN[1:0]$4908 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17429: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4615_EN[1:0]$5422, B=2'00, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4615_EN[1:0]$4911 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16040_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4615_EN[1:0]$4911 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4615_EN[1:0]$4911 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4615_EN[1:0]$4911 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17420: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4617_EN[1:0]$5425, B=2'00, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4617_EN[1:0]$4914 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16022_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4617_EN[1:0]$4914 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4617_EN[1:0]$4914 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4617_EN[1:0]$4914 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17411: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4619_EN[1:0]$5428, B=2'00, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4619_EN[1:0]$4917 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16004_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4619_EN[1:0]$4917 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4619_EN[1:0]$4917 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4619_EN[1:0]$4917 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17402: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4621_EN[1:0]$5431, B=2'00, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4621_EN[1:0]$4920 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15986_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4621_EN[1:0]$4920 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4621_EN[1:0]$4920 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4621_EN[1:0]$4920 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17393: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4623_EN[1:0]$5434, B=2'00, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4623_EN[1:0]$4923 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15968_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4623_EN[1:0]$4923 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4623_EN[1:0]$4923 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4623_EN[1:0]$4923 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17384: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4625_EN[1:0]$5437, B=2'00, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4625_EN[1:0]$4926 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15950_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4625_EN[1:0]$4926 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4625_EN[1:0]$4926 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4625_EN[1:0]$4926 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17375: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4627_EN[1:0]$5440, B=2'00, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4627_EN[1:0]$4929 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15932_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4627_EN[1:0]$4929 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4627_EN[1:0]$4929 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4627_EN[1:0]$4929 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17366: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4629_EN[1:0]$5443, B=2'00, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4629_EN[1:0]$4932 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15914_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4629_EN[1:0]$4932 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4629_EN[1:0]$4932 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4629_EN[1:0]$4932 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17357: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4631_EN[1:0]$5446, B=2'00, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4631_EN[1:0]$4935 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15896_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4631_EN[1:0]$4935 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4631_EN[1:0]$4935 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4631_EN[1:0]$4935 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17348: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4633_EN[1:0]$5449, B=2'00, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4633_EN[1:0]$4938 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15872_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4633_EN[1:0]$4938 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4633_EN[1:0]$4938 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4633_EN[1:0]$4938 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17339: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4635_EN[1:0]$5452, B=2'00, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4635_EN[1:0]$4941 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15854_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4635_EN[1:0]$4941 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4635_EN[1:0]$4941 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4635_EN[1:0]$4941 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17330: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4637_EN[1:0]$5455, B=2'00, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4637_EN[1:0]$4944 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15836_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4637_EN[1:0]$4944 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4637_EN[1:0]$4944 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4637_EN[1:0]$4944 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17321: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4639_EN[1:0]$5458, B=2'00, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4639_EN[1:0]$4947 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$15818_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4639_EN[1:0]$4947 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4639_EN[1:0]$4947 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4639_EN[1:0]$4947 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17780: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4537_EN[1:0]$5305, B=2'00, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4537_EN[1:0]$4794 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16742_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4537_EN[1:0]$4794 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4537_EN[1:0]$4794 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4537_EN[1:0]$4794 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17771: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4539_EN[1:0]$5308, B=2'00, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4539_EN[1:0]$4797 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16724_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4539_EN[1:0]$4797 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4539_EN[1:0]$4797 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4539_EN[1:0]$4797 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17762: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4541_EN[1:0]$5311, B=2'00, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4541_EN[1:0]$4800 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16706_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4541_EN[1:0]$4800 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4541_EN[1:0]$4800 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4541_EN[1:0]$4800 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17753: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4543_EN[1:0]$5314, B=2'00, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4543_EN[1:0]$4803 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16688_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4543_EN[1:0]$4803 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4543_EN[1:0]$4803 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4543_EN[1:0]$4803 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17744: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4545_EN[1:0]$5317, B=2'00, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4545_EN[1:0]$4806 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16670_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4545_EN[1:0]$4806 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4545_EN[1:0]$4806 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4545_EN[1:0]$4806 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17735: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4547_EN[1:0]$5320, B=2'00, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4547_EN[1:0]$4809 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16652_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4547_EN[1:0]$4809 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4547_EN[1:0]$4809 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4547_EN[1:0]$4809 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17726: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4549_EN[1:0]$5323, B=2'00, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4549_EN[1:0]$4812 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16634_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4549_EN[1:0]$4812 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4549_EN[1:0]$4812 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4549_EN[1:0]$4812 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17717: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4551_EN[1:0]$5326, B=2'00, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4551_EN[1:0]$4815 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16616_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4551_EN[1:0]$4815 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4551_EN[1:0]$4815 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4551_EN[1:0]$4815 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17708: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4553_EN[1:0]$5329, B=2'00, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4553_EN[1:0]$4818 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16598_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4553_EN[1:0]$4818 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4553_EN[1:0]$4818 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4553_EN[1:0]$4818 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17699: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4555_EN[1:0]$5332, B=2'00, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4555_EN[1:0]$4821 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16580_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4555_EN[1:0]$4821 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4555_EN[1:0]$4821 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4555_EN[1:0]$4821 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17690: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4557_EN[1:0]$5335, B=2'00, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4557_EN[1:0]$4824 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16562_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4557_EN[1:0]$4824 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4557_EN[1:0]$4824 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4557_EN[1:0]$4824 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17681: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4559_EN[1:0]$5338, B=2'00, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4559_EN[1:0]$4827 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16544_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4559_EN[1:0]$4827 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4559_EN[1:0]$4827 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4559_EN[1:0]$4827 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17672: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4561_EN[1:0]$5341, B=2'00, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4561_EN[1:0]$4830 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16526_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4561_EN[1:0]$4830 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4561_EN[1:0]$4830 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4561_EN[1:0]$4830 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17663: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4563_EN[1:0]$5344, B=2'00, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4563_EN[1:0]$4833 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16508_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4563_EN[1:0]$4833 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4563_EN[1:0]$4833 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4563_EN[1:0]$4833 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17654: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4565_EN[1:0]$5347, B=2'00, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4565_EN[1:0]$4836 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16490_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4565_EN[1:0]$4836 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4565_EN[1:0]$4836 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4565_EN[1:0]$4836 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17645: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4567_EN[1:0]$5350, B=2'00, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4567_EN[1:0]$4839 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16472_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4567_EN[1:0]$4839 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4567_EN[1:0]$4839 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4567_EN[1:0]$4839 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17888: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4513_EN[1:0]$5269, B=2'00, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4513_EN[1:0]$4758 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16958_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4513_EN[1:0]$4758 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4513_EN[1:0]$4758 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4513_EN[1:0]$4758 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17879: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4515_EN[1:0]$5272, B=2'00, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4515_EN[1:0]$4761 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16940_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4515_EN[1:0]$4761 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4515_EN[1:0]$4761 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4515_EN[1:0]$4761 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17870: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4517_EN[1:0]$5275, B=2'00, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4517_EN[1:0]$4764 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16922_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4517_EN[1:0]$4764 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4517_EN[1:0]$4764 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4517_EN[1:0]$4764 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17861: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4519_EN[1:0]$5278, B=2'00, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4519_EN[1:0]$4767 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16904_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4519_EN[1:0]$4767 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4519_EN[1:0]$4767 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4519_EN[1:0]$4767 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17852: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4521_EN[1:0]$5281, B=2'00, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4521_EN[1:0]$4770 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16886_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4521_EN[1:0]$4770 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4521_EN[1:0]$4770 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4521_EN[1:0]$4770 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17843: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4523_EN[1:0]$5284, B=2'00, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4523_EN[1:0]$4773 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16868_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4523_EN[1:0]$4773 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4523_EN[1:0]$4773 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4523_EN[1:0]$4773 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17834: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4525_EN[1:0]$5287, B=2'00, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4525_EN[1:0]$4776 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16850_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4525_EN[1:0]$4776 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4525_EN[1:0]$4776 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4525_EN[1:0]$4776 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17825: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4527_EN[1:0]$5290, B=2'00, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4527_EN[1:0]$4779 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16832_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4527_EN[1:0]$4779 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4527_EN[1:0]$4779 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4527_EN[1:0]$4779 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17816: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4529_EN[1:0]$5293, B=2'00, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4529_EN[1:0]$4782 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16814_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4529_EN[1:0]$4782 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4529_EN[1:0]$4782 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4529_EN[1:0]$4782 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17807: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4531_EN[1:0]$5296, B=2'00, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4531_EN[1:0]$4785 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16796_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4531_EN[1:0]$4785 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4531_EN[1:0]$4785 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4531_EN[1:0]$4785 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17636: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4569_EN[1:0]$5353, B=2'00, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4569_EN[1:0]$4842 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16454_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4569_EN[1:0]$4842 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4569_EN[1:0]$4842 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4569_EN[1:0]$4842 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17627: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4571_EN[1:0]$5356, B=2'00, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4571_EN[1:0]$4845 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16436_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4571_EN[1:0]$4845 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4571_EN[1:0]$4845 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4571_EN[1:0]$4845 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17798: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4533_EN[1:0]$5299, B=2'00, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4533_EN[1:0]$4788 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16778_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4533_EN[1:0]$4788 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4533_EN[1:0]$4788 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4533_EN[1:0]$4788 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17789: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4535_EN[1:0]$5302, B=2'00, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4535_EN[1:0]$4791 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16760_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4535_EN[1:0]$4791 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4535_EN[1:0]$4791 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4535_EN[1:0]$4791 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17618: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4573_EN[1:0]$5359, B=2'00, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4573_EN[1:0]$4848 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16418_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4573_EN[1:0]$4848 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4573_EN[1:0]$4848 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4573_EN[1:0]$4848 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17609: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4575_EN[1:0]$5362, B=2'00, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4575_EN[1:0]$4851 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16400_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4575_EN[1:0]$4851 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4575_EN[1:0]$4851 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4575_EN[1:0]$4851 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17600: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4577_EN[1:0]$5365, B=2'00, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4577_EN[1:0]$4854 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16382_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4577_EN[1:0]$4854 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4577_EN[1:0]$4854 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4577_EN[1:0]$4854 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17591: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4579_EN[1:0]$5368, B=2'00, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4579_EN[1:0]$4857 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16364_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4579_EN[1:0]$4857 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4579_EN[1:0]$4857 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4579_EN[1:0]$4857 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17582: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4581_EN[1:0]$5371, B=2'00, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4581_EN[1:0]$4860 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16346_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4581_EN[1:0]$4860 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4581_EN[1:0]$4860 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4581_EN[1:0]$4860 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17573: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4583_EN[1:0]$5374, B=2'00, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4583_EN[1:0]$4863 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16328_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4583_EN[1:0]$4863 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4583_EN[1:0]$4863 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4583_EN[1:0]$4863 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17564: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4585_EN[1:0]$5377, B=2'00, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4585_EN[1:0]$4866 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16310_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4585_EN[1:0]$4866 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4585_EN[1:0]$4866 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4585_EN[1:0]$4866 [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$17555: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4587_EN[1:0]$5380, B=2'00, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4587_EN[1:0]$4869 + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$procmux$16292_Y [0], B=1'0, Y=$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4587_EN[1:0]$4869 [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4587_EN[1:0]$4869 [1] = $flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_state$hardware/v2/rtl/dependency_manager.v:153$4587_EN[1:0]$4869 [0] + Optimizing cells in module \fpga_neural_v2_top. +Performed a total of 712 changes. + +19.12.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\fpga_neural_v2_top'. +Computing hashes of 4834 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. +Computing hashes of 4605 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. +Computing hashes of 4570 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. +Computing hashes of 4566 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. +Computing hashes of 4562 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. + +Removed a total of 272 cells. + +19.12.6. Executing OPT_DFF pass (perform DFF optimizations). + +19.12.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \fpga_neural_v2_top.. +Removed 0 unused cells and 2708 unused wires. + + +19.12.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module fpga_neural_v2_top. + + +19.12.9. Rerunning OPT passes. (Maybe there is more to do..) + +19.12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \fpga_neural_v2_top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +19.12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \fpga_neural_v2_top. + New ctrl vector for $pmux cell $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10136: { $auto$opt_reduce.cc:137:opt_pmux$21032 $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10079_CMP $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10083_CMP $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10091_CMP $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10012_CMP $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10128_CMP $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10178_CMP $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10186_CMP } + New ctrl vector for $pmux cell $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10271: { $auto$opt_reduce.cc:137:opt_pmux$21034 $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10079_CMP $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10083_CMP $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10087_CMP $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10091_CMP $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10012_CMP $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10128_CMP $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10178_CMP $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10182_CMP $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10186_CMP } + New ctrl vector for $pmux cell $flatten\u_sdram_backend.$procmux$9648: { $auto$opt_reduce.cc:137:opt_pmux$21036 $flatten\u_sdram_backend.$procmux$9155_CMP } + New ctrl vector for $pmux cell $flatten\u_sdram_backend.$procmux$9304: $auto$opt_reduce.cc:137:opt_pmux$21038 + New ctrl vector for $pmux cell $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$9758: { $auto$opt_reduce.cc:137:opt_pmux$21040 $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10012_CMP $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10128_CMP } + Optimizing cells in module \fpga_neural_v2_top. +Performed a total of 5 changes. + +19.12.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\fpga_neural_v2_top'. +Computing hashes of 4549 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. +Removed a total of 0 cells. + +19.12.13. Executing OPT_DFF pass (perform DFF optimizations). + +19.12.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \fpga_neural_v2_top.. +Removed 0 unused cells and 18 unused wires. + + +19.12.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module fpga_neural_v2_top. + +19.12.16. Rerunning OPT passes. (Maybe there is more to do..) + +19.12.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \fpga_neural_v2_top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +19.12.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \fpga_neural_v2_top. +Performed a total of 0 changes. + +19.12.19. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\fpga_neural_v2_top'. +Computing hashes of 4549 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. +Removed a total of 0 cells. + +19.12.20. Executing OPT_DFF pass (perform DFF optimizations). + +19.12.21. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \fpga_neural_v2_top.. + +19.12.22. Executing OPT_EXPR pass (perform const folding). +Optimizing module fpga_neural_v2_top. + +19.12.23. Finished fast OPT passes. (There is nothing left to do.) + +19.13. Executing FSM pass (extract and optimize FSM). + +19.13.1. Executing FSM_DETECT pass (finding FSMs in design). +Not marking fpga_neural_v2_top.u_arbiter.s_ready as FSM state register: + Users of register don't seem to benefit from recoding. +Found FSM state register fpga_neural_v2_top.u_dataflow_core.GEN_SLOT[0].u_mm.state. +Found FSM state register fpga_neural_v2_top.u_dataflow_core.u_director.dir_state. +Not marking fpga_neural_v2_top.u_dataflow_core.u_director.job_out_slot as FSM state register: + Users of register don't seem to benefit from recoding. +Not marking fpga_neural_v2_top.u_host_arb.s_ready as FSM state register: + Users of register don't seem to benefit from recoding. +Found FSM state register fpga_neural_v2_top.u_dataflow_core.GEN_SLOT[0].u_np.activation_reg. +Not marking fpga_neural_v2_top.u_dataflow_core.GEN_SLOT[0].u_np.bias_reg as FSM state register: + Users of register don't seem to benefit from recoding. +Found FSM state register fpga_neural_v2_top.u_dataflow_core.GEN_SLOT[0].u_np.np_state. +Not marking fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.ready_node_id as FSM state register: + Users of register don't seem to benefit from recoding. +Found FSM state register fpga_neural_v2_top.u_dataflow_core.GEN_SLOT[1].u_mm.state. +Not marking fpga_neural_v2_top.u_arbiter_wide.s_ready as FSM state register: + Users of register don't seem to benefit from recoding. +Found FSM state register fpga_neural_v2_top.u_sdram_backend.u_sdram_ctrl.state. +Found FSM state register fpga_neural_v2_top.u_dataflow_core.GEN_SLOT[1].u_np.activation_reg. +Not marking fpga_neural_v2_top.u_dataflow_core.GEN_SLOT[1].u_np.bias_reg as FSM state register: + Users of register don't seem to benefit from recoding. +Found FSM state register fpga_neural_v2_top.u_dataflow_core.GEN_SLOT[1].u_np.np_state. +Found FSM state register fpga_neural_v2_top.u_dataflow_core.GEN_SLOT[2].u_mm.state. +Found FSM state register fpga_neural_v2_top.u_dataflow_core.GEN_SLOT[2].u_np.activation_reg. +Not marking fpga_neural_v2_top.u_dataflow_core.GEN_SLOT[2].u_np.bias_reg as FSM state register: + Users of register don't seem to benefit from recoding. +Found FSM state register fpga_neural_v2_top.u_dataflow_core.GEN_SLOT[2].u_np.np_state. +Found FSM state register fpga_neural_v2_top.u_dataflow_core.GEN_SLOT[3].u_mm.state. +Not marking fpga_neural_v2_top.u_dataflow_core.u_act_fill.u_pf.mem_wdata as FSM state register: + Users of register don't seem to benefit from recoding. +Found FSM state register fpga_neural_v2_top.u_dataflow_core.u_act_fill.u_pf.state. +Found FSM state register fpga_neural_v2_top.u_dataflow_core.GEN_SLOT[3].u_np.activation_reg. +Not marking fpga_neural_v2_top.u_dataflow_core.GEN_SLOT[3].u_np.bias_reg as FSM state register: + Users of register don't seem to benefit from recoding. +Found FSM state register fpga_neural_v2_top.u_dataflow_core.GEN_SLOT[3].u_np.np_state. +Found FSM state register fpga_neural_v2_top.u_spi_bridge.state. +Found FSM state register fpga_neural_v2_top.u_sdram_backend.state. + +19.13.2. Executing FSM_EXTRACT pass (extracting FSM from design). +Extracting FSM `\u_dataflow_core.GEN_SLOT[0].u_mm.state' from module `\fpga_neural_v2_top'. + found $dff cell for state register: $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$procdff$20739 + root of input selection tree: $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$0\state[2:0] + found reset state: 3'000 (guessed from mux tree) + found ctrl input: \core_rst + found ctrl input: $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$procmux$19759_CMP + found ctrl input: $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$procmux$19888_CMP + found ctrl input: $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$procmux$19751_CMP + found ctrl input: $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$eq$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:192$3768_Y + found ctrl input: $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$procmux$19812_CMP + found state code: 3'000 + found ctrl input: \u_arbiter.s_ready [0] + found state code: 3'100 + found ctrl input: $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$logic_and$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:272$3780_Y + found state code: 3'011 + found ctrl input: $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$logic_and$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:191$3766_Y + found ctrl input: $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$eq$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:247$3775_Y + found state code: 3'010 + found ctrl input: \u_dataflow_core.u_director.slot_job_start [0] + found state code: 3'001 + found ctrl output: $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$procmux$19759_CMP + found ctrl output: $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$procmux$19888_CMP + found ctrl output: $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$procmux$19751_CMP + found ctrl output: $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$eq$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:192$3768_Y + found ctrl output: $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$procmux$19812_CMP + ctrl inputs: { \u_arbiter.s_ready [0] \u_dataflow_core.u_director.slot_job_start [0] $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$logic_and$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:272$3780_Y $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$eq$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:247$3775_Y $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$logic_and$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:191$3766_Y \core_rst } + ctrl outputs: { $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$procmux$19888_CMP $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$procmux$19812_CMP $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$procmux$19759_CMP $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$procmux$19751_CMP $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$0\state[2:0] $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$eq$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:192$3768_Y } + transition: 3'000 6'-0---0 -> 3'000 8'01000000 + transition: 3'000 6'-1---0 -> 3'001 8'01000010 + transition: 3'000 6'-----1 -> 3'000 8'01000000 + transition: 3'100 6'0----0 -> 3'100 8'00101000 + transition: 3'100 6'1----0 -> 3'000 8'00100000 + transition: 3'100 6'-----1 -> 3'000 8'00100000 + transition: 3'010 6'--0--0 -> 3'010 8'00010100 + transition: 3'010 6'--1--0 -> 3'011 8'00010110 + transition: 3'010 6'-----1 -> 3'000 8'00010000 + transition: 3'001 6'----00 -> 3'001 8'00000011 + transition: 3'001 6'---010 -> 3'001 8'00000011 + transition: 3'001 6'---110 -> 3'010 8'00000101 + transition: 3'001 6'-----1 -> 3'000 8'00000001 + transition: 3'011 6'-----0 -> 3'100 8'10001000 + transition: 3'011 6'-----1 -> 3'000 8'10000000 +Extracting FSM `\u_dataflow_core.u_director.dir_state' from module `\fpga_neural_v2_top'. + found $dff cell for state register: $flatten\u_dataflow_core.\u_director.$procdff$20582 + root of input selection tree: $flatten\u_dataflow_core.\u_director.$0\dir_state[3:0] + found reset state: 4'0000 (guessed from mux tree) + found ctrl input: \core_rst + found ctrl input: $flatten\u_dataflow_core.\u_director.$eq$hardware/v2/rtl/neural_director.v:229$4447_Y + found ctrl input: $auto$opt_reduce.cc:137:opt_pmux$21028 + found ctrl input: $flatten\u_dataflow_core.\u_director.$procmux$19257_CMP + found state code: 4'0011 + found ctrl input: $flatten\u_dataflow_core.\u_director.$logic_and$hardware/v2/rtl/neural_director.v:198$4379_Y + found state code: 4'0010 + found state code: 4'0001 + found state code: 4'0000 + found ctrl output: $flatten\u_dataflow_core.\u_director.$procmux$19257_CMP + found ctrl output: $flatten\u_dataflow_core.\u_director.$procmux$18955_CMP + found ctrl output: $flatten\u_dataflow_core.\u_director.$eq$hardware/v2/rtl/neural_director.v:229$4447_Y + found ctrl output: $flatten\u_dataflow_core.\u_director.$procmux$19262_CMP + ctrl inputs: { $flatten\u_dataflow_core.\u_director.$logic_and$hardware/v2/rtl/neural_director.v:198$4379_Y \core_rst $auto$opt_reduce.cc:137:opt_pmux$21028 } + ctrl outputs: { $flatten\u_dataflow_core.\u_director.$procmux$19262_CMP $flatten\u_dataflow_core.\u_director.$procmux$19257_CMP $flatten\u_dataflow_core.\u_director.$procmux$18955_CMP $flatten\u_dataflow_core.\u_director.$eq$hardware/v2/rtl/neural_director.v:229$4447_Y $flatten\u_dataflow_core.\u_director.$0\dir_state[3:0] } + transition: 4'0000 3'-0- -> 4'0001 8'10000001 + transition: 4'0000 3'-1- -> 4'0000 8'10000000 + transition: 4'0010 3'-0- -> 4'0001 8'00100001 + transition: 4'0010 3'-1- -> 4'0000 8'00100000 + transition: 4'0001 3'00- -> 4'0001 8'00010001 + transition: 4'0001 3'10- -> 4'0010 8'00010010 + transition: 4'0001 3'-1- -> 4'0000 8'00010000 + transition: 4'0011 3'-0- -> 4'0011 8'01000011 + transition: 4'0011 3'-1- -> 4'0000 8'01000000 +Extracting FSM `\u_dataflow_core.GEN_SLOT[0].u_np.activation_reg' from module `\fpga_neural_v2_top'. + found $dff cell for state register: $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procdff$20060 + root of input selection tree: $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$0\activation_reg[1:0] + found reset state: 2'01 (guessed from mux tree) + found ctrl input: \core_rst + found ctrl input: $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$eq$hardware/v2/rtl/neural_processor.v:300$3709_Y + found ctrl input: $flatten\u_dataflow_core.$logic_and$hardware/v2/nms/rtl/nms_dataflow_core_sdram.v:284$7309_Y + found state code: 2'01 + fsm extraction failed: at least two states are required. +Extracting FSM `\u_dataflow_core.GEN_SLOT[0].u_np.np_state' from module `\fpga_neural_v2_top'. + found $dff cell for state register: $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procdff$20057 + root of input selection tree: $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$0\np_state[3:0] + found reset state: 4'0000 (guessed from mux tree) + found ctrl input: \core_rst + found ctrl input: $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procmux$7535_CMP + found ctrl input: $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procmux$7536_CMP + found ctrl input: $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procmux$7539_CMP + found ctrl input: $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procmux$7542_CMP + found ctrl input: \u_dataflow_core.GEN_SLOT[0].u_mm.operand_ready + found ctrl input: $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$eq$hardware/v2/rtl/neural_processor.v:223$3687_Y + found ctrl input: $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$eq$hardware/v2/rtl/neural_processor.v:300$3709_Y + found state code: 4'0110 + found state code: 4'0000 + found ctrl input: $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$logic_and$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:272$3780_Y + found state code: 4'0101 + found ctrl input: \u_dataflow_core.GEN_SLOT[0].u_np.valid7 + found state code: 4'0100 + found ctrl input: $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$logic_and$hardware/v2/rtl/neural_processor.v:332$3715_Y + found state code: 4'0011 + found state code: 4'0010 + found ctrl input: $flatten\u_dataflow_core.$logic_and$hardware/v2/nms/rtl/nms_dataflow_core_sdram.v:284$7309_Y + found state code: 4'0001 + found ctrl output: $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procmux$7535_CMP + found ctrl output: $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procmux$7536_CMP + found ctrl output: $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$eq$hardware/v2/rtl/neural_processor.v:223$3687_Y + found ctrl output: $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$eq$hardware/v2/rtl/neural_processor.v:300$3709_Y + found ctrl output: $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procmux$7539_CMP + found ctrl output: $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procmux$7542_CMP + found ctrl output: \u_dataflow_core.GEN_SLOT[0].u_mm.operand_ready + ctrl inputs: { $flatten\u_dataflow_core.$logic_and$hardware/v2/nms/rtl/nms_dataflow_core_sdram.v:284$7309_Y $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$logic_and$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:272$3780_Y $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$logic_and$hardware/v2/rtl/neural_processor.v:332$3715_Y \u_dataflow_core.GEN_SLOT[0].u_np.valid7 \core_rst } + ctrl outputs: { \u_dataflow_core.GEN_SLOT[0].u_mm.operand_ready $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procmux$7542_CMP $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procmux$7539_CMP $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procmux$7536_CMP $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procmux$7535_CMP $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$0\np_state[3:0] $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$eq$hardware/v2/rtl/neural_processor.v:300$3709_Y $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$eq$hardware/v2/rtl/neural_processor.v:223$3687_Y } + transition: 4'0000 5'0---0 -> 4'0000 11'00000000010 + transition: 4'0000 5'1---0 -> 4'0001 11'00000000110 + transition: 4'0000 5'----1 -> 4'0000 11'00000000010 + transition: 4'0100 5'-0--0 -> 4'0100 11'00100010000 + transition: 4'0100 5'-1--0 -> 4'0101 11'00100010100 + transition: 4'0100 5'----1 -> 4'0000 11'00100000000 + transition: 4'0010 5'--0-0 -> 4'0010 11'10000001000 + transition: 4'0010 5'--1-0 -> 4'0011 11'10000001100 + transition: 4'0010 5'----1 -> 4'0000 11'10000000000 + transition: 4'0110 5'----0 -> 4'0110 11'00001011000 + transition: 4'0110 5'----1 -> 4'0000 11'00001000000 + transition: 4'0001 5'----0 -> 4'0010 11'00000001001 + transition: 4'0001 5'----1 -> 4'0000 11'00000000001 + transition: 4'0101 5'----0 -> 4'0000 11'00010000000 + transition: 4'0101 5'----1 -> 4'0000 11'00010000000 + transition: 4'0011 5'---00 -> 4'0011 11'01000001100 + transition: 4'0011 5'---10 -> 4'0100 11'01000010000 + transition: 4'0011 5'----1 -> 4'0000 11'01000000000 +Extracting FSM `\u_dataflow_core.GEN_SLOT[1].u_mm.state' from module `\fpga_neural_v2_top'. + found $dff cell for state register: $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$procdff$20739 + root of input selection tree: $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$0\state[2:0] + found reset state: 3'000 (guessed from mux tree) + found ctrl input: \core_rst + found ctrl input: $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$procmux$19759_CMP + found ctrl input: $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$procmux$19888_CMP + found ctrl input: $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$procmux$19751_CMP + found ctrl input: $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$eq$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:192$3768_Y + found ctrl input: $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$procmux$19812_CMP + found state code: 3'000 + found ctrl input: \u_arbiter.s_ready [1] + found state code: 3'100 + found ctrl input: $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$logic_and$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:272$3780_Y + found state code: 3'011 + found ctrl input: $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$logic_and$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:191$3766_Y + found ctrl input: $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$eq$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:247$3775_Y + found state code: 3'010 + found ctrl input: \u_dataflow_core.u_director.slot_job_start [1] + found state code: 3'001 + found ctrl output: $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$procmux$19759_CMP + found ctrl output: $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$procmux$19888_CMP + found ctrl output: $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$procmux$19751_CMP + found ctrl output: $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$eq$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:192$3768_Y + found ctrl output: $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$procmux$19812_CMP + ctrl inputs: { \u_arbiter.s_ready [1] \u_dataflow_core.u_director.slot_job_start [1] $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$logic_and$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:272$3780_Y $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$eq$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:247$3775_Y $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$logic_and$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:191$3766_Y \core_rst } + ctrl outputs: { $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$procmux$19888_CMP $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$procmux$19812_CMP $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$procmux$19759_CMP $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$procmux$19751_CMP $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$0\state[2:0] $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$eq$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:192$3768_Y } + transition: 3'000 6'-0---0 -> 3'000 8'01000000 + transition: 3'000 6'-1---0 -> 3'001 8'01000010 + transition: 3'000 6'-----1 -> 3'000 8'01000000 + transition: 3'100 6'0----0 -> 3'100 8'00101000 + transition: 3'100 6'1----0 -> 3'000 8'00100000 + transition: 3'100 6'-----1 -> 3'000 8'00100000 + transition: 3'010 6'--0--0 -> 3'010 8'00010100 + transition: 3'010 6'--1--0 -> 3'011 8'00010110 + transition: 3'010 6'-----1 -> 3'000 8'00010000 + transition: 3'001 6'----00 -> 3'001 8'00000011 + transition: 3'001 6'---010 -> 3'001 8'00000011 + transition: 3'001 6'---110 -> 3'010 8'00000101 + transition: 3'001 6'-----1 -> 3'000 8'00000001 + transition: 3'011 6'-----0 -> 3'100 8'10001000 + transition: 3'011 6'-----1 -> 3'000 8'10000000 +Extracting FSM `\u_sdram_backend.u_sdram_ctrl.state' from module `\fpga_neural_v2_top'. + found $dff cell for state register: $flatten\u_sdram_backend.\u_sdram_ctrl.$procdff$20197 + root of input selection tree: $flatten\u_sdram_backend.\u_sdram_ctrl.$0\state[4:0] + found reset state: 5'00000 (guessed from mux tree) + found ctrl input: \core_rst + found ctrl input: $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10186_CMP + found ctrl input: $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10182_CMP + found ctrl input: $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10178_CMP + found ctrl input: $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10128_CMP + found ctrl input: $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10012_CMP + found ctrl input: $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10091_CMP + found ctrl input: $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10087_CMP + found ctrl input: $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10083_CMP + found ctrl input: $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10079_CMP + found ctrl input: $auto$opt_reduce.cc:137:opt_pmux$21034 + found state code: 5'00111 + found ctrl input: $flatten\u_sdram_backend.\u_sdram_ctrl.$ne$hardware/v2/nms/rtl/sdram_controller.v:256$7426_Y + found state code: 5'00010 + found state code: 5'00011 + found state code: 5'00100 + found ctrl input: $flatten\u_sdram_backend.\u_sdram_ctrl.$lt$hardware/v2/nms/rtl/sdram_controller.v:279$7432_Y + found state code: 5'00110 + found ctrl input: $flatten\u_sdram_backend.\u_sdram_ctrl.$eq$hardware/v2/nms/rtl/sdram_controller.v:305$7436_Y + found ctrl input: $flatten\u_sdram_backend.\u_sdram_ctrl.$logic_or$hardware/v2/nms/rtl/sdram_controller.v:315$7437_Y + found state code: 5'01011 + found state code: 5'01001 + found ctrl input: \u_sdram_backend.u_sdram_ctrl.req_wr_reg + found state code: 5'01101 + found state code: 5'01111 + found state code: 5'01110 + found ctrl input: $flatten\u_sdram_backend.\u_sdram_ctrl.$eq$hardware/v2/nms/rtl/sdram_controller.v:411$7456_Y + found state code: 5'10000 + found ctrl input: $flatten\u_sdram_backend.\u_sdram_ctrl.$lt$hardware/v2/nms/rtl/sdram_controller.v:423$7458_Y + found state code: 5'00000 + found ctrl output: $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10083_CMP + found ctrl output: $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10087_CMP + found ctrl output: $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10091_CMP + found ctrl output: $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10012_CMP + found ctrl output: $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10128_CMP + found ctrl output: $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10186_CMP + found ctrl output: $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10079_CMP + found ctrl output: $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10178_CMP + found ctrl output: $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10137_CMP + found ctrl output: $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10160_CMP + found ctrl output: $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10170_CMP + found ctrl output: $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10182_CMP + ctrl inputs: { $flatten\u_sdram_backend.\u_sdram_ctrl.$lt$hardware/v2/nms/rtl/sdram_controller.v:423$7458_Y $flatten\u_sdram_backend.\u_sdram_ctrl.$eq$hardware/v2/nms/rtl/sdram_controller.v:411$7456_Y $flatten\u_sdram_backend.\u_sdram_ctrl.$logic_or$hardware/v2/nms/rtl/sdram_controller.v:315$7437_Y $flatten\u_sdram_backend.\u_sdram_ctrl.$eq$hardware/v2/nms/rtl/sdram_controller.v:305$7436_Y $flatten\u_sdram_backend.\u_sdram_ctrl.$lt$hardware/v2/nms/rtl/sdram_controller.v:279$7432_Y $flatten\u_sdram_backend.\u_sdram_ctrl.$ne$hardware/v2/nms/rtl/sdram_controller.v:256$7426_Y \u_sdram_backend.u_sdram_ctrl.req_wr_reg \core_rst $auto$opt_reduce.cc:137:opt_pmux$21034 } + ctrl outputs: { $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10186_CMP $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10182_CMP $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10178_CMP $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10170_CMP $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10160_CMP $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10137_CMP $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10128_CMP $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10091_CMP $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10087_CMP $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10083_CMP $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10079_CMP $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10012_CMP $flatten\u_sdram_backend.\u_sdram_ctrl.$0\state[4:0] } + transition: 5'00000 9'-----0-0- -> 5'00010 17'10000000000000010 + transition: 5'00000 9'-----1-0- -> 5'00000 17'10000000000000000 + transition: 5'00000 9'-------1- -> 5'00000 17'10000000000000000 + transition: 5'10000 9'-----0-0- -> 5'00111 17'00000100000000111 + transition: 5'10000 9'-----1-0- -> 5'10000 17'00000100000010000 + transition: 5'10000 9'-------1- -> 5'00000 17'00000100000000000 + transition: 5'00100 9'----00-0- -> 5'00110 17'00000010000000110 + transition: 5'00100 9'----10-0- -> 5'00011 17'00000010000000011 + transition: 5'00100 9'-----1-0- -> 5'00100 17'00000010000000100 + transition: 5'00100 9'-------1- -> 5'00000 17'00000010000000000 + transition: 5'00010 9'-----0-0- -> 5'00011 17'01000000000000011 + transition: 5'00010 9'-----1-0- -> 5'00010 17'01000000000000010 + transition: 5'00010 9'-------1- -> 5'00000 17'01000000000000000 + transition: 5'00110 9'-----0-0- -> 5'00111 17'00010000000000111 + transition: 5'00110 9'-----1-0- -> 5'00110 17'00010000000000110 + transition: 5'00110 9'-------1- -> 5'00000 17'00010000000000000 + transition: 5'01110 9'-0-----0- -> 5'01110 17'00000000010001110 + transition: 5'01110 9'-1-----0- -> 5'10000 17'00000000010010000 + transition: 5'01110 9'-------1- -> 5'00000 17'00000000010000000 + transition: 5'01001 9'-----0-0- -> 5'00111 17'00001000000000111 + transition: 5'01001 9'-----1-0- -> 5'01001 17'00001000000001001 + transition: 5'01001 9'-------1- -> 5'00000 17'00001000000000000 + transition: 5'01101 9'-----0-0- -> 5'01110 17'00000000100001110 + transition: 5'01101 9'-----1-0- -> 5'01101 17'00000000100001101 + transition: 5'01101 9'-------1- -> 5'00000 17'00000000100000000 + transition: 5'00011 9'-------0- -> 5'00100 17'00100000000000100 + transition: 5'00011 9'-------1- -> 5'00000 17'00100000000000000 + transition: 5'01011 9'-----000- -> 5'01101 17'00000001000001101 + transition: 5'01011 9'-----010- -> 5'01111 17'00000001000001111 + transition: 5'01011 9'-----1-0- -> 5'01011 17'00000001000001011 + transition: 5'01011 9'-------1- -> 5'00000 17'00000001000000000 + transition: 5'00111 9'--00---0- -> 5'00111 17'00000000000100111 + transition: 5'00111 9'--10---0- -> 5'01011 17'00000000000101011 + transition: 5'00111 9'---1---0- -> 5'01001 17'00000000000101001 + transition: 5'00111 9'-------1- -> 5'00000 17'00000000000100000 + transition: 5'01111 9'0------0- -> 5'10000 17'00000000001010000 + transition: 5'01111 9'1------0- -> 5'01111 17'00000000001001111 + transition: 5'01111 9'-------1- -> 5'00000 17'00000000001000000 +Extracting FSM `\u_dataflow_core.GEN_SLOT[1].u_np.activation_reg' from module `\fpga_neural_v2_top'. + found $dff cell for state register: $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procdff$20060 + root of input selection tree: $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$0\activation_reg[1:0] + found reset state: 2'01 (guessed from mux tree) + found ctrl input: \core_rst + found ctrl input: $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$eq$hardware/v2/rtl/neural_processor.v:300$3709_Y + found ctrl input: $flatten\u_dataflow_core.$logic_and$hardware/v2/nms/rtl/nms_dataflow_core_sdram.v:284$7312_Y + found state code: 2'01 + fsm extraction failed: at least two states are required. +Extracting FSM `\u_dataflow_core.GEN_SLOT[1].u_np.np_state' from module `\fpga_neural_v2_top'. + found $dff cell for state register: $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procdff$20057 + root of input selection tree: $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$0\np_state[3:0] + found reset state: 4'0000 (guessed from mux tree) + found ctrl input: \core_rst + found ctrl input: $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procmux$7535_CMP + found ctrl input: $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procmux$7536_CMP + found ctrl input: $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procmux$7539_CMP + found ctrl input: $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procmux$7542_CMP + found ctrl input: \u_dataflow_core.GEN_SLOT[1].u_mm.operand_ready + found ctrl input: $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$eq$hardware/v2/rtl/neural_processor.v:223$3687_Y + found ctrl input: $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$eq$hardware/v2/rtl/neural_processor.v:300$3709_Y + found state code: 4'0110 + found state code: 4'0000 + found ctrl input: $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$logic_and$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:272$3780_Y + found state code: 4'0101 + found ctrl input: \u_dataflow_core.GEN_SLOT[1].u_np.valid7 + found state code: 4'0100 + found ctrl input: $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$logic_and$hardware/v2/rtl/neural_processor.v:332$3715_Y + found state code: 4'0011 + found state code: 4'0010 + found ctrl input: $flatten\u_dataflow_core.$logic_and$hardware/v2/nms/rtl/nms_dataflow_core_sdram.v:284$7312_Y + found state code: 4'0001 + found ctrl output: $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procmux$7535_CMP + found ctrl output: $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procmux$7536_CMP + found ctrl output: $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$eq$hardware/v2/rtl/neural_processor.v:223$3687_Y + found ctrl output: $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$eq$hardware/v2/rtl/neural_processor.v:300$3709_Y + found ctrl output: $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procmux$7539_CMP + found ctrl output: $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procmux$7542_CMP + found ctrl output: \u_dataflow_core.GEN_SLOT[1].u_mm.operand_ready + ctrl inputs: { $flatten\u_dataflow_core.$logic_and$hardware/v2/nms/rtl/nms_dataflow_core_sdram.v:284$7312_Y $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$logic_and$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:272$3780_Y $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$logic_and$hardware/v2/rtl/neural_processor.v:332$3715_Y \u_dataflow_core.GEN_SLOT[1].u_np.valid7 \core_rst } + ctrl outputs: { \u_dataflow_core.GEN_SLOT[1].u_mm.operand_ready $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procmux$7542_CMP $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procmux$7539_CMP $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procmux$7536_CMP $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procmux$7535_CMP $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$0\np_state[3:0] $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$eq$hardware/v2/rtl/neural_processor.v:300$3709_Y $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$eq$hardware/v2/rtl/neural_processor.v:223$3687_Y } + transition: 4'0000 5'0---0 -> 4'0000 11'00000000010 + transition: 4'0000 5'1---0 -> 4'0001 11'00000000110 + transition: 4'0000 5'----1 -> 4'0000 11'00000000010 + transition: 4'0100 5'-0--0 -> 4'0100 11'00100010000 + transition: 4'0100 5'-1--0 -> 4'0101 11'00100010100 + transition: 4'0100 5'----1 -> 4'0000 11'00100000000 + transition: 4'0010 5'--0-0 -> 4'0010 11'10000001000 + transition: 4'0010 5'--1-0 -> 4'0011 11'10000001100 + transition: 4'0010 5'----1 -> 4'0000 11'10000000000 + transition: 4'0110 5'----0 -> 4'0110 11'00001011000 + transition: 4'0110 5'----1 -> 4'0000 11'00001000000 + transition: 4'0001 5'----0 -> 4'0010 11'00000001001 + transition: 4'0001 5'----1 -> 4'0000 11'00000000001 + transition: 4'0101 5'----0 -> 4'0000 11'00010000000 + transition: 4'0101 5'----1 -> 4'0000 11'00010000000 + transition: 4'0011 5'---00 -> 4'0011 11'01000001100 + transition: 4'0011 5'---10 -> 4'0100 11'01000010000 + transition: 4'0011 5'----1 -> 4'0000 11'01000000000 +Extracting FSM `\u_dataflow_core.GEN_SLOT[2].u_mm.state' from module `\fpga_neural_v2_top'. + found $dff cell for state register: $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$procdff$20739 + root of input selection tree: $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$0\state[2:0] + found reset state: 3'000 (guessed from mux tree) + found ctrl input: \core_rst + found ctrl input: $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$procmux$19759_CMP + found ctrl input: $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$procmux$19888_CMP + found ctrl input: $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$procmux$19751_CMP + found ctrl input: $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$eq$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:192$3768_Y + found ctrl input: $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$procmux$19812_CMP + found state code: 3'000 + found ctrl input: \u_arbiter.s_ready [2] + found state code: 3'100 + found ctrl input: $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$logic_and$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:272$3780_Y + found state code: 3'011 + found ctrl input: $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$logic_and$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:191$3766_Y + found ctrl input: $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$eq$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:247$3775_Y + found state code: 3'010 + found ctrl input: \u_dataflow_core.u_director.slot_job_start [2] + found state code: 3'001 + found ctrl output: $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$procmux$19759_CMP + found ctrl output: $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$procmux$19888_CMP + found ctrl output: $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$procmux$19751_CMP + found ctrl output: $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$eq$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:192$3768_Y + found ctrl output: $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$procmux$19812_CMP + ctrl inputs: { \u_arbiter.s_ready [2] \u_dataflow_core.u_director.slot_job_start [2] $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$logic_and$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:272$3780_Y $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$eq$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:247$3775_Y $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$logic_and$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:191$3766_Y \core_rst } + ctrl outputs: { $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$procmux$19888_CMP $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$procmux$19812_CMP $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$procmux$19759_CMP $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$procmux$19751_CMP $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$0\state[2:0] $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$eq$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:192$3768_Y } + transition: 3'000 6'-0---0 -> 3'000 8'01000000 + transition: 3'000 6'-1---0 -> 3'001 8'01000010 + transition: 3'000 6'-----1 -> 3'000 8'01000000 + transition: 3'100 6'0----0 -> 3'100 8'00101000 + transition: 3'100 6'1----0 -> 3'000 8'00100000 + transition: 3'100 6'-----1 -> 3'000 8'00100000 + transition: 3'010 6'--0--0 -> 3'010 8'00010100 + transition: 3'010 6'--1--0 -> 3'011 8'00010110 + transition: 3'010 6'-----1 -> 3'000 8'00010000 + transition: 3'001 6'----00 -> 3'001 8'00000011 + transition: 3'001 6'---010 -> 3'001 8'00000011 + transition: 3'001 6'---110 -> 3'010 8'00000101 + transition: 3'001 6'-----1 -> 3'000 8'00000001 + transition: 3'011 6'-----0 -> 3'100 8'10001000 + transition: 3'011 6'-----1 -> 3'000 8'10000000 +Extracting FSM `\u_dataflow_core.GEN_SLOT[2].u_np.activation_reg' from module `\fpga_neural_v2_top'. + found $dff cell for state register: $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procdff$20060 + root of input selection tree: $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$0\activation_reg[1:0] + found reset state: 2'01 (guessed from mux tree) + found ctrl input: \core_rst + found ctrl input: $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$eq$hardware/v2/rtl/neural_processor.v:300$3709_Y + found ctrl input: $flatten\u_dataflow_core.$logic_and$hardware/v2/nms/rtl/nms_dataflow_core_sdram.v:284$7315_Y + found state code: 2'01 + fsm extraction failed: at least two states are required. +Extracting FSM `\u_dataflow_core.GEN_SLOT[2].u_np.np_state' from module `\fpga_neural_v2_top'. + found $dff cell for state register: $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procdff$20057 + root of input selection tree: $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$0\np_state[3:0] + found reset state: 4'0000 (guessed from mux tree) + found ctrl input: \core_rst + found ctrl input: $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procmux$7535_CMP + found ctrl input: $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procmux$7536_CMP + found ctrl input: $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procmux$7539_CMP + found ctrl input: $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procmux$7542_CMP + found ctrl input: \u_dataflow_core.GEN_SLOT[2].u_mm.operand_ready + found ctrl input: $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$eq$hardware/v2/rtl/neural_processor.v:223$3687_Y + found ctrl input: $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$eq$hardware/v2/rtl/neural_processor.v:300$3709_Y + found state code: 4'0110 + found state code: 4'0000 + found ctrl input: $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$logic_and$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:272$3780_Y + found state code: 4'0101 + found ctrl input: \u_dataflow_core.GEN_SLOT[2].u_np.valid7 + found state code: 4'0100 + found ctrl input: $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$logic_and$hardware/v2/rtl/neural_processor.v:332$3715_Y + found state code: 4'0011 + found state code: 4'0010 + found ctrl input: $flatten\u_dataflow_core.$logic_and$hardware/v2/nms/rtl/nms_dataflow_core_sdram.v:284$7315_Y + found state code: 4'0001 + found ctrl output: $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procmux$7535_CMP + found ctrl output: $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procmux$7536_CMP + found ctrl output: $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$eq$hardware/v2/rtl/neural_processor.v:223$3687_Y + found ctrl output: $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$eq$hardware/v2/rtl/neural_processor.v:300$3709_Y + found ctrl output: $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procmux$7539_CMP + found ctrl output: $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procmux$7542_CMP + found ctrl output: \u_dataflow_core.GEN_SLOT[2].u_mm.operand_ready + ctrl inputs: { $flatten\u_dataflow_core.$logic_and$hardware/v2/nms/rtl/nms_dataflow_core_sdram.v:284$7315_Y $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$logic_and$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:272$3780_Y $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$logic_and$hardware/v2/rtl/neural_processor.v:332$3715_Y \u_dataflow_core.GEN_SLOT[2].u_np.valid7 \core_rst } + ctrl outputs: { \u_dataflow_core.GEN_SLOT[2].u_mm.operand_ready $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procmux$7542_CMP $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procmux$7539_CMP $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procmux$7536_CMP $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procmux$7535_CMP $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$0\np_state[3:0] $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$eq$hardware/v2/rtl/neural_processor.v:300$3709_Y $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$eq$hardware/v2/rtl/neural_processor.v:223$3687_Y } + transition: 4'0000 5'0---0 -> 4'0000 11'00000000010 + transition: 4'0000 5'1---0 -> 4'0001 11'00000000110 + transition: 4'0000 5'----1 -> 4'0000 11'00000000010 + transition: 4'0100 5'-0--0 -> 4'0100 11'00100010000 + transition: 4'0100 5'-1--0 -> 4'0101 11'00100010100 + transition: 4'0100 5'----1 -> 4'0000 11'00100000000 + transition: 4'0010 5'--0-0 -> 4'0010 11'10000001000 + transition: 4'0010 5'--1-0 -> 4'0011 11'10000001100 + transition: 4'0010 5'----1 -> 4'0000 11'10000000000 + transition: 4'0110 5'----0 -> 4'0110 11'00001011000 + transition: 4'0110 5'----1 -> 4'0000 11'00001000000 + transition: 4'0001 5'----0 -> 4'0010 11'00000001001 + transition: 4'0001 5'----1 -> 4'0000 11'00000000001 + transition: 4'0101 5'----0 -> 4'0000 11'00010000000 + transition: 4'0101 5'----1 -> 4'0000 11'00010000000 + transition: 4'0011 5'---00 -> 4'0011 11'01000001100 + transition: 4'0011 5'---10 -> 4'0100 11'01000010000 + transition: 4'0011 5'----1 -> 4'0000 11'01000000000 +Extracting FSM `\u_dataflow_core.GEN_SLOT[3].u_mm.state' from module `\fpga_neural_v2_top'. + found $dff cell for state register: $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$procdff$20739 + root of input selection tree: $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$0\state[2:0] + found reset state: 3'000 (guessed from mux tree) + found ctrl input: \core_rst + found ctrl input: $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$procmux$19759_CMP + found ctrl input: $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$procmux$19888_CMP + found ctrl input: $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$procmux$19751_CMP + found ctrl input: $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$eq$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:192$3768_Y + found ctrl input: $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$procmux$19812_CMP + found state code: 3'000 + found ctrl input: \u_arbiter.s_ready [3] + found state code: 3'100 + found ctrl input: $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$logic_and$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:272$3780_Y + found state code: 3'011 + found ctrl input: $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$logic_and$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:191$3766_Y + found ctrl input: $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$eq$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:247$3775_Y + found state code: 3'010 + found ctrl input: \u_dataflow_core.u_director.slot_job_start [3] + found state code: 3'001 + found ctrl output: $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$procmux$19759_CMP + found ctrl output: $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$procmux$19888_CMP + found ctrl output: $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$procmux$19751_CMP + found ctrl output: $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$eq$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:192$3768_Y + found ctrl output: $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$procmux$19812_CMP + ctrl inputs: { \u_arbiter.s_ready [3] \u_dataflow_core.u_director.slot_job_start [3] $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$logic_and$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:272$3780_Y $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$eq$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:247$3775_Y $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$logic_and$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:191$3766_Y \core_rst } + ctrl outputs: { $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$procmux$19888_CMP $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$procmux$19812_CMP $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$procmux$19759_CMP $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$procmux$19751_CMP $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$0\state[2:0] $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$eq$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:192$3768_Y } + transition: 3'000 6'-0---0 -> 3'000 8'01000000 + transition: 3'000 6'-1---0 -> 3'001 8'01000010 + transition: 3'000 6'-----1 -> 3'000 8'01000000 + transition: 3'100 6'0----0 -> 3'100 8'00101000 + transition: 3'100 6'1----0 -> 3'000 8'00100000 + transition: 3'100 6'-----1 -> 3'000 8'00100000 + transition: 3'010 6'--0--0 -> 3'010 8'00010100 + transition: 3'010 6'--1--0 -> 3'011 8'00010110 + transition: 3'010 6'-----1 -> 3'000 8'00010000 + transition: 3'001 6'----00 -> 3'001 8'00000011 + transition: 3'001 6'---010 -> 3'001 8'00000011 + transition: 3'001 6'---110 -> 3'010 8'00000101 + transition: 3'001 6'-----1 -> 3'000 8'00000001 + transition: 3'011 6'-----0 -> 3'100 8'10001000 + transition: 3'011 6'-----1 -> 3'000 8'10000000 +Extracting FSM `\u_dataflow_core.u_act_fill.u_pf.state' from module `\fpga_neural_v2_top'. + found $dff cell for state register: $flatten\u_dataflow_core.\u_act_fill.\u_pf.$procdff$20233 + root of input selection tree: $flatten\u_dataflow_core.\u_act_fill.\u_pf.$0\state[1:0] + found reset state: 2'00 (guessed from mux tree) + found ctrl input: \core_rst + found ctrl input: $flatten\u_dataflow_core.\u_act_fill.\u_pf.$procmux$10331_CMP + found ctrl input: $flatten\u_dataflow_core.\u_act_fill.\u_pf.$procmux$10371_CMP + found state code: 2'00 + found ctrl input: \u_arbiter.s_ready [4] + found ctrl input: $flatten\u_dataflow_core.\u_act_fill.\u_pf.$eq$hardware/v2/rtl/prefetch_engine.v:116$6857_Y + found state code: 2'11 + found ctrl input: \u_dataflow_core.u_act_fill.pf_start + found state code: 2'10 + found ctrl output: $flatten\u_dataflow_core.\u_act_fill.\u_pf.$procmux$10377_CMP + found ctrl output: $flatten\u_dataflow_core.\u_act_fill.\u_pf.$procmux$10371_CMP + found ctrl output: $flatten\u_dataflow_core.\u_act_fill.\u_pf.$procmux$10331_CMP + ctrl inputs: { \u_arbiter.s_ready [4] $flatten\u_dataflow_core.\u_act_fill.\u_pf.$eq$hardware/v2/rtl/prefetch_engine.v:116$6857_Y \u_dataflow_core.u_act_fill.pf_start \core_rst } + ctrl outputs: { $flatten\u_dataflow_core.\u_act_fill.\u_pf.$0\state[1:0] $flatten\u_dataflow_core.\u_act_fill.\u_pf.$procmux$10331_CMP $flatten\u_dataflow_core.\u_act_fill.\u_pf.$procmux$10371_CMP $flatten\u_dataflow_core.\u_act_fill.\u_pf.$procmux$10377_CMP } + transition: 2'00 4'--00 -> 2'00 5'00010 + transition: 2'00 4'--10 -> 2'10 5'10010 + transition: 2'00 4'---1 -> 2'00 5'00010 + transition: 2'10 4'0--0 -> 2'10 5'10100 + transition: 2'10 4'10-0 -> 2'10 5'10100 + transition: 2'10 4'11-0 -> 2'11 5'11100 + transition: 2'10 4'---1 -> 2'00 5'00100 + transition: 2'11 4'---0 -> 2'00 5'00001 + transition: 2'11 4'---1 -> 2'00 5'00001 +Extracting FSM `\u_dataflow_core.GEN_SLOT[3].u_np.activation_reg' from module `\fpga_neural_v2_top'. + found $dff cell for state register: $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procdff$20060 + root of input selection tree: $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$0\activation_reg[1:0] + found reset state: 2'01 (guessed from mux tree) + found ctrl input: \core_rst + found ctrl input: $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$eq$hardware/v2/rtl/neural_processor.v:300$3709_Y + found ctrl input: $flatten\u_dataflow_core.$logic_and$hardware/v2/nms/rtl/nms_dataflow_core_sdram.v:284$7318_Y + found state code: 2'01 + fsm extraction failed: at least two states are required. +Extracting FSM `\u_dataflow_core.GEN_SLOT[3].u_np.np_state' from module `\fpga_neural_v2_top'. + found $dff cell for state register: $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procdff$20057 + root of input selection tree: $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$0\np_state[3:0] + found reset state: 4'0000 (guessed from mux tree) + found ctrl input: \core_rst + found ctrl input: $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procmux$7535_CMP + found ctrl input: $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procmux$7536_CMP + found ctrl input: $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procmux$7539_CMP + found ctrl input: $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procmux$7542_CMP + found ctrl input: \u_dataflow_core.GEN_SLOT[3].u_mm.operand_ready + found ctrl input: $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$eq$hardware/v2/rtl/neural_processor.v:223$3687_Y + found ctrl input: $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$eq$hardware/v2/rtl/neural_processor.v:300$3709_Y + found state code: 4'0110 + found state code: 4'0000 + found ctrl input: $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$logic_and$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:272$3780_Y + found state code: 4'0101 + found ctrl input: \u_dataflow_core.GEN_SLOT[3].u_np.valid7 + found state code: 4'0100 + found ctrl input: $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$logic_and$hardware/v2/rtl/neural_processor.v:332$3715_Y + found state code: 4'0011 + found state code: 4'0010 + found ctrl input: $flatten\u_dataflow_core.$logic_and$hardware/v2/nms/rtl/nms_dataflow_core_sdram.v:284$7318_Y + found state code: 4'0001 + found ctrl output: $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procmux$7535_CMP + found ctrl output: $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procmux$7536_CMP + found ctrl output: $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$eq$hardware/v2/rtl/neural_processor.v:223$3687_Y + found ctrl output: $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$eq$hardware/v2/rtl/neural_processor.v:300$3709_Y + found ctrl output: $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procmux$7539_CMP + found ctrl output: $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procmux$7542_CMP + found ctrl output: \u_dataflow_core.GEN_SLOT[3].u_mm.operand_ready + ctrl inputs: { $flatten\u_dataflow_core.$logic_and$hardware/v2/nms/rtl/nms_dataflow_core_sdram.v:284$7318_Y $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$logic_and$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:272$3780_Y $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$logic_and$hardware/v2/rtl/neural_processor.v:332$3715_Y \u_dataflow_core.GEN_SLOT[3].u_np.valid7 \core_rst } + ctrl outputs: { \u_dataflow_core.GEN_SLOT[3].u_mm.operand_ready $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procmux$7542_CMP $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procmux$7539_CMP $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procmux$7536_CMP $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procmux$7535_CMP $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$0\np_state[3:0] $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$eq$hardware/v2/rtl/neural_processor.v:300$3709_Y $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$eq$hardware/v2/rtl/neural_processor.v:223$3687_Y } + transition: 4'0000 5'0---0 -> 4'0000 11'00000000010 + transition: 4'0000 5'1---0 -> 4'0001 11'00000000110 + transition: 4'0000 5'----1 -> 4'0000 11'00000000010 + transition: 4'0100 5'-0--0 -> 4'0100 11'00100010000 + transition: 4'0100 5'-1--0 -> 4'0101 11'00100010100 + transition: 4'0100 5'----1 -> 4'0000 11'00100000000 + transition: 4'0010 5'--0-0 -> 4'0010 11'10000001000 + transition: 4'0010 5'--1-0 -> 4'0011 11'10000001100 + transition: 4'0010 5'----1 -> 4'0000 11'10000000000 + transition: 4'0110 5'----0 -> 4'0110 11'00001011000 + transition: 4'0110 5'----1 -> 4'0000 11'00001000000 + transition: 4'0001 5'----0 -> 4'0010 11'00000001001 + transition: 4'0001 5'----1 -> 4'0000 11'00000000001 + transition: 4'0101 5'----0 -> 4'0000 11'00010000000 + transition: 4'0101 5'----1 -> 4'0000 11'00010000000 + transition: 4'0011 5'---00 -> 4'0011 11'01000001100 + transition: 4'0011 5'---10 -> 4'0100 11'01000010000 + transition: 4'0011 5'----1 -> 4'0000 11'01000000000 +Extracting FSM `\u_spi_bridge.state' from module `\fpga_neural_v2_top'. + found $dff cell for state register: $flatten\u_spi_bridge.$procdff$20554 + root of input selection tree: $flatten\u_spi_bridge.$0\state[3:0] + found reset state: 4'0000 (guessed from mux tree) + found ctrl input: \u_reset_sync.sync_ff [1] + found state code: 4'0000 + found ctrl input: \u_spi_bridge.cs_rose + found ctrl input: $flatten\u_spi_bridge.$logic_and$hardware/v2/rtl/spi_host_bridge.v:409$7386_Y + found ctrl input: $flatten\u_spi_bridge.$logic_and$hardware/v2/rtl/spi_host_bridge.v:397$7381_Y + found ctrl input: $flatten\u_spi_bridge.$logic_and$hardware/v2/rtl/spi_host_bridge.v:403$7384_Y + found ctrl input: $flatten\u_spi_bridge.$logic_and$hardware/v2/rtl/spi_host_bridge.v:382$7369_Y + found ctrl input: $flatten\u_spi_bridge.$logic_and$hardware/v2/rtl/spi_host_bridge.v:389$7372_Y + found ctrl input: $flatten\u_spi_bridge.$logic_and$hardware/v2/rtl/spi_host_bridge.v:376$7364_Y + found ctrl input: $flatten\u_spi_bridge.$logic_and$hardware/v2/rtl/spi_host_bridge.v:293$7351_Y + found ctrl input: $flatten\u_spi_bridge.$logic_and$hardware/v2/rtl/spi_host_bridge.v:296$7353_Y + found ctrl input: $flatten\u_spi_bridge.$procmux$18234_CMP + found ctrl input: $flatten\u_spi_bridge.$procmux$18221_CMP + found ctrl input: $flatten\u_spi_bridge.$procmux$18172_CMP + found ctrl input: $flatten\u_spi_bridge.$procmux$18278_CMP + found ctrl input: $flatten\u_spi_bridge.$procmux$18556_CMP + found ctrl input: $flatten\u_spi_bridge.$eq$hardware/v2/rtl/spi_host_bridge.v:255$7343_Y + found state code: 4'0110 + found ctrl input: $flatten\u_spi_bridge.$eq$hardware/v2/rtl/spi_host_bridge.v:357$7359_Y + found state code: 4'0111 + found state code: 4'0101 + found ctrl input: $flatten\u_spi_bridge.$procmux$18251_CMP + found state code: 4'0100 + found ctrl input: $flatten\u_spi_bridge.$procmux$18276_CMP + found state code: 4'0010 + found ctrl input: $flatten\u_spi_bridge.$procmux$18614_CMP + found ctrl input: $auto$opt_reduce.cc:137:opt_pmux$21030 + found state code: 4'1001 + found state code: 4'0001 + found state code: 4'0011 + found ctrl input: $flatten\u_spi_bridge.$eq$hardware/v2/rtl/spi_host_bridge.v:394$7375_Y + found state code: 4'1000 + found ctrl input: $flatten\u_spi_bridge.$logic_and$hardware/v2/rtl/spi_host_bridge.v:429$7398_Y + found ctrl output: $flatten\u_spi_bridge.$procmux$18556_CMP + found ctrl output: $flatten\u_spi_bridge.$procmux$18278_CMP + found ctrl output: $flatten\u_spi_bridge.$procmux$18234_CMP + found ctrl output: $flatten\u_spi_bridge.$procmux$18221_CMP + found ctrl output: $flatten\u_spi_bridge.$procmux$18172_CMP + found ctrl output: $flatten\u_spi_bridge.$eq$hardware/v2/rtl/spi_host_bridge.v:397$7377_Y + found ctrl output: $flatten\u_spi_bridge.$eq$hardware/v2/rtl/spi_host_bridge.v:382$7365_Y + found ctrl output: $flatten\u_spi_bridge.$eq$hardware/v2/rtl/spi_host_bridge.v:376$7362_Y + found ctrl output: $flatten\u_spi_bridge.$ne$hardware/v2/rtl/spi_host_bridge.v:293$7350_Y + found ctrl output: $flatten\u_spi_bridge.$ne$hardware/v2/rtl/spi_host_bridge.v:293$7348_Y + found ctrl output: $flatten\u_spi_bridge.$ne$hardware/v2/rtl/spi_host_bridge.v:293$7346_Y + found ctrl output: $flatten\u_spi_bridge.$eq$hardware/v2/rtl/spi_host_bridge.v:254$7341_Y + ctrl inputs: { \u_spi_bridge.cs_rose $flatten\u_spi_bridge.$eq$hardware/v2/rtl/spi_host_bridge.v:255$7343_Y $flatten\u_spi_bridge.$logic_and$hardware/v2/rtl/spi_host_bridge.v:293$7351_Y $flatten\u_spi_bridge.$logic_and$hardware/v2/rtl/spi_host_bridge.v:296$7353_Y $flatten\u_spi_bridge.$eq$hardware/v2/rtl/spi_host_bridge.v:357$7359_Y $flatten\u_spi_bridge.$logic_and$hardware/v2/rtl/spi_host_bridge.v:376$7364_Y $flatten\u_spi_bridge.$logic_and$hardware/v2/rtl/spi_host_bridge.v:382$7369_Y $flatten\u_spi_bridge.$logic_and$hardware/v2/rtl/spi_host_bridge.v:389$7372_Y $flatten\u_spi_bridge.$eq$hardware/v2/rtl/spi_host_bridge.v:394$7375_Y $flatten\u_spi_bridge.$logic_and$hardware/v2/rtl/spi_host_bridge.v:397$7381_Y $flatten\u_spi_bridge.$logic_and$hardware/v2/rtl/spi_host_bridge.v:403$7384_Y $flatten\u_spi_bridge.$logic_and$hardware/v2/rtl/spi_host_bridge.v:409$7386_Y $flatten\u_spi_bridge.$logic_and$hardware/v2/rtl/spi_host_bridge.v:429$7398_Y $flatten\u_spi_bridge.$procmux$18251_CMP $flatten\u_spi_bridge.$procmux$18276_CMP $flatten\u_spi_bridge.$procmux$18614_CMP \u_reset_sync.sync_ff [1] $auto$opt_reduce.cc:137:opt_pmux$21030 } + ctrl outputs: { $flatten\u_spi_bridge.$eq$hardware/v2/rtl/spi_host_bridge.v:254$7341_Y $flatten\u_spi_bridge.$0\state[3:0] $flatten\u_spi_bridge.$ne$hardware/v2/rtl/spi_host_bridge.v:293$7346_Y $flatten\u_spi_bridge.$ne$hardware/v2/rtl/spi_host_bridge.v:293$7348_Y $flatten\u_spi_bridge.$ne$hardware/v2/rtl/spi_host_bridge.v:293$7350_Y $flatten\u_spi_bridge.$eq$hardware/v2/rtl/spi_host_bridge.v:376$7362_Y $flatten\u_spi_bridge.$eq$hardware/v2/rtl/spi_host_bridge.v:382$7365_Y $flatten\u_spi_bridge.$eq$hardware/v2/rtl/spi_host_bridge.v:397$7377_Y $flatten\u_spi_bridge.$procmux$18172_CMP $flatten\u_spi_bridge.$procmux$18221_CMP $flatten\u_spi_bridge.$procmux$18234_CMP $flatten\u_spi_bridge.$procmux$18278_CMP $flatten\u_spi_bridge.$procmux$18556_CMP } + transition: 4'0000 18'----------------0- -> 4'0000 16'0000011100000001 + transition: 4'0000 18'0-00-000-000----1- -> 4'0000 16'0000011100000001 + transition: 4'0000 18'0-01-000-000---010 -> 4'1001 16'0100111100000001 + transition: 4'0000 18'0-01-000-000----11 -> 4'0011 16'0001111100000001 + transition: 4'0000 18'0-01-000-000---11- -> 4'0001 16'0000111100000001 + transition: 4'0000 18'0-1--000-000----1- -> 4'0000 16'0000011100000001 + transition: 4'0000 18'0----100-000----1- -> 4'1001 16'0100111100000001 + transition: 4'0000 18'0-----010000----1- -> 4'0101 16'0010111100000001 + transition: 4'0000 18'0-----011000----1- -> 4'1001 16'0100111100000001 + transition: 4'0000 18'0-00-01--000----1- -> 4'0000 16'0000011100000001 + transition: 4'0000 18'0-01-01--000---010 -> 4'1001 16'0100111100000001 + transition: 4'0000 18'0-01-01--000----11 -> 4'0011 16'0001111100000001 + transition: 4'0000 18'0-01-01--000---11- -> 4'0001 16'0000111100000001 + transition: 4'0000 18'0-1--01--000----1- -> 4'0000 16'0000011100000001 + transition: 4'0000 18'0----11--000----1- -> 4'1001 16'0100111100000001 + transition: 4'0000 18'0--------010----1- -> 4'1000 16'0100011100000001 + transition: 4'0000 18'0-00-000-1-0----1- -> 4'0000 16'0000011100000001 + transition: 4'0000 18'0-01-000-1-0---010 -> 4'1001 16'0100111100000001 + transition: 4'0000 18'0-01-000-1-0----11 -> 4'0011 16'0001111100000001 + transition: 4'0000 18'0-01-000-1-0---11- -> 4'0001 16'0000111100000001 + transition: 4'0000 18'0-1--000-1-0----1- -> 4'0000 16'0000011100000001 + transition: 4'0000 18'0----100-1-0----1- -> 4'1001 16'0100111100000001 + transition: 4'0000 18'0-----0101-0----1- -> 4'0101 16'0010111100000001 + transition: 4'0000 18'0-----0111-0----1- -> 4'1001 16'0100111100000001 + transition: 4'0000 18'0-00-01--1-0----1- -> 4'0000 16'0000011100000001 + transition: 4'0000 18'0-01-01--1-0---010 -> 4'1001 16'0100111100000001 + transition: 4'0000 18'0-01-01--1-0----11 -> 4'0011 16'0001111100000001 + transition: 4'0000 18'0-01-01--1-0---11- -> 4'0001 16'0000111100000001 + transition: 4'0000 18'0-1--01--1-0----1- -> 4'0000 16'0000011100000001 + transition: 4'0000 18'0----11--1-0----1- -> 4'1001 16'0100111100000001 + transition: 4'0000 18'00------0--1----1- -> 4'0111 16'0011111100000001 + transition: 4'0000 18'00------1--1----1- -> 4'1001 16'0100111100000001 + transition: 4'0000 18'0100-000-001----1- -> 4'0000 16'0000011100000001 + transition: 4'0000 18'0101-000-001---010 -> 4'1001 16'0100111100000001 + transition: 4'0000 18'0101-000-001----11 -> 4'0011 16'0001111100000001 + transition: 4'0000 18'0101-000-001---11- -> 4'0001 16'0000111100000001 + transition: 4'0000 18'011--000-001----1- -> 4'0000 16'0000011100000001 + transition: 4'0000 18'01---100-001----1- -> 4'1001 16'0100111100000001 + transition: 4'0000 18'01----010001----1- -> 4'0101 16'0010111100000001 + transition: 4'0000 18'01----011001----1- -> 4'1001 16'0100111100000001 + transition: 4'0000 18'0100-01--001----1- -> 4'0000 16'0000011100000001 + transition: 4'0000 18'0101-01--001---010 -> 4'1001 16'0100111100000001 + transition: 4'0000 18'0101-01--001----11 -> 4'0011 16'0001111100000001 + transition: 4'0000 18'0101-01--001---11- -> 4'0001 16'0000111100000001 + transition: 4'0000 18'011--01--001----1- -> 4'0000 16'0000011100000001 + transition: 4'0000 18'01---11--001----1- -> 4'1001 16'0100111100000001 + transition: 4'0000 18'01-------011----1- -> 4'1000 16'0100011100000001 + transition: 4'0000 18'0100-000-1-1----1- -> 4'0000 16'0000011100000001 + transition: 4'0000 18'0101-000-1-1---010 -> 4'1001 16'0100111100000001 + transition: 4'0000 18'0101-000-1-1----11 -> 4'0011 16'0001111100000001 + transition: 4'0000 18'0101-000-1-1---11- -> 4'0001 16'0000111100000001 + transition: 4'0000 18'011--000-1-1----1- -> 4'0000 16'0000011100000001 + transition: 4'0000 18'01---100-1-1----1- -> 4'1001 16'0100111100000001 + transition: 4'0000 18'01----0101-1----1- -> 4'0101 16'0010111100000001 + transition: 4'0000 18'01----0111-1----1- -> 4'1001 16'0100111100000001 + transition: 4'0000 18'0100-01--1-1----1- -> 4'0000 16'0000011100000001 + transition: 4'0000 18'0101-01--1-1---010 -> 4'1001 16'0100111100000001 + transition: 4'0000 18'0101-01--1-1----11 -> 4'0011 16'0001111100000001 + transition: 4'0000 18'0101-01--1-1---11- -> 4'0001 16'0000111100000001 + transition: 4'0000 18'011--01--1-1----1- -> 4'0000 16'0000011100000001 + transition: 4'0000 18'01---11--1-1----1- -> 4'1001 16'0100111100000001 + transition: 4'0000 18'1---------------1- -> 4'0000 16'0000011100000001 + transition: 4'1000 18'----------------0- -> 4'0000 16'1000011100000000 + transition: 4'1000 18'0-00-000-000----1- -> 4'1000 16'1100011100000000 + transition: 4'1000 18'0-01-000-000----1- -> 4'1000 16'1100011100000000 + transition: 4'1000 18'0-1--000-000----1- -> 4'0000 16'1000011100000000 + transition: 4'1000 18'0----100-000----1- -> 4'1001 16'1100111100000000 + transition: 4'1000 18'0-----010000----1- -> 4'0101 16'1010111100000000 + transition: 4'1000 18'0-----011000----1- -> 4'1001 16'1100111100000000 + transition: 4'1000 18'0-00-01--000----1- -> 4'1000 16'1100011100000000 + transition: 4'1000 18'0-01-01--000----1- -> 4'1000 16'1100011100000000 + transition: 4'1000 18'0-1--01--000----1- -> 4'0000 16'1000011100000000 + transition: 4'1000 18'0----11--000----1- -> 4'1001 16'1100111100000000 + transition: 4'1000 18'0--------010----1- -> 4'1000 16'1100011100000000 + transition: 4'1000 18'0-00-000-1-0----1- -> 4'1000 16'1100011100000000 + transition: 4'1000 18'0-01-000-1-0----1- -> 4'1000 16'1100011100000000 + transition: 4'1000 18'0-1--000-1-0----1- -> 4'0000 16'1000011100000000 + transition: 4'1000 18'0----100-1-0----1- -> 4'1001 16'1100111100000000 + transition: 4'1000 18'0-----0101-0----1- -> 4'0101 16'1010111100000000 + transition: 4'1000 18'0-----0111-0----1- -> 4'1001 16'1100111100000000 + transition: 4'1000 18'0-00-01--1-0----1- -> 4'1000 16'1100011100000000 + transition: 4'1000 18'0-01-01--1-0----1- -> 4'1000 16'1100011100000000 + transition: 4'1000 18'0-1--01--1-0----1- -> 4'0000 16'1000011100000000 + transition: 4'1000 18'0----11--1-0----1- -> 4'1001 16'1100111100000000 + transition: 4'1000 18'00------0--1----1- -> 4'0111 16'1011111100000000 + transition: 4'1000 18'00------1--1----1- -> 4'1001 16'1100111100000000 + transition: 4'1000 18'0100-000-001----1- -> 4'1000 16'1100011100000000 + transition: 4'1000 18'0101-000-001----1- -> 4'1000 16'1100011100000000 + transition: 4'1000 18'011--000-001----1- -> 4'0000 16'1000011100000000 + transition: 4'1000 18'01---100-001----1- -> 4'1001 16'1100111100000000 + transition: 4'1000 18'01----010001----1- -> 4'0101 16'1010111100000000 + transition: 4'1000 18'01----011001----1- -> 4'1001 16'1100111100000000 + transition: 4'1000 18'0100-01--001----1- -> 4'1000 16'1100011100000000 + transition: 4'1000 18'0101-01--001----1- -> 4'1000 16'1100011100000000 + transition: 4'1000 18'011--01--001----1- -> 4'0000 16'1000011100000000 + transition: 4'1000 18'01---11--001----1- -> 4'1001 16'1100111100000000 + transition: 4'1000 18'01-------011----1- -> 4'1000 16'1100011100000000 + transition: 4'1000 18'0100-000-1-1----1- -> 4'1000 16'1100011100000000 + transition: 4'1000 18'0101-000-1-1----1- -> 4'1000 16'1100011100000000 + transition: 4'1000 18'011--000-1-1----1- -> 4'0000 16'1000011100000000 + transition: 4'1000 18'01---100-1-1----1- -> 4'1001 16'1100111100000000 + transition: 4'1000 18'01----0101-1----1- -> 4'0101 16'1010111100000000 + transition: 4'1000 18'01----0111-1----1- -> 4'1001 16'1100111100000000 + transition: 4'1000 18'0100-01--1-1----1- -> 4'1000 16'1100011100000000 + transition: 4'1000 18'0101-01--1-1----1- -> 4'1000 16'1100011100000000 + transition: 4'1000 18'011--01--1-1----1- -> 4'0000 16'1000011100000000 + transition: 4'1000 18'01---11--1-1----1- -> 4'1001 16'1100111100000000 + transition: 4'1000 18'1---------------1- -> 4'0000 16'1000011100000000 + transition: 4'0100 18'----------------0- -> 4'0000 16'0000011100001000 + transition: 4'0100 18'0-00-000-000----1- -> 4'0100 16'0010011100001000 + transition: 4'0100 18'00010000-000----1- -> 4'0111 16'0011111100001000 + transition: 4'0100 18'00011000-000----1- -> 4'0101 16'0010111100001000 + transition: 4'0100 18'0101-000-000----1- -> 4'0100 16'0010011100001000 + transition: 4'0100 18'0-1--000-000----1- -> 4'0000 16'0000011100001000 + transition: 4'0100 18'0----100-000----1- -> 4'1001 16'0100111100001000 + transition: 4'0100 18'0-----010000----1- -> 4'0101 16'0010111100001000 + transition: 4'0100 18'0-----011000----1- -> 4'1001 16'0100111100001000 + transition: 4'0100 18'0-00-01--000----1- -> 4'0100 16'0010011100001000 + transition: 4'0100 18'0001001--000----1- -> 4'0111 16'0011111100001000 + transition: 4'0100 18'0001101--000----1- -> 4'0101 16'0010111100001000 + transition: 4'0100 18'0101-01--000----1- -> 4'0100 16'0010011100001000 + transition: 4'0100 18'0-1--01--000----1- -> 4'0000 16'0000011100001000 + transition: 4'0100 18'0----11--000----1- -> 4'1001 16'0100111100001000 + transition: 4'0100 18'0--------010----1- -> 4'1000 16'0100011100001000 + transition: 4'0100 18'0-00-000-1-0----1- -> 4'0100 16'0010011100001000 + transition: 4'0100 18'00010000-1-0----1- -> 4'0111 16'0011111100001000 + transition: 4'0100 18'00011000-1-0----1- -> 4'0101 16'0010111100001000 + transition: 4'0100 18'0101-000-1-0----1- -> 4'0100 16'0010011100001000 + transition: 4'0100 18'0-1--000-1-0----1- -> 4'0000 16'0000011100001000 + transition: 4'0100 18'0----100-1-0----1- -> 4'1001 16'0100111100001000 + transition: 4'0100 18'0-----0101-0----1- -> 4'0101 16'0010111100001000 + transition: 4'0100 18'0-----0111-0----1- -> 4'1001 16'0100111100001000 + transition: 4'0100 18'0-00-01--1-0----1- -> 4'0100 16'0010011100001000 + transition: 4'0100 18'0001001--1-0----1- -> 4'0111 16'0011111100001000 + transition: 4'0100 18'0001101--1-0----1- -> 4'0101 16'0010111100001000 + transition: 4'0100 18'0101-01--1-0----1- -> 4'0100 16'0010011100001000 + transition: 4'0100 18'0-1--01--1-0----1- -> 4'0000 16'0000011100001000 + transition: 4'0100 18'0----11--1-0----1- -> 4'1001 16'0100111100001000 + transition: 4'0100 18'00------0--1----1- -> 4'0111 16'0011111100001000 + transition: 4'0100 18'00------1--1----1- -> 4'1001 16'0100111100001000 + transition: 4'0100 18'0100-000-001----1- -> 4'0100 16'0010011100001000 + transition: 4'0100 18'0101-000-001----1- -> 4'0100 16'0010011100001000 + transition: 4'0100 18'011--000-001----1- -> 4'0000 16'0000011100001000 + transition: 4'0100 18'01---100-001----1- -> 4'1001 16'0100111100001000 + transition: 4'0100 18'01----010001----1- -> 4'0101 16'0010111100001000 + transition: 4'0100 18'01----011001----1- -> 4'1001 16'0100111100001000 + transition: 4'0100 18'0100-01--001----1- -> 4'0100 16'0010011100001000 + transition: 4'0100 18'0101-01--001----1- -> 4'0100 16'0010011100001000 + transition: 4'0100 18'011--01--001----1- -> 4'0000 16'0000011100001000 + transition: 4'0100 18'01---11--001----1- -> 4'1001 16'0100111100001000 + transition: 4'0100 18'01-------011----1- -> 4'1000 16'0100011100001000 + transition: 4'0100 18'0100-000-1-1----1- -> 4'0100 16'0010011100001000 + transition: 4'0100 18'0101-000-1-1----1- -> 4'0100 16'0010011100001000 + transition: 4'0100 18'011--000-1-1----1- -> 4'0000 16'0000011100001000 + transition: 4'0100 18'01---100-1-1----1- -> 4'1001 16'0100111100001000 + transition: 4'0100 18'01----0101-1----1- -> 4'0101 16'0010111100001000 + transition: 4'0100 18'01----0111-1----1- -> 4'1001 16'0100111100001000 + transition: 4'0100 18'0100-01--1-1----1- -> 4'0100 16'0010011100001000 + transition: 4'0100 18'0101-01--1-1----1- -> 4'0100 16'0010011100001000 + transition: 4'0100 18'011--01--1-1----1- -> 4'0000 16'0000011100001000 + transition: 4'0100 18'01---11--1-1----1- -> 4'1001 16'0100111100001000 + transition: 4'0100 18'1---------------1- -> 4'0000 16'0000011100001000 + transition: 4'0010 18'----------------0- -> 4'0000 16'0000001110000000 + transition: 4'0010 18'0-00-000-000----1- -> 4'0010 16'0001001110000000 + transition: 4'0010 18'0-01-000-000----1- -> 4'0010 16'0001001110000000 + transition: 4'0010 18'0-1--000-000----1- -> 4'0000 16'0000001110000000 + transition: 4'0010 18'0----100-000----1- -> 4'1001 16'0100101110000000 + transition: 4'0010 18'0-----010000----1- -> 4'0101 16'0010101110000000 + transition: 4'0010 18'0-----011000----1- -> 4'1001 16'0100101110000000 + transition: 4'0010 18'0-00-01--000----1- -> 4'0010 16'0001001110000000 + transition: 4'0010 18'0-01-01--000----1- -> 4'0010 16'0001001110000000 + transition: 4'0010 18'0-1--01--000----1- -> 4'0000 16'0000001110000000 + transition: 4'0010 18'0----11--000----1- -> 4'1001 16'0100101110000000 + transition: 4'0010 18'0--------010----1- -> 4'1000 16'0100001110000000 + transition: 4'0010 18'0-00-000-1-0----1- -> 4'0010 16'0001001110000000 + transition: 4'0010 18'0-01-000-1-0----1- -> 4'0010 16'0001001110000000 + transition: 4'0010 18'0-1--000-1-0----1- -> 4'0000 16'0000001110000000 + transition: 4'0010 18'0----100-1-0----1- -> 4'1001 16'0100101110000000 + transition: 4'0010 18'0-----0101-0----1- -> 4'0101 16'0010101110000000 + transition: 4'0010 18'0-----0111-0----1- -> 4'1001 16'0100101110000000 + transition: 4'0010 18'0-00-01--1-0----1- -> 4'0010 16'0001001110000000 + transition: 4'0010 18'0-01-01--1-0----1- -> 4'0010 16'0001001110000000 + transition: 4'0010 18'0-1--01--1-0----1- -> 4'0000 16'0000001110000000 + transition: 4'0010 18'0----11--1-0----1- -> 4'1001 16'0100101110000000 + transition: 4'0010 18'00------0--1----1- -> 4'0111 16'0011101110000000 + transition: 4'0010 18'00------1--1----1- -> 4'1001 16'0100101110000000 + transition: 4'0010 18'0100-000-001----1- -> 4'0010 16'0001001110000000 + transition: 4'0010 18'0101-000-001----1- -> 4'0010 16'0001001110000000 + transition: 4'0010 18'011--000-001----1- -> 4'0000 16'0000001110000000 + transition: 4'0010 18'01---100-001----1- -> 4'1001 16'0100101110000000 + transition: 4'0010 18'01----010001----1- -> 4'0101 16'0010101110000000 + transition: 4'0010 18'01----011001----1- -> 4'1001 16'0100101110000000 + transition: 4'0010 18'0100-01--001----1- -> 4'0010 16'0001001110000000 + transition: 4'0010 18'0101-01--001----1- -> 4'0010 16'0001001110000000 + transition: 4'0010 18'011--01--001----1- -> 4'0000 16'0000001110000000 + transition: 4'0010 18'01---11--001----1- -> 4'1001 16'0100101110000000 + transition: 4'0010 18'01-------011----1- -> 4'1000 16'0100001110000000 + transition: 4'0010 18'0100-000-1-1----1- -> 4'0010 16'0001001110000000 + transition: 4'0010 18'0101-000-1-1----1- -> 4'0010 16'0001001110000000 + transition: 4'0010 18'011--000-1-1----1- -> 4'0000 16'0000001110000000 + transition: 4'0010 18'01---100-1-1----1- -> 4'1001 16'0100101110000000 + transition: 4'0010 18'01----0101-1----1- -> 4'0101 16'0010101110000000 + transition: 4'0010 18'01----0111-1----1- -> 4'1001 16'0100101110000000 + transition: 4'0010 18'0100-01--1-1----1- -> 4'0010 16'0001001110000000 + transition: 4'0010 18'0101-01--1-1----1- -> 4'0010 16'0001001110000000 + transition: 4'0010 18'011--01--1-1----1- -> 4'0000 16'0000001110000000 + transition: 4'0010 18'01---11--1-1----1- -> 4'1001 16'0100101110000000 + transition: 4'0010 18'1-00-000-000----1- -> 4'0010 16'0001001110000000 + transition: 4'0010 18'1-01-000-000----1- -> 4'0010 16'0001001110000000 + transition: 4'0010 18'1-1--000-000----1- -> 4'0000 16'0000001110000000 + transition: 4'0010 18'1----100-000----1- -> 4'1001 16'0100101110000000 + transition: 4'0010 18'1-----010000----1- -> 4'0101 16'0010101110000000 + transition: 4'0010 18'1-----011000----1- -> 4'1001 16'0100101110000000 + transition: 4'0010 18'1-00-01--000----1- -> 4'0010 16'0001001110000000 + transition: 4'0010 18'1-01-01--000----1- -> 4'0010 16'0001001110000000 + transition: 4'0010 18'1-1--01--000----1- -> 4'0000 16'0000001110000000 + transition: 4'0010 18'1----11--000----1- -> 4'1001 16'0100101110000000 + transition: 4'0010 18'1--------010----1- -> 4'1000 16'0100001110000000 + transition: 4'0010 18'1-00-000-1-0----1- -> 4'0010 16'0001001110000000 + transition: 4'0010 18'1-01-000-1-0----1- -> 4'0010 16'0001001110000000 + transition: 4'0010 18'1-1--000-1-0----1- -> 4'0000 16'0000001110000000 + transition: 4'0010 18'1----100-1-0----1- -> 4'1001 16'0100101110000000 + transition: 4'0010 18'1-----0101-0----1- -> 4'0101 16'0010101110000000 + transition: 4'0010 18'1-----0111-0----1- -> 4'1001 16'0100101110000000 + transition: 4'0010 18'1-00-01--1-0----1- -> 4'0010 16'0001001110000000 + transition: 4'0010 18'1-01-01--1-0----1- -> 4'0010 16'0001001110000000 + transition: 4'0010 18'1-1--01--1-0----1- -> 4'0000 16'0000001110000000 + transition: 4'0010 18'1----11--1-0----1- -> 4'1001 16'0100101110000000 + transition: 4'0010 18'10------0--1----1- -> 4'0111 16'0011101110000000 + transition: 4'0010 18'10------1--1----1- -> 4'1001 16'0100101110000000 + transition: 4'0010 18'1100-000-001----1- -> 4'0010 16'0001001110000000 + transition: 4'0010 18'1101-000-001----1- -> 4'0010 16'0001001110000000 + transition: 4'0010 18'111--000-001----1- -> 4'0000 16'0000001110000000 + transition: 4'0010 18'11---100-001----1- -> 4'1001 16'0100101110000000 + transition: 4'0010 18'11----010001----1- -> 4'0101 16'0010101110000000 + transition: 4'0010 18'11----011001----1- -> 4'1001 16'0100101110000000 + transition: 4'0010 18'1100-01--001----1- -> 4'0010 16'0001001110000000 + transition: 4'0010 18'1101-01--001----1- -> 4'0010 16'0001001110000000 + transition: 4'0010 18'111--01--001----1- -> 4'0000 16'0000001110000000 + transition: 4'0010 18'11---11--001----1- -> 4'1001 16'0100101110000000 + transition: 4'0010 18'11-------011----1- -> 4'1000 16'0100001110000000 + transition: 4'0010 18'1100-000-1-1----1- -> 4'0010 16'0001001110000000 + transition: 4'0010 18'1101-000-1-1----1- -> 4'0010 16'0001001110000000 + transition: 4'0010 18'111--000-1-1----1- -> 4'0000 16'0000001110000000 + transition: 4'0010 18'11---100-1-1----1- -> 4'1001 16'0100101110000000 + transition: 4'0010 18'11----0101-1----1- -> 4'0101 16'0010101110000000 + transition: 4'0010 18'11----0111-1----1- -> 4'1001 16'0100101110000000 + transition: 4'0010 18'1100-01--1-1----1- -> 4'0010 16'0001001110000000 + transition: 4'0010 18'1101-01--1-1----1- -> 4'0010 16'0001001110000000 + transition: 4'0010 18'111--01--1-1----1- -> 4'0000 16'0000001110000000 + transition: 4'0010 18'11---11--1-1----1- -> 4'1001 16'0100101110000000 + transition: 4'0110 18'----------------0- -> 4'0000 16'0000010101000000 + transition: 4'0110 18'0-00-000-000----1- -> 4'0110 16'0011010101000000 + transition: 4'0110 18'0-01-000-000----1- -> 4'0110 16'0011010101000000 + transition: 4'0110 18'0-1--000-000----1- -> 4'0000 16'0000010101000000 + transition: 4'0110 18'0----100-000----1- -> 4'1001 16'0100110101000000 + transition: 4'0110 18'0-----010000----1- -> 4'0101 16'0010110101000000 + transition: 4'0110 18'0-----011000----1- -> 4'1001 16'0100110101000000 + transition: 4'0110 18'0-00-01--000----1- -> 4'0110 16'0011010101000000 + transition: 4'0110 18'0-01-01--000----1- -> 4'0110 16'0011010101000000 + transition: 4'0110 18'0-1--01--000----1- -> 4'0000 16'0000010101000000 + transition: 4'0110 18'0----11--000----1- -> 4'1001 16'0100110101000000 + transition: 4'0110 18'0--------010----1- -> 4'1000 16'0100010101000000 + transition: 4'0110 18'0-00-000-1-0----1- -> 4'0110 16'0011010101000000 + transition: 4'0110 18'0-01-000-1-0----1- -> 4'0110 16'0011010101000000 + transition: 4'0110 18'0-1--000-1-0----1- -> 4'0000 16'0000010101000000 + transition: 4'0110 18'0----100-1-0----1- -> 4'1001 16'0100110101000000 + transition: 4'0110 18'0-----0101-0----1- -> 4'0101 16'0010110101000000 + transition: 4'0110 18'0-----0111-0----1- -> 4'1001 16'0100110101000000 + transition: 4'0110 18'0-00-01--1-0----1- -> 4'0110 16'0011010101000000 + transition: 4'0110 18'0-01-01--1-0----1- -> 4'0110 16'0011010101000000 + transition: 4'0110 18'0-1--01--1-0----1- -> 4'0000 16'0000010101000000 + transition: 4'0110 18'0----11--1-0----1- -> 4'1001 16'0100110101000000 + transition: 4'0110 18'00------0--1----1- -> 4'0111 16'0011110101000000 + transition: 4'0110 18'00------1--1----1- -> 4'1001 16'0100110101000000 + transition: 4'0110 18'0100-000-001----1- -> 4'0110 16'0011010101000000 + transition: 4'0110 18'0101-000-001----1- -> 4'0110 16'0011010101000000 + transition: 4'0110 18'011--000-001----1- -> 4'0000 16'0000010101000000 + transition: 4'0110 18'01---100-001----1- -> 4'1001 16'0100110101000000 + transition: 4'0110 18'01----010001----1- -> 4'0101 16'0010110101000000 + transition: 4'0110 18'01----011001----1- -> 4'1001 16'0100110101000000 + transition: 4'0110 18'0100-01--001----1- -> 4'0110 16'0011010101000000 + transition: 4'0110 18'0101-01--001----1- -> 4'0110 16'0011010101000000 + transition: 4'0110 18'011--01--001----1- -> 4'0000 16'0000010101000000 + transition: 4'0110 18'01---11--001----1- -> 4'1001 16'0100110101000000 + transition: 4'0110 18'01-------011----1- -> 4'1000 16'0100010101000000 + transition: 4'0110 18'0100-000-1-1----1- -> 4'0110 16'0011010101000000 + transition: 4'0110 18'0101-000-1-1----1- -> 4'0110 16'0011010101000000 + transition: 4'0110 18'011--000-1-1----1- -> 4'0000 16'0000010101000000 + transition: 4'0110 18'01---100-1-1----1- -> 4'1001 16'0100110101000000 + transition: 4'0110 18'01----0101-1----1- -> 4'0101 16'0010110101000000 + transition: 4'0110 18'01----0111-1----1- -> 4'1001 16'0100110101000000 + transition: 4'0110 18'0100-01--1-1----1- -> 4'0110 16'0011010101000000 + transition: 4'0110 18'0101-01--1-1----1- -> 4'0110 16'0011010101000000 + transition: 4'0110 18'011--01--1-1----1- -> 4'0000 16'0000010101000000 + transition: 4'0110 18'01---11--1-1----1- -> 4'1001 16'0100110101000000 + transition: 4'0110 18'1-00-000-000----1- -> 4'0110 16'0011010101000000 + transition: 4'0110 18'1-01-000-000----1- -> 4'0110 16'0011010101000000 + transition: 4'0110 18'1-1--000-000----1- -> 4'0000 16'0000010101000000 + transition: 4'0110 18'1----100-000----1- -> 4'1001 16'0100110101000000 + transition: 4'0110 18'1-----010000----1- -> 4'0101 16'0010110101000000 + transition: 4'0110 18'1-----011000----1- -> 4'1001 16'0100110101000000 + transition: 4'0110 18'1-00-01--000----1- -> 4'0110 16'0011010101000000 + transition: 4'0110 18'1-01-01--000----1- -> 4'0110 16'0011010101000000 + transition: 4'0110 18'1-1--01--000----1- -> 4'0000 16'0000010101000000 + transition: 4'0110 18'1----11--000----1- -> 4'1001 16'0100110101000000 + transition: 4'0110 18'1--------010----1- -> 4'1000 16'0100010101000000 + transition: 4'0110 18'1-00-000-1-0----1- -> 4'0110 16'0011010101000000 + transition: 4'0110 18'1-01-000-1-0----1- -> 4'0110 16'0011010101000000 + transition: 4'0110 18'1-1--000-1-0----1- -> 4'0000 16'0000010101000000 + transition: 4'0110 18'1----100-1-0----1- -> 4'1001 16'0100110101000000 + transition: 4'0110 18'1-----0101-0----1- -> 4'0101 16'0010110101000000 + transition: 4'0110 18'1-----0111-0----1- -> 4'1001 16'0100110101000000 + transition: 4'0110 18'1-00-01--1-0----1- -> 4'0110 16'0011010101000000 + transition: 4'0110 18'1-01-01--1-0----1- -> 4'0110 16'0011010101000000 + transition: 4'0110 18'1-1--01--1-0----1- -> 4'0000 16'0000010101000000 + transition: 4'0110 18'1----11--1-0----1- -> 4'1001 16'0100110101000000 + transition: 4'0110 18'10------0--1----1- -> 4'0111 16'0011110101000000 + transition: 4'0110 18'10------1--1----1- -> 4'1001 16'0100110101000000 + transition: 4'0110 18'1100-000-001----1- -> 4'0110 16'0011010101000000 + transition: 4'0110 18'1101-000-001----1- -> 4'0110 16'0011010101000000 + transition: 4'0110 18'111--000-001----1- -> 4'0000 16'0000010101000000 + transition: 4'0110 18'11---100-001----1- -> 4'1001 16'0100110101000000 + transition: 4'0110 18'11----010001----1- -> 4'0101 16'0010110101000000 + transition: 4'0110 18'11----011001----1- -> 4'1001 16'0100110101000000 + transition: 4'0110 18'1100-01--001----1- -> 4'0110 16'0011010101000000 + transition: 4'0110 18'1101-01--001----1- -> 4'0110 16'0011010101000000 + transition: 4'0110 18'111--01--001----1- -> 4'0000 16'0000010101000000 + transition: 4'0110 18'11---11--001----1- -> 4'1001 16'0100110101000000 + transition: 4'0110 18'11-------011----1- -> 4'1000 16'0100010101000000 + transition: 4'0110 18'1100-000-1-1----1- -> 4'0110 16'0011010101000000 + transition: 4'0110 18'1101-000-1-1----1- -> 4'0110 16'0011010101000000 + transition: 4'0110 18'111--000-1-1----1- -> 4'0000 16'0000010101000000 + transition: 4'0110 18'11---100-1-1----1- -> 4'1001 16'0100110101000000 + transition: 4'0110 18'11----0101-1----1- -> 4'0101 16'0010110101000000 + transition: 4'0110 18'11----0111-1----1- -> 4'1001 16'0100110101000000 + transition: 4'0110 18'1100-01--1-1----1- -> 4'0110 16'0011010101000000 + transition: 4'0110 18'1101-01--1-1----1- -> 4'0110 16'0011010101000000 + transition: 4'0110 18'111--01--1-1----1- -> 4'0000 16'0000010101000000 + transition: 4'0110 18'11---11--1-1----1- -> 4'1001 16'0100110101000000 + transition: 4'0001 18'----------------0- -> 4'0000 16'0000011100000010 + transition: 4'0001 18'0-00-000-000----1- -> 4'0001 16'0000111100000010 + transition: 4'0001 18'0-01-000-000--0-1- -> 4'0001 16'0000111100000010 + transition: 4'0001 18'0-01-000-000--1-1- -> 4'0010 16'0001011100000010 + transition: 4'0001 18'0-1--000-000----1- -> 4'0000 16'0000011100000010 + transition: 4'0001 18'0----100-000----1- -> 4'1001 16'0100111100000010 + transition: 4'0001 18'0-----010000----1- -> 4'0101 16'0010111100000010 + transition: 4'0001 18'0-----011000----1- -> 4'1001 16'0100111100000010 + transition: 4'0001 18'0-00-01--000----1- -> 4'0001 16'0000111100000010 + transition: 4'0001 18'0-01-01--000--0-1- -> 4'0001 16'0000111100000010 + transition: 4'0001 18'0-01-01--000--1-1- -> 4'0010 16'0001011100000010 + transition: 4'0001 18'0-1--01--000----1- -> 4'0000 16'0000011100000010 + transition: 4'0001 18'0----11--000----1- -> 4'1001 16'0100111100000010 + transition: 4'0001 18'0--------010----1- -> 4'1000 16'0100011100000010 + transition: 4'0001 18'0-00-000-1-0----1- -> 4'0001 16'0000111100000010 + transition: 4'0001 18'0-01-000-1-0--0-1- -> 4'0001 16'0000111100000010 + transition: 4'0001 18'0-01-000-1-0--1-1- -> 4'0010 16'0001011100000010 + transition: 4'0001 18'0-1--000-1-0----1- -> 4'0000 16'0000011100000010 + transition: 4'0001 18'0----100-1-0----1- -> 4'1001 16'0100111100000010 + transition: 4'0001 18'0-----0101-0----1- -> 4'0101 16'0010111100000010 + transition: 4'0001 18'0-----0111-0----1- -> 4'1001 16'0100111100000010 + transition: 4'0001 18'0-00-01--1-0----1- -> 4'0001 16'0000111100000010 + transition: 4'0001 18'0-01-01--1-0--0-1- -> 4'0001 16'0000111100000010 + transition: 4'0001 18'0-01-01--1-0--1-1- -> 4'0010 16'0001011100000010 + transition: 4'0001 18'0-1--01--1-0----1- -> 4'0000 16'0000011100000010 + transition: 4'0001 18'0----11--1-0----1- -> 4'1001 16'0100111100000010 + transition: 4'0001 18'00------0--1----1- -> 4'0111 16'0011111100000010 + transition: 4'0001 18'00------1--1----1- -> 4'1001 16'0100111100000010 + transition: 4'0001 18'0100-000-001----1- -> 4'0001 16'0000111100000010 + transition: 4'0001 18'0101-000-001--0-1- -> 4'0001 16'0000111100000010 + transition: 4'0001 18'0101-000-001--1-1- -> 4'0010 16'0001011100000010 + transition: 4'0001 18'011--000-001----1- -> 4'0000 16'0000011100000010 + transition: 4'0001 18'01---100-001----1- -> 4'1001 16'0100111100000010 + transition: 4'0001 18'01----010001----1- -> 4'0101 16'0010111100000010 + transition: 4'0001 18'01----011001----1- -> 4'1001 16'0100111100000010 + transition: 4'0001 18'0100-01--001----1- -> 4'0001 16'0000111100000010 + transition: 4'0001 18'0101-01--001--0-1- -> 4'0001 16'0000111100000010 + transition: 4'0001 18'0101-01--001--1-1- -> 4'0010 16'0001011100000010 + transition: 4'0001 18'011--01--001----1- -> 4'0000 16'0000011100000010 + transition: 4'0001 18'01---11--001----1- -> 4'1001 16'0100111100000010 + transition: 4'0001 18'01-------011----1- -> 4'1000 16'0100011100000010 + transition: 4'0001 18'0100-000-1-1----1- -> 4'0001 16'0000111100000010 + transition: 4'0001 18'0101-000-1-1--0-1- -> 4'0001 16'0000111100000010 + transition: 4'0001 18'0101-000-1-1--1-1- -> 4'0010 16'0001011100000010 + transition: 4'0001 18'011--000-1-1----1- -> 4'0000 16'0000011100000010 + transition: 4'0001 18'01---100-1-1----1- -> 4'1001 16'0100111100000010 + transition: 4'0001 18'01----0101-1----1- -> 4'0101 16'0010111100000010 + transition: 4'0001 18'01----0111-1----1- -> 4'1001 16'0100111100000010 + transition: 4'0001 18'0100-01--1-1----1- -> 4'0001 16'0000111100000010 + transition: 4'0001 18'0101-01--1-1--0-1- -> 4'0001 16'0000111100000010 + transition: 4'0001 18'0101-01--1-1--1-1- -> 4'0010 16'0001011100000010 + transition: 4'0001 18'011--01--1-1----1- -> 4'0000 16'0000011100000010 + transition: 4'0001 18'01---11--1-1----1- -> 4'1001 16'0100111100000010 + transition: 4'0001 18'1---------------1- -> 4'0000 16'0000011100000010 + transition: 4'1001 18'----------------0- -> 4'0000 16'0000011100000000 + transition: 4'1001 18'0-00-000-000----1- -> 4'1001 16'0100111100000000 + transition: 4'1001 18'0-01-000-000----1- -> 4'1001 16'0100111100000000 + transition: 4'1001 18'0-1--000-000----1- -> 4'0000 16'0000011100000000 + transition: 4'1001 18'0----100-000----1- -> 4'1001 16'0100111100000000 + transition: 4'1001 18'0-----010000----1- -> 4'0101 16'0010111100000000 + transition: 4'1001 18'0-----011000----1- -> 4'1001 16'0100111100000000 + transition: 4'1001 18'0-00-01--000----1- -> 4'1001 16'0100111100000000 + transition: 4'1001 18'0-01-01--000----1- -> 4'1001 16'0100111100000000 + transition: 4'1001 18'0-1--01--000----1- -> 4'0000 16'0000011100000000 + transition: 4'1001 18'0----11--000----1- -> 4'1001 16'0100111100000000 + transition: 4'1001 18'0--------010----1- -> 4'1000 16'0100011100000000 + transition: 4'1001 18'0-00-000-1-0----1- -> 4'1001 16'0100111100000000 + transition: 4'1001 18'0-01-000-1-0----1- -> 4'1001 16'0100111100000000 + transition: 4'1001 18'0-1--000-1-0----1- -> 4'0000 16'0000011100000000 + transition: 4'1001 18'0----100-1-0----1- -> 4'1001 16'0100111100000000 + transition: 4'1001 18'0-----0101-0----1- -> 4'0101 16'0010111100000000 + transition: 4'1001 18'0-----0111-0----1- -> 4'1001 16'0100111100000000 + transition: 4'1001 18'0-00-01--1-0----1- -> 4'1001 16'0100111100000000 + transition: 4'1001 18'0-01-01--1-0----1- -> 4'1001 16'0100111100000000 + transition: 4'1001 18'0-1--01--1-0----1- -> 4'0000 16'0000011100000000 + transition: 4'1001 18'0----11--1-0----1- -> 4'1001 16'0100111100000000 + transition: 4'1001 18'00------0--1----1- -> 4'0111 16'0011111100000000 + transition: 4'1001 18'00------1--1----1- -> 4'1001 16'0100111100000000 + transition: 4'1001 18'0100-000-001----1- -> 4'1001 16'0100111100000000 + transition: 4'1001 18'0101-000-001----1- -> 4'1001 16'0100111100000000 + transition: 4'1001 18'011--000-001----1- -> 4'0000 16'0000011100000000 + transition: 4'1001 18'01---100-001----1- -> 4'1001 16'0100111100000000 + transition: 4'1001 18'01----010001----1- -> 4'0101 16'0010111100000000 + transition: 4'1001 18'01----011001----1- -> 4'1001 16'0100111100000000 + transition: 4'1001 18'0100-01--001----1- -> 4'1001 16'0100111100000000 + transition: 4'1001 18'0101-01--001----1- -> 4'1001 16'0100111100000000 + transition: 4'1001 18'011--01--001----1- -> 4'0000 16'0000011100000000 + transition: 4'1001 18'01---11--001----1- -> 4'1001 16'0100111100000000 + transition: 4'1001 18'01-------011----1- -> 4'1000 16'0100011100000000 + transition: 4'1001 18'0100-000-1-1----1- -> 4'1001 16'0100111100000000 + transition: 4'1001 18'0101-000-1-1----1- -> 4'1001 16'0100111100000000 + transition: 4'1001 18'011--000-1-1----1- -> 4'0000 16'0000011100000000 + transition: 4'1001 18'01---100-1-1----1- -> 4'1001 16'0100111100000000 + transition: 4'1001 18'01----0101-1----1- -> 4'0101 16'0010111100000000 + transition: 4'1001 18'01----0111-1----1- -> 4'1001 16'0100111100000000 + transition: 4'1001 18'0100-01--1-1----1- -> 4'1001 16'0100111100000000 + transition: 4'1001 18'0101-01--1-1----1- -> 4'1001 16'0100111100000000 + transition: 4'1001 18'011--01--1-1----1- -> 4'0000 16'0000011100000000 + transition: 4'1001 18'01---11--1-1----1- -> 4'1001 16'0100111100000000 + transition: 4'1001 18'1---------------1- -> 4'0000 16'0000011100000000 + transition: 4'0101 18'----------------0- -> 4'0000 16'0000011100000100 + transition: 4'0101 18'0-00-000-000----1- -> 4'0101 16'0010111100000100 + transition: 4'0101 18'0001-000-000----1- -> 4'0110 16'0011011100000100 + transition: 4'0101 18'0101-000-000----1- -> 4'0101 16'0010111100000100 + transition: 4'0101 18'0-1--000-000----1- -> 4'0000 16'0000011100000100 + transition: 4'0101 18'0----100-000----1- -> 4'1001 16'0100111100000100 + transition: 4'0101 18'0-----010000----1- -> 4'0101 16'0010111100000100 + transition: 4'0101 18'0-----011000----1- -> 4'1001 16'0100111100000100 + transition: 4'0101 18'0-00-01--000----1- -> 4'0101 16'0010111100000100 + transition: 4'0101 18'0001-01--000----1- -> 4'0110 16'0011011100000100 + transition: 4'0101 18'0101-01--000----1- -> 4'0101 16'0010111100000100 + transition: 4'0101 18'0-1--01--000----1- -> 4'0000 16'0000011100000100 + transition: 4'0101 18'0----11--000----1- -> 4'1001 16'0100111100000100 + transition: 4'0101 18'0--------010----1- -> 4'1000 16'0100011100000100 + transition: 4'0101 18'0-00-000-1-0----1- -> 4'0101 16'0010111100000100 + transition: 4'0101 18'0001-000-1-0----1- -> 4'0110 16'0011011100000100 + transition: 4'0101 18'0101-000-1-0----1- -> 4'0101 16'0010111100000100 + transition: 4'0101 18'0-1--000-1-0----1- -> 4'0000 16'0000011100000100 + transition: 4'0101 18'0----100-1-0----1- -> 4'1001 16'0100111100000100 + transition: 4'0101 18'0-----0101-0----1- -> 4'0101 16'0010111100000100 + transition: 4'0101 18'0-----0111-0----1- -> 4'1001 16'0100111100000100 + transition: 4'0101 18'0-00-01--1-0----1- -> 4'0101 16'0010111100000100 + transition: 4'0101 18'0001-01--1-0----1- -> 4'0110 16'0011011100000100 + transition: 4'0101 18'0101-01--1-0----1- -> 4'0101 16'0010111100000100 + transition: 4'0101 18'0-1--01--1-0----1- -> 4'0000 16'0000011100000100 + transition: 4'0101 18'0----11--1-0----1- -> 4'1001 16'0100111100000100 + transition: 4'0101 18'00------0--1----1- -> 4'0111 16'0011111100000100 + transition: 4'0101 18'00------1--1----1- -> 4'1001 16'0100111100000100 + transition: 4'0101 18'0100-000-001----1- -> 4'0101 16'0010111100000100 + transition: 4'0101 18'0101-000-001----1- -> 4'0101 16'0010111100000100 + transition: 4'0101 18'011--000-001----1- -> 4'0000 16'0000011100000100 + transition: 4'0101 18'01---100-001----1- -> 4'1001 16'0100111100000100 + transition: 4'0101 18'01----010001----1- -> 4'0101 16'0010111100000100 + transition: 4'0101 18'01----011001----1- -> 4'1001 16'0100111100000100 + transition: 4'0101 18'0100-01--001----1- -> 4'0101 16'0010111100000100 + transition: 4'0101 18'0101-01--001----1- -> 4'0101 16'0010111100000100 + transition: 4'0101 18'011--01--001----1- -> 4'0000 16'0000011100000100 + transition: 4'0101 18'01---11--001----1- -> 4'1001 16'0100111100000100 + transition: 4'0101 18'01-------011----1- -> 4'1000 16'0100011100000100 + transition: 4'0101 18'0100-000-1-1----1- -> 4'0101 16'0010111100000100 + transition: 4'0101 18'0101-000-1-1----1- -> 4'0101 16'0010111100000100 + transition: 4'0101 18'011--000-1-1----1- -> 4'0000 16'0000011100000100 + transition: 4'0101 18'01---100-1-1----1- -> 4'1001 16'0100111100000100 + transition: 4'0101 18'01----0101-1----1- -> 4'0101 16'0010111100000100 + transition: 4'0101 18'01----0111-1----1- -> 4'1001 16'0100111100000100 + transition: 4'0101 18'0100-01--1-1----1- -> 4'0101 16'0010111100000100 + transition: 4'0101 18'0101-01--1-1----1- -> 4'0101 16'0010111100000100 + transition: 4'0101 18'011--01--1-1----1- -> 4'0000 16'0000011100000100 + transition: 4'0101 18'01---11--1-1----1- -> 4'1001 16'0100111100000100 + transition: 4'0101 18'1---------------1- -> 4'0000 16'0000011100000100 + transition: 4'0011 18'----------------0- -> 4'0000 16'0000011100010000 + transition: 4'0011 18'0-00-000-000----1- -> 4'0011 16'0001111100010000 + transition: 4'0011 18'0-01-000-000-0--1- -> 4'0011 16'0001111100010000 + transition: 4'0011 18'0-01-000-000-1--1- -> 4'0100 16'0010011100010000 + transition: 4'0011 18'0-1--000-000----1- -> 4'0000 16'0000011100010000 + transition: 4'0011 18'0----100-000----1- -> 4'1001 16'0100111100010000 + transition: 4'0011 18'0-----010000----1- -> 4'0101 16'0010111100010000 + transition: 4'0011 18'0-----011000----1- -> 4'1001 16'0100111100010000 + transition: 4'0011 18'0-00-01--000----1- -> 4'0011 16'0001111100010000 + transition: 4'0011 18'0-01-01--000-0--1- -> 4'0011 16'0001111100010000 + transition: 4'0011 18'0-01-01--000-1--1- -> 4'0100 16'0010011100010000 + transition: 4'0011 18'0-1--01--000----1- -> 4'0000 16'0000011100010000 + transition: 4'0011 18'0----11--000----1- -> 4'1001 16'0100111100010000 + transition: 4'0011 18'0--------010----1- -> 4'1000 16'0100011100010000 + transition: 4'0011 18'0-00-000-1-0----1- -> 4'0011 16'0001111100010000 + transition: 4'0011 18'0-01-000-1-0-0--1- -> 4'0011 16'0001111100010000 + transition: 4'0011 18'0-01-000-1-0-1--1- -> 4'0100 16'0010011100010000 + transition: 4'0011 18'0-1--000-1-0----1- -> 4'0000 16'0000011100010000 + transition: 4'0011 18'0----100-1-0----1- -> 4'1001 16'0100111100010000 + transition: 4'0011 18'0-----0101-0----1- -> 4'0101 16'0010111100010000 + transition: 4'0011 18'0-----0111-0----1- -> 4'1001 16'0100111100010000 + transition: 4'0011 18'0-00-01--1-0----1- -> 4'0011 16'0001111100010000 + transition: 4'0011 18'0-01-01--1-0-0--1- -> 4'0011 16'0001111100010000 + transition: 4'0011 18'0-01-01--1-0-1--1- -> 4'0100 16'0010011100010000 + transition: 4'0011 18'0-1--01--1-0----1- -> 4'0000 16'0000011100010000 + transition: 4'0011 18'0----11--1-0----1- -> 4'1001 16'0100111100010000 + transition: 4'0011 18'00------0--1----1- -> 4'0111 16'0011111100010000 + transition: 4'0011 18'00------1--1----1- -> 4'1001 16'0100111100010000 + transition: 4'0011 18'0100-000-001----1- -> 4'0011 16'0001111100010000 + transition: 4'0011 18'0101-000-001-0--1- -> 4'0011 16'0001111100010000 + transition: 4'0011 18'0101-000-001-1--1- -> 4'0100 16'0010011100010000 + transition: 4'0011 18'011--000-001----1- -> 4'0000 16'0000011100010000 + transition: 4'0011 18'01---100-001----1- -> 4'1001 16'0100111100010000 + transition: 4'0011 18'01----010001----1- -> 4'0101 16'0010111100010000 + transition: 4'0011 18'01----011001----1- -> 4'1001 16'0100111100010000 + transition: 4'0011 18'0100-01--001----1- -> 4'0011 16'0001111100010000 + transition: 4'0011 18'0101-01--001-0--1- -> 4'0011 16'0001111100010000 + transition: 4'0011 18'0101-01--001-1--1- -> 4'0100 16'0010011100010000 + transition: 4'0011 18'011--01--001----1- -> 4'0000 16'0000011100010000 + transition: 4'0011 18'01---11--001----1- -> 4'1001 16'0100111100010000 + transition: 4'0011 18'01-------011----1- -> 4'1000 16'0100011100010000 + transition: 4'0011 18'0100-000-1-1----1- -> 4'0011 16'0001111100010000 + transition: 4'0011 18'0101-000-1-1-0--1- -> 4'0011 16'0001111100010000 + transition: 4'0011 18'0101-000-1-1-1--1- -> 4'0100 16'0010011100010000 + transition: 4'0011 18'011--000-1-1----1- -> 4'0000 16'0000011100010000 + transition: 4'0011 18'01---100-1-1----1- -> 4'1001 16'0100111100010000 + transition: 4'0011 18'01----0101-1----1- -> 4'0101 16'0010111100010000 + transition: 4'0011 18'01----0111-1----1- -> 4'1001 16'0100111100010000 + transition: 4'0011 18'0100-01--1-1----1- -> 4'0011 16'0001111100010000 + transition: 4'0011 18'0101-01--1-1-0--1- -> 4'0011 16'0001111100010000 + transition: 4'0011 18'0101-01--1-1-1--1- -> 4'0100 16'0010011100010000 + transition: 4'0011 18'011--01--1-1----1- -> 4'0000 16'0000011100010000 + transition: 4'0011 18'01---11--1-1----1- -> 4'1001 16'0100111100010000 + transition: 4'0011 18'1---------------1- -> 4'0000 16'0000011100010000 + transition: 4'0111 18'----------------0- -> 4'0000 16'0000011000100000 + transition: 4'0111 18'0-00-000-000----1- -> 4'0111 16'0011111000100000 + transition: 4'0111 18'0-01-000-000----1- -> 4'0111 16'0011111000100000 + transition: 4'0111 18'0-1--000-000----1- -> 4'0000 16'0000011000100000 + transition: 4'0111 18'0----100-000----1- -> 4'1001 16'0100111000100000 + transition: 4'0111 18'0-----010000----1- -> 4'0101 16'0010111000100000 + transition: 4'0111 18'0-----011000----1- -> 4'1001 16'0100111000100000 + transition: 4'0111 18'0-00-01--000----1- -> 4'0111 16'0011111000100000 + transition: 4'0111 18'0-01-01--000----1- -> 4'0111 16'0011111000100000 + transition: 4'0111 18'0-1--01--000----1- -> 4'0000 16'0000011000100000 + transition: 4'0111 18'0----11--000----1- -> 4'1001 16'0100111000100000 + transition: 4'0111 18'0--------010----1- -> 4'1000 16'0100011000100000 + transition: 4'0111 18'0-00-000-1-0----1- -> 4'0111 16'0011111000100000 + transition: 4'0111 18'0-01-000-1-0----1- -> 4'0111 16'0011111000100000 + transition: 4'0111 18'0-1--000-1-0----1- -> 4'0000 16'0000011000100000 + transition: 4'0111 18'0----100-1-0----1- -> 4'1001 16'0100111000100000 + transition: 4'0111 18'0-----0101-0----1- -> 4'0101 16'0010111000100000 + transition: 4'0111 18'0-----0111-0----1- -> 4'1001 16'0100111000100000 + transition: 4'0111 18'0-00-01--1-0----1- -> 4'0111 16'0011111000100000 + transition: 4'0111 18'0-01-01--1-0----1- -> 4'0111 16'0011111000100000 + transition: 4'0111 18'0-1--01--1-0----1- -> 4'0000 16'0000011000100000 + transition: 4'0111 18'0----11--1-0----1- -> 4'1001 16'0100111000100000 + transition: 4'0111 18'00------0--1----1- -> 4'0111 16'0011111000100000 + transition: 4'0111 18'00------1--1----1- -> 4'1001 16'0100111000100000 + transition: 4'0111 18'0100-000-001----1- -> 4'0111 16'0011111000100000 + transition: 4'0111 18'0101-000-001----1- -> 4'0111 16'0011111000100000 + transition: 4'0111 18'011--000-001----1- -> 4'0000 16'0000011000100000 + transition: 4'0111 18'01---100-001----1- -> 4'1001 16'0100111000100000 + transition: 4'0111 18'01----010001----1- -> 4'0101 16'0010111000100000 + transition: 4'0111 18'01----011001----1- -> 4'1001 16'0100111000100000 + transition: 4'0111 18'0100-01--001----1- -> 4'0111 16'0011111000100000 + transition: 4'0111 18'0101-01--001----1- -> 4'0111 16'0011111000100000 + transition: 4'0111 18'011--01--001----1- -> 4'0000 16'0000011000100000 + transition: 4'0111 18'01---11--001----1- -> 4'1001 16'0100111000100000 + transition: 4'0111 18'01-------011----1- -> 4'1000 16'0100011000100000 + transition: 4'0111 18'0100-000-1-1----1- -> 4'0111 16'0011111000100000 + transition: 4'0111 18'0101-000-1-1----1- -> 4'0111 16'0011111000100000 + transition: 4'0111 18'011--000-1-1----1- -> 4'0000 16'0000011000100000 + transition: 4'0111 18'01---100-1-1----1- -> 4'1001 16'0100111000100000 + transition: 4'0111 18'01----0101-1----1- -> 4'0101 16'0010111000100000 + transition: 4'0111 18'01----0111-1----1- -> 4'1001 16'0100111000100000 + transition: 4'0111 18'0100-01--1-1----1- -> 4'0111 16'0011111000100000 + transition: 4'0111 18'0101-01--1-1----1- -> 4'0111 16'0011111000100000 + transition: 4'0111 18'011--01--1-1----1- -> 4'0000 16'0000011000100000 + transition: 4'0111 18'01---11--1-1----1- -> 4'1001 16'0100111000100000 + transition: 4'0111 18'1-00-000-000----1- -> 4'0111 16'0011111000100000 + transition: 4'0111 18'1-01-000-000----1- -> 4'0111 16'0011111000100000 + transition: 4'0111 18'1-1--000-000----1- -> 4'0000 16'0000011000100000 + transition: 4'0111 18'1----100-000----1- -> 4'1001 16'0100111000100000 + transition: 4'0111 18'1-----010000----1- -> 4'0101 16'0010111000100000 + transition: 4'0111 18'1-----011000----1- -> 4'1001 16'0100111000100000 + transition: 4'0111 18'1-00-01--000----1- -> 4'0111 16'0011111000100000 + transition: 4'0111 18'1-01-01--000----1- -> 4'0111 16'0011111000100000 + transition: 4'0111 18'1-1--01--000----1- -> 4'0000 16'0000011000100000 + transition: 4'0111 18'1----11--000----1- -> 4'1001 16'0100111000100000 + transition: 4'0111 18'1--------010----1- -> 4'1000 16'0100011000100000 + transition: 4'0111 18'1-00-000-1-0----1- -> 4'0111 16'0011111000100000 + transition: 4'0111 18'1-01-000-1-0----1- -> 4'0111 16'0011111000100000 + transition: 4'0111 18'1-1--000-1-0----1- -> 4'0000 16'0000011000100000 + transition: 4'0111 18'1----100-1-0----1- -> 4'1001 16'0100111000100000 + transition: 4'0111 18'1-----0101-0----1- -> 4'0101 16'0010111000100000 + transition: 4'0111 18'1-----0111-0----1- -> 4'1001 16'0100111000100000 + transition: 4'0111 18'1-00-01--1-0----1- -> 4'0111 16'0011111000100000 + transition: 4'0111 18'1-01-01--1-0----1- -> 4'0111 16'0011111000100000 + transition: 4'0111 18'1-1--01--1-0----1- -> 4'0000 16'0000011000100000 + transition: 4'0111 18'1----11--1-0----1- -> 4'1001 16'0100111000100000 + transition: 4'0111 18'10------0--1----1- -> 4'0111 16'0011111000100000 + transition: 4'0111 18'10------1--1----1- -> 4'1001 16'0100111000100000 + transition: 4'0111 18'1100-000-001----1- -> 4'0111 16'0011111000100000 + transition: 4'0111 18'1101-000-001----1- -> 4'0111 16'0011111000100000 + transition: 4'0111 18'111--000-001----1- -> 4'0000 16'0000011000100000 + transition: 4'0111 18'11---100-001----1- -> 4'1001 16'0100111000100000 + transition: 4'0111 18'11----010001----1- -> 4'0101 16'0010111000100000 + transition: 4'0111 18'11----011001----1- -> 4'1001 16'0100111000100000 + transition: 4'0111 18'1100-01--001----1- -> 4'0111 16'0011111000100000 + transition: 4'0111 18'1101-01--001----1- -> 4'0111 16'0011111000100000 + transition: 4'0111 18'111--01--001----1- -> 4'0000 16'0000011000100000 + transition: 4'0111 18'11---11--001----1- -> 4'1001 16'0100111000100000 + transition: 4'0111 18'11-------011----1- -> 4'1000 16'0100011000100000 + transition: 4'0111 18'1100-000-1-1----1- -> 4'0111 16'0011111000100000 + transition: 4'0111 18'1101-000-1-1----1- -> 4'0111 16'0011111000100000 + transition: 4'0111 18'111--000-1-1----1- -> 4'0000 16'0000011000100000 + transition: 4'0111 18'11---100-1-1----1- -> 4'1001 16'0100111000100000 + transition: 4'0111 18'11----0101-1----1- -> 4'0101 16'0010111000100000 + transition: 4'0111 18'11----0111-1----1- -> 4'1001 16'0100111000100000 + transition: 4'0111 18'1100-01--1-1----1- -> 4'0111 16'0011111000100000 + transition: 4'0111 18'1101-01--1-1----1- -> 4'0111 16'0011111000100000 + transition: 4'0111 18'111--01--1-1----1- -> 4'0000 16'0000011000100000 + transition: 4'0111 18'11---11--1-1----1- -> 4'1001 16'0100111000100000 +Extracting FSM `\u_sdram_backend.state' from module `\fpga_neural_v2_top'. + found $dff cell for state register: $flatten\u_sdram_backend.$procdff$20155 + root of input selection tree: $flatten\u_sdram_backend.$0\state[2:0] + found reset state: 3'000 (guessed from mux tree) + found ctrl input: \core_rst + found ctrl input: $flatten\u_sdram_backend.$procmux$9155_CMP + found ctrl input: $auto$opt_reduce.cc:137:opt_pmux$21036 + found state code: 3'000 + found ctrl input: \u_sdram_backend.w_cache_hit + found ctrl input: \u_sdram_backend.w_eff_req + found ctrl input: $flatten\u_sdram_backend.$logic_and$hardware/v2/nms/rtl/sdram_unified_backend.v:264$7029_Y + found ctrl input: $flatten\u_sdram_backend.$logic_and$hardware/v2/nms/rtl/sdram_unified_backend.v:272$7030_Y + found state code: 3'011 + found state code: 3'010 + found state code: 3'001 + found ctrl input: \u_sdram_backend.u_sdram_ctrl.ready + found ctrl output: $flatten\u_sdram_backend.$procmux$9155_CMP + found ctrl output: $flatten\u_sdram_backend.$procmux$9308_CMP + found ctrl output: $flatten\u_sdram_backend.$procmux$9305_CMP + found ctrl output: $flatten\u_sdram_backend.$procmux$8835_CMP + ctrl inputs: { \u_sdram_backend.w_cache_hit \u_sdram_backend.w_eff_req $flatten\u_sdram_backend.$logic_and$hardware/v2/nms/rtl/sdram_unified_backend.v:264$7029_Y $flatten\u_sdram_backend.$logic_and$hardware/v2/nms/rtl/sdram_unified_backend.v:272$7030_Y \u_sdram_backend.u_sdram_ctrl.ready \core_rst $auto$opt_reduce.cc:137:opt_pmux$21036 } + ctrl outputs: { $flatten\u_sdram_backend.$0\state[2:0] $flatten\u_sdram_backend.$procmux$8835_CMP $flatten\u_sdram_backend.$procmux$9155_CMP $flatten\u_sdram_backend.$procmux$9305_CMP $flatten\u_sdram_backend.$procmux$9308_CMP } + transition: 3'000 7'0000-0- -> 3'000 7'0000100 + transition: 3'000 7'0001-0- -> 3'011 7'0110100 + transition: 3'000 7'001--0- -> 3'010 7'0100100 + transition: 3'000 7'01---0- -> 3'001 7'0010100 + transition: 3'000 7'1----0- -> 3'000 7'0000100 + transition: 3'000 7'-----1- -> 3'000 7'0000100 + transition: 3'010 7'----00- -> 3'010 7'0100001 + transition: 3'010 7'----10- -> 3'000 7'0000001 + transition: 3'010 7'-----1- -> 3'000 7'0000001 + transition: 3'001 7'----00- -> 3'001 7'0011000 + transition: 3'001 7'----10- -> 3'000 7'0001000 + transition: 3'001 7'-----1- -> 3'000 7'0001000 + transition: 3'011 7'----00- -> 3'011 7'0110010 + transition: 3'011 7'----10- -> 3'000 7'0000010 + transition: 3'011 7'-----1- -> 3'000 7'0000010 + +19.13.3. Executing FSM_OPT pass (simple optimizations of FSMs). +Optimizing FSM `$fsm$\u_sdram_backend.state$21144' from module `\fpga_neural_v2_top'. + Removing unused input signal $auto$opt_reduce.cc:137:opt_pmux$21036. +Optimizing FSM `$fsm$\u_spi_bridge.state$21130' from module `\fpga_neural_v2_top'. + Merging pattern 18'0-00-000-000----1- and 18'0-01-000-000----1- from group (1 1 16'1100011100000000). + Merging pattern 18'0-01-000-000----1- and 18'0-00-000-000----1- from group (1 1 16'1100011100000000). + Merging pattern 18'0-00-01--000----1- and 18'0-01-01--000----1- from group (1 1 16'1100011100000000). + Merging pattern 18'0-01-01--000----1- and 18'0-00-01--000----1- from group (1 1 16'1100011100000000). + Merging pattern 18'0-00-000-1-0----1- and 18'0-01-000-1-0----1- from group (1 1 16'1100011100000000). + Merging pattern 18'0-01-000-1-0----1- and 18'0-00-000-1-0----1- from group (1 1 16'1100011100000000). + Merging pattern 18'0-00-01--1-0----1- and 18'0-01-01--1-0----1- from group (1 1 16'1100011100000000). + Merging pattern 18'0-01-01--1-0----1- and 18'0-00-01--1-0----1- from group (1 1 16'1100011100000000). + Merging pattern 18'0100-000-001----1- and 18'0101-000-001----1- from group (1 1 16'1100011100000000). + Merging pattern 18'0101-000-001----1- and 18'0100-000-001----1- from group (1 1 16'1100011100000000). + Merging pattern 18'0100-01--001----1- and 18'0101-01--001----1- from group (1 1 16'1100011100000000). + Merging pattern 18'0101-01--001----1- and 18'0100-01--001----1- from group (1 1 16'1100011100000000). + Merging pattern 18'0100-000-1-1----1- and 18'0101-000-1-1----1- from group (1 1 16'1100011100000000). + Merging pattern 18'0101-000-1-1----1- and 18'0100-000-1-1----1- from group (1 1 16'1100011100000000). + Merging pattern 18'0100-01--1-1----1- and 18'0101-01--1-1----1- from group (1 1 16'1100011100000000). + Merging pattern 18'0101-01--1-1----1- and 18'0100-01--1-1----1- from group (1 1 16'1100011100000000). + Merging pattern 18'0101-000-000----1- and 18'0101-000-001----1- from group (2 2 16'0010011100001000). + Merging pattern 18'0101-01--000----1- and 18'0101-01--001----1- from group (2 2 16'0010011100001000). + Merging pattern 18'0101-000-1-0----1- and 18'0101-000-1-1----1- from group (2 2 16'0010011100001000). + Merging pattern 18'0101-01--1-0----1- and 18'0101-01--1-1----1- from group (2 2 16'0010011100001000). + Merging pattern 18'0101-000-001----1- and 18'0101-000-000----1- from group (2 2 16'0010011100001000). + Merging pattern 18'0101-01--001----1- and 18'0101-01--000----1- from group (2 2 16'0010011100001000). + Merging pattern 18'0101-000-1-1----1- and 18'0101-000-1-0----1- from group (2 2 16'0010011100001000). + Merging pattern 18'0101-01--1-1----1- and 18'0101-01--1-0----1- from group (2 2 16'0010011100001000). + Merging pattern 18'0-1--000-000----1- and 18'1-1--000-000----1- from group (3 0 16'0000001110000000). + Merging pattern 18'1-1--000-000----1- and 18'0-1--000-000----1- from group (3 0 16'0000001110000000). + Merging pattern 18'0-1--01--000----1- and 18'1-1--01--000----1- from group (3 0 16'0000001110000000). + Merging pattern 18'1-1--01--000----1- and 18'0-1--01--000----1- from group (3 0 16'0000001110000000). + Merging pattern 18'0-1--000-1-0----1- and 18'1-1--000-1-0----1- from group (3 0 16'0000001110000000). + Merging pattern 18'1-1--000-1-0----1- and 18'0-1--000-1-0----1- from group (3 0 16'0000001110000000). + Merging pattern 18'0-1--01--1-0----1- and 18'1-1--01--1-0----1- from group (3 0 16'0000001110000000). + Merging pattern 18'1-1--01--1-0----1- and 18'0-1--01--1-0----1- from group (3 0 16'0000001110000000). + Merging pattern 18'011--000-001----1- and 18'111--000-001----1- from group (3 0 16'0000001110000000). + Merging pattern 18'111--000-001----1- and 18'011--000-001----1- from group (3 0 16'0000001110000000). + Merging pattern 18'011--01--001----1- and 18'111--01--001----1- from group (3 0 16'0000001110000000). + Merging pattern 18'111--01--001----1- and 18'011--01--001----1- from group (3 0 16'0000001110000000). + Merging pattern 18'011--000-1-1----1- and 18'111--000-1-1----1- from group (3 0 16'0000001110000000). + Merging pattern 18'111--000-1-1----1- and 18'011--000-1-1----1- from group (3 0 16'0000001110000000). + Merging pattern 18'011--01--1-1----1- and 18'111--01--1-1----1- from group (3 0 16'0000001110000000). + Merging pattern 18'111--01--1-1----1- and 18'011--01--1-1----1- from group (3 0 16'0000001110000000). + Merging pattern 18'0--------010----1- and 18'1--------010----1- from group (3 1 16'0100001110000000). + Merging pattern 18'1--------010----1- and 18'0--------010----1- from group (3 1 16'0100001110000000). + Merging pattern 18'01-------011----1- and 18'11-------011----1- from group (3 1 16'0100001110000000). + Merging pattern 18'11-------011----1- and 18'01-------011----1- from group (3 1 16'0100001110000000). + Merging pattern 18'0-00-000-000----1- and 18'0-01-000-000----1- from group (3 3 16'0001001110000000). + Merging pattern 18'1-00-000-000----1- and 18'1-01-000-000----1- from group (3 3 16'0001001110000000). + Merging pattern 18'0-01-000-000----1- and 18'0-00-000-000----1- from group (3 3 16'0001001110000000). + Merging pattern 18'1-01-000-000----1- and 18'1-00-000-000----1- from group (3 3 16'0001001110000000). + Merging pattern 18'0-00-01--000----1- and 18'0-01-01--000----1- from group (3 3 16'0001001110000000). + Merging pattern 18'1-00-01--000----1- and 18'1-01-01--000----1- from group (3 3 16'0001001110000000). + Merging pattern 18'0-01-01--000----1- and 18'0-00-01--000----1- from group (3 3 16'0001001110000000). + Merging pattern 18'1-01-01--000----1- and 18'1-00-01--000----1- from group (3 3 16'0001001110000000). + Merging pattern 18'0-00-000-1-0----1- and 18'0-01-000-1-0----1- from group (3 3 16'0001001110000000). + Merging pattern 18'1-00-000-1-0----1- and 18'1-01-000-1-0----1- from group (3 3 16'0001001110000000). + Merging pattern 18'0-01-000-1-0----1- and 18'0-00-000-1-0----1- from group (3 3 16'0001001110000000). + Merging pattern 18'1-01-000-1-0----1- and 18'1-00-000-1-0----1- from group (3 3 16'0001001110000000). + Merging pattern 18'0-00-01--1-0----1- and 18'0-01-01--1-0----1- from group (3 3 16'0001001110000000). + Merging pattern 18'1-00-01--1-0----1- and 18'1-01-01--1-0----1- from group (3 3 16'0001001110000000). + Merging pattern 18'0-01-01--1-0----1- and 18'0-00-01--1-0----1- from group (3 3 16'0001001110000000). + Merging pattern 18'1-01-01--1-0----1- and 18'1-00-01--1-0----1- from group (3 3 16'0001001110000000). + Merging pattern 18'0100-000-001----1- and 18'0101-000-001----1- from group (3 3 16'0001001110000000). + Merging pattern 18'1100-000-001----1- and 18'1101-000-001----1- from group (3 3 16'0001001110000000). + Merging pattern 18'0101-000-001----1- and 18'0100-000-001----1- from group (3 3 16'0001001110000000). + Merging pattern 18'1101-000-001----1- and 18'1100-000-001----1- from group (3 3 16'0001001110000000). + Merging pattern 18'0100-01--001----1- and 18'0101-01--001----1- from group (3 3 16'0001001110000000). + Merging pattern 18'1100-01--001----1- and 18'1101-01--001----1- from group (3 3 16'0001001110000000). + Merging pattern 18'0101-01--001----1- and 18'0100-01--001----1- from group (3 3 16'0001001110000000). + Merging pattern 18'1101-01--001----1- and 18'1100-01--001----1- from group (3 3 16'0001001110000000). + Merging pattern 18'0100-000-1-1----1- and 18'0101-000-1-1----1- from group (3 3 16'0001001110000000). + Merging pattern 18'1100-000-1-1----1- and 18'1101-000-1-1----1- from group (3 3 16'0001001110000000). + Merging pattern 18'0101-000-1-1----1- and 18'0100-000-1-1----1- from group (3 3 16'0001001110000000). + Merging pattern 18'1101-000-1-1----1- and 18'1100-000-1-1----1- from group (3 3 16'0001001110000000). + Merging pattern 18'0100-01--1-1----1- and 18'0101-01--1-1----1- from group (3 3 16'0001001110000000). + Merging pattern 18'1100-01--1-1----1- and 18'1101-01--1-1----1- from group (3 3 16'0001001110000000). + Merging pattern 18'0101-01--1-1----1- and 18'0100-01--1-1----1- from group (3 3 16'0001001110000000). + Merging pattern 18'1101-01--1-1----1- and 18'1100-01--1-1----1- from group (3 3 16'0001001110000000). + Merging pattern 18'0-0--000-000----1- and 18'1-0--000-000----1- from group (3 3 16'0001001110000000). + Merging pattern 18'1-0--000-000----1- and 18'0-0--000-000----1- from group (3 3 16'0001001110000000). + Merging pattern 18'0-0--01--000----1- and 18'1-0--01--000----1- from group (3 3 16'0001001110000000). + Merging pattern 18'1-0--01--000----1- and 18'0-0--01--000----1- from group (3 3 16'0001001110000000). + Merging pattern 18'0-0--000-1-0----1- and 18'1-0--000-1-0----1- from group (3 3 16'0001001110000000). + Merging pattern 18'1-0--000-1-0----1- and 18'0-0--000-1-0----1- from group (3 3 16'0001001110000000). + Merging pattern 18'0-0--01--1-0----1- and 18'1-0--01--1-0----1- from group (3 3 16'0001001110000000). + Merging pattern 18'1-0--01--1-0----1- and 18'0-0--01--1-0----1- from group (3 3 16'0001001110000000). + Merging pattern 18'010--000-001----1- and 18'110--000-001----1- from group (3 3 16'0001001110000000). + Merging pattern 18'110--000-001----1- and 18'010--000-001----1- from group (3 3 16'0001001110000000). + Merging pattern 18'010--01--001----1- and 18'110--01--001----1- from group (3 3 16'0001001110000000). + Merging pattern 18'110--01--001----1- and 18'010--01--001----1- from group (3 3 16'0001001110000000). + Merging pattern 18'010--000-1-1----1- and 18'110--000-1-1----1- from group (3 3 16'0001001110000000). + Merging pattern 18'110--000-1-1----1- and 18'010--000-1-1----1- from group (3 3 16'0001001110000000). + Merging pattern 18'010--01--1-1----1- and 18'110--01--1-1----1- from group (3 3 16'0001001110000000). + Merging pattern 18'110--01--1-1----1- and 18'010--01--1-1----1- from group (3 3 16'0001001110000000). + Merging pattern 18'0-----011000----1- and 18'1-----011000----1- from group (3 6 16'0100101110000000). + Merging pattern 18'1-----011000----1- and 18'0-----011000----1- from group (3 6 16'0100101110000000). + Merging pattern 18'0----100-000----1- and 18'1----100-000----1- from group (3 6 16'0100101110000000). + Merging pattern 18'1----100-000----1- and 18'0----100-000----1- from group (3 6 16'0100101110000000). + Merging pattern 18'0----11--000----1- and 18'1----11--000----1- from group (3 6 16'0100101110000000). + Merging pattern 18'1----11--000----1- and 18'0----11--000----1- from group (3 6 16'0100101110000000). + Merging pattern 18'0-----0111-0----1- and 18'1-----0111-0----1- from group (3 6 16'0100101110000000). + Merging pattern 18'1-----0111-0----1- and 18'0-----0111-0----1- from group (3 6 16'0100101110000000). + Merging pattern 18'0----100-1-0----1- and 18'1----100-1-0----1- from group (3 6 16'0100101110000000). + Merging pattern 18'1----100-1-0----1- and 18'0----100-1-0----1- from group (3 6 16'0100101110000000). + Merging pattern 18'0----11--1-0----1- and 18'1----11--1-0----1- from group (3 6 16'0100101110000000). + Merging pattern 18'1----11--1-0----1- and 18'0----11--1-0----1- from group (3 6 16'0100101110000000). + Merging pattern 18'01----011001----1- and 18'11----011001----1- from group (3 6 16'0100101110000000). + Merging pattern 18'11----011001----1- and 18'01----011001----1- from group (3 6 16'0100101110000000). + Merging pattern 18'01---100-001----1- and 18'11---100-001----1- from group (3 6 16'0100101110000000). + Merging pattern 18'11---100-001----1- and 18'01---100-001----1- from group (3 6 16'0100101110000000). + Merging pattern 18'01---11--001----1- and 18'11---11--001----1- from group (3 6 16'0100101110000000). + Merging pattern 18'11---11--001----1- and 18'01---11--001----1- from group (3 6 16'0100101110000000). + Merging pattern 18'01----0111-1----1- and 18'11----0111-1----1- from group (3 6 16'0100101110000000). + Merging pattern 18'11----0111-1----1- and 18'01----0111-1----1- from group (3 6 16'0100101110000000). + Merging pattern 18'01---100-1-1----1- and 18'11---100-1-1----1- from group (3 6 16'0100101110000000). + Merging pattern 18'11---100-1-1----1- and 18'01---100-1-1----1- from group (3 6 16'0100101110000000). + Merging pattern 18'01---11--1-1----1- and 18'11---11--1-1----1- from group (3 6 16'0100101110000000). + Merging pattern 18'11---11--1-1----1- and 18'01---11--1-1----1- from group (3 6 16'0100101110000000). + Merging pattern 18'00------1--1----1- and 18'10------1--1----1- from group (3 6 16'0100101110000000). + Merging pattern 18'10------1--1----1- and 18'00------1--1----1- from group (3 6 16'0100101110000000). + Merging pattern 18'0-----010000----1- and 18'1-----010000----1- from group (3 7 16'0010101110000000). + Merging pattern 18'1-----010000----1- and 18'0-----010000----1- from group (3 7 16'0010101110000000). + Merging pattern 18'0-----0101-0----1- and 18'1-----0101-0----1- from group (3 7 16'0010101110000000). + Merging pattern 18'1-----0101-0----1- and 18'0-----0101-0----1- from group (3 7 16'0010101110000000). + Merging pattern 18'01----010001----1- and 18'11----010001----1- from group (3 7 16'0010101110000000). + Merging pattern 18'11----010001----1- and 18'01----010001----1- from group (3 7 16'0010101110000000). + Merging pattern 18'01----0101-1----1- and 18'11----0101-1----1- from group (3 7 16'0010101110000000). + Merging pattern 18'11----0101-1----1- and 18'01----0101-1----1- from group (3 7 16'0010101110000000). + Merging pattern 18'00------0--1----1- and 18'10------0--1----1- from group (3 9 16'0011101110000000). + Merging pattern 18'10------0--1----1- and 18'00------0--1----1- from group (3 9 16'0011101110000000). + Merging pattern 18'0-1--000-000----1- and 18'1-1--000-000----1- from group (4 0 16'0000010101000000). + Merging pattern 18'1-1--000-000----1- and 18'0-1--000-000----1- from group (4 0 16'0000010101000000). + Merging pattern 18'0-1--01--000----1- and 18'1-1--01--000----1- from group (4 0 16'0000010101000000). + Merging pattern 18'1-1--01--000----1- and 18'0-1--01--000----1- from group (4 0 16'0000010101000000). + Merging pattern 18'0-1--000-1-0----1- and 18'1-1--000-1-0----1- from group (4 0 16'0000010101000000). + Merging pattern 18'1-1--000-1-0----1- and 18'0-1--000-1-0----1- from group (4 0 16'0000010101000000). + Merging pattern 18'0-1--01--1-0----1- and 18'1-1--01--1-0----1- from group (4 0 16'0000010101000000). + Merging pattern 18'1-1--01--1-0----1- and 18'0-1--01--1-0----1- from group (4 0 16'0000010101000000). + Merging pattern 18'011--000-001----1- and 18'111--000-001----1- from group (4 0 16'0000010101000000). + Merging pattern 18'111--000-001----1- and 18'011--000-001----1- from group (4 0 16'0000010101000000). + Merging pattern 18'011--01--001----1- and 18'111--01--001----1- from group (4 0 16'0000010101000000). + Merging pattern 18'111--01--001----1- and 18'011--01--001----1- from group (4 0 16'0000010101000000). + Merging pattern 18'011--000-1-1----1- and 18'111--000-1-1----1- from group (4 0 16'0000010101000000). + Merging pattern 18'111--000-1-1----1- and 18'011--000-1-1----1- from group (4 0 16'0000010101000000). + Merging pattern 18'011--01--1-1----1- and 18'111--01--1-1----1- from group (4 0 16'0000010101000000). + Merging pattern 18'111--01--1-1----1- and 18'011--01--1-1----1- from group (4 0 16'0000010101000000). + Merging pattern 18'0--------010----1- and 18'1--------010----1- from group (4 1 16'0100010101000000). + Merging pattern 18'1--------010----1- and 18'0--------010----1- from group (4 1 16'0100010101000000). + Merging pattern 18'01-------011----1- and 18'11-------011----1- from group (4 1 16'0100010101000000). + Merging pattern 18'11-------011----1- and 18'01-------011----1- from group (4 1 16'0100010101000000). + Merging pattern 18'0-00-000-000----1- and 18'0-01-000-000----1- from group (4 4 16'0011010101000000). + Merging pattern 18'1-00-000-000----1- and 18'1-01-000-000----1- from group (4 4 16'0011010101000000). + Merging pattern 18'0-01-000-000----1- and 18'0-00-000-000----1- from group (4 4 16'0011010101000000). + Merging pattern 18'1-01-000-000----1- and 18'1-00-000-000----1- from group (4 4 16'0011010101000000). + Merging pattern 18'0-00-01--000----1- and 18'0-01-01--000----1- from group (4 4 16'0011010101000000). + Merging pattern 18'1-00-01--000----1- and 18'1-01-01--000----1- from group (4 4 16'0011010101000000). + Merging pattern 18'0-01-01--000----1- and 18'0-00-01--000----1- from group (4 4 16'0011010101000000). + Merging pattern 18'1-01-01--000----1- and 18'1-00-01--000----1- from group (4 4 16'0011010101000000). + Merging pattern 18'0-00-000-1-0----1- and 18'0-01-000-1-0----1- from group (4 4 16'0011010101000000). + Merging pattern 18'1-00-000-1-0----1- and 18'1-01-000-1-0----1- from group (4 4 16'0011010101000000). + Merging pattern 18'0-01-000-1-0----1- and 18'0-00-000-1-0----1- from group (4 4 16'0011010101000000). + Merging pattern 18'1-01-000-1-0----1- and 18'1-00-000-1-0----1- from group (4 4 16'0011010101000000). + Merging pattern 18'0-00-01--1-0----1- and 18'0-01-01--1-0----1- from group (4 4 16'0011010101000000). + Merging pattern 18'1-00-01--1-0----1- and 18'1-01-01--1-0----1- from group (4 4 16'0011010101000000). + Merging pattern 18'0-01-01--1-0----1- and 18'0-00-01--1-0----1- from group (4 4 16'0011010101000000). + Merging pattern 18'1-01-01--1-0----1- and 18'1-00-01--1-0----1- from group (4 4 16'0011010101000000). + Merging pattern 18'0100-000-001----1- and 18'0101-000-001----1- from group (4 4 16'0011010101000000). + Merging pattern 18'1100-000-001----1- and 18'1101-000-001----1- from group (4 4 16'0011010101000000). + Merging pattern 18'0101-000-001----1- and 18'0100-000-001----1- from group (4 4 16'0011010101000000). + Merging pattern 18'1101-000-001----1- and 18'1100-000-001----1- from group (4 4 16'0011010101000000). + Merging pattern 18'0100-01--001----1- and 18'0101-01--001----1- from group (4 4 16'0011010101000000). + Merging pattern 18'1100-01--001----1- and 18'1101-01--001----1- from group (4 4 16'0011010101000000). + Merging pattern 18'0101-01--001----1- and 18'0100-01--001----1- from group (4 4 16'0011010101000000). + Merging pattern 18'1101-01--001----1- and 18'1100-01--001----1- from group (4 4 16'0011010101000000). + Merging pattern 18'0100-000-1-1----1- and 18'0101-000-1-1----1- from group (4 4 16'0011010101000000). + Merging pattern 18'1100-000-1-1----1- and 18'1101-000-1-1----1- from group (4 4 16'0011010101000000). + Merging pattern 18'0101-000-1-1----1- and 18'0100-000-1-1----1- from group (4 4 16'0011010101000000). + Merging pattern 18'1101-000-1-1----1- and 18'1100-000-1-1----1- from group (4 4 16'0011010101000000). + Merging pattern 18'0100-01--1-1----1- and 18'0101-01--1-1----1- from group (4 4 16'0011010101000000). + Merging pattern 18'1100-01--1-1----1- and 18'1101-01--1-1----1- from group (4 4 16'0011010101000000). + Merging pattern 18'0101-01--1-1----1- and 18'0100-01--1-1----1- from group (4 4 16'0011010101000000). + Merging pattern 18'1101-01--1-1----1- and 18'1100-01--1-1----1- from group (4 4 16'0011010101000000). + Merging pattern 18'0-0--000-000----1- and 18'1-0--000-000----1- from group (4 4 16'0011010101000000). + Merging pattern 18'1-0--000-000----1- and 18'0-0--000-000----1- from group (4 4 16'0011010101000000). + Merging pattern 18'0-0--01--000----1- and 18'1-0--01--000----1- from group (4 4 16'0011010101000000). + Merging pattern 18'1-0--01--000----1- and 18'0-0--01--000----1- from group (4 4 16'0011010101000000). + Merging pattern 18'0-0--000-1-0----1- and 18'1-0--000-1-0----1- from group (4 4 16'0011010101000000). + Merging pattern 18'1-0--000-1-0----1- and 18'0-0--000-1-0----1- from group (4 4 16'0011010101000000). + Merging pattern 18'0-0--01--1-0----1- and 18'1-0--01--1-0----1- from group (4 4 16'0011010101000000). + Merging pattern 18'1-0--01--1-0----1- and 18'0-0--01--1-0----1- from group (4 4 16'0011010101000000). + Merging pattern 18'010--000-001----1- and 18'110--000-001----1- from group (4 4 16'0011010101000000). + Merging pattern 18'110--000-001----1- and 18'010--000-001----1- from group (4 4 16'0011010101000000). + Merging pattern 18'010--01--001----1- and 18'110--01--001----1- from group (4 4 16'0011010101000000). + Merging pattern 18'110--01--001----1- and 18'010--01--001----1- from group (4 4 16'0011010101000000). + Merging pattern 18'010--000-1-1----1- and 18'110--000-1-1----1- from group (4 4 16'0011010101000000). + Merging pattern 18'110--000-1-1----1- and 18'010--000-1-1----1- from group (4 4 16'0011010101000000). + Merging pattern 18'010--01--1-1----1- and 18'110--01--1-1----1- from group (4 4 16'0011010101000000). + Merging pattern 18'110--01--1-1----1- and 18'010--01--1-1----1- from group (4 4 16'0011010101000000). + Merging pattern 18'0-----011000----1- and 18'1-----011000----1- from group (4 6 16'0100110101000000). + Merging pattern 18'1-----011000----1- and 18'0-----011000----1- from group (4 6 16'0100110101000000). + Merging pattern 18'0----100-000----1- and 18'1----100-000----1- from group (4 6 16'0100110101000000). + Merging pattern 18'1----100-000----1- and 18'0----100-000----1- from group (4 6 16'0100110101000000). + Merging pattern 18'0----11--000----1- and 18'1----11--000----1- from group (4 6 16'0100110101000000). + Merging pattern 18'1----11--000----1- and 18'0----11--000----1- from group (4 6 16'0100110101000000). + Merging pattern 18'0-----0111-0----1- and 18'1-----0111-0----1- from group (4 6 16'0100110101000000). + Merging pattern 18'1-----0111-0----1- and 18'0-----0111-0----1- from group (4 6 16'0100110101000000). + Merging pattern 18'0----100-1-0----1- and 18'1----100-1-0----1- from group (4 6 16'0100110101000000). + Merging pattern 18'1----100-1-0----1- and 18'0----100-1-0----1- from group (4 6 16'0100110101000000). + Merging pattern 18'0----11--1-0----1- and 18'1----11--1-0----1- from group (4 6 16'0100110101000000). + Merging pattern 18'1----11--1-0----1- and 18'0----11--1-0----1- from group (4 6 16'0100110101000000). + Merging pattern 18'01----011001----1- and 18'11----011001----1- from group (4 6 16'0100110101000000). + Merging pattern 18'11----011001----1- and 18'01----011001----1- from group (4 6 16'0100110101000000). + Merging pattern 18'01---100-001----1- and 18'11---100-001----1- from group (4 6 16'0100110101000000). + Merging pattern 18'11---100-001----1- and 18'01---100-001----1- from group (4 6 16'0100110101000000). + Merging pattern 18'01---11--001----1- and 18'11---11--001----1- from group (4 6 16'0100110101000000). + Merging pattern 18'11---11--001----1- and 18'01---11--001----1- from group (4 6 16'0100110101000000). + Merging pattern 18'01----0111-1----1- and 18'11----0111-1----1- from group (4 6 16'0100110101000000). + Merging pattern 18'11----0111-1----1- and 18'01----0111-1----1- from group (4 6 16'0100110101000000). + Merging pattern 18'01---100-1-1----1- and 18'11---100-1-1----1- from group (4 6 16'0100110101000000). + Merging pattern 18'11---100-1-1----1- and 18'01---100-1-1----1- from group (4 6 16'0100110101000000). + Merging pattern 18'01---11--1-1----1- and 18'11---11--1-1----1- from group (4 6 16'0100110101000000). + Merging pattern 18'11---11--1-1----1- and 18'01---11--1-1----1- from group (4 6 16'0100110101000000). + Merging pattern 18'00------1--1----1- and 18'10------1--1----1- from group (4 6 16'0100110101000000). + Merging pattern 18'10------1--1----1- and 18'00------1--1----1- from group (4 6 16'0100110101000000). + Merging pattern 18'0-----010000----1- and 18'1-----010000----1- from group (4 7 16'0010110101000000). + Merging pattern 18'1-----010000----1- and 18'0-----010000----1- from group (4 7 16'0010110101000000). + Merging pattern 18'0-----0101-0----1- and 18'1-----0101-0----1- from group (4 7 16'0010110101000000). + Merging pattern 18'1-----0101-0----1- and 18'0-----0101-0----1- from group (4 7 16'0010110101000000). + Merging pattern 18'01----010001----1- and 18'11----010001----1- from group (4 7 16'0010110101000000). + Merging pattern 18'11----010001----1- and 18'01----010001----1- from group (4 7 16'0010110101000000). + Merging pattern 18'01----0101-1----1- and 18'11----0101-1----1- from group (4 7 16'0010110101000000). + Merging pattern 18'11----0101-1----1- and 18'01----0101-1----1- from group (4 7 16'0010110101000000). + Merging pattern 18'00------0--1----1- and 18'10------0--1----1- from group (4 9 16'0011110101000000). + Merging pattern 18'10------0--1----1- and 18'00------0--1----1- from group (4 9 16'0011110101000000). + Merging pattern 18'0-00-000-000----1- and 18'0-01-000-000----1- from group (6 6 16'0100111100000000). + Merging pattern 18'0-01-000-000----1- and 18'0-00-000-000----1- from group (6 6 16'0100111100000000). + Merging pattern 18'0-00-01--000----1- and 18'0-01-01--000----1- from group (6 6 16'0100111100000000). + Merging pattern 18'0-01-01--000----1- and 18'0-00-01--000----1- from group (6 6 16'0100111100000000). + Merging pattern 18'0-00-000-1-0----1- and 18'0-01-000-1-0----1- from group (6 6 16'0100111100000000). + Merging pattern 18'0-01-000-1-0----1- and 18'0-00-000-1-0----1- from group (6 6 16'0100111100000000). + Merging pattern 18'0-00-01--1-0----1- and 18'0-01-01--1-0----1- from group (6 6 16'0100111100000000). + Merging pattern 18'0-01-01--1-0----1- and 18'0-00-01--1-0----1- from group (6 6 16'0100111100000000). + Merging pattern 18'0100-000-001----1- and 18'0101-000-001----1- from group (6 6 16'0100111100000000). + Merging pattern 18'0101-000-001----1- and 18'0100-000-001----1- from group (6 6 16'0100111100000000). + Merging pattern 18'0100-01--001----1- and 18'0101-01--001----1- from group (6 6 16'0100111100000000). + Merging pattern 18'0101-01--001----1- and 18'0100-01--001----1- from group (6 6 16'0100111100000000). + Merging pattern 18'0100-000-1-1----1- and 18'0101-000-1-1----1- from group (6 6 16'0100111100000000). + Merging pattern 18'0101-000-1-1----1- and 18'0100-000-1-1----1- from group (6 6 16'0100111100000000). + Merging pattern 18'0100-01--1-1----1- and 18'0101-01--1-1----1- from group (6 6 16'0100111100000000). + Merging pattern 18'0101-01--1-1----1- and 18'0100-01--1-1----1- from group (6 6 16'0100111100000000). + Merging pattern 18'0101-000-000----1- and 18'0101-000-001----1- from group (7 7 16'0010111100000100). + Merging pattern 18'0101-01--000----1- and 18'0101-01--001----1- from group (7 7 16'0010111100000100). + Merging pattern 18'0101-000-1-0----1- and 18'0101-000-1-1----1- from group (7 7 16'0010111100000100). + Merging pattern 18'0101-01--1-0----1- and 18'0101-01--1-1----1- from group (7 7 16'0010111100000100). + Merging pattern 18'0101-000-001----1- and 18'0101-000-000----1- from group (7 7 16'0010111100000100). + Merging pattern 18'0101-01--001----1- and 18'0101-01--000----1- from group (7 7 16'0010111100000100). + Merging pattern 18'0101-000-1-1----1- and 18'0101-000-1-0----1- from group (7 7 16'0010111100000100). + Merging pattern 18'0101-01--1-1----1- and 18'0101-01--1-0----1- from group (7 7 16'0010111100000100). + Merging pattern 18'0-1--000-000----1- and 18'1-1--000-000----1- from group (9 0 16'0000011000100000). + Merging pattern 18'1-1--000-000----1- and 18'0-1--000-000----1- from group (9 0 16'0000011000100000). + Merging pattern 18'0-1--01--000----1- and 18'1-1--01--000----1- from group (9 0 16'0000011000100000). + Merging pattern 18'1-1--01--000----1- and 18'0-1--01--000----1- from group (9 0 16'0000011000100000). + Merging pattern 18'0-1--000-1-0----1- and 18'1-1--000-1-0----1- from group (9 0 16'0000011000100000). + Merging pattern 18'1-1--000-1-0----1- and 18'0-1--000-1-0----1- from group (9 0 16'0000011000100000). + Merging pattern 18'0-1--01--1-0----1- and 18'1-1--01--1-0----1- from group (9 0 16'0000011000100000). + Merging pattern 18'1-1--01--1-0----1- and 18'0-1--01--1-0----1- from group (9 0 16'0000011000100000). + Merging pattern 18'011--000-001----1- and 18'111--000-001----1- from group (9 0 16'0000011000100000). + Merging pattern 18'111--000-001----1- and 18'011--000-001----1- from group (9 0 16'0000011000100000). + Merging pattern 18'011--01--001----1- and 18'111--01--001----1- from group (9 0 16'0000011000100000). + Merging pattern 18'111--01--001----1- and 18'011--01--001----1- from group (9 0 16'0000011000100000). + Merging pattern 18'011--000-1-1----1- and 18'111--000-1-1----1- from group (9 0 16'0000011000100000). + Merging pattern 18'111--000-1-1----1- and 18'011--000-1-1----1- from group (9 0 16'0000011000100000). + Merging pattern 18'011--01--1-1----1- and 18'111--01--1-1----1- from group (9 0 16'0000011000100000). + Merging pattern 18'111--01--1-1----1- and 18'011--01--1-1----1- from group (9 0 16'0000011000100000). + Merging pattern 18'0--------010----1- and 18'1--------010----1- from group (9 1 16'0100011000100000). + Merging pattern 18'1--------010----1- and 18'0--------010----1- from group (9 1 16'0100011000100000). + Merging pattern 18'01-------011----1- and 18'11-------011----1- from group (9 1 16'0100011000100000). + Merging pattern 18'11-------011----1- and 18'01-------011----1- from group (9 1 16'0100011000100000). + Merging pattern 18'0-----011000----1- and 18'1-----011000----1- from group (9 6 16'0100111000100000). + Merging pattern 18'1-----011000----1- and 18'0-----011000----1- from group (9 6 16'0100111000100000). + Merging pattern 18'0----100-000----1- and 18'1----100-000----1- from group (9 6 16'0100111000100000). + Merging pattern 18'1----100-000----1- and 18'0----100-000----1- from group (9 6 16'0100111000100000). + Merging pattern 18'0----11--000----1- and 18'1----11--000----1- from group (9 6 16'0100111000100000). + Merging pattern 18'1----11--000----1- and 18'0----11--000----1- from group (9 6 16'0100111000100000). + Merging pattern 18'0-----0111-0----1- and 18'1-----0111-0----1- from group (9 6 16'0100111000100000). + Merging pattern 18'1-----0111-0----1- and 18'0-----0111-0----1- from group (9 6 16'0100111000100000). + Merging pattern 18'0----100-1-0----1- and 18'1----100-1-0----1- from group (9 6 16'0100111000100000). + Merging pattern 18'1----100-1-0----1- and 18'0----100-1-0----1- from group (9 6 16'0100111000100000). + Merging pattern 18'0----11--1-0----1- and 18'1----11--1-0----1- from group (9 6 16'0100111000100000). + Merging pattern 18'1----11--1-0----1- and 18'0----11--1-0----1- from group (9 6 16'0100111000100000). + Merging pattern 18'01----011001----1- and 18'11----011001----1- from group (9 6 16'0100111000100000). + Merging pattern 18'11----011001----1- and 18'01----011001----1- from group (9 6 16'0100111000100000). + Merging pattern 18'01---100-001----1- and 18'11---100-001----1- from group (9 6 16'0100111000100000). + Merging pattern 18'11---100-001----1- and 18'01---100-001----1- from group (9 6 16'0100111000100000). + Merging pattern 18'01---11--001----1- and 18'11---11--001----1- from group (9 6 16'0100111000100000). + Merging pattern 18'11---11--001----1- and 18'01---11--001----1- from group (9 6 16'0100111000100000). + Merging pattern 18'01----0111-1----1- and 18'11----0111-1----1- from group (9 6 16'0100111000100000). + Merging pattern 18'11----0111-1----1- and 18'01----0111-1----1- from group (9 6 16'0100111000100000). + Merging pattern 18'01---100-1-1----1- and 18'11---100-1-1----1- from group (9 6 16'0100111000100000). + Merging pattern 18'11---100-1-1----1- and 18'01---100-1-1----1- from group (9 6 16'0100111000100000). + Merging pattern 18'01---11--1-1----1- and 18'11---11--1-1----1- from group (9 6 16'0100111000100000). + Merging pattern 18'11---11--1-1----1- and 18'01---11--1-1----1- from group (9 6 16'0100111000100000). + Merging pattern 18'00------1--1----1- and 18'10------1--1----1- from group (9 6 16'0100111000100000). + Merging pattern 18'10------1--1----1- and 18'00------1--1----1- from group (9 6 16'0100111000100000). + Merging pattern 18'0-----010000----1- and 18'1-----010000----1- from group (9 7 16'0010111000100000). + Merging pattern 18'1-----010000----1- and 18'0-----010000----1- from group (9 7 16'0010111000100000). + Merging pattern 18'0-----0101-0----1- and 18'1-----0101-0----1- from group (9 7 16'0010111000100000). + Merging pattern 18'1-----0101-0----1- and 18'0-----0101-0----1- from group (9 7 16'0010111000100000). + Merging pattern 18'01----010001----1- and 18'11----010001----1- from group (9 7 16'0010111000100000). + Merging pattern 18'11----010001----1- and 18'01----010001----1- from group (9 7 16'0010111000100000). + Merging pattern 18'01----0101-1----1- and 18'11----0101-1----1- from group (9 7 16'0010111000100000). + Merging pattern 18'11----0101-1----1- and 18'01----0101-1----1- from group (9 7 16'0010111000100000). + Merging pattern 18'0-00-000-000----1- and 18'0-01-000-000----1- from group (9 9 16'0011111000100000). + Merging pattern 18'1-00-000-000----1- and 18'1-01-000-000----1- from group (9 9 16'0011111000100000). + Merging pattern 18'0-01-000-000----1- and 18'0-00-000-000----1- from group (9 9 16'0011111000100000). + Merging pattern 18'1-01-000-000----1- and 18'1-00-000-000----1- from group (9 9 16'0011111000100000). + Merging pattern 18'0-00-01--000----1- and 18'0-01-01--000----1- from group (9 9 16'0011111000100000). + Merging pattern 18'1-00-01--000----1- and 18'1-01-01--000----1- from group (9 9 16'0011111000100000). + Merging pattern 18'0-01-01--000----1- and 18'0-00-01--000----1- from group (9 9 16'0011111000100000). + Merging pattern 18'1-01-01--000----1- and 18'1-00-01--000----1- from group (9 9 16'0011111000100000). + Merging pattern 18'0-00-000-1-0----1- and 18'0-01-000-1-0----1- from group (9 9 16'0011111000100000). + Merging pattern 18'1-00-000-1-0----1- and 18'1-01-000-1-0----1- from group (9 9 16'0011111000100000). + Merging pattern 18'0-01-000-1-0----1- and 18'0-00-000-1-0----1- from group (9 9 16'0011111000100000). + Merging pattern 18'1-01-000-1-0----1- and 18'1-00-000-1-0----1- from group (9 9 16'0011111000100000). + Merging pattern 18'0-00-01--1-0----1- and 18'0-01-01--1-0----1- from group (9 9 16'0011111000100000). + Merging pattern 18'1-00-01--1-0----1- and 18'1-01-01--1-0----1- from group (9 9 16'0011111000100000). + Merging pattern 18'0-01-01--1-0----1- and 18'0-00-01--1-0----1- from group (9 9 16'0011111000100000). + Merging pattern 18'1-01-01--1-0----1- and 18'1-00-01--1-0----1- from group (9 9 16'0011111000100000). + Merging pattern 18'0100-000-001----1- and 18'0101-000-001----1- from group (9 9 16'0011111000100000). + Merging pattern 18'1100-000-001----1- and 18'1101-000-001----1- from group (9 9 16'0011111000100000). + Merging pattern 18'0101-000-001----1- and 18'0100-000-001----1- from group (9 9 16'0011111000100000). + Merging pattern 18'1101-000-001----1- and 18'1100-000-001----1- from group (9 9 16'0011111000100000). + Merging pattern 18'0100-01--001----1- and 18'0101-01--001----1- from group (9 9 16'0011111000100000). + Merging pattern 18'1100-01--001----1- and 18'1101-01--001----1- from group (9 9 16'0011111000100000). + Merging pattern 18'0101-01--001----1- and 18'0100-01--001----1- from group (9 9 16'0011111000100000). + Merging pattern 18'1101-01--001----1- and 18'1100-01--001----1- from group (9 9 16'0011111000100000). + Merging pattern 18'0100-000-1-1----1- and 18'0101-000-1-1----1- from group (9 9 16'0011111000100000). + Merging pattern 18'1100-000-1-1----1- and 18'1101-000-1-1----1- from group (9 9 16'0011111000100000). + Merging pattern 18'0101-000-1-1----1- and 18'0100-000-1-1----1- from group (9 9 16'0011111000100000). + Merging pattern 18'1101-000-1-1----1- and 18'1100-000-1-1----1- from group (9 9 16'0011111000100000). + Merging pattern 18'0100-01--1-1----1- and 18'0101-01--1-1----1- from group (9 9 16'0011111000100000). + Merging pattern 18'1100-01--1-1----1- and 18'1101-01--1-1----1- from group (9 9 16'0011111000100000). + Merging pattern 18'0101-01--1-1----1- and 18'0100-01--1-1----1- from group (9 9 16'0011111000100000). + Merging pattern 18'1101-01--1-1----1- and 18'1100-01--1-1----1- from group (9 9 16'0011111000100000). + Merging pattern 18'0-0--000-000----1- and 18'1-0--000-000----1- from group (9 9 16'0011111000100000). + Merging pattern 18'1-0--000-000----1- and 18'0-0--000-000----1- from group (9 9 16'0011111000100000). + Merging pattern 18'0-0--01--000----1- and 18'1-0--01--000----1- from group (9 9 16'0011111000100000). + Merging pattern 18'1-0--01--000----1- and 18'0-0--01--000----1- from group (9 9 16'0011111000100000). + Merging pattern 18'0-0--000-1-0----1- and 18'1-0--000-1-0----1- from group (9 9 16'0011111000100000). + Merging pattern 18'1-0--000-1-0----1- and 18'0-0--000-1-0----1- from group (9 9 16'0011111000100000). + Merging pattern 18'0-0--01--1-0----1- and 18'1-0--01--1-0----1- from group (9 9 16'0011111000100000). + Merging pattern 18'1-0--01--1-0----1- and 18'0-0--01--1-0----1- from group (9 9 16'0011111000100000). + Merging pattern 18'010--000-001----1- and 18'110--000-001----1- from group (9 9 16'0011111000100000). + Merging pattern 18'110--000-001----1- and 18'010--000-001----1- from group (9 9 16'0011111000100000). + Merging pattern 18'010--01--001----1- and 18'110--01--001----1- from group (9 9 16'0011111000100000). + Merging pattern 18'110--01--001----1- and 18'010--01--001----1- from group (9 9 16'0011111000100000). + Merging pattern 18'010--000-1-1----1- and 18'110--000-1-1----1- from group (9 9 16'0011111000100000). + Merging pattern 18'110--000-1-1----1- and 18'010--000-1-1----1- from group (9 9 16'0011111000100000). + Merging pattern 18'010--01--1-1----1- and 18'110--01--1-1----1- from group (9 9 16'0011111000100000). + Merging pattern 18'110--01--1-1----1- and 18'010--01--1-1----1- from group (9 9 16'0011111000100000). + Merging pattern 18'00------0--1----1- and 18'10------0--1----1- from group (9 9 16'0011111000100000). + Merging pattern 18'10------0--1----1- and 18'00------0--1----1- from group (9 9 16'0011111000100000). + Removing unused input signal $flatten\u_spi_bridge.$logic_and$hardware/v2/rtl/spi_host_bridge.v:429$7398_Y. +Optimizing FSM `$fsm$\u_dataflow_core.GEN_SLOT[3].u_np.np_state$21121' from module `\fpga_neural_v2_top'. + Merging pattern 5'----0 and 5'----1 from group (5 0 11'00010000000). + Merging pattern 5'----1 and 5'----0 from group (5 0 11'00010000000). +Optimizing FSM `$fsm$\u_dataflow_core.u_act_fill.u_pf.state$21116' from module `\fpga_neural_v2_top'. + Merging pattern 4'---0 and 4'---1 from group (2 0 5'00001). + Merging pattern 4'---1 and 4'---0 from group (2 0 5'00001). +Optimizing FSM `$fsm$\u_dataflow_core.GEN_SLOT[3].u_mm.state$21109' from module `\fpga_neural_v2_top'. +Optimizing FSM `$fsm$\u_dataflow_core.GEN_SLOT[2].u_np.np_state$21100' from module `\fpga_neural_v2_top'. + Merging pattern 5'----0 and 5'----1 from group (5 0 11'00010000000). + Merging pattern 5'----1 and 5'----0 from group (5 0 11'00010000000). +Optimizing FSM `$fsm$\u_dataflow_core.GEN_SLOT[2].u_mm.state$21093' from module `\fpga_neural_v2_top'. +Optimizing FSM `$fsm$\u_dataflow_core.GEN_SLOT[1].u_np.np_state$21084' from module `\fpga_neural_v2_top'. + Merging pattern 5'----0 and 5'----1 from group (5 0 11'00010000000). + Merging pattern 5'----1 and 5'----0 from group (5 0 11'00010000000). +Optimizing FSM `$fsm$\u_sdram_backend.u_sdram_ctrl.state$21070' from module `\fpga_neural_v2_top'. + Removing unused input signal $auto$opt_reduce.cc:137:opt_pmux$21034. +Optimizing FSM `$fsm$\u_dataflow_core.GEN_SLOT[1].u_mm.state$21063' from module `\fpga_neural_v2_top'. +Optimizing FSM `$fsm$\u_dataflow_core.GEN_SLOT[0].u_np.np_state$21054' from module `\fpga_neural_v2_top'. + Merging pattern 5'----0 and 5'----1 from group (5 0 11'00010000000). + Merging pattern 5'----1 and 5'----0 from group (5 0 11'00010000000). +Optimizing FSM `$fsm$\u_dataflow_core.u_director.dir_state$21048' from module `\fpga_neural_v2_top'. + Removing unused input signal $auto$opt_reduce.cc:137:opt_pmux$21028. +Optimizing FSM `$fsm$\u_dataflow_core.GEN_SLOT[0].u_mm.state$21041' from module `\fpga_neural_v2_top'. + +19.13.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \fpga_neural_v2_top.. +Removed 203 unused cells and 208 unused wires. + + +19.13.5. Executing FSM_OPT pass (simple optimizations of FSMs). +Optimizing FSM `$fsm$\u_dataflow_core.GEN_SLOT[3].u_np.np_state$21121' from module `\fpga_neural_v2_top'. + Removing unused output signal $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$0\np_state[3:0] [0]. + Removing unused output signal $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$0\np_state[3:0] [1]. + Removing unused output signal $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$0\np_state[3:0] [2]. + Removing unused output signal $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$0\np_state[3:0] [3]. + Removing unused output signal $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procmux$7535_CMP. + Removing unused output signal $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procmux$7536_CMP. +Optimizing FSM `$fsm$\u_spi_bridge.state$21130' from module `\fpga_neural_v2_top'. + Removing unused output signal $flatten\u_spi_bridge.$0\state[3:0] [0]. + Removing unused output signal $flatten\u_spi_bridge.$0\state[3:0] [1]. + Removing unused output signal $flatten\u_spi_bridge.$0\state[3:0] [2]. + Removing unused output signal $flatten\u_spi_bridge.$0\state[3:0] [3]. +Optimizing FSM `$fsm$\u_sdram_backend.state$21144' from module `\fpga_neural_v2_top'. + Removing unused output signal $flatten\u_sdram_backend.$0\state[2:0] [0]. + Removing unused output signal $flatten\u_sdram_backend.$0\state[2:0] [1]. + Removing unused output signal $flatten\u_sdram_backend.$0\state[2:0] [2]. +Optimizing FSM `$fsm$\u_dataflow_core.GEN_SLOT[0].u_mm.state$21041' from module `\fpga_neural_v2_top'. + Removing unused output signal $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$0\state[2:0] [0]. + Removing unused output signal $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$0\state[2:0] [1]. + Removing unused output signal $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$0\state[2:0] [2]. +Optimizing FSM `$fsm$\u_dataflow_core.u_director.dir_state$21048' from module `\fpga_neural_v2_top'. + Removing unused output signal $flatten\u_dataflow_core.\u_director.$0\dir_state[3:0] [0]. + Removing unused output signal $flatten\u_dataflow_core.\u_director.$0\dir_state[3:0] [1]. + Removing unused output signal $flatten\u_dataflow_core.\u_director.$0\dir_state[3:0] [2]. + Removing unused output signal $flatten\u_dataflow_core.\u_director.$0\dir_state[3:0] [3]. + Removing unused output signal $flatten\u_dataflow_core.\u_director.$procmux$19257_CMP. + Removing unused output signal $flatten\u_dataflow_core.\u_director.$procmux$19262_CMP. +Optimizing FSM `$fsm$\u_dataflow_core.GEN_SLOT[0].u_np.np_state$21054' from module `\fpga_neural_v2_top'. + Removing unused output signal $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$0\np_state[3:0] [0]. + Removing unused output signal $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$0\np_state[3:0] [1]. + Removing unused output signal $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$0\np_state[3:0] [2]. + Removing unused output signal $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$0\np_state[3:0] [3]. + Removing unused output signal $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procmux$7535_CMP. + Removing unused output signal $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procmux$7536_CMP. +Optimizing FSM `$fsm$\u_dataflow_core.GEN_SLOT[1].u_mm.state$21063' from module `\fpga_neural_v2_top'. + Removing unused output signal $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$0\state[2:0] [0]. + Removing unused output signal $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$0\state[2:0] [1]. + Removing unused output signal $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$0\state[2:0] [2]. +Optimizing FSM `$fsm$\u_sdram_backend.u_sdram_ctrl.state$21070' from module `\fpga_neural_v2_top'. + Removing unused output signal $flatten\u_sdram_backend.\u_sdram_ctrl.$0\state[4:0] [0]. + Removing unused output signal $flatten\u_sdram_backend.\u_sdram_ctrl.$0\state[4:0] [1]. + Removing unused output signal $flatten\u_sdram_backend.\u_sdram_ctrl.$0\state[4:0] [2]. + Removing unused output signal $flatten\u_sdram_backend.\u_sdram_ctrl.$0\state[4:0] [3]. + Removing unused output signal $flatten\u_sdram_backend.\u_sdram_ctrl.$0\state[4:0] [4]. +Optimizing FSM `$fsm$\u_dataflow_core.GEN_SLOT[1].u_np.np_state$21084' from module `\fpga_neural_v2_top'. + Removing unused output signal $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$0\np_state[3:0] [0]. + Removing unused output signal $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$0\np_state[3:0] [1]. + Removing unused output signal $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$0\np_state[3:0] [2]. + Removing unused output signal $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$0\np_state[3:0] [3]. + Removing unused output signal $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procmux$7535_CMP. + Removing unused output signal $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procmux$7536_CMP. +Optimizing FSM `$fsm$\u_dataflow_core.GEN_SLOT[2].u_mm.state$21093' from module `\fpga_neural_v2_top'. + Removing unused output signal $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$0\state[2:0] [0]. + Removing unused output signal $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$0\state[2:0] [1]. + Removing unused output signal $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$0\state[2:0] [2]. +Optimizing FSM `$fsm$\u_dataflow_core.GEN_SLOT[2].u_np.np_state$21100' from module `\fpga_neural_v2_top'. + Removing unused output signal $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$0\np_state[3:0] [0]. + Removing unused output signal $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$0\np_state[3:0] [1]. + Removing unused output signal $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$0\np_state[3:0] [2]. + Removing unused output signal $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$0\np_state[3:0] [3]. + Removing unused output signal $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procmux$7535_CMP. + Removing unused output signal $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procmux$7536_CMP. +Optimizing FSM `$fsm$\u_dataflow_core.GEN_SLOT[3].u_mm.state$21109' from module `\fpga_neural_v2_top'. + Removing unused output signal $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$0\state[2:0] [0]. + Removing unused output signal $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$0\state[2:0] [1]. + Removing unused output signal $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$0\state[2:0] [2]. +Optimizing FSM `$fsm$\u_dataflow_core.u_act_fill.u_pf.state$21116' from module `\fpga_neural_v2_top'. + Removing unused output signal $flatten\u_dataflow_core.\u_act_fill.\u_pf.$0\state[1:0] [0]. + Removing unused output signal $flatten\u_dataflow_core.\u_act_fill.\u_pf.$0\state[1:0] [1]. + +19.13.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). +Recoding FSM `$fsm$\u_dataflow_core.GEN_SLOT[3].u_np.np_state$21121' from module `\fpga_neural_v2_top' using `auto' encoding: + mapping auto encoding to `one-hot` for this FSM. + 0000 -> ------1 + 0100 -> -----1- + 0010 -> ----1-- + 0110 -> ---1--- + 0001 -> --1---- + 0101 -> -1----- + 0011 -> 1------ +Recoding FSM `$fsm$\u_spi_bridge.state$21130' from module `\fpga_neural_v2_top' using `auto' encoding: + mapping auto encoding to `one-hot` for this FSM. + 0000 -> ---------1 + 1000 -> --------1- + 0100 -> -------1-- + 0010 -> ------1--- + 0110 -> -----1---- + 0001 -> ----1----- + 1001 -> ---1------ + 0101 -> --1------- + 0011 -> -1-------- + 0111 -> 1--------- +Recoding FSM `$fsm$\u_sdram_backend.state$21144' from module `\fpga_neural_v2_top' using `auto' encoding: + mapping auto encoding to `one-hot` for this FSM. + 000 -> ---1 + 010 -> --1- + 001 -> -1-- + 011 -> 1--- +Recoding FSM `$fsm$\u_dataflow_core.GEN_SLOT[0].u_mm.state$21041' from module `\fpga_neural_v2_top' using `auto' encoding: + mapping auto encoding to `one-hot` for this FSM. + 000 -> ----1 + 100 -> ---1- + 010 -> --1-- + 001 -> -1--- + 011 -> 1---- +Recoding FSM `$fsm$\u_dataflow_core.u_director.dir_state$21048' from module `\fpga_neural_v2_top' using `auto' encoding: + mapping auto encoding to `one-hot` for this FSM. + 0000 -> ---1 + 0010 -> --1- + 0001 -> -1-- + 0011 -> 1--- +Recoding FSM `$fsm$\u_dataflow_core.GEN_SLOT[0].u_np.np_state$21054' from module `\fpga_neural_v2_top' using `auto' encoding: + mapping auto encoding to `one-hot` for this FSM. + 0000 -> ------1 + 0100 -> -----1- + 0010 -> ----1-- + 0110 -> ---1--- + 0001 -> --1---- + 0101 -> -1----- + 0011 -> 1------ +Recoding FSM `$fsm$\u_dataflow_core.GEN_SLOT[1].u_mm.state$21063' from module `\fpga_neural_v2_top' using `auto' encoding: + mapping auto encoding to `one-hot` for this FSM. + 000 -> ----1 + 100 -> ---1- + 010 -> --1-- + 001 -> -1--- + 011 -> 1---- +Recoding FSM `$fsm$\u_sdram_backend.u_sdram_ctrl.state$21070' from module `\fpga_neural_v2_top' using `auto' encoding: + mapping auto encoding to `one-hot` for this FSM. + 00000 -> -----------1 + 10000 -> ----------1- + 00100 -> ---------1-- + 00010 -> --------1--- + 00110 -> -------1---- + 01110 -> ------1----- + 01001 -> -----1------ + 01101 -> ----1------- + 00011 -> ---1-------- + 01011 -> --1--------- + 00111 -> -1---------- + 01111 -> 1----------- +Recoding FSM `$fsm$\u_dataflow_core.GEN_SLOT[1].u_np.np_state$21084' from module `\fpga_neural_v2_top' using `auto' encoding: + mapping auto encoding to `one-hot` for this FSM. + 0000 -> ------1 + 0100 -> -----1- + 0010 -> ----1-- + 0110 -> ---1--- + 0001 -> --1---- + 0101 -> -1----- + 0011 -> 1------ +Recoding FSM `$fsm$\u_dataflow_core.GEN_SLOT[2].u_mm.state$21093' from module `\fpga_neural_v2_top' using `auto' encoding: + mapping auto encoding to `one-hot` for this FSM. + 000 -> ----1 + 100 -> ---1- + 010 -> --1-- + 001 -> -1--- + 011 -> 1---- +Recoding FSM `$fsm$\u_dataflow_core.GEN_SLOT[2].u_np.np_state$21100' from module `\fpga_neural_v2_top' using `auto' encoding: + mapping auto encoding to `one-hot` for this FSM. + 0000 -> ------1 + 0100 -> -----1- + 0010 -> ----1-- + 0110 -> ---1--- + 0001 -> --1---- + 0101 -> -1----- + 0011 -> 1------ +Recoding FSM `$fsm$\u_dataflow_core.GEN_SLOT[3].u_mm.state$21109' from module `\fpga_neural_v2_top' using `auto' encoding: + mapping auto encoding to `one-hot` for this FSM. + 000 -> ----1 + 100 -> ---1- + 010 -> --1-- + 001 -> -1--- + 011 -> 1---- +Recoding FSM `$fsm$\u_dataflow_core.u_act_fill.u_pf.state$21116' from module `\fpga_neural_v2_top' using `auto' encoding: + mapping auto encoding to `one-hot` for this FSM. + 00 -> --1 + 10 -> -1- + 11 -> 1-- + +19.13.7. Executing FSM_INFO pass (dumping all available information on FSM cells). + +FSM `$fsm$\u_dataflow_core.GEN_SLOT[3].u_np.np_state$21121' from module `fpga_neural_v2_top': +------------------------------------- + + Information on FSM $fsm$\u_dataflow_core.GEN_SLOT[3].u_np.np_state$21121 (\u_dataflow_core.GEN_SLOT[3].u_np.np_state): + + Number of input signals: 5 + Number of output signals: 5 + Number of state bits: 7 + + Input signals: + 0: \core_rst + 1: \u_dataflow_core.GEN_SLOT[3].u_np.valid7 + 2: $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$logic_and$hardware/v2/rtl/neural_processor.v:332$3715_Y + 3: $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$logic_and$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:272$3780_Y + 4: $flatten\u_dataflow_core.$logic_and$hardware/v2/nms/rtl/nms_dataflow_core_sdram.v:284$7318_Y + + Output signals: + 0: $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$eq$hardware/v2/rtl/neural_processor.v:223$3687_Y + 1: $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$eq$hardware/v2/rtl/neural_processor.v:300$3709_Y + 2: $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procmux$7539_CMP + 3: $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procmux$7542_CMP + 4: \u_dataflow_core.GEN_SLOT[3].u_mm.operand_ready + + State encoding: + 0: 7'------1 + 1: 7'-----1- + 2: 7'----1-- + 3: 7'---1--- + 4: 7'--1---- + 5: 7'-1----- + 6: 7'1------ + + Transition Table (state_in, ctrl_in, state_out, ctrl_out): + 0: 0 5'0---0 -> 0 5'00010 + 1: 0 5'----1 -> 0 5'00010 + 2: 0 5'1---0 -> 4 5'00010 + 3: 1 5'----1 -> 0 5'00100 + 4: 1 5'-0--0 -> 1 5'00100 + 5: 1 5'-1--0 -> 5 5'00100 + 6: 2 5'----1 -> 0 5'10000 + 7: 2 5'--0-0 -> 2 5'10000 + 8: 2 5'--1-0 -> 6 5'10000 + 9: 3 5'----1 -> 0 5'00000 + 10: 3 5'----0 -> 3 5'00000 + 11: 4 5'----1 -> 0 5'00001 + 12: 4 5'----0 -> 2 5'00001 + 13: 5 5'----- -> 0 5'00000 + 14: 6 5'----1 -> 0 5'01000 + 15: 6 5'---10 -> 1 5'01000 + 16: 6 5'---00 -> 6 5'01000 + +------------------------------------- + +FSM `$fsm$\u_spi_bridge.state$21130' from module `fpga_neural_v2_top': +------------------------------------- + + Information on FSM $fsm$\u_spi_bridge.state$21130 (\u_spi_bridge.state): + + Number of input signals: 17 + Number of output signals: 12 + Number of state bits: 10 + + Input signals: + 0: $auto$opt_reduce.cc:137:opt_pmux$21030 + 1: \u_reset_sync.sync_ff [1] + 2: $flatten\u_spi_bridge.$procmux$18614_CMP + 3: $flatten\u_spi_bridge.$procmux$18276_CMP + 4: $flatten\u_spi_bridge.$procmux$18251_CMP + 5: $flatten\u_spi_bridge.$logic_and$hardware/v2/rtl/spi_host_bridge.v:409$7386_Y + 6: $flatten\u_spi_bridge.$logic_and$hardware/v2/rtl/spi_host_bridge.v:403$7384_Y + 7: $flatten\u_spi_bridge.$logic_and$hardware/v2/rtl/spi_host_bridge.v:397$7381_Y + 8: $flatten\u_spi_bridge.$eq$hardware/v2/rtl/spi_host_bridge.v:394$7375_Y + 9: $flatten\u_spi_bridge.$logic_and$hardware/v2/rtl/spi_host_bridge.v:389$7372_Y + 10: $flatten\u_spi_bridge.$logic_and$hardware/v2/rtl/spi_host_bridge.v:382$7369_Y + 11: $flatten\u_spi_bridge.$logic_and$hardware/v2/rtl/spi_host_bridge.v:376$7364_Y + 12: $flatten\u_spi_bridge.$eq$hardware/v2/rtl/spi_host_bridge.v:357$7359_Y + 13: $flatten\u_spi_bridge.$logic_and$hardware/v2/rtl/spi_host_bridge.v:296$7353_Y + 14: $flatten\u_spi_bridge.$logic_and$hardware/v2/rtl/spi_host_bridge.v:293$7351_Y + 15: $flatten\u_spi_bridge.$eq$hardware/v2/rtl/spi_host_bridge.v:255$7343_Y + 16: \u_spi_bridge.cs_rose + + Output signals: + 0: $flatten\u_spi_bridge.$procmux$18556_CMP + 1: $flatten\u_spi_bridge.$procmux$18278_CMP + 2: $flatten\u_spi_bridge.$procmux$18234_CMP + 3: $flatten\u_spi_bridge.$procmux$18221_CMP + 4: $flatten\u_spi_bridge.$procmux$18172_CMP + 5: $flatten\u_spi_bridge.$eq$hardware/v2/rtl/spi_host_bridge.v:397$7377_Y + 6: $flatten\u_spi_bridge.$eq$hardware/v2/rtl/spi_host_bridge.v:382$7365_Y + 7: $flatten\u_spi_bridge.$eq$hardware/v2/rtl/spi_host_bridge.v:376$7362_Y + 8: $flatten\u_spi_bridge.$ne$hardware/v2/rtl/spi_host_bridge.v:293$7350_Y + 9: $flatten\u_spi_bridge.$ne$hardware/v2/rtl/spi_host_bridge.v:293$7348_Y + 10: $flatten\u_spi_bridge.$ne$hardware/v2/rtl/spi_host_bridge.v:293$7346_Y + 11: $flatten\u_spi_bridge.$eq$hardware/v2/rtl/spi_host_bridge.v:254$7341_Y + + State encoding: + 0: 10'---------1 + 1: 10'--------1- + 2: 10'-------1-- + 3: 10'------1--- + 4: 10'-----1---- + 5: 10'----1----- + 6: 10'---1------ + 7: 10'--1------- + 8: 10'-1-------- + 9: 10'1--------- + + Transition Table (state_in, ctrl_in, state_out, ctrl_out): + 0: 0 17'---------------0- -> 0 12'011100000001 + 1: 0 17'0-00-000-000---1- -> 0 12'011100000001 + 2: 0 17'0-1--000-000---1- -> 0 12'011100000001 + 3: 0 17'0-00-01--000---1- -> 0 12'011100000001 + 4: 0 17'0-1--01--000---1- -> 0 12'011100000001 + 5: 0 17'0-00-000-1-0---1- -> 0 12'011100000001 + 6: 0 17'0-1--000-1-0---1- -> 0 12'011100000001 + 7: 0 17'0-00-01--1-0---1- -> 0 12'011100000001 + 8: 0 17'0-1--01--1-0---1- -> 0 12'011100000001 + 9: 0 17'0100-000-001---1- -> 0 12'011100000001 + 10: 0 17'011--000-001---1- -> 0 12'011100000001 + 11: 0 17'0100-01--001---1- -> 0 12'011100000001 + 12: 0 17'011--01--001---1- -> 0 12'011100000001 + 13: 0 17'0100-000-1-1---1- -> 0 12'011100000001 + 14: 0 17'011--000-1-1---1- -> 0 12'011100000001 + 15: 0 17'0100-01--1-1---1- -> 0 12'011100000001 + 16: 0 17'011--01--1-1---1- -> 0 12'011100000001 + 17: 0 17'1--------------1- -> 0 12'011100000001 + 18: 0 17'0--------010---1- -> 1 12'011100000001 + 19: 0 17'01-------011---1- -> 1 12'011100000001 + 20: 0 17'0-01-000-000--11- -> 5 12'011100000001 + 21: 0 17'0-01-01--000--11- -> 5 12'011100000001 + 22: 0 17'0-01-000-1-0--11- -> 5 12'011100000001 + 23: 0 17'0-01-01--1-0--11- -> 5 12'011100000001 + 24: 0 17'0101-000-001--11- -> 5 12'011100000001 + 25: 0 17'0101-01--001--11- -> 5 12'011100000001 + 26: 0 17'0101-000-1-1--11- -> 5 12'011100000001 + 27: 0 17'0101-01--1-1--11- -> 5 12'011100000001 + 28: 0 17'0-01-000-000--010 -> 6 12'011100000001 + 29: 0 17'0-01-01--000--010 -> 6 12'011100000001 + 30: 0 17'0-01-000-1-0--010 -> 6 12'011100000001 + 31: 0 17'0-01-01--1-0--010 -> 6 12'011100000001 + 32: 0 17'0101-000-001--010 -> 6 12'011100000001 + 33: 0 17'0101-01--001--010 -> 6 12'011100000001 + 34: 0 17'0101-000-1-1--010 -> 6 12'011100000001 + 35: 0 17'0101-01--1-1--010 -> 6 12'011100000001 + 36: 0 17'0-----011000---1- -> 6 12'011100000001 + 37: 0 17'0----100-000---1- -> 6 12'011100000001 + 38: 0 17'0----11--000---1- -> 6 12'011100000001 + 39: 0 17'0-----0111-0---1- -> 6 12'011100000001 + 40: 0 17'0----100-1-0---1- -> 6 12'011100000001 + 41: 0 17'0----11--1-0---1- -> 6 12'011100000001 + 42: 0 17'01----011001---1- -> 6 12'011100000001 + 43: 0 17'01---100-001---1- -> 6 12'011100000001 + 44: 0 17'01---11--001---1- -> 6 12'011100000001 + 45: 0 17'01----0111-1---1- -> 6 12'011100000001 + 46: 0 17'01---100-1-1---1- -> 6 12'011100000001 + 47: 0 17'01---11--1-1---1- -> 6 12'011100000001 + 48: 0 17'00------1--1---1- -> 6 12'011100000001 + 49: 0 17'0-----010000---1- -> 7 12'011100000001 + 50: 0 17'0-----0101-0---1- -> 7 12'011100000001 + 51: 0 17'01----010001---1- -> 7 12'011100000001 + 52: 0 17'01----0101-1---1- -> 7 12'011100000001 + 53: 0 17'0-01-000-000---11 -> 8 12'011100000001 + 54: 0 17'0-01-01--000---11 -> 8 12'011100000001 + 55: 0 17'0-01-000-1-0---11 -> 8 12'011100000001 + 56: 0 17'0-01-01--1-0---11 -> 8 12'011100000001 + 57: 0 17'0101-000-001---11 -> 8 12'011100000001 + 58: 0 17'0101-01--001---11 -> 8 12'011100000001 + 59: 0 17'0101-000-1-1---11 -> 8 12'011100000001 + 60: 0 17'0101-01--1-1---11 -> 8 12'011100000001 + 61: 0 17'00------0--1---1- -> 9 12'011100000001 + 62: 1 17'---------------0- -> 0 12'111100000000 + 63: 1 17'0-1--000-000---1- -> 0 12'111100000000 + 64: 1 17'0-1--01--000---1- -> 0 12'111100000000 + 65: 1 17'0-1--000-1-0---1- -> 0 12'111100000000 + 66: 1 17'0-1--01--1-0---1- -> 0 12'111100000000 + 67: 1 17'011--000-001---1- -> 0 12'111100000000 + 68: 1 17'011--01--001---1- -> 0 12'111100000000 + 69: 1 17'011--000-1-1---1- -> 0 12'111100000000 + 70: 1 17'011--01--1-1---1- -> 0 12'111100000000 + 71: 1 17'1--------------1- -> 0 12'111100000000 + 72: 1 17'0-0--000-000---1- -> 1 12'111100000000 + 73: 1 17'0-0--01--000---1- -> 1 12'111100000000 + 74: 1 17'0--------010---1- -> 1 12'111100000000 + 75: 1 17'0-0--000-1-0---1- -> 1 12'111100000000 + 76: 1 17'0-0--01--1-0---1- -> 1 12'111100000000 + 77: 1 17'010--000-001---1- -> 1 12'111100000000 + 78: 1 17'010--01--001---1- -> 1 12'111100000000 + 79: 1 17'01-------011---1- -> 1 12'111100000000 + 80: 1 17'010--000-1-1---1- -> 1 12'111100000000 + 81: 1 17'010--01--1-1---1- -> 1 12'111100000000 + 82: 1 17'0-----011000---1- -> 6 12'111100000000 + 83: 1 17'0----100-000---1- -> 6 12'111100000000 + 84: 1 17'0----11--000---1- -> 6 12'111100000000 + 85: 1 17'0-----0111-0---1- -> 6 12'111100000000 + 86: 1 17'0----100-1-0---1- -> 6 12'111100000000 + 87: 1 17'0----11--1-0---1- -> 6 12'111100000000 + 88: 1 17'01----011001---1- -> 6 12'111100000000 + 89: 1 17'01---100-001---1- -> 6 12'111100000000 + 90: 1 17'01---11--001---1- -> 6 12'111100000000 + 91: 1 17'01----0111-1---1- -> 6 12'111100000000 + 92: 1 17'01---100-1-1---1- -> 6 12'111100000000 + 93: 1 17'01---11--1-1---1- -> 6 12'111100000000 + 94: 1 17'00------1--1---1- -> 6 12'111100000000 + 95: 1 17'0-----010000---1- -> 7 12'111100000000 + 96: 1 17'0-----0101-0---1- -> 7 12'111100000000 + 97: 1 17'01----010001---1- -> 7 12'111100000000 + 98: 1 17'01----0101-1---1- -> 7 12'111100000000 + 99: 1 17'00------0--1---1- -> 9 12'111100000000 + 100: 2 17'---------------0- -> 0 12'011100001000 + 101: 2 17'0-1--000-000---1- -> 0 12'011100001000 + 102: 2 17'0-1--01--000---1- -> 0 12'011100001000 + 103: 2 17'0-1--000-1-0---1- -> 0 12'011100001000 + 104: 2 17'0-1--01--1-0---1- -> 0 12'011100001000 + 105: 2 17'011--000-001---1- -> 0 12'011100001000 + 106: 2 17'011--01--001---1- -> 0 12'011100001000 + 107: 2 17'011--000-1-1---1- -> 0 12'011100001000 + 108: 2 17'011--01--1-1---1- -> 0 12'011100001000 + 109: 2 17'1--------------1- -> 0 12'011100001000 + 110: 2 17'0--------010---1- -> 1 12'011100001000 + 111: 2 17'01-------011---1- -> 1 12'011100001000 + 112: 2 17'0-00-000-000---1- -> 2 12'011100001000 + 113: 2 17'0-00-01--000---1- -> 2 12'011100001000 + 114: 2 17'0-00-000-1-0---1- -> 2 12'011100001000 + 115: 2 17'0-00-01--1-0---1- -> 2 12'011100001000 + 116: 2 17'0100-000-001---1- -> 2 12'011100001000 + 117: 2 17'0100-01--001---1- -> 2 12'011100001000 + 118: 2 17'0100-000-1-1---1- -> 2 12'011100001000 + 119: 2 17'0100-01--1-1---1- -> 2 12'011100001000 + 120: 2 17'0101-000-00----1- -> 2 12'011100001000 + 121: 2 17'0101-01--00----1- -> 2 12'011100001000 + 122: 2 17'0101-000-1-----1- -> 2 12'011100001000 + 123: 2 17'0101-01--1-----1- -> 2 12'011100001000 + 124: 2 17'0-----011000---1- -> 6 12'011100001000 + 125: 2 17'0----100-000---1- -> 6 12'011100001000 + 126: 2 17'0----11--000---1- -> 6 12'011100001000 + 127: 2 17'0-----0111-0---1- -> 6 12'011100001000 + 128: 2 17'0----100-1-0---1- -> 6 12'011100001000 + 129: 2 17'0----11--1-0---1- -> 6 12'011100001000 + 130: 2 17'01----011001---1- -> 6 12'011100001000 + 131: 2 17'01---100-001---1- -> 6 12'011100001000 + 132: 2 17'01---11--001---1- -> 6 12'011100001000 + 133: 2 17'01----0111-1---1- -> 6 12'011100001000 + 134: 2 17'01---100-1-1---1- -> 6 12'011100001000 + 135: 2 17'01---11--1-1---1- -> 6 12'011100001000 + 136: 2 17'00------1--1---1- -> 6 12'011100001000 + 137: 2 17'0-----010000---1- -> 7 12'011100001000 + 138: 2 17'00011000-000---1- -> 7 12'011100001000 + 139: 2 17'0001101--000---1- -> 7 12'011100001000 + 140: 2 17'0-----0101-0---1- -> 7 12'011100001000 + 141: 2 17'00011000-1-0---1- -> 7 12'011100001000 + 142: 2 17'0001101--1-0---1- -> 7 12'011100001000 + 143: 2 17'01----010001---1- -> 7 12'011100001000 + 144: 2 17'01----0101-1---1- -> 7 12'011100001000 + 145: 2 17'00010000-000---1- -> 9 12'011100001000 + 146: 2 17'0001001--000---1- -> 9 12'011100001000 + 147: 2 17'00010000-1-0---1- -> 9 12'011100001000 + 148: 2 17'0001001--1-0---1- -> 9 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12'011000100000 + 422: 9 17'-11--01--001---1- -> 0 12'011000100000 + 423: 9 17'-11--000-1-1---1- -> 0 12'011000100000 + 424: 9 17'-11--01--1-1---1- -> 0 12'011000100000 + 425: 9 17'---------010---1- -> 1 12'011000100000 + 426: 9 17'-1-------011---1- -> 1 12'011000100000 + 427: 9 17'------011000---1- -> 6 12'011000100000 + 428: 9 17'-----100-000---1- -> 6 12'011000100000 + 429: 9 17'-----11--000---1- -> 6 12'011000100000 + 430: 9 17'------0111-0---1- -> 6 12'011000100000 + 431: 9 17'-----100-1-0---1- -> 6 12'011000100000 + 432: 9 17'-----11--1-0---1- -> 6 12'011000100000 + 433: 9 17'-1----011001---1- -> 6 12'011000100000 + 434: 9 17'-1---100-001---1- -> 6 12'011000100000 + 435: 9 17'-1---11--001---1- -> 6 12'011000100000 + 436: 9 17'-1----0111-1---1- -> 6 12'011000100000 + 437: 9 17'-1---100-1-1---1- -> 6 12'011000100000 + 438: 9 17'-1---11--1-1---1- -> 6 12'011000100000 + 439: 9 17'-0------1--1---1- -> 6 12'011000100000 + 440: 9 17'------010000---1- -> 7 12'011000100000 + 441: 9 17'------0101-0---1- -> 7 12'011000100000 + 442: 9 17'-1----010001---1- -> 7 12'011000100000 + 443: 9 17'-1----0101-1---1- -> 7 12'011000100000 + 444: 9 17'--0--000-000---1- -> 9 12'011000100000 + 445: 9 17'--0--01--000---1- -> 9 12'011000100000 + 446: 9 17'--0--000-1-0---1- -> 9 12'011000100000 + 447: 9 17'--0--01--1-0---1- -> 9 12'011000100000 + 448: 9 17'-10--000-001---1- -> 9 12'011000100000 + 449: 9 17'-10--01--001---1- -> 9 12'011000100000 + 450: 9 17'-10--000-1-1---1- -> 9 12'011000100000 + 451: 9 17'-10--01--1-1---1- -> 9 12'011000100000 + 452: 9 17'-0------0--1---1- -> 9 12'011000100000 + +------------------------------------- + +FSM `$fsm$\u_sdram_backend.state$21144' from module `fpga_neural_v2_top': +------------------------------------- + + Information on FSM $fsm$\u_sdram_backend.state$21144 (\u_sdram_backend.state): + + Number of input signals: 6 + Number of output signals: 4 + Number of state bits: 4 + + Input signals: + 0: \core_rst + 1: \u_sdram_backend.u_sdram_ctrl.ready + 2: $flatten\u_sdram_backend.$logic_and$hardware/v2/nms/rtl/sdram_unified_backend.v:272$7030_Y + 3: $flatten\u_sdram_backend.$logic_and$hardware/v2/nms/rtl/sdram_unified_backend.v:264$7029_Y + 4: \u_sdram_backend.w_eff_req + 5: \u_sdram_backend.w_cache_hit + + Output signals: + 0: $flatten\u_sdram_backend.$procmux$9308_CMP + 1: $flatten\u_sdram_backend.$procmux$9305_CMP + 2: $flatten\u_sdram_backend.$procmux$9155_CMP + 3: $flatten\u_sdram_backend.$procmux$8835_CMP + + State encoding: + 0: 4'---1 + 1: 4'--1- + 2: 4'-1-- + 3: 4'1--- + + Transition Table (state_in, ctrl_in, state_out, ctrl_out): + 0: 0 6'0000-0 -> 0 4'0100 + 1: 0 6'1----0 -> 0 4'0100 + 2: 0 6'-----1 -> 0 4'0100 + 3: 0 6'001--0 -> 1 4'0100 + 4: 0 6'01---0 -> 2 4'0100 + 5: 0 6'0001-0 -> 3 4'0100 + 6: 1 6'----10 -> 0 4'0001 + 7: 1 6'-----1 -> 0 4'0001 + 8: 1 6'----00 -> 1 4'0001 + 9: 2 6'----10 -> 0 4'1000 + 10: 2 6'-----1 -> 0 4'1000 + 11: 2 6'----00 -> 2 4'1000 + 12: 3 6'----10 -> 0 4'0010 + 13: 3 6'-----1 -> 0 4'0010 + 14: 3 6'----00 -> 3 4'0010 + +------------------------------------- + +FSM `$fsm$\u_dataflow_core.GEN_SLOT[0].u_mm.state$21041' from module `fpga_neural_v2_top': +------------------------------------- + + Information on FSM $fsm$\u_dataflow_core.GEN_SLOT[0].u_mm.state$21041 (\u_dataflow_core.GEN_SLOT[0].u_mm.state): + + Number of input signals: 6 + Number of output signals: 5 + Number of state bits: 5 + + Input signals: + 0: \core_rst + 1: $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$logic_and$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:191$3766_Y + 2: $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$eq$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:247$3775_Y + 3: $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$logic_and$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:272$3780_Y + 4: \u_dataflow_core.u_director.slot_job_start [0] + 5: \u_arbiter.s_ready [0] + + Output signals: + 0: $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$eq$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:192$3768_Y + 1: $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$procmux$19751_CMP + 2: $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$procmux$19759_CMP + 3: $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$procmux$19812_CMP + 4: $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$procmux$19888_CMP + + State encoding: + 0: 5'----1 + 1: 5'---1- + 2: 5'--1-- + 3: 5'-1--- + 4: 5'1---- + + Transition Table (state_in, ctrl_in, state_out, ctrl_out): + 0: 0 6'-0---0 -> 0 5'01000 + 1: 0 6'-----1 -> 0 5'01000 + 2: 0 6'-1---0 -> 3 5'01000 + 3: 1 6'1----0 -> 0 5'00100 + 4: 1 6'-----1 -> 0 5'00100 + 5: 1 6'0----0 -> 1 5'00100 + 6: 2 6'-----1 -> 0 5'00010 + 7: 2 6'--0--0 -> 2 5'00010 + 8: 2 6'--1--0 -> 4 5'00010 + 9: 3 6'-----1 -> 0 5'00001 + 10: 3 6'---110 -> 2 5'00001 + 11: 3 6'----00 -> 3 5'00001 + 12: 3 6'---010 -> 3 5'00001 + 13: 4 6'-----1 -> 0 5'10000 + 14: 4 6'-----0 -> 1 5'10000 + +------------------------------------- + +FSM `$fsm$\u_dataflow_core.u_director.dir_state$21048' from module `fpga_neural_v2_top': +------------------------------------- + + Information on FSM $fsm$\u_dataflow_core.u_director.dir_state$21048 (\u_dataflow_core.u_director.dir_state): + + Number of input signals: 2 + Number of output signals: 2 + Number of state bits: 4 + + Input signals: + 0: \core_rst + 1: $flatten\u_dataflow_core.\u_director.$logic_and$hardware/v2/rtl/neural_director.v:198$4379_Y + + Output signals: + 0: $flatten\u_dataflow_core.\u_director.$eq$hardware/v2/rtl/neural_director.v:229$4447_Y + 1: $flatten\u_dataflow_core.\u_director.$procmux$18955_CMP + + State encoding: + 0: 4'---1 + 1: 4'--1- + 2: 4'-1-- + 3: 4'1--- + + Transition Table (state_in, ctrl_in, state_out, ctrl_out): + 0: 0 2'-1 -> 0 2'00 + 1: 0 2'-0 -> 2 2'00 + 2: 1 2'-1 -> 0 2'10 + 3: 1 2'-0 -> 2 2'10 + 4: 2 2'-1 -> 0 2'01 + 5: 2 2'10 -> 1 2'01 + 6: 2 2'00 -> 2 2'01 + 7: 3 2'-1 -> 0 2'00 + 8: 3 2'-0 -> 3 2'00 + +------------------------------------- + +FSM `$fsm$\u_dataflow_core.GEN_SLOT[0].u_np.np_state$21054' from module `fpga_neural_v2_top': +------------------------------------- + + Information on FSM $fsm$\u_dataflow_core.GEN_SLOT[0].u_np.np_state$21054 (\u_dataflow_core.GEN_SLOT[0].u_np.np_state): + + Number of input signals: 5 + Number of output signals: 5 + Number of state bits: 7 + + Input signals: + 0: \core_rst + 1: \u_dataflow_core.GEN_SLOT[0].u_np.valid7 + 2: $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$logic_and$hardware/v2/rtl/neural_processor.v:332$3715_Y + 3: $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$logic_and$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:272$3780_Y + 4: $flatten\u_dataflow_core.$logic_and$hardware/v2/nms/rtl/nms_dataflow_core_sdram.v:284$7309_Y + + Output signals: + 0: $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$eq$hardware/v2/rtl/neural_processor.v:223$3687_Y + 1: $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$eq$hardware/v2/rtl/neural_processor.v:300$3709_Y + 2: $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procmux$7539_CMP + 3: $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procmux$7542_CMP + 4: \u_dataflow_core.GEN_SLOT[0].u_mm.operand_ready + + State encoding: + 0: 7'------1 + 1: 7'-----1- + 2: 7'----1-- + 3: 7'---1--- + 4: 7'--1---- + 5: 7'-1----- + 6: 7'1------ + + Transition Table (state_in, ctrl_in, state_out, ctrl_out): + 0: 0 5'0---0 -> 0 5'00010 + 1: 0 5'----1 -> 0 5'00010 + 2: 0 5'1---0 -> 4 5'00010 + 3: 1 5'----1 -> 0 5'00100 + 4: 1 5'-0--0 -> 1 5'00100 + 5: 1 5'-1--0 -> 5 5'00100 + 6: 2 5'----1 -> 0 5'10000 + 7: 2 5'--0-0 -> 2 5'10000 + 8: 2 5'--1-0 -> 6 5'10000 + 9: 3 5'----1 -> 0 5'00000 + 10: 3 5'----0 -> 3 5'00000 + 11: 4 5'----1 -> 0 5'00001 + 12: 4 5'----0 -> 2 5'00001 + 13: 5 5'----- -> 0 5'00000 + 14: 6 5'----1 -> 0 5'01000 + 15: 6 5'---10 -> 1 5'01000 + 16: 6 5'---00 -> 6 5'01000 + +------------------------------------- + +FSM `$fsm$\u_dataflow_core.GEN_SLOT[1].u_mm.state$21063' from module `fpga_neural_v2_top': +------------------------------------- + + Information on FSM $fsm$\u_dataflow_core.GEN_SLOT[1].u_mm.state$21063 (\u_dataflow_core.GEN_SLOT[1].u_mm.state): + + Number of input signals: 6 + Number of output signals: 5 + Number of state bits: 5 + + Input signals: + 0: \core_rst + 1: $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$logic_and$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:191$3766_Y + 2: $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$eq$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:247$3775_Y + 3: $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$logic_and$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:272$3780_Y + 4: \u_dataflow_core.u_director.slot_job_start [1] + 5: \u_arbiter.s_ready [1] + + Output signals: + 0: $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$eq$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:192$3768_Y + 1: $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$procmux$19751_CMP + 2: $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$procmux$19759_CMP + 3: $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$procmux$19812_CMP + 4: $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$procmux$19888_CMP + + State encoding: + 0: 5'----1 + 1: 5'---1- + 2: 5'--1-- + 3: 5'-1--- + 4: 5'1---- + + Transition Table (state_in, ctrl_in, state_out, ctrl_out): + 0: 0 6'-0---0 -> 0 5'01000 + 1: 0 6'-----1 -> 0 5'01000 + 2: 0 6'-1---0 -> 3 5'01000 + 3: 1 6'1----0 -> 0 5'00100 + 4: 1 6'-----1 -> 0 5'00100 + 5: 1 6'0----0 -> 1 5'00100 + 6: 2 6'-----1 -> 0 5'00010 + 7: 2 6'--0--0 -> 2 5'00010 + 8: 2 6'--1--0 -> 4 5'00010 + 9: 3 6'-----1 -> 0 5'00001 + 10: 3 6'---110 -> 2 5'00001 + 11: 3 6'----00 -> 3 5'00001 + 12: 3 6'---010 -> 3 5'00001 + 13: 4 6'-----1 -> 0 5'10000 + 14: 4 6'-----0 -> 1 5'10000 + +------------------------------------- + +FSM `$fsm$\u_sdram_backend.u_sdram_ctrl.state$21070' from module `fpga_neural_v2_top': +------------------------------------- + + Information on FSM $fsm$\u_sdram_backend.u_sdram_ctrl.state$21070 (\u_sdram_backend.u_sdram_ctrl.state): + + Number of input signals: 8 + Number of output signals: 12 + Number of state bits: 12 + + Input signals: + 0: \core_rst + 1: \u_sdram_backend.u_sdram_ctrl.req_wr_reg + 2: $flatten\u_sdram_backend.\u_sdram_ctrl.$ne$hardware/v2/nms/rtl/sdram_controller.v:256$7426_Y + 3: $flatten\u_sdram_backend.\u_sdram_ctrl.$lt$hardware/v2/nms/rtl/sdram_controller.v:279$7432_Y + 4: $flatten\u_sdram_backend.\u_sdram_ctrl.$eq$hardware/v2/nms/rtl/sdram_controller.v:305$7436_Y + 5: $flatten\u_sdram_backend.\u_sdram_ctrl.$logic_or$hardware/v2/nms/rtl/sdram_controller.v:315$7437_Y + 6: $flatten\u_sdram_backend.\u_sdram_ctrl.$eq$hardware/v2/nms/rtl/sdram_controller.v:411$7456_Y + 7: $flatten\u_sdram_backend.\u_sdram_ctrl.$lt$hardware/v2/nms/rtl/sdram_controller.v:423$7458_Y + + Output signals: + 0: $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10012_CMP + 1: $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10079_CMP + 2: $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10083_CMP + 3: $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10087_CMP + 4: $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10091_CMP + 5: $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10128_CMP + 6: $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10137_CMP + 7: $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10160_CMP + 8: $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10170_CMP + 9: $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10178_CMP + 10: $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10182_CMP + 11: $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10186_CMP + + State encoding: + 0: 12'-----------1 + 1: 12'----------1- + 2: 12'---------1-- + 3: 12'--------1--- + 4: 12'-------1---- + 5: 12'------1----- + 6: 12'-----1------ + 7: 12'----1------- + 8: 12'---1-------- + 9: 12'--1--------- + 10: 12'-1---------- + 11: 12'1----------- + + Transition Table (state_in, ctrl_in, state_out, ctrl_out): + 0: 0 8'-----1-0 -> 0 12'100000000000 + 1: 0 8'-------1 -> 0 12'100000000000 + 2: 0 8'-----0-0 -> 3 12'100000000000 + 3: 1 8'-------1 -> 0 12'000001000000 + 4: 1 8'-----1-0 -> 1 12'000001000000 + 5: 1 8'-----0-0 -> 10 12'000001000000 + 6: 2 8'-------1 -> 0 12'000000100000 + 7: 2 8'-----1-0 -> 2 12'000000100000 + 8: 2 8'----00-0 -> 4 12'000000100000 + 9: 2 8'----10-0 -> 8 12'000000100000 + 10: 3 8'-------1 -> 0 12'010000000000 + 11: 3 8'-----1-0 -> 3 12'010000000000 + 12: 3 8'-----0-0 -> 8 12'010000000000 + 13: 4 8'-------1 -> 0 12'000100000000 + 14: 4 8'-----1-0 -> 4 12'000100000000 + 15: 4 8'-----0-0 -> 10 12'000100000000 + 16: 5 8'-------1 -> 0 12'000000000100 + 17: 5 8'-1-----0 -> 1 12'000000000100 + 18: 5 8'-0-----0 -> 5 12'000000000100 + 19: 6 8'-------1 -> 0 12'000010000000 + 20: 6 8'-----1-0 -> 6 12'000010000000 + 21: 6 8'-----0-0 -> 10 12'000010000000 + 22: 7 8'-------1 -> 0 12'000000001000 + 23: 7 8'-----0-0 -> 5 12'000000001000 + 24: 7 8'-----1-0 -> 7 12'000000001000 + 25: 8 8'-------1 -> 0 12'001000000000 + 26: 8 8'-------0 -> 2 12'001000000000 + 27: 9 8'-------1 -> 0 12'000000010000 + 28: 9 8'-----000 -> 7 12'000000010000 + 29: 9 8'-----1-0 -> 9 12'000000010000 + 30: 9 8'-----010 -> 11 12'000000010000 + 31: 10 8'-------1 -> 0 12'000000000001 + 32: 10 8'---1---0 -> 6 12'000000000001 + 33: 10 8'--10---0 -> 9 12'000000000001 + 34: 10 8'--00---0 -> 10 12'000000000001 + 35: 11 8'-------1 -> 0 12'000000000010 + 36: 11 8'0------0 -> 1 12'000000000010 + 37: 11 8'1------0 -> 11 12'000000000010 + +------------------------------------- + +FSM `$fsm$\u_dataflow_core.GEN_SLOT[1].u_np.np_state$21084' from module `fpga_neural_v2_top': +------------------------------------- + + Information on FSM $fsm$\u_dataflow_core.GEN_SLOT[1].u_np.np_state$21084 (\u_dataflow_core.GEN_SLOT[1].u_np.np_state): + + Number of input signals: 5 + Number of output signals: 5 + Number of state bits: 7 + + Input signals: + 0: \core_rst + 1: \u_dataflow_core.GEN_SLOT[1].u_np.valid7 + 2: $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$logic_and$hardware/v2/rtl/neural_processor.v:332$3715_Y + 3: $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$logic_and$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:272$3780_Y + 4: $flatten\u_dataflow_core.$logic_and$hardware/v2/nms/rtl/nms_dataflow_core_sdram.v:284$7312_Y + + Output signals: + 0: $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$eq$hardware/v2/rtl/neural_processor.v:223$3687_Y + 1: $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$eq$hardware/v2/rtl/neural_processor.v:300$3709_Y + 2: $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procmux$7539_CMP + 3: $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procmux$7542_CMP + 4: \u_dataflow_core.GEN_SLOT[1].u_mm.operand_ready + + State encoding: + 0: 7'------1 + 1: 7'-----1- + 2: 7'----1-- + 3: 7'---1--- + 4: 7'--1---- + 5: 7'-1----- + 6: 7'1------ + + Transition Table (state_in, ctrl_in, state_out, ctrl_out): + 0: 0 5'0---0 -> 0 5'00010 + 1: 0 5'----1 -> 0 5'00010 + 2: 0 5'1---0 -> 4 5'00010 + 3: 1 5'----1 -> 0 5'00100 + 4: 1 5'-0--0 -> 1 5'00100 + 5: 1 5'-1--0 -> 5 5'00100 + 6: 2 5'----1 -> 0 5'10000 + 7: 2 5'--0-0 -> 2 5'10000 + 8: 2 5'--1-0 -> 6 5'10000 + 9: 3 5'----1 -> 0 5'00000 + 10: 3 5'----0 -> 3 5'00000 + 11: 4 5'----1 -> 0 5'00001 + 12: 4 5'----0 -> 2 5'00001 + 13: 5 5'----- -> 0 5'00000 + 14: 6 5'----1 -> 0 5'01000 + 15: 6 5'---10 -> 1 5'01000 + 16: 6 5'---00 -> 6 5'01000 + +------------------------------------- + +FSM `$fsm$\u_dataflow_core.GEN_SLOT[2].u_mm.state$21093' from module `fpga_neural_v2_top': +------------------------------------- + + Information on FSM $fsm$\u_dataflow_core.GEN_SLOT[2].u_mm.state$21093 (\u_dataflow_core.GEN_SLOT[2].u_mm.state): + + Number of input signals: 6 + Number of output signals: 5 + Number of state bits: 5 + + Input signals: + 0: \core_rst + 1: $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$logic_and$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:191$3766_Y + 2: $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$eq$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:247$3775_Y + 3: $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$logic_and$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:272$3780_Y + 4: \u_dataflow_core.u_director.slot_job_start [2] + 5: \u_arbiter.s_ready [2] + + Output signals: + 0: $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$eq$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:192$3768_Y + 1: $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$procmux$19751_CMP + 2: $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$procmux$19759_CMP + 3: $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$procmux$19812_CMP + 4: $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$procmux$19888_CMP + + State encoding: + 0: 5'----1 + 1: 5'---1- + 2: 5'--1-- + 3: 5'-1--- + 4: 5'1---- + + Transition Table (state_in, ctrl_in, state_out, ctrl_out): + 0: 0 6'-0---0 -> 0 5'01000 + 1: 0 6'-----1 -> 0 5'01000 + 2: 0 6'-1---0 -> 3 5'01000 + 3: 1 6'1----0 -> 0 5'00100 + 4: 1 6'-----1 -> 0 5'00100 + 5: 1 6'0----0 -> 1 5'00100 + 6: 2 6'-----1 -> 0 5'00010 + 7: 2 6'--0--0 -> 2 5'00010 + 8: 2 6'--1--0 -> 4 5'00010 + 9: 3 6'-----1 -> 0 5'00001 + 10: 3 6'---110 -> 2 5'00001 + 11: 3 6'----00 -> 3 5'00001 + 12: 3 6'---010 -> 3 5'00001 + 13: 4 6'-----1 -> 0 5'10000 + 14: 4 6'-----0 -> 1 5'10000 + +------------------------------------- + +FSM `$fsm$\u_dataflow_core.GEN_SLOT[2].u_np.np_state$21100' from module `fpga_neural_v2_top': +------------------------------------- + + Information on FSM $fsm$\u_dataflow_core.GEN_SLOT[2].u_np.np_state$21100 (\u_dataflow_core.GEN_SLOT[2].u_np.np_state): + + Number of input signals: 5 + Number of output signals: 5 + Number of state bits: 7 + + Input signals: + 0: \core_rst + 1: \u_dataflow_core.GEN_SLOT[2].u_np.valid7 + 2: $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$logic_and$hardware/v2/rtl/neural_processor.v:332$3715_Y + 3: $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$logic_and$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:272$3780_Y + 4: $flatten\u_dataflow_core.$logic_and$hardware/v2/nms/rtl/nms_dataflow_core_sdram.v:284$7315_Y + + Output signals: + 0: $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$eq$hardware/v2/rtl/neural_processor.v:223$3687_Y + 1: $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$eq$hardware/v2/rtl/neural_processor.v:300$3709_Y + 2: $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procmux$7539_CMP + 3: $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procmux$7542_CMP + 4: \u_dataflow_core.GEN_SLOT[2].u_mm.operand_ready + + State encoding: + 0: 7'------1 + 1: 7'-----1- + 2: 7'----1-- + 3: 7'---1--- + 4: 7'--1---- + 5: 7'-1----- + 6: 7'1------ + + Transition Table (state_in, ctrl_in, state_out, ctrl_out): + 0: 0 5'0---0 -> 0 5'00010 + 1: 0 5'----1 -> 0 5'00010 + 2: 0 5'1---0 -> 4 5'00010 + 3: 1 5'----1 -> 0 5'00100 + 4: 1 5'-0--0 -> 1 5'00100 + 5: 1 5'-1--0 -> 5 5'00100 + 6: 2 5'----1 -> 0 5'10000 + 7: 2 5'--0-0 -> 2 5'10000 + 8: 2 5'--1-0 -> 6 5'10000 + 9: 3 5'----1 -> 0 5'00000 + 10: 3 5'----0 -> 3 5'00000 + 11: 4 5'----1 -> 0 5'00001 + 12: 4 5'----0 -> 2 5'00001 + 13: 5 5'----- -> 0 5'00000 + 14: 6 5'----1 -> 0 5'01000 + 15: 6 5'---10 -> 1 5'01000 + 16: 6 5'---00 -> 6 5'01000 + +------------------------------------- + +FSM `$fsm$\u_dataflow_core.GEN_SLOT[3].u_mm.state$21109' from module `fpga_neural_v2_top': +------------------------------------- + + Information on FSM $fsm$\u_dataflow_core.GEN_SLOT[3].u_mm.state$21109 (\u_dataflow_core.GEN_SLOT[3].u_mm.state): + + Number of input signals: 6 + Number of output signals: 5 + Number of state bits: 5 + + Input signals: + 0: \core_rst + 1: $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$logic_and$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:191$3766_Y + 2: $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$eq$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:247$3775_Y + 3: $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$logic_and$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:272$3780_Y + 4: \u_dataflow_core.u_director.slot_job_start [3] + 5: \u_arbiter.s_ready [3] + + Output signals: + 0: $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$eq$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:192$3768_Y + 1: $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$procmux$19751_CMP + 2: $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$procmux$19759_CMP + 3: $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$procmux$19812_CMP + 4: $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$procmux$19888_CMP + + State encoding: + 0: 5'----1 + 1: 5'---1- + 2: 5'--1-- + 3: 5'-1--- + 4: 5'1---- + + Transition Table (state_in, ctrl_in, state_out, ctrl_out): + 0: 0 6'-0---0 -> 0 5'01000 + 1: 0 6'-----1 -> 0 5'01000 + 2: 0 6'-1---0 -> 3 5'01000 + 3: 1 6'1----0 -> 0 5'00100 + 4: 1 6'-----1 -> 0 5'00100 + 5: 1 6'0----0 -> 1 5'00100 + 6: 2 6'-----1 -> 0 5'00010 + 7: 2 6'--0--0 -> 2 5'00010 + 8: 2 6'--1--0 -> 4 5'00010 + 9: 3 6'-----1 -> 0 5'00001 + 10: 3 6'---110 -> 2 5'00001 + 11: 3 6'----00 -> 3 5'00001 + 12: 3 6'---010 -> 3 5'00001 + 13: 4 6'-----1 -> 0 5'10000 + 14: 4 6'-----0 -> 1 5'10000 + +------------------------------------- + +FSM `$fsm$\u_dataflow_core.u_act_fill.u_pf.state$21116' from module `fpga_neural_v2_top': +------------------------------------- + + Information on FSM $fsm$\u_dataflow_core.u_act_fill.u_pf.state$21116 (\u_dataflow_core.u_act_fill.u_pf.state): + + Number of input signals: 4 + Number of output signals: 3 + Number of state bits: 3 + + Input signals: + 0: \core_rst + 1: \u_dataflow_core.u_act_fill.pf_start + 2: $flatten\u_dataflow_core.\u_act_fill.\u_pf.$eq$hardware/v2/rtl/prefetch_engine.v:116$6857_Y + 3: \u_arbiter.s_ready [4] + + Output signals: + 0: $flatten\u_dataflow_core.\u_act_fill.\u_pf.$procmux$10377_CMP + 1: $flatten\u_dataflow_core.\u_act_fill.\u_pf.$procmux$10371_CMP + 2: $flatten\u_dataflow_core.\u_act_fill.\u_pf.$procmux$10331_CMP + + State encoding: + 0: 3'--1 + 1: 3'-1- + 2: 3'1-- + + Transition Table (state_in, ctrl_in, state_out, ctrl_out): + 0: 0 4'--00 -> 0 3'010 + 1: 0 4'---1 -> 0 3'010 + 2: 0 4'--10 -> 1 3'010 + 3: 1 4'---1 -> 0 3'100 + 4: 1 4'10-0 -> 1 3'100 + 5: 1 4'0--0 -> 1 3'100 + 6: 1 4'11-0 -> 2 3'100 + 7: 2 4'---- -> 0 3'001 + +------------------------------------- + +19.13.8. Executing FSM_MAP pass (mapping FSMs to basic logic). +Mapping FSM `$fsm$\u_dataflow_core.GEN_SLOT[3].u_np.np_state$21121' from module `\fpga_neural_v2_top'. +Mapping FSM `$fsm$\u_spi_bridge.state$21130' from module `\fpga_neural_v2_top'. +Mapping FSM `$fsm$\u_sdram_backend.state$21144' from module `\fpga_neural_v2_top'. +Mapping FSM `$fsm$\u_dataflow_core.GEN_SLOT[0].u_mm.state$21041' from module `\fpga_neural_v2_top'. +Mapping FSM `$fsm$\u_dataflow_core.u_director.dir_state$21048' from module `\fpga_neural_v2_top'. +Mapping FSM `$fsm$\u_dataflow_core.GEN_SLOT[0].u_np.np_state$21054' from module `\fpga_neural_v2_top'. +Mapping FSM `$fsm$\u_dataflow_core.GEN_SLOT[1].u_mm.state$21063' from module `\fpga_neural_v2_top'. +Mapping FSM `$fsm$\u_sdram_backend.u_sdram_ctrl.state$21070' from module `\fpga_neural_v2_top'. +Mapping FSM `$fsm$\u_dataflow_core.GEN_SLOT[1].u_np.np_state$21084' from module `\fpga_neural_v2_top'. +Mapping FSM `$fsm$\u_dataflow_core.GEN_SLOT[2].u_mm.state$21093' from module `\fpga_neural_v2_top'. +Mapping FSM `$fsm$\u_dataflow_core.GEN_SLOT[2].u_np.np_state$21100' from module `\fpga_neural_v2_top'. +Mapping FSM `$fsm$\u_dataflow_core.GEN_SLOT[3].u_mm.state$21109' from module `\fpga_neural_v2_top'. +Mapping FSM `$fsm$\u_dataflow_core.u_act_fill.u_pf.state$21116' from module `\fpga_neural_v2_top'. + +19.14. Executing OPT pass (performing simple optimizations). + +19.14.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module fpga_neural_v2_top. + + +19.14.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\fpga_neural_v2_top'. +Computing hashes of 5098 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. +Computing hashes of 4976 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. + +Removed a total of 122 cells. + +19.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \fpga_neural_v2_top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +19.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \fpga_neural_v2_top. +Performed a total of 0 changes. + +19.14.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\fpga_neural_v2_top'. +Computing hashes of 4976 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. +Removed a total of 0 cells. + +19.14.6. Executing OPT_DFF pass (perform DFF optimizations). +Adding SRST signal on $flatten\u_spi_bridge.$procdff$20573 ($dff) from module fpga_neural_v2_top (D = { \u_spi_bridge.cs_n_sync [1:0] \spi_cs_n }, Q = \u_spi_bridge.cs_n_sync, rval = 3'111). +Adding SRST signal on $flatten\u_spi_bridge.$procdff$20572 ($dff) from module fpga_neural_v2_top (D = { \u_spi_bridge.mosi_sync [1:0] \spi_mosi }, Q = \u_spi_bridge.mosi_sync, rval = 3'000). +Adding SRST signal on $flatten\u_spi_bridge.$procdff$20571 ($dff) from module fpga_neural_v2_top (D = { \u_spi_bridge.sclk_sync [1:0] \spi_sclk }, Q = \u_spi_bridge.sclk_sync, rval = 3'000). +Adding SRST signal on $flatten\u_spi_bridge.$procdff$20570 ($dff) from module fpga_neural_v2_top (D = \u_spi_bridge.cs_n_sync [2], Q = \u_spi_bridge.cs_n_prev, rval = 1'1). +Adding SRST signal on $flatten\u_spi_bridge.$procdff$20569 ($dff) from module fpga_neural_v2_top (D = \u_spi_bridge.sclk_sync [2], Q = \u_spi_bridge.sclk_prev, rval = 1'0). +Adding SRST signal on $flatten\u_spi_bridge.$procdff$20568 ($dff) from module fpga_neural_v2_top (D = $flatten\u_spi_bridge.$procmux$18893_Y, Q = \u_spi_bridge.miso_shift_bit, rval = 1'0). +Adding EN signal on $auto$ff.cc:337:slice$22645 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_spi_bridge.$shiftx$hardware/v2/rtl/spi_host_bridge.v:211$7337_Y, Q = \u_spi_bridge.miso_shift_bit). +Adding SRST signal on $flatten\u_spi_bridge.$procdff$20567 ($dff) from module fpga_neural_v2_top (D = $flatten\u_spi_bridge.$procmux$18873_Y, Q = \u_spi_bridge.rx_valid, rval = 1'0). +Adding SRST signal on $flatten\u_spi_bridge.$procdff$20566 ($dff) from module fpga_neural_v2_top (D = $flatten\u_spi_bridge.$procmux$18907_Y, Q = \u_spi_bridge.rx_byte, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:337:slice$22662 ($sdff) from module fpga_neural_v2_top (D = { \u_spi_bridge.rx_shift [6:0] \u_spi_bridge.mosi_sync [2] }, Q = \u_spi_bridge.rx_byte). +Adding SRST signal on $flatten\u_spi_bridge.$procdff$20565 ($dff) from module fpga_neural_v2_top (D = $flatten\u_spi_bridge.$procmux$18918_Y, Q = \u_spi_bridge.rx_shift, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:337:slice$22670 ($sdff) from module fpga_neural_v2_top (D = { \u_spi_bridge.rx_shift [6:0] \u_spi_bridge.mosi_sync [2] }, Q = \u_spi_bridge.rx_shift). +Adding SRST signal on $flatten\u_spi_bridge.$procdff$20564 ($dff) from module fpga_neural_v2_top (D = $flatten\u_spi_bridge.$procmux$18929_Y, Q = \u_spi_bridge.bit_count, rval = 3'000). +Adding EN signal on $auto$ff.cc:337:slice$22678 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_spi_bridge.$procmux$18925_Y, Q = \u_spi_bridge.bit_count). +Adding SRST signal on $flatten\u_spi_bridge.$procdff$20563 ($dff) from module fpga_neural_v2_top (D = $flatten\u_spi_bridge.$procmux$18466_Y, Q = \u_spi_bridge.last_job_accepted_r, rval = 1'0). +Adding EN signal on $auto$ff.cc:337:slice$22688 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_spi_bridge.$procmux$18466_Y, Q = \u_spi_bridge.last_job_accepted_r). +Adding SRST signal on $flatten\u_spi_bridge.$procdff$20562 ($dff) from module fpga_neural_v2_top (D = $flatten\u_spi_bridge.$procmux$18479_Y, Q = \u_spi_bridge.mem_busy_r, rval = 1'0). +Adding EN signal on $auto$ff.cc:337:slice$22700 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_spi_bridge.$procmux$18479_Y, Q = \u_spi_bridge.mem_busy_r). +Adding SRST signal on $flatten\u_spi_bridge.$procdff$20561 ($dff) from module fpga_neural_v2_top (D = $flatten\u_spi_bridge.$eq$hardware/v2/rtl/spi_host_bridge.v:376$7362_Y, Q = \u_spi_bridge.job_busy_r, rval = 1'0). +Adding SRST signal on $flatten\u_spi_bridge.$procdff$20560 ($dff) from module fpga_neural_v2_top (D = { $flatten\u_spi_bridge.$procmux$18535_Y $flatten\u_spi_bridge.$procmux$18243_Y }, Q = \u_spi_bridge.cur_word, rval = 16'0000000000000000). +Adding SRST signal on $flatten\u_spi_bridge.$procdff$20559 ($dff) from module fpga_neural_v2_top (D = $flatten\u_spi_bridge.$procmux$18517_Y, Q = \u_spi_bridge.word_cnt, rval = 16'0000000000000000). +Adding SRST signal on $flatten\u_spi_bridge.$procdff$20558 ($dff) from module fpga_neural_v2_top (D = { $flatten\u_spi_bridge.$procmux$18493_Y $flatten\u_spi_bridge.$procmux$18225_Y }, Q = \u_spi_bridge.len_words, rval = 16'0000000000000000). +Adding EN signal on $auto$ff.cc:337:slice$22707 ($sdff) from module fpga_neural_v2_top (D = \u_spi_bridge.rx_byte, Q = \u_spi_bridge.len_words [7:0]). +Adding EN signal on $auto$ff.cc:337:slice$22707 ($sdff) from module fpga_neural_v2_top (D = \u_spi_bridge.rx_byte, Q = \u_spi_bridge.len_words [15:8]). +Adding SRST signal on $flatten\u_spi_bridge.$procdff$20557 ($dff) from module fpga_neural_v2_top (D = $flatten\u_spi_bridge.$procmux$18575_Y, Q = \u_spi_bridge.byte_idx, rval = 4'0000). +Adding SRST signal on $flatten\u_spi_bridge.$procdff$20556 ($dff) from module fpga_neural_v2_top (D = $flatten\u_spi_bridge.$procmux$18589_Y, Q = \u_spi_bridge.opcode, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:337:slice$22721 ($sdff) from module fpga_neural_v2_top (D = \u_spi_bridge.rx_byte, Q = \u_spi_bridge.opcode). +Adding SRST signal on $flatten\u_spi_bridge.$procdff$20555 ($dff) from module fpga_neural_v2_top (D = $flatten\u_spi_bridge.$procmux$18438_Y, Q = \u_spi_bridge.soft_rst_pulse, rval = 1'0). +Adding SRST signal on $flatten\u_spi_bridge.$procdff$20553 ($dff) from module fpga_neural_v2_top (D = $flatten\u_spi_bridge.$procmux$18646_Y, Q = \u_spi_bridge.mem_ub_n, rval = 1'0). +Adding EN signal on $auto$ff.cc:337:slice$22730 ($sdff) from module fpga_neural_v2_top (D = 1'0, Q = \u_spi_bridge.mem_ub_n). +Adding SRST signal on $flatten\u_spi_bridge.$procdff$20552 ($dff) from module fpga_neural_v2_top (D = $flatten\u_spi_bridge.$procmux$18655_Y, Q = \u_spi_bridge.mem_lb_n, rval = 1'0). +Adding EN signal on $auto$ff.cc:337:slice$22736 ($sdff) from module fpga_neural_v2_top (D = 1'0, Q = \u_spi_bridge.mem_lb_n). +Adding SRST signal on $flatten\u_spi_bridge.$procdff$20551 ($dff) from module fpga_neural_v2_top (D = $flatten\u_spi_bridge.$procmux$18664_Y, Q = \u_spi_bridge.mem_wdata, rval = 16'0000000000000000). +Adding EN signal on $auto$ff.cc:337:slice$22742 ($sdff) from module fpga_neural_v2_top (D = \u_spi_bridge.cur_word, Q = \u_spi_bridge.mem_wdata). +Adding SRST signal on $flatten\u_spi_bridge.$procdff$20550 ($dff) from module fpga_neural_v2_top (D = { $flatten\u_spi_bridge.$procmux$18186_Y $flatten\u_spi_bridge.$procmux$18211_Y $flatten\u_spi_bridge.$procmux$18267_Y }, Q = \u_spi_bridge.mem_addr, rval = 23'00000000000000000000000). +Adding SRST signal on $flatten\u_spi_bridge.$procdff$20549 ($dff) from module fpga_neural_v2_top (D = $flatten\u_spi_bridge.$procmux$18686_Y, Q = \u_spi_bridge.mem_wr, rval = 1'0). +Adding EN signal on $auto$ff.cc:337:slice$22745 ($sdff) from module fpga_neural_v2_top (D = 1'1, Q = \u_spi_bridge.mem_wr). +Adding SRST signal on $flatten\u_spi_bridge.$procdff$20548 ($dff) from module fpga_neural_v2_top (D = $flatten\u_spi_bridge.$procmux$18449_Y, Q = \u_spi_bridge.mem_req, rval = 1'0). +Adding SRST signal on $flatten\u_spi_bridge.$procdff$20547 ($dff) from module fpga_neural_v2_top (D = { $flatten\u_spi_bridge.$procmux$18299_Y $flatten\u_spi_bridge.$procmux$18680_Y $flatten\u_spi_bridge.$procmux$18282_Y }, Q = \u_spi_bridge.reg_result_addr, rval = 23'00000000000000000000000). +Adding EN signal on $auto$ff.cc:337:slice$22752 ($sdff) from module fpga_neural_v2_top (D = \u_spi_bridge.rx_byte, Q = \u_spi_bridge.reg_result_addr [15:8]). +Adding EN signal on $auto$ff.cc:337:slice$22752 ($sdff) from module fpga_neural_v2_top (D = \u_spi_bridge.rx_byte [6:0], Q = \u_spi_bridge.reg_result_addr [22:16]). +Adding EN signal on $auto$ff.cc:337:slice$22752 ($sdff) from module fpga_neural_v2_top (D = \u_spi_bridge.rx_byte, Q = \u_spi_bridge.reg_result_addr [7:0]). +Adding SRST signal on $flatten\u_spi_bridge.$procdff$20546 ($dff) from module fpga_neural_v2_top (D = { $flatten\u_spi_bridge.$procmux$18708_Y $flatten\u_spi_bridge.$procmux$18317_Y }, Q = \u_spi_bridge.reg_n_tiles, rval = 16'0000000000000000). +Adding EN signal on $auto$ff.cc:337:slice$22768 ($sdff) from module fpga_neural_v2_top (D = \u_spi_bridge.rx_byte, Q = \u_spi_bridge.reg_n_tiles [15:8]). +Adding EN signal on $auto$ff.cc:337:slice$22768 ($sdff) from module fpga_neural_v2_top (D = \u_spi_bridge.rx_byte, Q = \u_spi_bridge.reg_n_tiles [7:0]). +Adding SRST signal on $flatten\u_spi_bridge.$procdff$20545 ($dff) from module fpga_neural_v2_top (D = { $flatten\u_spi_bridge.$procmux$18359_Y $flatten\u_spi_bridge.$procmux$18729_Y $flatten\u_spi_bridge.$procmux$18337_Y }, Q = \u_spi_bridge.reg_w_base, rval = 23'00000000000000000000000). +Adding EN signal on $auto$ff.cc:337:slice$22779 ($sdff) from module fpga_neural_v2_top (D = \u_spi_bridge.rx_byte, Q = \u_spi_bridge.reg_w_base [15:8]). +Adding EN signal on $auto$ff.cc:337:slice$22779 ($sdff) from module fpga_neural_v2_top (D = \u_spi_bridge.rx_byte [6:0], Q = \u_spi_bridge.reg_w_base [22:16]). +Adding EN signal on $auto$ff.cc:337:slice$22779 ($sdff) from module fpga_neural_v2_top (D = \u_spi_bridge.rx_byte, Q = \u_spi_bridge.reg_w_base [7:0]). +Adding SRST signal on $flatten\u_spi_bridge.$procdff$20544 ($dff) from module fpga_neural_v2_top (D = { $flatten\u_spi_bridge.$procmux$18407_Y $flatten\u_spi_bridge.$procmux$18753_Y $flatten\u_spi_bridge.$procmux$18382_Y }, Q = \u_spi_bridge.reg_x_base, rval = 23'00000000000000000000000). +Adding EN signal on $auto$ff.cc:337:slice$22795 ($sdff) from module fpga_neural_v2_top (D = \u_spi_bridge.rx_byte, Q = \u_spi_bridge.reg_x_base [15:8]). +Adding EN signal on $auto$ff.cc:337:slice$22795 ($sdff) from module fpga_neural_v2_top (D = \u_spi_bridge.rx_byte [6:0], Q = \u_spi_bridge.reg_x_base [22:16]). +Adding EN signal on $auto$ff.cc:337:slice$22795 ($sdff) from module fpga_neural_v2_top (D = \u_spi_bridge.rx_byte, Q = \u_spi_bridge.reg_x_base [7:0]). +Adding SRST signal on $flatten\u_spi_bridge.$procdff$20543 ($dff) from module fpga_neural_v2_top (D = { $flatten\u_spi_bridge.$procmux$18780_Y $flatten\u_spi_bridge.$procmux$18433_Y }, Q = \u_spi_bridge.reg_producer_ids, rval = 16'0000000000000000). +Adding EN signal on $auto$ff.cc:337:slice$22811 ($sdff) from module fpga_neural_v2_top (D = \u_spi_bridge.rx_byte, Q = \u_spi_bridge.reg_producer_ids [7:0]). +Adding EN signal on $auto$ff.cc:337:slice$22811 ($sdff) from module fpga_neural_v2_top (D = \u_spi_bridge.rx_byte, Q = \u_spi_bridge.reg_producer_ids [15:8]). +Adding SRST signal on $flatten\u_spi_bridge.$procdff$20542 ($dff) from module fpga_neural_v2_top (D = $flatten\u_spi_bridge.$procmux$18811_Y, Q = \u_spi_bridge.reg_required, rval = 3'000). +Adding EN signal on $auto$ff.cc:337:slice$22822 ($sdff) from module fpga_neural_v2_top (D = \u_spi_bridge.rx_byte [2:0], Q = \u_spi_bridge.reg_required). +Adding SRST signal on $flatten\u_spi_bridge.$procdff$20541 ($dff) from module fpga_neural_v2_top (D = $flatten\u_spi_bridge.$procmux$18840_Y, Q = \u_spi_bridge.reg_node_id, rval = 4'0000). +Adding EN signal on $auto$ff.cc:337:slice$22828 ($sdff) from module fpga_neural_v2_top (D = \u_spi_bridge.rx_byte [3:0], Q = \u_spi_bridge.reg_node_id). +Adding SRST signal on $flatten\u_spi_bridge.$procdff$20540 ($dff) from module fpga_neural_v2_top (D = $flatten\u_spi_bridge.$procmux$18855_Y, Q = \u_spi_bridge.reg_valid, rval = 1'0). +Adding EN signal on $auto$ff.cc:337:slice$22834 ($sdff) from module fpga_neural_v2_top (D = 1'1, Q = \u_spi_bridge.reg_valid). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procdff$20042 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[3].u_np.valid_tree [1], Q = \u_dataflow_core.GEN_SLOT[3].u_np.valid_tree [2], rval = 1'0). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procdff$20043 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[3].u_np.last_tree [1], Q = \u_dataflow_core.GEN_SLOT[3].u_np.last_tree [2], rval = 1'0). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procdff$20046 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[3].u_np.valid_tree [0], Q = \u_dataflow_core.GEN_SLOT[3].u_np.valid_tree [1], rval = 1'0). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procdff$20047 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[3].u_np.last_tree [0], Q = \u_dataflow_core.GEN_SLOT[3].u_np.last_tree [1], rval = 1'0). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procdff$20052 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[3].u_np.valid1, Q = \u_dataflow_core.GEN_SLOT[3].u_np.valid_tree [0], rval = 1'0). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procdff$20053 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[3].u_np.last1, Q = \u_dataflow_core.GEN_SLOT[3].u_np.last_tree [0], rval = 1'0). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procdff$20054 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procmux$7580_Y, Q = \u_dataflow_core.GEN_SLOT[3].u_np.result_valid, rval = 1'0). +Adding EN signal on $auto$ff.cc:337:slice$22850 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procmux$7580_Y, Q = \u_dataflow_core.GEN_SLOT[3].u_np.result_valid). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procdff$20055 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procmux$7570_Y, Q = \u_dataflow_core.GEN_SLOT[3].u_np.result_data, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:337:slice$22860 ($sdff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[3].u_np.y7, Q = \u_dataflow_core.GEN_SLOT[3].u_np.result_data). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procdff$20059 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procmux$7525_Y, Q = \u_dataflow_core.GEN_SLOT[3].u_np.bias_reg, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:337:slice$22864 ($sdff) from module fpga_neural_v2_top (D = 8'00000000, Q = \u_dataflow_core.GEN_SLOT[3].u_np.bias_reg). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procdff$20060 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procmux$7511_Y, Q = \u_dataflow_core.GEN_SLOT[3].u_np.activation_reg, rval = 2'01). +Adding EN signal on $auto$ff.cc:337:slice$22868 ($sdff) from module fpga_neural_v2_top (D = 2'01, Q = \u_dataflow_core.GEN_SLOT[3].u_np.activation_reg). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procdff$20062 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[3].u_np.last6, Q = \u_dataflow_core.GEN_SLOT[3].u_np.valid7, rval = 1'0). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procdff$20063 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procmux$7592_Y, Q = \u_dataflow_core.GEN_SLOT[3].u_np.y7). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procdff$20064 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[3].u_np.valid5, Q = \u_dataflow_core.GEN_SLOT[3].u_np.valid6, rval = 1'0). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procdff$20065 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[3].u_np.last5, Q = \u_dataflow_core.GEN_SLOT[3].u_np.last6, rval = 1'0). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procdff$20066 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$add$hardware/v2/rtl/neural_processor.v:252$3690_Y, Q = \u_dataflow_core.GEN_SLOT[3].u_np.final_acc_reg). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procdff$20067 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procmux$7612_Y, Q = \u_dataflow_core.GEN_SLOT[3].u_np.acc_reg, rval = 0). +Adding EN signal on $auto$ff.cc:337:slice$22877 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$add$hardware/v2/rtl/neural_processor.v:226$3688_Y, Q = \u_dataflow_core.GEN_SLOT[3].u_np.acc_reg). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procdff$20068 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[3].u_np.valid_tree [2], Q = \u_dataflow_core.GEN_SLOT[3].u_np.valid5, rval = 1'0). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procdff$20069 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[3].u_np.last_tree [2], Q = \u_dataflow_core.GEN_SLOT[3].u_np.last5, rval = 1'0). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procdff$20071 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[3].u_np.valid0, Q = \u_dataflow_core.GEN_SLOT[3].u_np.valid1, rval = 1'0). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procdff$20072 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[3].u_np.last0, Q = \u_dataflow_core.GEN_SLOT[3].u_np.last1, rval = 1'0). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procdff$20073 ($dff) from module fpga_neural_v2_top (D = { \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[0] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[0] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[0] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[0] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[0] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[0] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[0] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[0] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[0] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[0] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[0] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[0] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[0] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[0] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[0] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[0] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[0] }, Q = \u_dataflow_core.GEN_SLOT[3].u_np.prod1[0]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procdff$20074 ($dff) from module fpga_neural_v2_top (D = { \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[1] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[1] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[1] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[1] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[1] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[1] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[1] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[1] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[1] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[1] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[1] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[1] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[1] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[1] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[1] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[1] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[1] }, Q = \u_dataflow_core.GEN_SLOT[3].u_np.prod1[1]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procdff$20075 ($dff) from module fpga_neural_v2_top (D = { \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[2] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[2] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[2] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[2] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[2] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[2] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[2] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[2] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[2] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[2] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[2] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[2] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[2] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[2] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[2] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[2] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[2] }, Q = \u_dataflow_core.GEN_SLOT[3].u_np.prod1[2]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procdff$20076 ($dff) from module fpga_neural_v2_top (D = { \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[3] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[3] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[3] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[3] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[3] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[3] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[3] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[3] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[3] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[3] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[3] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[3] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[3] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[3] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[3] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[3] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[3] }, Q = \u_dataflow_core.GEN_SLOT[3].u_np.prod1[3]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procdff$20077 ($dff) from module fpga_neural_v2_top (D = { \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[4] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[4] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[4] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[4] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[4] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[4] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[4] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[4] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[4] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[4] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[4] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[4] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[4] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[4] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[4] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[4] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[4] }, Q = \u_dataflow_core.GEN_SLOT[3].u_np.prod1[4]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procdff$20078 ($dff) from module fpga_neural_v2_top (D = { \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[5] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[5] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[5] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[5] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[5] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[5] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[5] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[5] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[5] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[5] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[5] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[5] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[5] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[5] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[5] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[5] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[5] }, Q = \u_dataflow_core.GEN_SLOT[3].u_np.prod1[5]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procdff$20079 ($dff) from module fpga_neural_v2_top (D = { \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[6] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[6] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[6] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[6] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[6] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[6] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[6] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[6] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[6] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[6] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[6] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[6] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[6] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[6] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[6] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[6] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[6] }, Q = \u_dataflow_core.GEN_SLOT[3].u_np.prod1[6]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procdff$20080 ($dff) from module fpga_neural_v2_top (D = { \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[7] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[7] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[7] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[7] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[7] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[7] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[7] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[7] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[7] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[7] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[7] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[7] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[7] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[7] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[7] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[7] [15] \u_dataflow_core.GEN_SLOT[3].u_np.product_comb[7] }, Q = \u_dataflow_core.GEN_SLOT[3].u_np.prod1[7]). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procdff$20081 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$logic_and$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:191$3766_Y, Q = \u_dataflow_core.GEN_SLOT[3].u_np.valid0, rval = 1'0). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procdff$20082 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[3].u_mm.buf_last, Q = \u_dataflow_core.GEN_SLOT[3].u_np.last0, rval = 1'0). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procdff$20084 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[3].u_mm.buf_input [7:0], Q = \u_dataflow_core.GEN_SLOT[3].u_np.x0[0]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procdff$20085 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[3].u_mm.buf_input [15:8], Q = \u_dataflow_core.GEN_SLOT[3].u_np.x0[1]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procdff$20086 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[3].u_mm.buf_input [23:16], Q = \u_dataflow_core.GEN_SLOT[3].u_np.x0[2]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procdff$20087 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[3].u_mm.buf_input [31:24], Q = \u_dataflow_core.GEN_SLOT[3].u_np.x0[3]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procdff$20088 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[3].u_mm.buf_input [39:32], Q = \u_dataflow_core.GEN_SLOT[3].u_np.x0[4]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procdff$20089 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[3].u_mm.buf_input [47:40], Q = \u_dataflow_core.GEN_SLOT[3].u_np.x0[5]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procdff$20090 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[3].u_mm.buf_input [55:48], Q = \u_dataflow_core.GEN_SLOT[3].u_np.x0[6]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procdff$20091 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[3].u_mm.buf_input [63:56], Q = \u_dataflow_core.GEN_SLOT[3].u_np.x0[7]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procdff$20092 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[3].u_mm.buf_weight [7:0], Q = \u_dataflow_core.GEN_SLOT[3].u_np.w0[0]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procdff$20093 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[3].u_mm.buf_weight [15:8], Q = \u_dataflow_core.GEN_SLOT[3].u_np.w0[1]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procdff$20094 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[3].u_mm.buf_weight [23:16], Q = \u_dataflow_core.GEN_SLOT[3].u_np.w0[2]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procdff$20095 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[3].u_mm.buf_weight [31:24], Q = \u_dataflow_core.GEN_SLOT[3].u_np.w0[3]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procdff$20096 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[3].u_mm.buf_weight [39:32], Q = \u_dataflow_core.GEN_SLOT[3].u_np.w0[4]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procdff$20097 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[3].u_mm.buf_weight [47:40], Q = \u_dataflow_core.GEN_SLOT[3].u_np.w0[5]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procdff$20098 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[3].u_mm.buf_weight [55:48], Q = \u_dataflow_core.GEN_SLOT[3].u_np.w0[6]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procdff$20099 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[3].u_mm.buf_weight [63:56], Q = \u_dataflow_core.GEN_SLOT[3].u_np.w0[7]). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$procdff$20738 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$procmux$19750_Y, Q = \u_dataflow_core.GEN_SLOT[3].u_mm.result_ready, rval = 1'0). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$procdff$20742 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$procmux$19756_Y, Q = \u_dataflow_core.GEN_SLOT[3].u_mm.job_done, rval = 1'0). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$procdff$20743 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[3].u_mm.rd_ptr [3:0], Q = \u_dataflow_core.GEN_SLOT[3].u_mm.act_rd_addr). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$procdff$20744 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[3].u_mm.rd_ptr [3:0], Q = \u_dataflow_core.GEN_SLOT[3].u_mm.wgt_rd_addr). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$procdff$20745 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$procmux$19988_Y, Q = \u_dataflow_core.GEN_SLOT[3].u_mm.job_active_reg, rval = 1'0). +Adding EN signal on $auto$ff.cc:337:slice$22995 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$procmux$19988_Y, Q = \u_dataflow_core.GEN_SLOT[3].u_mm.job_active_reg). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$procdff$20746 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.u_director.slot_x_base [91:69], Q = \u_dataflow_core.GEN_SLOT[3].u_mm.x_base_reg). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$procdff$20747 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.u_director.slot_w_base [91:69], Q = \u_dataflow_core.GEN_SLOT[3].u_mm.w_base_reg). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$procdff$20748 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.u_director.slot_result_addr [91:69], Q = \u_dataflow_core.GEN_SLOT[3].u_mm.result_addr_reg). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$procdff$20749 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.u_director.slot_n_tiles [63:48], Q = \u_dataflow_core.GEN_SLOT[3].u_mm.n_tiles_reg). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$procdff$20750 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$procmux$19923_Y, Q = \u_dataflow_core.GEN_SLOT[3].u_mm.tile_idx, rval = 5'00000). +Adding EN signal on $auto$ff.cc:337:slice$23027 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$procmux$19923_Y, Q = \u_dataflow_core.GEN_SLOT[3].u_mm.tile_idx). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$procdff$20751 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$procmux$19906_Y, Q = \u_dataflow_core.GEN_SLOT[3].u_mm.rd_ptr, rval = 5'00000). +Adding EN signal on $auto$ff.cc:337:slice$23039 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$procmux$19906_Y, Q = \u_dataflow_core.GEN_SLOT[3].u_mm.rd_ptr). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$procdff$20752 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$procmux$19893_Y, Q = \u_dataflow_core.GEN_SLOT[3].u_mm.wr_mem_req, rval = 1'0). +Adding EN signal on $auto$ff.cc:337:slice$23049 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$procmux$19893_Y, Q = \u_dataflow_core.GEN_SLOT[3].u_mm.wr_mem_req). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$procdff$20753 ($dff) from module fpga_neural_v2_top (D = { 1'0 \u_dataflow_core.GEN_SLOT[3].u_mm.result_addr_reg [22:1] }, Q = \u_dataflow_core.GEN_SLOT[3].u_mm.wr_mem_addr). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$procdff$20754 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$ternary$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:273$3781_Y, Q = \u_dataflow_core.GEN_SLOT[3].u_mm.wr_mem_wdata). +Adding SRST signal on $auto$ff.cc:337:slice$23058 ($dffe) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[3].u_np.result_data, Q = \u_dataflow_core.GEN_SLOT[3].u_mm.wr_mem_wdata [15:8], rval = 8'00000000). +Adding SRST signal on $auto$ff.cc:337:slice$23058 ($dffe) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[3].u_np.result_data, Q = \u_dataflow_core.GEN_SLOT[3].u_mm.wr_mem_wdata [7:0], rval = 8'00000000). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$procdff$20755 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$procmux$19870_Y, Q = \u_dataflow_core.GEN_SLOT[3].u_mm.wr_mem_lb_n, rval = 1'1). +Adding EN signal on $auto$ff.cc:337:slice$23065 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$ternary$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:274$3782_Y, Q = \u_dataflow_core.GEN_SLOT[3].u_mm.wr_mem_lb_n). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$procdff$20756 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$procmux$19860_Y, Q = \u_dataflow_core.GEN_SLOT[3].u_mm.wr_mem_ub_n, rval = 1'1). +Adding EN signal on $auto$ff.cc:337:slice$23069 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$ternary$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:275$3783_Y, Q = \u_dataflow_core.GEN_SLOT[3].u_mm.wr_mem_ub_n). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$procdff$20757 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$procmux$19847_Y, Q = \u_dataflow_core.GEN_SLOT[3].u_mm.rd_pending, rval = 1'0). +Adding EN signal on $auto$ff.cc:337:slice$23073 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$procmux$19847_Y, Q = \u_dataflow_core.GEN_SLOT[3].u_mm.rd_pending). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$procdff$20759 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$eq$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:263$3778_Y, Q = \u_dataflow_core.GEN_SLOT[3].u_mm.rd_pending_last). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$procdff$20760 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$procmux$19808_Y, Q = \u_dataflow_core.GEN_SLOT[3].u_mm.buf_valid, rval = 1'0). +Adding EN signal on $auto$ff.cc:337:slice$23086 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$procmux$19808_Y, Q = \u_dataflow_core.GEN_SLOT[3].u_mm.buf_valid). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$procdff$20761 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[3].u_mm.act_rd_data, Q = \u_dataflow_core.GEN_SLOT[3].u_mm.buf_input). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$procdff$20762 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[3].u_mm.wgt_rd_data, Q = \u_dataflow_core.GEN_SLOT[3].u_mm.buf_weight). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$procdff$20763 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[3].u_mm.rd_pending_last, Q = \u_dataflow_core.GEN_SLOT[3].u_mm.buf_last). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$procdff$20245 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$procmux$10567_Y, Q = \u_dataflow_core.GEN_SLOT[3].u_mm.u_wpf.req_outstanding, rval = 1'0). +Adding EN signal on $auto$ff.cc:337:slice$23111 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$procmux$10567_Y, Q = \u_dataflow_core.GEN_SLOT[3].u_mm.u_wpf.req_outstanding). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$procdff$20244 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$procmux$10579_Y, Q = \u_dataflow_core.GEN_SLOT[3].u_mm.u_wpf.fetch_word, rval = 1'0). +Adding EN signal on $auto$ff.cc:337:slice$23119 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$procmux$10577_Y, Q = \u_dataflow_core.GEN_SLOT[3].u_mm.u_wpf.fetch_word). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$procdff$20243 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$procmux$10591_Y, Q = \u_dataflow_core.GEN_SLOT[3].u_mm.u_wpf.fetch_tile, rval = 5'00000). +Adding EN signal on $auto$ff.cc:337:slice$23125 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:134$6818_Y, Q = \u_dataflow_core.GEN_SLOT[3].u_mm.u_wpf.fetch_tile). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$procdff$20242 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$procmux$10603_Y, Q = \u_dataflow_core.GEN_SLOT[3].u_mm.u_wpf.ready_count, rval = 5'00000). +Adding EN signal on $auto$ff.cc:337:slice$23135 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:133$6817_Y, Q = \u_dataflow_core.GEN_SLOT[3].u_mm.u_wpf.ready_count). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$procdff$20241 ($dff) from module fpga_neural_v2_top (D = \u_arbiter_wide.s_rdata [255:192], Q = \u_dataflow_core.GEN_SLOT[3].u_mm.u_wpf.wgt_fill_data). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$procdff$20240 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[3].u_mm.u_wpf.fetch_tile [3:0], Q = \u_dataflow_core.GEN_SLOT[3].u_mm.u_wpf.wgt_fill_addr). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$procdff$20239 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$procmux$10527_Y, Q = \u_dataflow_core.GEN_SLOT[3].u_mm.u_wpf.wgt_fill_we, rval = 1'0). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$procdff$20238 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$procmux$10643_Y, Q = \u_dataflow_core.GEN_SLOT[3].u_mm.u_wpf.mem_addr). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$procdff$20237 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$procmux$10545_Y, Q = \u_dataflow_core.GEN_SLOT[3].u_mm.u_wpf.mem_req, rval = 1'0). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procdff$20042 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[2].u_np.valid_tree [1], Q = \u_dataflow_core.GEN_SLOT[2].u_np.valid_tree [2], rval = 1'0). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procdff$20043 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[2].u_np.last_tree [1], Q = \u_dataflow_core.GEN_SLOT[2].u_np.last_tree [2], rval = 1'0). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procdff$20046 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[2].u_np.valid_tree [0], Q = \u_dataflow_core.GEN_SLOT[2].u_np.valid_tree [1], rval = 1'0). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procdff$20047 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[2].u_np.last_tree [0], Q = \u_dataflow_core.GEN_SLOT[2].u_np.last_tree [1], rval = 1'0). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procdff$20052 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[2].u_np.valid1, Q = \u_dataflow_core.GEN_SLOT[2].u_np.valid_tree [0], rval = 1'0). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procdff$20053 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[2].u_np.last1, Q = \u_dataflow_core.GEN_SLOT[2].u_np.last_tree [0], rval = 1'0). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procdff$20054 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procmux$7580_Y, Q = \u_dataflow_core.GEN_SLOT[2].u_np.result_valid, rval = 1'0). +Adding EN signal on $auto$ff.cc:337:slice$23186 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procmux$7580_Y, Q = \u_dataflow_core.GEN_SLOT[2].u_np.result_valid). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procdff$20055 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procmux$7570_Y, Q = \u_dataflow_core.GEN_SLOT[2].u_np.result_data, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:337:slice$23196 ($sdff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[2].u_np.y7, Q = \u_dataflow_core.GEN_SLOT[2].u_np.result_data). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procdff$20059 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procmux$7525_Y, Q = \u_dataflow_core.GEN_SLOT[2].u_np.bias_reg, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:337:slice$23200 ($sdff) from module fpga_neural_v2_top (D = 8'00000000, Q = \u_dataflow_core.GEN_SLOT[2].u_np.bias_reg). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procdff$20060 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procmux$7511_Y, Q = \u_dataflow_core.GEN_SLOT[2].u_np.activation_reg, rval = 2'01). +Adding EN signal on $auto$ff.cc:337:slice$23204 ($sdff) from module fpga_neural_v2_top (D = 2'01, Q = \u_dataflow_core.GEN_SLOT[2].u_np.activation_reg). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procdff$20062 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[2].u_np.last6, Q = \u_dataflow_core.GEN_SLOT[2].u_np.valid7, rval = 1'0). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procdff$20063 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procmux$7592_Y, Q = \u_dataflow_core.GEN_SLOT[2].u_np.y7). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procdff$20064 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[2].u_np.valid5, Q = \u_dataflow_core.GEN_SLOT[2].u_np.valid6, rval = 1'0). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procdff$20065 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[2].u_np.last5, Q = \u_dataflow_core.GEN_SLOT[2].u_np.last6, rval = 1'0). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procdff$20066 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$add$hardware/v2/rtl/neural_processor.v:252$3690_Y, Q = \u_dataflow_core.GEN_SLOT[2].u_np.final_acc_reg). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procdff$20067 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procmux$7612_Y, Q = \u_dataflow_core.GEN_SLOT[2].u_np.acc_reg, rval = 0). +Adding EN signal on $auto$ff.cc:337:slice$23213 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$add$hardware/v2/rtl/neural_processor.v:226$3688_Y, Q = \u_dataflow_core.GEN_SLOT[2].u_np.acc_reg). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procdff$20068 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[2].u_np.valid_tree [2], Q = \u_dataflow_core.GEN_SLOT[2].u_np.valid5, rval = 1'0). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procdff$20069 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[2].u_np.last_tree [2], Q = \u_dataflow_core.GEN_SLOT[2].u_np.last5, rval = 1'0). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procdff$20071 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[2].u_np.valid0, Q = \u_dataflow_core.GEN_SLOT[2].u_np.valid1, rval = 1'0). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procdff$20072 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[2].u_np.last0, Q = \u_dataflow_core.GEN_SLOT[2].u_np.last1, rval = 1'0). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procdff$20073 ($dff) from module fpga_neural_v2_top (D = { \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[0] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[0] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[0] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[0] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[0] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[0] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[0] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[0] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[0] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[0] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[0] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[0] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[0] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[0] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[0] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[0] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[0] }, Q = \u_dataflow_core.GEN_SLOT[2].u_np.prod1[0]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procdff$20074 ($dff) from module fpga_neural_v2_top (D = { \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[1] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[1] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[1] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[1] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[1] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[1] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[1] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[1] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[1] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[1] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[1] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[1] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[1] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[1] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[1] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[1] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[1] }, Q = \u_dataflow_core.GEN_SLOT[2].u_np.prod1[1]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procdff$20075 ($dff) from module fpga_neural_v2_top (D = { \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[2] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[2] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[2] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[2] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[2] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[2] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[2] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[2] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[2] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[2] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[2] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[2] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[2] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[2] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[2] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[2] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[2] }, Q = \u_dataflow_core.GEN_SLOT[2].u_np.prod1[2]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procdff$20076 ($dff) from module fpga_neural_v2_top (D = { \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[3] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[3] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[3] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[3] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[3] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[3] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[3] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[3] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[3] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[3] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[3] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[3] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[3] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[3] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[3] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[3] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[3] }, Q = \u_dataflow_core.GEN_SLOT[2].u_np.prod1[3]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procdff$20077 ($dff) from module fpga_neural_v2_top (D = { \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[4] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[4] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[4] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[4] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[4] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[4] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[4] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[4] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[4] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[4] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[4] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[4] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[4] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[4] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[4] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[4] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[4] }, Q = \u_dataflow_core.GEN_SLOT[2].u_np.prod1[4]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procdff$20078 ($dff) from module fpga_neural_v2_top (D = { \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[5] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[5] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[5] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[5] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[5] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[5] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[5] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[5] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[5] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[5] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[5] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[5] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[5] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[5] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[5] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[5] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[5] }, Q = \u_dataflow_core.GEN_SLOT[2].u_np.prod1[5]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procdff$20079 ($dff) from module fpga_neural_v2_top (D = { \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[6] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[6] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[6] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[6] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[6] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[6] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[6] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[6] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[6] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[6] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[6] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[6] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[6] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[6] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[6] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[6] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[6] }, Q = \u_dataflow_core.GEN_SLOT[2].u_np.prod1[6]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procdff$20080 ($dff) from module fpga_neural_v2_top (D = { \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[7] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[7] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[7] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[7] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[7] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[7] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[7] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[7] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[7] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[7] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[7] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[7] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[7] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[7] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[7] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[7] [15] \u_dataflow_core.GEN_SLOT[2].u_np.product_comb[7] }, Q = \u_dataflow_core.GEN_SLOT[2].u_np.prod1[7]). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procdff$20081 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$logic_and$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:191$3766_Y, Q = \u_dataflow_core.GEN_SLOT[2].u_np.valid0, rval = 1'0). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procdff$20082 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[2].u_mm.buf_last, Q = \u_dataflow_core.GEN_SLOT[2].u_np.last0, rval = 1'0). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procdff$20084 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[2].u_mm.buf_input [7:0], Q = \u_dataflow_core.GEN_SLOT[2].u_np.x0[0]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procdff$20085 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[2].u_mm.buf_input [15:8], Q = \u_dataflow_core.GEN_SLOT[2].u_np.x0[1]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procdff$20086 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[2].u_mm.buf_input [23:16], Q = \u_dataflow_core.GEN_SLOT[2].u_np.x0[2]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procdff$20087 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[2].u_mm.buf_input [31:24], Q = \u_dataflow_core.GEN_SLOT[2].u_np.x0[3]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procdff$20088 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[2].u_mm.buf_input [39:32], Q = \u_dataflow_core.GEN_SLOT[2].u_np.x0[4]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procdff$20089 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[2].u_mm.buf_input [47:40], Q = \u_dataflow_core.GEN_SLOT[2].u_np.x0[5]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procdff$20090 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[2].u_mm.buf_input [55:48], Q = \u_dataflow_core.GEN_SLOT[2].u_np.x0[6]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procdff$20091 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[2].u_mm.buf_input [63:56], Q = \u_dataflow_core.GEN_SLOT[2].u_np.x0[7]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procdff$20092 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[2].u_mm.buf_weight [7:0], Q = \u_dataflow_core.GEN_SLOT[2].u_np.w0[0]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procdff$20093 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[2].u_mm.buf_weight [15:8], Q = \u_dataflow_core.GEN_SLOT[2].u_np.w0[1]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procdff$20094 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[2].u_mm.buf_weight [23:16], Q = \u_dataflow_core.GEN_SLOT[2].u_np.w0[2]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procdff$20095 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[2].u_mm.buf_weight [31:24], Q = \u_dataflow_core.GEN_SLOT[2].u_np.w0[3]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procdff$20096 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[2].u_mm.buf_weight [39:32], Q = \u_dataflow_core.GEN_SLOT[2].u_np.w0[4]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procdff$20097 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[2].u_mm.buf_weight [47:40], Q = \u_dataflow_core.GEN_SLOT[2].u_np.w0[5]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procdff$20098 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[2].u_mm.buf_weight [55:48], Q = \u_dataflow_core.GEN_SLOT[2].u_np.w0[6]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procdff$20099 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[2].u_mm.buf_weight [63:56], Q = \u_dataflow_core.GEN_SLOT[2].u_np.w0[7]). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$procdff$20738 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$procmux$19750_Y, Q = \u_dataflow_core.GEN_SLOT[2].u_mm.result_ready, rval = 1'0). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$procdff$20742 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$procmux$19756_Y, Q = \u_dataflow_core.GEN_SLOT[2].u_mm.job_done, rval = 1'0). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$procdff$20743 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[2].u_mm.rd_ptr [3:0], Q = \u_dataflow_core.GEN_SLOT[2].u_mm.act_rd_addr). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$procdff$20744 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[2].u_mm.rd_ptr [3:0], Q = \u_dataflow_core.GEN_SLOT[2].u_mm.wgt_rd_addr). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$procdff$20745 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$procmux$19988_Y, Q = \u_dataflow_core.GEN_SLOT[2].u_mm.job_active_reg, rval = 1'0). +Adding EN signal on $auto$ff.cc:337:slice$23331 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$procmux$19988_Y, Q = \u_dataflow_core.GEN_SLOT[2].u_mm.job_active_reg). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$procdff$20746 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.u_director.slot_x_base [68:46], Q = \u_dataflow_core.GEN_SLOT[2].u_mm.x_base_reg). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$procdff$20747 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.u_director.slot_w_base [68:46], Q = \u_dataflow_core.GEN_SLOT[2].u_mm.w_base_reg). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$procdff$20748 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.u_director.slot_result_addr [68:46], Q = \u_dataflow_core.GEN_SLOT[2].u_mm.result_addr_reg). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$procdff$20749 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.u_director.slot_n_tiles [47:32], Q = \u_dataflow_core.GEN_SLOT[2].u_mm.n_tiles_reg). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$procdff$20750 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$procmux$19923_Y, Q = \u_dataflow_core.GEN_SLOT[2].u_mm.tile_idx, rval = 5'00000). +Adding EN signal on $auto$ff.cc:337:slice$23363 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$procmux$19923_Y, Q = \u_dataflow_core.GEN_SLOT[2].u_mm.tile_idx). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$procdff$20751 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$procmux$19906_Y, Q = \u_dataflow_core.GEN_SLOT[2].u_mm.rd_ptr, rval = 5'00000). +Adding EN signal on $auto$ff.cc:337:slice$23375 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$procmux$19906_Y, Q = \u_dataflow_core.GEN_SLOT[2].u_mm.rd_ptr). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$procdff$20752 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$procmux$19893_Y, Q = \u_dataflow_core.GEN_SLOT[2].u_mm.wr_mem_req, rval = 1'0). +Adding EN signal on $auto$ff.cc:337:slice$23385 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$procmux$19893_Y, Q = \u_dataflow_core.GEN_SLOT[2].u_mm.wr_mem_req). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$procdff$20753 ($dff) from module fpga_neural_v2_top (D = { 1'0 \u_dataflow_core.GEN_SLOT[2].u_mm.result_addr_reg [22:1] }, Q = \u_dataflow_core.GEN_SLOT[2].u_mm.wr_mem_addr). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$procdff$20754 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$ternary$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:273$3781_Y, Q = \u_dataflow_core.GEN_SLOT[2].u_mm.wr_mem_wdata). +Adding SRST signal on $auto$ff.cc:337:slice$23394 ($dffe) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[2].u_np.result_data, Q = \u_dataflow_core.GEN_SLOT[2].u_mm.wr_mem_wdata [15:8], rval = 8'00000000). +Adding SRST signal on $auto$ff.cc:337:slice$23394 ($dffe) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[2].u_np.result_data, Q = \u_dataflow_core.GEN_SLOT[2].u_mm.wr_mem_wdata [7:0], rval = 8'00000000). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$procdff$20755 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$procmux$19870_Y, Q = \u_dataflow_core.GEN_SLOT[2].u_mm.wr_mem_lb_n, rval = 1'1). +Adding EN signal on $auto$ff.cc:337:slice$23401 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$ternary$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:274$3782_Y, Q = \u_dataflow_core.GEN_SLOT[2].u_mm.wr_mem_lb_n). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$procdff$20756 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$procmux$19860_Y, Q = \u_dataflow_core.GEN_SLOT[2].u_mm.wr_mem_ub_n, rval = 1'1). +Adding EN signal on $auto$ff.cc:337:slice$23405 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$ternary$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:275$3783_Y, Q = \u_dataflow_core.GEN_SLOT[2].u_mm.wr_mem_ub_n). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$procdff$20757 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$procmux$19847_Y, Q = \u_dataflow_core.GEN_SLOT[2].u_mm.rd_pending, rval = 1'0). +Adding EN signal on $auto$ff.cc:337:slice$23409 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$procmux$19847_Y, Q = \u_dataflow_core.GEN_SLOT[2].u_mm.rd_pending). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$procdff$20759 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$eq$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:263$3778_Y, Q = \u_dataflow_core.GEN_SLOT[2].u_mm.rd_pending_last). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$procdff$20760 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$procmux$19808_Y, Q = \u_dataflow_core.GEN_SLOT[2].u_mm.buf_valid, rval = 1'0). +Adding EN signal on $auto$ff.cc:337:slice$23422 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$procmux$19808_Y, Q = \u_dataflow_core.GEN_SLOT[2].u_mm.buf_valid). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$procdff$20761 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[2].u_mm.act_rd_data, Q = \u_dataflow_core.GEN_SLOT[2].u_mm.buf_input). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$procdff$20762 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[2].u_mm.wgt_rd_data, Q = \u_dataflow_core.GEN_SLOT[2].u_mm.buf_weight). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$procdff$20763 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[2].u_mm.rd_pending_last, Q = \u_dataflow_core.GEN_SLOT[2].u_mm.buf_last). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$procdff$20245 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$procmux$10567_Y, Q = \u_dataflow_core.GEN_SLOT[2].u_mm.u_wpf.req_outstanding, rval = 1'0). +Adding EN signal on $auto$ff.cc:337:slice$23447 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$procmux$10567_Y, Q = \u_dataflow_core.GEN_SLOT[2].u_mm.u_wpf.req_outstanding). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$procdff$20244 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$procmux$10579_Y, Q = \u_dataflow_core.GEN_SLOT[2].u_mm.u_wpf.fetch_word, rval = 1'0). +Adding EN signal on $auto$ff.cc:337:slice$23455 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$procmux$10577_Y, Q = \u_dataflow_core.GEN_SLOT[2].u_mm.u_wpf.fetch_word). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$procdff$20243 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$procmux$10591_Y, Q = \u_dataflow_core.GEN_SLOT[2].u_mm.u_wpf.fetch_tile, rval = 5'00000). +Adding EN signal on $auto$ff.cc:337:slice$23461 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:134$6818_Y, Q = \u_dataflow_core.GEN_SLOT[2].u_mm.u_wpf.fetch_tile). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$procdff$20242 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$procmux$10603_Y, Q = \u_dataflow_core.GEN_SLOT[2].u_mm.u_wpf.ready_count, rval = 5'00000). +Adding EN signal on $auto$ff.cc:337:slice$23471 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:133$6817_Y, Q = \u_dataflow_core.GEN_SLOT[2].u_mm.u_wpf.ready_count). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$procdff$20241 ($dff) from module fpga_neural_v2_top (D = \u_arbiter_wide.s_rdata [191:128], Q = \u_dataflow_core.GEN_SLOT[2].u_mm.u_wpf.wgt_fill_data). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$procdff$20240 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[2].u_mm.u_wpf.fetch_tile [3:0], Q = \u_dataflow_core.GEN_SLOT[2].u_mm.u_wpf.wgt_fill_addr). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$procdff$20239 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$procmux$10527_Y, Q = \u_dataflow_core.GEN_SLOT[2].u_mm.u_wpf.wgt_fill_we, rval = 1'0). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$procdff$20238 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$procmux$10643_Y, Q = \u_dataflow_core.GEN_SLOT[2].u_mm.u_wpf.mem_addr). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$procdff$20237 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$procmux$10545_Y, Q = \u_dataflow_core.GEN_SLOT[2].u_mm.u_wpf.mem_req, rval = 1'0). +Adding SRST signal on $flatten\u_arbiter_wide.$procdff$20146 ($dff) from module fpga_neural_v2_top (D = { $flatten\u_arbiter_wide.$procmux$8606_Y $flatten\u_arbiter_wide.$procmux$8582_Y $flatten\u_arbiter_wide.$procmux$8618_Y $flatten\u_arbiter_wide.$procmux$8654_Y }, Q = \u_arbiter_wide.pending_addr, rval = 92'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:337:slice$23516 ($sdff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[3].u_mm.u_wpf.mem_addr, Q = \u_arbiter_wide.pending_addr [91:69]). +Adding EN signal on $auto$ff.cc:337:slice$23516 ($sdff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[2].u_mm.u_wpf.mem_addr, Q = \u_arbiter_wide.pending_addr [68:46]). +Adding EN signal on $auto$ff.cc:337:slice$23516 ($sdff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[1].u_mm.u_wpf.mem_addr, Q = \u_arbiter_wide.pending_addr [45:23]). +Adding EN signal on $auto$ff.cc:337:slice$23516 ($sdff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[0].u_mm.u_wpf.mem_addr, Q = \u_arbiter_wide.pending_addr [22:0]). +Adding SRST signal on $flatten\u_arbiter_wide.$procdff$20145 ($dff) from module fpga_neural_v2_top (D = $flatten\u_arbiter_wide.$6$lookahead\pending$7074[3:0]$7086, Q = \u_arbiter_wide.pending, rval = 4'0000). +Adding SRST signal on $flatten\u_arbiter_wide.$procdff$20144 ($dff) from module fpga_neural_v2_top (D = $flatten\u_arbiter_wide.$procmux$8743_Y, Q = \u_arbiter_wide.owner, rval = 3'000). +Adding EN signal on $auto$ff.cc:337:slice$23522 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_arbiter_wide.$procmux$8743_Y, Q = \u_arbiter_wide.owner). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procdff$20042 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[1].u_np.valid_tree [1], Q = \u_dataflow_core.GEN_SLOT[1].u_np.valid_tree [2], rval = 1'0). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procdff$20043 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[1].u_np.last_tree [1], Q = \u_dataflow_core.GEN_SLOT[1].u_np.last_tree [2], rval = 1'0). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procdff$20046 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[1].u_np.valid_tree [0], Q = \u_dataflow_core.GEN_SLOT[1].u_np.valid_tree [1], rval = 1'0). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procdff$20047 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[1].u_np.last_tree [0], Q = \u_dataflow_core.GEN_SLOT[1].u_np.last_tree [1], rval = 1'0). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procdff$20052 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[1].u_np.valid1, Q = \u_dataflow_core.GEN_SLOT[1].u_np.valid_tree [0], rval = 1'0). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procdff$20053 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[1].u_np.last1, Q = \u_dataflow_core.GEN_SLOT[1].u_np.last_tree [0], rval = 1'0). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procdff$20054 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procmux$7580_Y, Q = \u_dataflow_core.GEN_SLOT[1].u_np.result_valid, rval = 1'0). +Adding EN signal on $auto$ff.cc:337:slice$23536 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procmux$7580_Y, Q = \u_dataflow_core.GEN_SLOT[1].u_np.result_valid). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procdff$20055 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procmux$7570_Y, Q = \u_dataflow_core.GEN_SLOT[1].u_np.result_data, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:337:slice$23546 ($sdff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[1].u_np.y7, Q = \u_dataflow_core.GEN_SLOT[1].u_np.result_data). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procdff$20059 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procmux$7525_Y, Q = \u_dataflow_core.GEN_SLOT[1].u_np.bias_reg, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:337:slice$23550 ($sdff) from module fpga_neural_v2_top (D = 8'00000000, Q = \u_dataflow_core.GEN_SLOT[1].u_np.bias_reg). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procdff$20060 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procmux$7511_Y, Q = \u_dataflow_core.GEN_SLOT[1].u_np.activation_reg, rval = 2'01). +Adding EN signal on $auto$ff.cc:337:slice$23554 ($sdff) from module fpga_neural_v2_top (D = 2'01, Q = \u_dataflow_core.GEN_SLOT[1].u_np.activation_reg). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procdff$20062 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[1].u_np.last6, Q = \u_dataflow_core.GEN_SLOT[1].u_np.valid7, rval = 1'0). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procdff$20063 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procmux$7592_Y, Q = \u_dataflow_core.GEN_SLOT[1].u_np.y7). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procdff$20064 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[1].u_np.valid5, Q = \u_dataflow_core.GEN_SLOT[1].u_np.valid6, rval = 1'0). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procdff$20065 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[1].u_np.last5, Q = \u_dataflow_core.GEN_SLOT[1].u_np.last6, rval = 1'0). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procdff$20066 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$add$hardware/v2/rtl/neural_processor.v:252$3690_Y, Q = \u_dataflow_core.GEN_SLOT[1].u_np.final_acc_reg). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procdff$20067 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procmux$7612_Y, Q = \u_dataflow_core.GEN_SLOT[1].u_np.acc_reg, rval = 0). +Adding EN signal on $auto$ff.cc:337:slice$23563 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$add$hardware/v2/rtl/neural_processor.v:226$3688_Y, Q = \u_dataflow_core.GEN_SLOT[1].u_np.acc_reg). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procdff$20068 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[1].u_np.valid_tree [2], Q = \u_dataflow_core.GEN_SLOT[1].u_np.valid5, rval = 1'0). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procdff$20069 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[1].u_np.last_tree [2], Q = \u_dataflow_core.GEN_SLOT[1].u_np.last5, rval = 1'0). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procdff$20071 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[1].u_np.valid0, Q = \u_dataflow_core.GEN_SLOT[1].u_np.valid1, rval = 1'0). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procdff$20072 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[1].u_np.last0, Q = \u_dataflow_core.GEN_SLOT[1].u_np.last1, rval = 1'0). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procdff$20073 ($dff) from module fpga_neural_v2_top (D = { \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[0] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[0] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[0] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[0] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[0] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[0] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[0] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[0] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[0] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[0] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[0] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[0] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[0] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[0] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[0] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[0] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[0] }, Q = \u_dataflow_core.GEN_SLOT[1].u_np.prod1[0]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procdff$20074 ($dff) from module fpga_neural_v2_top (D = { \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[1] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[1] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[1] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[1] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[1] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[1] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[1] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[1] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[1] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[1] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[1] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[1] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[1] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[1] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[1] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[1] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[1] }, Q = \u_dataflow_core.GEN_SLOT[1].u_np.prod1[1]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procdff$20075 ($dff) from module fpga_neural_v2_top (D = { \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[2] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[2] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[2] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[2] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[2] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[2] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[2] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[2] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[2] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[2] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[2] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[2] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[2] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[2] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[2] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[2] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[2] }, Q = \u_dataflow_core.GEN_SLOT[1].u_np.prod1[2]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procdff$20076 ($dff) from module fpga_neural_v2_top (D = { \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[3] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[3] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[3] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[3] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[3] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[3] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[3] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[3] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[3] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[3] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[3] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[3] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[3] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[3] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[3] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[3] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[3] }, Q = \u_dataflow_core.GEN_SLOT[1].u_np.prod1[3]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procdff$20077 ($dff) from module fpga_neural_v2_top (D = { \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[4] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[4] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[4] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[4] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[4] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[4] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[4] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[4] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[4] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[4] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[4] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[4] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[4] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[4] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[4] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[4] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[4] }, Q = \u_dataflow_core.GEN_SLOT[1].u_np.prod1[4]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procdff$20078 ($dff) from module fpga_neural_v2_top (D = { \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[5] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[5] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[5] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[5] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[5] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[5] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[5] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[5] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[5] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[5] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[5] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[5] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[5] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[5] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[5] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[5] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[5] }, Q = \u_dataflow_core.GEN_SLOT[1].u_np.prod1[5]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procdff$20079 ($dff) from module fpga_neural_v2_top (D = { \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[6] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[6] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[6] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[6] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[6] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[6] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[6] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[6] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[6] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[6] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[6] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[6] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[6] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[6] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[6] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[6] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[6] }, Q = \u_dataflow_core.GEN_SLOT[1].u_np.prod1[6]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procdff$20080 ($dff) from module fpga_neural_v2_top (D = { \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[7] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[7] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[7] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[7] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[7] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[7] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[7] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[7] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[7] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[7] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[7] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[7] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[7] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[7] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[7] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[7] [15] \u_dataflow_core.GEN_SLOT[1].u_np.product_comb[7] }, Q = \u_dataflow_core.GEN_SLOT[1].u_np.prod1[7]). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procdff$20081 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$logic_and$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:191$3766_Y, Q = \u_dataflow_core.GEN_SLOT[1].u_np.valid0, rval = 1'0). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procdff$20082 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[1].u_mm.buf_last, Q = \u_dataflow_core.GEN_SLOT[1].u_np.last0, rval = 1'0). +Adding SRST signal on $flatten\u_arbiter_wide.$procdff$20140 ($dff) from module fpga_neural_v2_top (D = $flatten\u_arbiter_wide.$procmux$8779_Y, Q = \u_arbiter_wide.m_addr, rval = 23'00000000000000000000000). +Adding EN signal on $auto$ff.cc:337:slice$23585 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_arbiter_wide.$shiftx$hardware/v2/rtl/slot_mem_arbiter_wide.v:163$7095_Y, Q = \u_arbiter_wide.m_addr). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procdff$20084 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[1].u_mm.buf_input [7:0], Q = \u_dataflow_core.GEN_SLOT[1].u_np.x0[0]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procdff$20085 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[1].u_mm.buf_input [15:8], Q = \u_dataflow_core.GEN_SLOT[1].u_np.x0[1]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procdff$20086 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[1].u_mm.buf_input [23:16], Q = \u_dataflow_core.GEN_SLOT[1].u_np.x0[2]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procdff$20087 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[1].u_mm.buf_input [31:24], Q = \u_dataflow_core.GEN_SLOT[1].u_np.x0[3]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procdff$20088 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[1].u_mm.buf_input [39:32], Q = \u_dataflow_core.GEN_SLOT[1].u_np.x0[4]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procdff$20089 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[1].u_mm.buf_input [47:40], Q = \u_dataflow_core.GEN_SLOT[1].u_np.x0[5]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procdff$20090 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[1].u_mm.buf_input [55:48], Q = \u_dataflow_core.GEN_SLOT[1].u_np.x0[6]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procdff$20091 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[1].u_mm.buf_input [63:56], Q = \u_dataflow_core.GEN_SLOT[1].u_np.x0[7]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procdff$20092 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[1].u_mm.buf_weight [7:0], Q = \u_dataflow_core.GEN_SLOT[1].u_np.w0[0]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procdff$20093 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[1].u_mm.buf_weight [15:8], Q = \u_dataflow_core.GEN_SLOT[1].u_np.w0[1]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procdff$20094 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[1].u_mm.buf_weight [23:16], Q = \u_dataflow_core.GEN_SLOT[1].u_np.w0[2]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procdff$20095 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[1].u_mm.buf_weight [31:24], Q = \u_dataflow_core.GEN_SLOT[1].u_np.w0[3]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procdff$20096 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[1].u_mm.buf_weight [39:32], Q = \u_dataflow_core.GEN_SLOT[1].u_np.w0[4]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procdff$20097 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[1].u_mm.buf_weight [47:40], Q = \u_dataflow_core.GEN_SLOT[1].u_np.w0[5]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procdff$20098 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[1].u_mm.buf_weight [55:48], Q = \u_dataflow_core.GEN_SLOT[1].u_np.w0[6]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procdff$20099 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[1].u_mm.buf_weight [63:56], Q = \u_dataflow_core.GEN_SLOT[1].u_np.w0[7]). +Adding SRST signal on $flatten\u_arbiter_wide.$procdff$20138 ($dff) from module fpga_neural_v2_top (D = $flatten\u_arbiter_wide.$procmux$8690_Y, Q = \u_arbiter_wide.m_req, rval = 1'0). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$procdff$20738 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$procmux$19750_Y, Q = \u_dataflow_core.GEN_SLOT[1].u_mm.result_ready, rval = 1'0). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$procdff$20742 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$procmux$19756_Y, Q = \u_dataflow_core.GEN_SLOT[1].u_mm.job_done, rval = 1'0). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$procdff$20743 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[1].u_mm.rd_ptr [3:0], Q = \u_dataflow_core.GEN_SLOT[1].u_mm.act_rd_addr). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$procdff$20744 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[1].u_mm.rd_ptr [3:0], Q = \u_dataflow_core.GEN_SLOT[1].u_mm.wgt_rd_addr). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$procdff$20745 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$procmux$19988_Y, Q = \u_dataflow_core.GEN_SLOT[1].u_mm.job_active_reg, rval = 1'0). +Adding EN signal on $auto$ff.cc:337:slice$23690 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$procmux$19988_Y, Q = \u_dataflow_core.GEN_SLOT[1].u_mm.job_active_reg). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$procdff$20746 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.u_director.slot_x_base [45:23], Q = \u_dataflow_core.GEN_SLOT[1].u_mm.x_base_reg). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$procdff$20747 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.u_director.slot_w_base [45:23], Q = \u_dataflow_core.GEN_SLOT[1].u_mm.w_base_reg). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$procdff$20748 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.u_director.slot_result_addr [45:23], Q = \u_dataflow_core.GEN_SLOT[1].u_mm.result_addr_reg). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$procdff$20749 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.u_director.slot_n_tiles [31:16], Q = \u_dataflow_core.GEN_SLOT[1].u_mm.n_tiles_reg). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$procdff$20750 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$procmux$19923_Y, Q = \u_dataflow_core.GEN_SLOT[1].u_mm.tile_idx, rval = 5'00000). +Adding EN signal on $auto$ff.cc:337:slice$23722 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$procmux$19923_Y, Q = \u_dataflow_core.GEN_SLOT[1].u_mm.tile_idx). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$procdff$20751 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$procmux$19906_Y, Q = \u_dataflow_core.GEN_SLOT[1].u_mm.rd_ptr, rval = 5'00000). +Adding EN signal on $auto$ff.cc:337:slice$23734 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$procmux$19906_Y, Q = \u_dataflow_core.GEN_SLOT[1].u_mm.rd_ptr). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$procdff$20752 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$procmux$19893_Y, Q = \u_dataflow_core.GEN_SLOT[1].u_mm.wr_mem_req, rval = 1'0). +Adding EN signal on $auto$ff.cc:337:slice$23744 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$procmux$19893_Y, Q = \u_dataflow_core.GEN_SLOT[1].u_mm.wr_mem_req). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$procdff$20753 ($dff) from module fpga_neural_v2_top (D = { 1'0 \u_dataflow_core.GEN_SLOT[1].u_mm.result_addr_reg [22:1] }, Q = \u_dataflow_core.GEN_SLOT[1].u_mm.wr_mem_addr). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$procdff$20754 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$ternary$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:273$3781_Y, Q = \u_dataflow_core.GEN_SLOT[1].u_mm.wr_mem_wdata). +Adding SRST signal on $auto$ff.cc:337:slice$23753 ($dffe) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[1].u_np.result_data, Q = \u_dataflow_core.GEN_SLOT[1].u_mm.wr_mem_wdata [15:8], rval = 8'00000000). +Adding SRST signal on $auto$ff.cc:337:slice$23753 ($dffe) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[1].u_np.result_data, Q = \u_dataflow_core.GEN_SLOT[1].u_mm.wr_mem_wdata [7:0], rval = 8'00000000). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$procdff$20755 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$procmux$19870_Y, Q = \u_dataflow_core.GEN_SLOT[1].u_mm.wr_mem_lb_n, rval = 1'1). +Adding EN signal on $auto$ff.cc:337:slice$23760 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$ternary$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:274$3782_Y, Q = \u_dataflow_core.GEN_SLOT[1].u_mm.wr_mem_lb_n). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$procdff$20756 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$procmux$19860_Y, Q = \u_dataflow_core.GEN_SLOT[1].u_mm.wr_mem_ub_n, rval = 1'1). +Adding EN signal on $auto$ff.cc:337:slice$23764 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$ternary$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:275$3783_Y, Q = \u_dataflow_core.GEN_SLOT[1].u_mm.wr_mem_ub_n). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$procdff$20757 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$procmux$19847_Y, Q = \u_dataflow_core.GEN_SLOT[1].u_mm.rd_pending, rval = 1'0). +Adding EN signal on $auto$ff.cc:337:slice$23768 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$procmux$19847_Y, Q = \u_dataflow_core.GEN_SLOT[1].u_mm.rd_pending). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$procdff$20759 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$eq$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:263$3778_Y, Q = \u_dataflow_core.GEN_SLOT[1].u_mm.rd_pending_last). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$procdff$20760 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$procmux$19808_Y, Q = \u_dataflow_core.GEN_SLOT[1].u_mm.buf_valid, rval = 1'0). +Adding EN signal on $auto$ff.cc:337:slice$23781 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$procmux$19808_Y, Q = \u_dataflow_core.GEN_SLOT[1].u_mm.buf_valid). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$procdff$20761 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[1].u_mm.act_rd_data, Q = \u_dataflow_core.GEN_SLOT[1].u_mm.buf_input). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$procdff$20762 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[1].u_mm.wgt_rd_data, Q = \u_dataflow_core.GEN_SLOT[1].u_mm.buf_weight). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$procdff$20763 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[1].u_mm.rd_pending_last, Q = \u_dataflow_core.GEN_SLOT[1].u_mm.buf_last). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$procdff$20245 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$procmux$10567_Y, Q = \u_dataflow_core.GEN_SLOT[1].u_mm.u_wpf.req_outstanding, rval = 1'0). +Adding EN signal on $auto$ff.cc:337:slice$23806 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$procmux$10567_Y, Q = \u_dataflow_core.GEN_SLOT[1].u_mm.u_wpf.req_outstanding). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$procdff$20244 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$procmux$10579_Y, Q = \u_dataflow_core.GEN_SLOT[1].u_mm.u_wpf.fetch_word, rval = 1'0). +Adding EN signal on $auto$ff.cc:337:slice$23814 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$procmux$10577_Y, Q = \u_dataflow_core.GEN_SLOT[1].u_mm.u_wpf.fetch_word). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$procdff$20243 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$procmux$10591_Y, Q = \u_dataflow_core.GEN_SLOT[1].u_mm.u_wpf.fetch_tile, rval = 5'00000). +Adding EN signal on $auto$ff.cc:337:slice$23820 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:134$6818_Y, Q = \u_dataflow_core.GEN_SLOT[1].u_mm.u_wpf.fetch_tile). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$procdff$20242 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$procmux$10603_Y, Q = \u_dataflow_core.GEN_SLOT[1].u_mm.u_wpf.ready_count, rval = 5'00000). +Adding EN signal on $auto$ff.cc:337:slice$23830 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:133$6817_Y, Q = \u_dataflow_core.GEN_SLOT[1].u_mm.u_wpf.ready_count). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$procdff$20241 ($dff) from module fpga_neural_v2_top (D = \u_arbiter_wide.s_rdata [127:64], Q = \u_dataflow_core.GEN_SLOT[1].u_mm.u_wpf.wgt_fill_data). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$procdff$20240 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[1].u_mm.u_wpf.fetch_tile [3:0], Q = \u_dataflow_core.GEN_SLOT[1].u_mm.u_wpf.wgt_fill_addr). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$procdff$20239 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$procmux$10527_Y, Q = \u_dataflow_core.GEN_SLOT[1].u_mm.u_wpf.wgt_fill_we, rval = 1'0). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$procdff$20238 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$procmux$10643_Y, Q = \u_dataflow_core.GEN_SLOT[1].u_mm.u_wpf.mem_addr). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$procdff$20237 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$procmux$10545_Y, Q = \u_dataflow_core.GEN_SLOT[1].u_mm.u_wpf.mem_req, rval = 1'0). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procdff$20042 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[0].u_np.valid_tree [1], Q = \u_dataflow_core.GEN_SLOT[0].u_np.valid_tree [2], rval = 1'0). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procdff$20043 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[0].u_np.last_tree [1], Q = \u_dataflow_core.GEN_SLOT[0].u_np.last_tree [2], rval = 1'0). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procdff$20046 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[0].u_np.valid_tree [0], Q = \u_dataflow_core.GEN_SLOT[0].u_np.valid_tree [1], rval = 1'0). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procdff$20047 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[0].u_np.last_tree [0], Q = \u_dataflow_core.GEN_SLOT[0].u_np.last_tree [1], rval = 1'0). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procdff$20052 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[0].u_np.valid1, Q = \u_dataflow_core.GEN_SLOT[0].u_np.valid_tree [0], rval = 1'0). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procdff$20053 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[0].u_np.last1, Q = \u_dataflow_core.GEN_SLOT[0].u_np.last_tree [0], rval = 1'0). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procdff$20054 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procmux$7580_Y, Q = \u_dataflow_core.GEN_SLOT[0].u_np.result_valid, rval = 1'0). +Adding EN signal on $auto$ff.cc:337:slice$23881 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procmux$7580_Y, Q = \u_dataflow_core.GEN_SLOT[0].u_np.result_valid). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procdff$20055 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procmux$7570_Y, Q = \u_dataflow_core.GEN_SLOT[0].u_np.result_data, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:337:slice$23891 ($sdff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[0].u_np.y7, Q = \u_dataflow_core.GEN_SLOT[0].u_np.result_data). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procdff$20059 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procmux$7525_Y, Q = \u_dataflow_core.GEN_SLOT[0].u_np.bias_reg, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:337:slice$23895 ($sdff) from module fpga_neural_v2_top (D = 8'00000000, Q = \u_dataflow_core.GEN_SLOT[0].u_np.bias_reg). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procdff$20060 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procmux$7511_Y, Q = \u_dataflow_core.GEN_SLOT[0].u_np.activation_reg, rval = 2'01). +Adding EN signal on $auto$ff.cc:337:slice$23899 ($sdff) from module fpga_neural_v2_top (D = 2'01, Q = \u_dataflow_core.GEN_SLOT[0].u_np.activation_reg). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procdff$20062 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[0].u_np.last6, Q = \u_dataflow_core.GEN_SLOT[0].u_np.valid7, rval = 1'0). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procdff$20063 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procmux$7592_Y, Q = \u_dataflow_core.GEN_SLOT[0].u_np.y7). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procdff$20064 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[0].u_np.valid5, Q = \u_dataflow_core.GEN_SLOT[0].u_np.valid6, rval = 1'0). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procdff$20065 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[0].u_np.last5, Q = \u_dataflow_core.GEN_SLOT[0].u_np.last6, rval = 1'0). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procdff$20066 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$add$hardware/v2/rtl/neural_processor.v:252$3690_Y, Q = \u_dataflow_core.GEN_SLOT[0].u_np.final_acc_reg). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procdff$20067 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procmux$7612_Y, Q = \u_dataflow_core.GEN_SLOT[0].u_np.acc_reg, rval = 0). +Adding EN signal on $auto$ff.cc:337:slice$23908 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$add$hardware/v2/rtl/neural_processor.v:226$3688_Y, Q = \u_dataflow_core.GEN_SLOT[0].u_np.acc_reg). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procdff$20068 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[0].u_np.valid_tree [2], Q = \u_dataflow_core.GEN_SLOT[0].u_np.valid5, rval = 1'0). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procdff$20069 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[0].u_np.last_tree [2], Q = \u_dataflow_core.GEN_SLOT[0].u_np.last5, rval = 1'0). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procdff$20071 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[0].u_np.valid0, Q = \u_dataflow_core.GEN_SLOT[0].u_np.valid1, rval = 1'0). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procdff$20072 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[0].u_np.last0, Q = \u_dataflow_core.GEN_SLOT[0].u_np.last1, rval = 1'0). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procdff$20073 ($dff) from module fpga_neural_v2_top (D = { \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[0] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[0] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[0] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[0] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[0] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[0] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[0] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[0] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[0] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[0] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[0] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[0] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[0] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[0] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[0] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[0] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[0] }, Q = \u_dataflow_core.GEN_SLOT[0].u_np.prod1[0]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procdff$20074 ($dff) from module fpga_neural_v2_top (D = { \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[1] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[1] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[1] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[1] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[1] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[1] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[1] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[1] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[1] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[1] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[1] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[1] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[1] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[1] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[1] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[1] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[1] }, Q = \u_dataflow_core.GEN_SLOT[0].u_np.prod1[1]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procdff$20075 ($dff) from module fpga_neural_v2_top (D = { \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[2] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[2] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[2] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[2] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[2] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[2] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[2] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[2] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[2] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[2] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[2] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[2] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[2] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[2] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[2] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[2] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[2] }, Q = \u_dataflow_core.GEN_SLOT[0].u_np.prod1[2]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procdff$20076 ($dff) from module fpga_neural_v2_top (D = { \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[3] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[3] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[3] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[3] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[3] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[3] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[3] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[3] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[3] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[3] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[3] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[3] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[3] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[3] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[3] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[3] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[3] }, Q = \u_dataflow_core.GEN_SLOT[0].u_np.prod1[3]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procdff$20077 ($dff) from module fpga_neural_v2_top (D = { \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[4] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[4] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[4] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[4] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[4] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[4] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[4] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[4] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[4] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[4] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[4] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[4] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[4] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[4] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[4] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[4] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[4] }, Q = \u_dataflow_core.GEN_SLOT[0].u_np.prod1[4]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procdff$20078 ($dff) from module fpga_neural_v2_top (D = { \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[5] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[5] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[5] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[5] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[5] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[5] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[5] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[5] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[5] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[5] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[5] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[5] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[5] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[5] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[5] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[5] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[5] }, Q = \u_dataflow_core.GEN_SLOT[0].u_np.prod1[5]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procdff$20079 ($dff) from module fpga_neural_v2_top (D = { \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[6] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[6] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[6] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[6] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[6] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[6] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[6] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[6] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[6] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[6] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[6] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[6] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[6] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[6] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[6] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[6] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[6] }, Q = \u_dataflow_core.GEN_SLOT[0].u_np.prod1[6]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procdff$20080 ($dff) from module fpga_neural_v2_top (D = { \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[7] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[7] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[7] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[7] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[7] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[7] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[7] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[7] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[7] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[7] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[7] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[7] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[7] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[7] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[7] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[7] [15] \u_dataflow_core.GEN_SLOT[0].u_np.product_comb[7] }, Q = \u_dataflow_core.GEN_SLOT[0].u_np.prod1[7]). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procdff$20081 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$logic_and$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:191$3766_Y, Q = \u_dataflow_core.GEN_SLOT[0].u_np.valid0, rval = 1'0). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procdff$20082 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[0].u_mm.buf_last, Q = \u_dataflow_core.GEN_SLOT[0].u_np.last0, rval = 1'0). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procdff$20084 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[0].u_mm.buf_input [7:0], Q = \u_dataflow_core.GEN_SLOT[0].u_np.x0[0]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procdff$20085 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[0].u_mm.buf_input [15:8], Q = \u_dataflow_core.GEN_SLOT[0].u_np.x0[1]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procdff$20086 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[0].u_mm.buf_input [23:16], Q = \u_dataflow_core.GEN_SLOT[0].u_np.x0[2]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procdff$20087 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[0].u_mm.buf_input [31:24], Q = \u_dataflow_core.GEN_SLOT[0].u_np.x0[3]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procdff$20088 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[0].u_mm.buf_input [39:32], Q = \u_dataflow_core.GEN_SLOT[0].u_np.x0[4]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procdff$20089 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[0].u_mm.buf_input [47:40], Q = \u_dataflow_core.GEN_SLOT[0].u_np.x0[5]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procdff$20090 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[0].u_mm.buf_input [55:48], Q = \u_dataflow_core.GEN_SLOT[0].u_np.x0[6]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procdff$20091 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[0].u_mm.buf_input [63:56], Q = \u_dataflow_core.GEN_SLOT[0].u_np.x0[7]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procdff$20092 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[0].u_mm.buf_weight [7:0], Q = \u_dataflow_core.GEN_SLOT[0].u_np.w0[0]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procdff$20093 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[0].u_mm.buf_weight [15:8], Q = \u_dataflow_core.GEN_SLOT[0].u_np.w0[1]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procdff$20094 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[0].u_mm.buf_weight [23:16], Q = \u_dataflow_core.GEN_SLOT[0].u_np.w0[2]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procdff$20095 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[0].u_mm.buf_weight [31:24], Q = \u_dataflow_core.GEN_SLOT[0].u_np.w0[3]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procdff$20096 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[0].u_mm.buf_weight [39:32], Q = \u_dataflow_core.GEN_SLOT[0].u_np.w0[4]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procdff$20097 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[0].u_mm.buf_weight [47:40], Q = \u_dataflow_core.GEN_SLOT[0].u_np.w0[5]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procdff$20098 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[0].u_mm.buf_weight [55:48], Q = \u_dataflow_core.GEN_SLOT[0].u_np.w0[6]). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procdff$20099 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[0].u_mm.buf_weight [63:56], Q = \u_dataflow_core.GEN_SLOT[0].u_np.w0[7]). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$procdff$20738 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$procmux$19750_Y, Q = \u_dataflow_core.GEN_SLOT[0].u_mm.result_ready, rval = 1'0). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$procdff$20742 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$procmux$19756_Y, Q = \u_dataflow_core.GEN_SLOT[0].u_mm.job_done, rval = 1'0). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$procdff$20743 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[0].u_mm.rd_ptr [3:0], Q = \u_dataflow_core.GEN_SLOT[0].u_mm.act_rd_addr). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$procdff$20744 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[0].u_mm.rd_ptr [3:0], Q = \u_dataflow_core.GEN_SLOT[0].u_mm.wgt_rd_addr). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$procdff$20745 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$procmux$19988_Y, Q = \u_dataflow_core.GEN_SLOT[0].u_mm.job_active_reg, rval = 1'0). +Adding EN signal on $auto$ff.cc:337:slice$24026 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$procmux$19988_Y, Q = \u_dataflow_core.GEN_SLOT[0].u_mm.job_active_reg). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$procdff$20746 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.u_director.slot_x_base [22:0], Q = \u_dataflow_core.GEN_SLOT[0].u_mm.x_base_reg). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$procdff$20747 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.u_director.slot_w_base [22:0], Q = \u_dataflow_core.GEN_SLOT[0].u_mm.w_base_reg). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$procdff$20748 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.u_director.slot_result_addr [22:0], Q = \u_dataflow_core.GEN_SLOT[0].u_mm.result_addr_reg). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$procdff$20749 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.u_director.slot_n_tiles [15:0], Q = \u_dataflow_core.GEN_SLOT[0].u_mm.n_tiles_reg). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$procdff$20750 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$procmux$19923_Y, Q = \u_dataflow_core.GEN_SLOT[0].u_mm.tile_idx, rval = 5'00000). +Adding EN signal on $auto$ff.cc:337:slice$24058 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$procmux$19923_Y, Q = \u_dataflow_core.GEN_SLOT[0].u_mm.tile_idx). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$procdff$20751 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$procmux$19906_Y, Q = \u_dataflow_core.GEN_SLOT[0].u_mm.rd_ptr, rval = 5'00000). +Adding EN signal on $auto$ff.cc:337:slice$24070 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$procmux$19906_Y, Q = \u_dataflow_core.GEN_SLOT[0].u_mm.rd_ptr). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$procdff$20752 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$procmux$19893_Y, Q = \u_dataflow_core.GEN_SLOT[0].u_mm.wr_mem_req, rval = 1'0). +Adding EN signal on $auto$ff.cc:337:slice$24080 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$procmux$19893_Y, Q = \u_dataflow_core.GEN_SLOT[0].u_mm.wr_mem_req). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$procdff$20753 ($dff) from module fpga_neural_v2_top (D = { 1'0 \u_dataflow_core.GEN_SLOT[0].u_mm.result_addr_reg [22:1] }, Q = \u_dataflow_core.GEN_SLOT[0].u_mm.wr_mem_addr). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$procdff$20754 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$ternary$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:273$3781_Y, Q = \u_dataflow_core.GEN_SLOT[0].u_mm.wr_mem_wdata). +Adding SRST signal on $auto$ff.cc:337:slice$24089 ($dffe) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[0].u_np.result_data, Q = \u_dataflow_core.GEN_SLOT[0].u_mm.wr_mem_wdata [15:8], rval = 8'00000000). +Adding SRST signal on $auto$ff.cc:337:slice$24089 ($dffe) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[0].u_np.result_data, Q = \u_dataflow_core.GEN_SLOT[0].u_mm.wr_mem_wdata [7:0], rval = 8'00000000). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$procdff$20755 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$procmux$19870_Y, Q = \u_dataflow_core.GEN_SLOT[0].u_mm.wr_mem_lb_n, rval = 1'1). +Adding EN signal on $auto$ff.cc:337:slice$24096 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$ternary$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:274$3782_Y, Q = \u_dataflow_core.GEN_SLOT[0].u_mm.wr_mem_lb_n). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$procdff$20756 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$procmux$19860_Y, Q = \u_dataflow_core.GEN_SLOT[0].u_mm.wr_mem_ub_n, rval = 1'1). +Adding EN signal on $auto$ff.cc:337:slice$24100 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$ternary$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:275$3783_Y, Q = \u_dataflow_core.GEN_SLOT[0].u_mm.wr_mem_ub_n). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$procdff$20757 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$procmux$19847_Y, Q = \u_dataflow_core.GEN_SLOT[0].u_mm.rd_pending, rval = 1'0). +Adding EN signal on $auto$ff.cc:337:slice$24104 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$procmux$19847_Y, Q = \u_dataflow_core.GEN_SLOT[0].u_mm.rd_pending). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$procdff$20759 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$eq$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:263$3778_Y, Q = \u_dataflow_core.GEN_SLOT[0].u_mm.rd_pending_last). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$procdff$20760 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$procmux$19808_Y, Q = \u_dataflow_core.GEN_SLOT[0].u_mm.buf_valid, rval = 1'0). +Adding EN signal on $auto$ff.cc:337:slice$24117 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$procmux$19808_Y, Q = \u_dataflow_core.GEN_SLOT[0].u_mm.buf_valid). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$procdff$20761 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[0].u_mm.act_rd_data, Q = \u_dataflow_core.GEN_SLOT[0].u_mm.buf_input). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$procdff$20762 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[0].u_mm.wgt_rd_data, Q = \u_dataflow_core.GEN_SLOT[0].u_mm.buf_weight). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$procdff$20763 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[0].u_mm.rd_pending_last, Q = \u_dataflow_core.GEN_SLOT[0].u_mm.buf_last). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$procdff$20245 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$procmux$10567_Y, Q = \u_dataflow_core.GEN_SLOT[0].u_mm.u_wpf.req_outstanding, rval = 1'0). +Adding EN signal on $auto$ff.cc:337:slice$24142 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$procmux$10567_Y, Q = \u_dataflow_core.GEN_SLOT[0].u_mm.u_wpf.req_outstanding). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$procdff$20244 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$procmux$10579_Y, Q = \u_dataflow_core.GEN_SLOT[0].u_mm.u_wpf.fetch_word, rval = 1'0). +Adding EN signal on $auto$ff.cc:337:slice$24150 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$procmux$10577_Y, Q = \u_dataflow_core.GEN_SLOT[0].u_mm.u_wpf.fetch_word). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$procdff$20243 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$procmux$10591_Y, Q = \u_dataflow_core.GEN_SLOT[0].u_mm.u_wpf.fetch_tile, rval = 5'00000). +Adding EN signal on $auto$ff.cc:337:slice$24156 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:134$6818_Y, Q = \u_dataflow_core.GEN_SLOT[0].u_mm.u_wpf.fetch_tile). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$procdff$20242 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$procmux$10603_Y, Q = \u_dataflow_core.GEN_SLOT[0].u_mm.u_wpf.ready_count, rval = 5'00000). +Adding EN signal on $auto$ff.cc:337:slice$24166 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:133$6817_Y, Q = \u_dataflow_core.GEN_SLOT[0].u_mm.u_wpf.ready_count). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$procdff$20241 ($dff) from module fpga_neural_v2_top (D = \u_arbiter_wide.s_rdata [63:0], Q = \u_dataflow_core.GEN_SLOT[0].u_mm.u_wpf.wgt_fill_data). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$procdff$20240 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[0].u_mm.u_wpf.fetch_tile [3:0], Q = \u_dataflow_core.GEN_SLOT[0].u_mm.u_wpf.wgt_fill_addr). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$procdff$20239 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$procmux$10527_Y, Q = \u_dataflow_core.GEN_SLOT[0].u_mm.u_wpf.wgt_fill_we, rval = 1'0). +Adding EN signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$procdff$20238 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$procmux$10643_Y, Q = \u_dataflow_core.GEN_SLOT[0].u_mm.u_wpf.mem_addr). +Adding SRST signal on $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$procdff$20237 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$procmux$10545_Y, Q = \u_dataflow_core.GEN_SLOT[0].u_mm.u_wpf.mem_req, rval = 1'0). +Adding SRST signal on $flatten\u_sdram_backend.$procdff$20156 ($dff) from module fpga_neural_v2_top (D = $flatten\u_sdram_backend.$procmux$9636_Y, Q = \u_sdram_backend.w_rdata, rval = 64'0000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:337:slice$24211 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_sdram_backend.$procmux$9636_Y, Q = \u_sdram_backend.w_rdata). +Adding SRST signal on $flatten\u_sdram_backend.$procdff$20157 ($dff) from module fpga_neural_v2_top (D = $flatten\u_sdram_backend.$procmux$9318_Y, Q = \u_sdram_backend.w_ready, rval = 1'0). +Adding SRST signal on $flatten\u_sdram_backend.$procdff$20158 ($dff) from module fpga_neural_v2_top (D = $flatten\u_sdram_backend.$procmux$9622_Y, Q = \u_sdram_backend.ar_rdata, rval = 16'0000000000000000). +Adding EN signal on $auto$ff.cc:337:slice$24222 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_sdram_backend.$shiftx$hardware/v2/nms/rtl/sdram_unified_backend.v:306$7071_Y, Q = \u_sdram_backend.ar_rdata). +Adding SRST signal on $flatten\u_sdram_backend.$procdff$20159 ($dff) from module fpga_neural_v2_top (D = $flatten\u_sdram_backend.$3$memwr$\w_cache_valid$hardware/v2/nms/rtl/sdram_unified_backend.v:298$6941_EN[0:0]$7051, Q = \u_sdram_backend.ar_ready, rval = 1'0). +Adding SRST signal on $flatten\u_sdram_backend.$procdff$20160 ($dff) from module fpga_neural_v2_top (D = $flatten\u_sdram_backend.$procmux$9613_Y, Q = \u_sdram_backend.w_alloc_ptr, rval = 2'00). +Adding EN signal on $auto$ff.cc:337:slice$24231 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_sdram_backend.$ternary$hardware/v2/nms/rtl/sdram_unified_backend.v:299$7068_Y, Q = \u_sdram_backend.w_alloc_ptr). +Adding SRST signal on $flatten\u_sdram_backend.$procdff$20161 ($dff) from module fpga_neural_v2_top (D = $flatten\u_sdram_backend.$procmux$9337_Y, Q = \u_sdram_backend.ctrl_req, rval = 1'0). +Adding SRST signal on $flatten\u_sdram_backend.$procdff$20162 ($dff) from module fpga_neural_v2_top (D = $flatten\u_sdram_backend.$procmux$9602_Y, Q = \u_sdram_backend.ctrl_wr, rval = 1'0). +Adding EN signal on $auto$ff.cc:337:slice$24240 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_sdram_backend.$procmux$9597_Y, Q = \u_sdram_backend.ctrl_wr). +Adding SRST signal on $flatten\u_sdram_backend.$procdff$20163 ($dff) from module fpga_neural_v2_top (D = $flatten\u_sdram_backend.$procmux$9582_Y, Q = \u_sdram_backend.ctrl_addr, rval = 22'0000000000000000000000). +Adding EN signal on $auto$ff.cc:337:slice$24248 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_sdram_backend.$procmux$9577_Y, Q = \u_sdram_backend.ctrl_addr). +Adding SRST signal on $flatten\u_sdram_backend.$procdff$20164 ($dff) from module fpga_neural_v2_top (D = $flatten\u_sdram_backend.$procmux$9562_Y, Q = \u_sdram_backend.ctrl_wdata, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:337:slice$24256 ($sdff) from module fpga_neural_v2_top (D = { \u_sdram_backend.ar_eff_wdata \u_sdram_backend.ar_eff_wdata \u_sdram_backend.ar_eff_wdata \u_sdram_backend.ar_eff_wdata \u_sdram_backend.ar_eff_wdata \u_sdram_backend.ar_eff_wdata \u_sdram_backend.ar_eff_wdata \u_sdram_backend.ar_eff_wdata }, Q = \u_sdram_backend.ctrl_wdata). +Adding SRST signal on $flatten\u_sdram_backend.$procdff$20165 ($dff) from module fpga_neural_v2_top (D = $flatten\u_sdram_backend.$procmux$9542_Y, Q = \u_sdram_backend.ctrl_wmask, rval = 16'1111111111111111). +Adding EN signal on $auto$ff.cc:337:slice$24266 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_sdram_backend.$procmux$9537_Y, Q = \u_sdram_backend.ctrl_wmask). +Adding SRST signal on $flatten\u_sdram_backend.$procdff$20166 ($dff) from module fpga_neural_v2_top (D = $flatten\u_sdram_backend.$procmux$9522_Y, Q = \u_sdram_backend.w_pending_upper_half, rval = 1'0). +Adding EN signal on $auto$ff.cc:337:slice$24274 ($sdff) from module fpga_neural_v2_top (D = \u_sdram_backend.w_eff_addr [3], Q = \u_sdram_backend.w_pending_upper_half). +Adding SRST signal on $flatten\u_sdram_backend.$procdff$20167 ($dff) from module fpga_neural_v2_top (D = $flatten\u_sdram_backend.$procmux$9507_Y, Q = \u_sdram_backend.w_pending_addr, rval = 23'00000000000000000000000). +Adding EN signal on $auto$ff.cc:337:slice$24280 ($sdff) from module fpga_neural_v2_top (D = \u_sdram_backend.w_eff_addr, Q = \u_sdram_backend.w_pending_addr). +Adding SRST signal on $flatten\u_sdram_backend.$procdff$20168 ($dff) from module fpga_neural_v2_top (D = $flatten\u_sdram_backend.$procmux$9492_Y, Q = \u_sdram_backend.ar_pending_word, rval = 3'000). +Adding EN signal on $auto$ff.cc:337:slice$24286 ($sdff) from module fpga_neural_v2_top (D = \u_sdram_backend.ar_eff_addr [2:0], Q = \u_sdram_backend.ar_pending_word). +Adding SRST signal on $flatten\u_sdram_backend.$procdff$20169 ($dff) from module fpga_neural_v2_top (D = $flatten\u_sdram_backend.$procmux$9474_Y, Q = \u_sdram_backend.w_req_pending, rval = 1'0). +Adding SRST signal on $flatten\u_sdram_backend.$procdff$20170 ($dff) from module fpga_neural_v2_top (D = \u_sdram_backend.w_eff_addr, Q = \u_sdram_backend.w_req_addr_lat, rval = 23'00000000000000000000000). +Adding SRST signal on $flatten\u_sdram_backend.$procdff$20171 ($dff) from module fpga_neural_v2_top (D = $flatten\u_sdram_backend.$procmux$9452_Y, Q = \u_sdram_backend.ar_req_pending, rval = 1'0). +Adding SRST signal on $flatten\u_sdram_backend.$procdff$20172 ($dff) from module fpga_neural_v2_top (D = \u_sdram_backend.ar_eff_wr, Q = \u_sdram_backend.ar_req_wr_lat, rval = 1'0). +Adding SRST signal on $flatten\u_sdram_backend.$procdff$20173 ($dff) from module fpga_neural_v2_top (D = \u_sdram_backend.ar_eff_addr, Q = \u_sdram_backend.ar_req_addr_lat, rval = 23'00000000000000000000000). +Adding EN signal on $auto$ff.cc:337:slice$24298 ($sdff) from module fpga_neural_v2_top (D = \u_host_arb.m_addr [22], Q = \u_sdram_backend.ar_req_addr_lat [22]). +Adding SRST signal on $flatten\u_sdram_backend.$procdff$20174 ($dff) from module fpga_neural_v2_top (D = \u_sdram_backend.ar_eff_wdata, Q = \u_sdram_backend.ar_req_wdata_lat, rval = 16'0000000000000000). +Adding SRST signal on $flatten\u_sdram_backend.$procdff$20175 ($dff) from module fpga_neural_v2_top (D = \u_sdram_backend.ar_eff_lbn, Q = \u_sdram_backend.ar_req_lbn_lat, rval = 1'1). +Adding SRST signal on $flatten\u_sdram_backend.$procdff$20176 ($dff) from module fpga_neural_v2_top (D = \u_sdram_backend.ar_eff_ubn, Q = \u_sdram_backend.ar_req_ubn_lat, rval = 1'1). +Adding SRST signal on $flatten\u_dataflow_core.\u_act_fill.$procdff$20629 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[3].u_mm.n_tiles_reg, Q = \u_dataflow_core.u_act_fill.n_tiles_masked[3], rval = 16'0000000000000000). +Adding SRST signal on $flatten\u_dataflow_core.\u_act_fill.$procdff$20630 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[2].u_mm.n_tiles_reg, Q = \u_dataflow_core.u_act_fill.n_tiles_masked[2], rval = 16'0000000000000000). +Adding SRST signal on $flatten\u_dataflow_core.\u_act_fill.$procdff$20631 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[1].u_mm.n_tiles_reg, Q = \u_dataflow_core.u_act_fill.n_tiles_masked[1], rval = 16'0000000000000000). +Adding SRST signal on $flatten\u_dataflow_core.\u_act_fill.$procdff$20632 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[0].u_mm.n_tiles_reg, Q = \u_dataflow_core.u_act_fill.n_tiles_masked[0], rval = 16'0000000000000000). +Adding SRST signal on $flatten\u_dataflow_core.\u_act_fill.$procdff$20633 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\u_act_fill.$procmux$19388_Y, Q = \u_dataflow_core.u_act_fill.state, rval = 1'0). +Adding SRST signal on $flatten\u_dataflow_core.\u_act_fill.$procdff$20634 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\u_act_fill.$procmux$19381_Y, Q = \u_dataflow_core.u_act_fill.resident_tag, rval = 23'11111111111111111111111). +Adding EN signal on $auto$ff.cc:337:slice$24325 ($sdff) from module fpga_neural_v2_top (D = \u_dataflow_core.u_act_fill.desired_x_base, Q = \u_dataflow_core.u_act_fill.resident_tag). +Adding SRST signal on $flatten\u_dataflow_core.\u_act_fill.$procdff$20635 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\u_act_fill.$procmux$19374_Y, Q = \u_dataflow_core.u_act_fill.resident_count, rval = 5'00000). +Adding EN signal on $auto$ff.cc:337:slice$24327 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\u_act_fill.$add$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:181$4176_Y, Q = \u_dataflow_core.u_act_fill.resident_count). +Adding SRST signal on $flatten\u_dataflow_core.\u_act_fill.$procdff$20636 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\u_act_fill.$procmux$19349_Y, Q = \u_dataflow_core.u_act_fill.pf_start, rval = 1'0). +Adding EN signal on $flatten\u_dataflow_core.\u_act_fill.$procdff$20637 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\u_act_fill.$add$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:207$4192_Y, Q = \u_dataflow_core.u_act_fill.pf_addr). +Adding SRST signal on $flatten\u_dataflow_core.\u_act_fill.$procdff$20638 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\u_act_fill.$procmux$19343_Y, Q = \u_dataflow_core.u_act_fill.fill_we_reg, rval = 1'0). +Adding EN signal on $flatten\u_dataflow_core.\u_act_fill.$procdff$20639 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.u_act_fill.resident_count [3:0], Q = \u_dataflow_core.u_act_fill.fill_addr_reg). +Adding EN signal on $flatten\u_dataflow_core.\u_act_fill.$procdff$20640 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.u_act_fill.u_pf.tile_w, Q = \u_dataflow_core.u_act_fill.fill_data_reg). +Adding SRST signal on $flatten\u_dataflow_core.\u_act_fill.$procdff$20641 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.u_act_fill.max_n_tiles_comb, Q = \u_dataflow_core.u_act_fill.max_n_tiles_reg, rval = 16'0000000000000000). +Adding SRST signal on $flatten\u_dataflow_core.\u_act_fill.\u_pf.$procdff$20234 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\u_act_fill.\u_pf.$procmux$10395_Y, Q = \u_dataflow_core.u_act_fill.u_pf.word_idx, rval = 3'000). +Adding EN signal on $auto$ff.cc:337:slice$24353 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\u_act_fill.\u_pf.$procmux$10395_Y, Q = \u_dataflow_core.u_act_fill.u_pf.word_idx). +Adding SRST signal on $flatten\u_dataflow_core.\u_act_fill.\u_pf.$procdff$20232 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\u_act_fill.\u_pf.$procmux$10427_Y, Q = \u_dataflow_core.u_act_fill.u_pf.mem_ub_n, rval = 1'1). +Adding EN signal on $auto$ff.cc:337:slice$24365 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\u_act_fill.\u_pf.$procmux$10427_Y, Q = \u_dataflow_core.u_act_fill.u_pf.mem_ub_n). +Adding SRST signal on $flatten\u_dataflow_core.\u_act_fill.\u_pf.$procdff$20231 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\u_act_fill.\u_pf.$procmux$10443_Y, Q = \u_dataflow_core.u_act_fill.u_pf.mem_lb_n, rval = 1'1). +Adding EN signal on $auto$ff.cc:337:slice$24377 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\u_act_fill.\u_pf.$procmux$10443_Y, Q = \u_dataflow_core.u_act_fill.u_pf.mem_lb_n). +Adding EN signal on $flatten\u_dataflow_core.\u_act_fill.\u_pf.$procdff$20230 ($dff) from module fpga_neural_v2_top (D = 16'0000000000000000, Q = \u_dataflow_core.u_act_fill.u_pf.mem_wdata). +Adding SRST signal on $flatten\u_dataflow_core.\u_act_fill.\u_pf.$procdff$20229 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\u_act_fill.\u_pf.$procmux$10462_Y, Q = \u_dataflow_core.u_act_fill.u_pf.mem_addr, rval = 23'00000000000000000000000). +Adding EN signal on $auto$ff.cc:337:slice$24390 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\u_act_fill.\u_pf.$procmux$10462_Y, Q = \u_dataflow_core.u_act_fill.u_pf.mem_addr). +Adding SRST signal on $flatten\u_dataflow_core.\u_act_fill.\u_pf.$procdff$20228 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\u_act_fill.\u_pf.$procmux$10478_Y, Q = \u_dataflow_core.u_act_fill.u_pf.mem_wr, rval = 1'0). +Adding EN signal on $auto$ff.cc:337:slice$24402 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\u_act_fill.\u_pf.$procmux$10478_Y, Q = \u_dataflow_core.u_act_fill.u_pf.mem_wr). +Adding SRST signal on $flatten\u_dataflow_core.\u_act_fill.\u_pf.$procdff$20227 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\u_act_fill.\u_pf.$procmux$10367_Y, Q = \u_dataflow_core.u_act_fill.u_pf.mem_req, rval = 1'0). +Adding EN signal on $flatten\u_dataflow_core.\u_act_fill.\u_pf.$procdff$20226 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\u_act_fill.\u_pf.$or$hardware/v2/rtl/prefetch_engine.v:115$6856_Y, Q = \u_dataflow_core.u_act_fill.u_pf.tile_w). +Adding SRST signal on $flatten\u_dataflow_core.\u_act_fill.\u_pf.$procdff$20225 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\u_act_fill.\u_pf.$procmux$10376_Y, Q = \u_dataflow_core.u_act_fill.u_pf.fetch_done, rval = 1'0). +Adding SRST signal on $flatten\u_dataflow_core.\u_act_fill.\u_pf.$procdff$20224 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\u_act_fill.\u_pf.$procmux$10487_Y, Q = \u_dataflow_core.u_act_fill.u_pf.fetch_busy, rval = 1'0). +Adding EN signal on $auto$ff.cc:337:slice$24421 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\u_act_fill.\u_pf.$procmux$10487_Y, Q = \u_dataflow_core.u_act_fill.u_pf.fetch_busy). +Adding EN signal on $flatten\u_sdram_backend.\u_sdram_ctrl.$procdff$20221 ($dff) from module fpga_neural_v2_top (D = $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$9928_Y, Q = \u_sdram_backend.u_sdram_ctrl.dq_out). +Adding SRST signal on $flatten\u_sdram_backend.\u_sdram_ctrl.$procdff$20220 ($dff) from module fpga_neural_v2_top (D = $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$9807_Y, Q = \u_sdram_backend.u_sdram_ctrl.dq_out_en, rval = 1'0). +Adding SRST signal on $flatten\u_sdram_backend.\u_sdram_ctrl.$procdff$20219 ($dff) from module fpga_neural_v2_top (D = $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$9954_Y, Q = \u_sdram_backend.u_sdram_ctrl.req_pending, rval = 1'0). +Adding EN signal on $flatten\u_sdram_backend.\u_sdram_ctrl.$procdff$20218 ($dff) from module fpga_neural_v2_top (D = \u_sdram_backend.ctrl_wmask, Q = \u_sdram_backend.u_sdram_ctrl.wmask_reg). +Adding EN signal on $flatten\u_sdram_backend.\u_sdram_ctrl.$procdff$20217 ($dff) from module fpga_neural_v2_top (D = \u_sdram_backend.ctrl_wdata, Q = \u_sdram_backend.u_sdram_ctrl.wdata_reg). +Adding EN signal on $flatten\u_sdram_backend.\u_sdram_ctrl.$procdff$20216 ($dff) from module fpga_neural_v2_top (D = \u_sdram_backend.ctrl_addr [7:0], Q = \u_sdram_backend.u_sdram_ctrl.req_col_reg). +Adding EN signal on $flatten\u_sdram_backend.\u_sdram_ctrl.$procdff$20215 ($dff) from module fpga_neural_v2_top (D = \u_sdram_backend.u_sdram_ctrl.eff_row, Q = \u_sdram_backend.u_sdram_ctrl.req_row_reg). +Adding EN signal on $flatten\u_sdram_backend.\u_sdram_ctrl.$procdff$20214 ($dff) from module fpga_neural_v2_top (D = \u_sdram_backend.u_sdram_ctrl.eff_bank, Q = \u_sdram_backend.u_sdram_ctrl.req_bank_reg). +Adding EN signal on $flatten\u_sdram_backend.\u_sdram_ctrl.$procdff$20213 ($dff) from module fpga_neural_v2_top (D = \u_sdram_backend.ctrl_wr, Q = \u_sdram_backend.u_sdram_ctrl.req_wr_reg). +Adding EN signal on $flatten\u_sdram_backend.\u_sdram_ctrl.$procdff$20212 ($dff) from module fpga_neural_v2_top (D = $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10078_Y, Q = \u_sdram_backend.u_sdram_ctrl.burst_idx). +Adding SRST signal on $flatten\u_sdram_backend.\u_sdram_ctrl.$procdff$20211 ($dff) from module fpga_neural_v2_top (D = $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10107_Y, Q = \u_sdram_backend.u_sdram_ctrl.refresh_timer, rval = 14'00001111101000). +Adding SRST signal on $flatten\u_sdram_backend.\u_sdram_ctrl.$procdff$20210 ($dff) from module fpga_neural_v2_top (D = $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10127_Y, Q = \u_sdram_backend.u_sdram_ctrl.init_ref_cnt, rval = 4'0000). +Adding EN signal on $auto$ff.cc:337:slice$24482 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_sdram_backend.\u_sdram_ctrl.$add$hardware/v2/nms/rtl/sdram_controller.v:280$7433_Y, Q = \u_sdram_backend.u_sdram_ctrl.init_ref_cnt). +Adding SRST signal on $flatten\u_sdram_backend.\u_sdram_ctrl.$procdff$20209 ($dff) from module fpga_neural_v2_top (D = $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10136_Y, Q = \u_sdram_backend.u_sdram_ctrl.wait_cnt, rval = 14'11001000000000). +Adding EN signal on $auto$ff.cc:337:slice$24488 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10136_Y, Q = \u_sdram_backend.u_sdram_ctrl.wait_cnt). +Adding SRST signal on $flatten\u_sdram_backend.\u_sdram_ctrl.$procdff$20207 ($dff) from module fpga_neural_v2_top (D = $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$9793_Y, Q = \u_sdram_backend.u_sdram_ctrl.ready, rval = 1'0). +Adding EN signal on $flatten\u_sdram_backend.\u_sdram_ctrl.$procdff$20206 ($dff) from module fpga_neural_v2_top (D = $flatten\u_sdram_backend.\u_sdram_ctrl.$or$hardware/v2/nms/rtl/sdram_controller.v:410$7455_Y [127:16], Q = \u_sdram_backend.u_sdram_ctrl.rdata [127:16]). +Adding EN signal on $flatten\u_sdram_backend.\u_sdram_ctrl.$procdff$20206 ($dff) from module fpga_neural_v2_top (D = $flatten\u_sdram_backend.\u_sdram_ctrl.$2$lookahead\rdata$7416[127:0]$7425 [15:0], Q = \u_sdram_backend.u_sdram_ctrl.rdata [15:0]). +Adding SRST signal on $flatten\u_sdram_backend.\u_sdram_ctrl.$procdff$20205 ($dff) from module fpga_neural_v2_top (D = $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$9824_Y, Q = \u_sdram_backend.u_sdram_ctrl.sdram_dqm, rval = 2'00). +Adding SRST signal on $flatten\u_sdram_backend.\u_sdram_ctrl.$procdff$20204 ($dff) from module fpga_neural_v2_top (D = { $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10220_Y $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$9758_Y $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$9732_Y }, Q = \u_sdram_backend.u_sdram_ctrl.sdram_a, rval = 12'000000000000). +Adding EN signal on $auto$ff.cc:337:slice$24522 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$9758_Y, Q = \u_sdram_backend.u_sdram_ctrl.sdram_a [10]). +Adding EN signal on $auto$ff.cc:337:slice$24522 ($sdff) from module fpga_neural_v2_top (D = { $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10220_Y $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$9732_Y }, Q = { \u_sdram_backend.u_sdram_ctrl.sdram_a [11] \u_sdram_backend.u_sdram_ctrl.sdram_a [9:0] }). +Adding SRST signal on $flatten\u_sdram_backend.\u_sdram_ctrl.$procdff$20203 ($dff) from module fpga_neural_v2_top (D = $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10246_Y, Q = \u_sdram_backend.u_sdram_ctrl.sdram_ba, rval = 2'00). +Adding EN signal on $auto$ff.cc:337:slice$24553 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10246_Y, Q = \u_sdram_backend.u_sdram_ctrl.sdram_ba). +Adding SRST signal on $flatten\u_sdram_backend.\u_sdram_ctrl.$procdff$20202 ($dff) from module fpga_neural_v2_top (D = $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$9844_Y, Q = \u_sdram_backend.u_sdram_ctrl.sdram_we_n, rval = 1'1). +Adding SRST signal on $flatten\u_sdram_backend.\u_sdram_ctrl.$procdff$20201 ($dff) from module fpga_neural_v2_top (D = $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$9868_Y, Q = \u_sdram_backend.u_sdram_ctrl.sdram_cas_n, rval = 1'1). +Adding SRST signal on $flatten\u_sdram_backend.\u_sdram_ctrl.$procdff$20200 ($dff) from module fpga_neural_v2_top (D = $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$9897_Y, Q = \u_sdram_backend.u_sdram_ctrl.sdram_ras_n, rval = 1'1). +Adding EN signal on $flatten\u_sdram_backend.\u_sdram_ctrl.$procdff$20198 ($dff) from module fpga_neural_v2_top (D = 1'1, Q = \u_sdram_backend.u_sdram_ctrl.sdram_cke). +Adding SRST signal on $flatten\u_dataflow_core.\u_director.$procdff$20574 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\u_director.$or$hardware/v2/rtl/neural_director.v:206$4386_Y, Q = \u_dataflow_core.u_director.slot_job_start, rval = 4'0000). +Adding SRST signal on $flatten\u_dataflow_core.\u_director.$procdff$20575 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\u_director.$2$lookahead\slot_x_base$4277[91:0]$4372, Q = \u_dataflow_core.u_director.slot_x_base, rval = 92'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:337:slice$24578 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\u_director.$or$hardware/v2/rtl/neural_director.v:207$4396_Y, Q = \u_dataflow_core.u_director.slot_x_base). +Adding SRST signal on $flatten\u_dataflow_core.\u_director.$procdff$20576 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\u_director.$2$lookahead\slot_w_base$4278[91:0]$4373, Q = \u_dataflow_core.u_director.slot_w_base, rval = 92'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:337:slice$24580 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\u_director.$or$hardware/v2/rtl/neural_director.v:208$4406_Y, Q = \u_dataflow_core.u_director.slot_w_base). +Adding SRST signal on $flatten\u_dataflow_core.\u_director.$procdff$20577 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\u_director.$2$lookahead\slot_n_tiles$4279[63:0]$4374, Q = \u_dataflow_core.u_director.slot_n_tiles, rval = 64'0000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:337:slice$24582 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\u_director.$or$hardware/v2/rtl/neural_director.v:209$4416_Y, Q = \u_dataflow_core.u_director.slot_n_tiles). +Adding SRST signal on $flatten\u_dataflow_core.\u_director.$procdff$20578 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\u_director.$2$lookahead\slot_result_addr$4280[91:0]$4375, Q = \u_dataflow_core.u_director.slot_result_addr, rval = 92'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:337:slice$24584 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\u_director.$or$hardware/v2/rtl/neural_director.v:210$4426_Y, Q = \u_dataflow_core.u_director.slot_result_addr). +Adding SRST signal on $flatten\u_dataflow_core.\u_director.$procdff$20579 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\u_director.$2$lookahead\slot_node_id$4281[63:0]$4376, Q = \u_dataflow_core.u_director.slot_node_id, rval = 64'0000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:337:slice$24586 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\u_director.$or$hardware/v2/rtl/neural_director.v:211$4436_Y, Q = \u_dataflow_core.u_director.slot_node_id). +Adding SRST signal on $flatten\u_dataflow_core.\u_director.$procdff$20580 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\u_director.$procmux$19140_Y, Q = \u_dataflow_core.u_director.job_out_done, rval = 1'0). +Adding SRST signal on $flatten\u_dataflow_core.\u_director.$procdff$20581 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\u_director.$procmux$19266_Y, Q = \u_dataflow_core.u_director.job_out_slot, rval = 2'00). +Adding EN signal on $auto$ff.cc:337:slice$24589 ($sdff) from module fpga_neural_v2_top (D = \u_dataflow_core.u_director.done_slot_idx, Q = \u_dataflow_core.u_director.job_out_slot). +Adding SRST signal on $flatten\u_dataflow_core.\u_director.$procdff$20584 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\u_director.$procmux$19247_Y, Q = \u_dataflow_core.u_director.q_head, rval = 3'000). +Adding EN signal on $auto$ff.cc:337:slice$24591 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\u_director.$ternary$hardware/v2/rtl/neural_director.v:213$4446_Y, Q = \u_dataflow_core.u_director.q_head). +Adding SRST signal on $flatten\u_dataflow_core.\u_director.$procdff$20585 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\u_director.$procmux$19240_Y, Q = \u_dataflow_core.u_director.q_tail, rval = 3'000). +Adding EN signal on $auto$ff.cc:337:slice$24593 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\u_director.$ternary$hardware/v2/rtl/neural_director.v:168$4360_Y, Q = \u_dataflow_core.u_director.q_tail). +Adding SRST signal on $flatten\u_dataflow_core.\u_director.$procdff$20586 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\u_director.$procmux$19167_Y, Q = \u_dataflow_core.u_director.q_count, rval = 4'0000). +Adding EN signal on $auto$ff.cc:337:slice$24595 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\u_director.$procmux$19167_Y, Q = \u_dataflow_core.u_director.q_count). +Adding SRST signal on $flatten\u_dataflow_core.\u_director.$procdff$20587 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\u_director.$2$lookahead\slot_busy$4282[3:0]$4377, Q = \u_dataflow_core.u_director.slot_busy, rval = 4'0000). +Adding SRST signal on $flatten\u_dataflow_core.$procdff$20539 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.$procmux$18160_Y, Q = \u_dataflow_core.GEN_SLOT[0].job_valid_np, rval = 1'0). +Adding EN signal on $auto$ff.cc:337:slice$24600 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.$procmux$18160_Y, Q = \u_dataflow_core.GEN_SLOT[0].job_valid_np). +Adding SRST signal on $flatten\u_dataflow_core.$procdff$20538 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.$procmux$18152_Y, Q = \u_dataflow_core.GEN_SLOT[1].job_valid_np, rval = 1'0). +Adding EN signal on $auto$ff.cc:337:slice$24604 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.$procmux$18152_Y, Q = \u_dataflow_core.GEN_SLOT[1].job_valid_np). +Adding SRST signal on $flatten\u_dataflow_core.$procdff$20537 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.$procmux$18144_Y, Q = \u_dataflow_core.GEN_SLOT[2].job_valid_np, rval = 1'0). +Adding EN signal on $auto$ff.cc:337:slice$24608 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.$procmux$18144_Y, Q = \u_dataflow_core.GEN_SLOT[2].job_valid_np). +Adding SRST signal on $flatten\u_dataflow_core.$procdff$20536 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.$procmux$18136_Y, Q = \u_dataflow_core.GEN_SLOT[3].job_valid_np, rval = 1'0). +Adding EN signal on $auto$ff.cc:337:slice$24612 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.$procmux$18136_Y, Q = \u_dataflow_core.GEN_SLOT[3].job_valid_np). +Adding SRST signal on $flatten\u_arbiter_wide.$procdff$20137 ($dff) from module fpga_neural_v2_top (D = { $flatten\u_arbiter_wide.$procmux$8451_Y $flatten\u_arbiter_wide.$procmux$8462_Y $flatten\u_arbiter_wide.$procmux$8484_Y $flatten\u_arbiter_wide.$procmux$8506_Y }, Q = \u_arbiter_wide.s_ready, rval = 4'0000). +Adding SRST signal on $flatten\u_arbiter.$procdff$20114 ($dff) from module fpga_neural_v2_top (D = { $flatten\u_arbiter.$procmux$7978_Y $flatten\u_arbiter.$procmux$7924_Y $flatten\u_arbiter.$procmux$7960_Y $flatten\u_arbiter.$procmux$7996_Y $flatten\u_arbiter.$procmux$8032_Y }, Q = \u_arbiter.pending_ub_n, rval = 5'11111). +Adding EN signal on $auto$ff.cc:337:slice$24621 ($sdff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[3].u_mm.wr_mem_ub_n, Q = \u_arbiter.pending_ub_n [3]). +Adding EN signal on $auto$ff.cc:337:slice$24621 ($sdff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[2].u_mm.wr_mem_ub_n, Q = \u_arbiter.pending_ub_n [2]). +Adding EN signal on $auto$ff.cc:337:slice$24621 ($sdff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[1].u_mm.wr_mem_ub_n, Q = \u_arbiter.pending_ub_n [1]). +Adding EN signal on $auto$ff.cc:337:slice$24621 ($sdff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[0].u_mm.wr_mem_ub_n, Q = \u_arbiter.pending_ub_n [0]). +Adding EN signal on $auto$ff.cc:337:slice$24621 ($sdff) from module fpga_neural_v2_top (D = \u_dataflow_core.u_act_fill.u_pf.mem_ub_n, Q = \u_arbiter.pending_ub_n [4]). +Adding SRST signal on $flatten\u_arbiter.$procdff$20113 ($dff) from module fpga_neural_v2_top (D = { $flatten\u_arbiter.$procmux$8014_Y $flatten\u_arbiter.$procmux$7930_Y $flatten\u_arbiter.$procmux$7966_Y $flatten\u_arbiter.$procmux$8002_Y $flatten\u_arbiter.$procmux$8038_Y }, Q = \u_arbiter.pending_lb_n, rval = 5'11111). +Adding EN signal on $auto$ff.cc:337:slice$24627 ($sdff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[3].u_mm.wr_mem_lb_n, Q = \u_arbiter.pending_lb_n [3]). +Adding EN signal on $auto$ff.cc:337:slice$24627 ($sdff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[2].u_mm.wr_mem_lb_n, Q = \u_arbiter.pending_lb_n [2]). +Adding EN signal on $auto$ff.cc:337:slice$24627 ($sdff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[1].u_mm.wr_mem_lb_n, Q = \u_arbiter.pending_lb_n [1]). +Adding EN signal on $auto$ff.cc:337:slice$24627 ($sdff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[0].u_mm.wr_mem_lb_n, Q = \u_arbiter.pending_lb_n [0]). +Adding EN signal on $auto$ff.cc:337:slice$24627 ($sdff) from module fpga_neural_v2_top (D = \u_dataflow_core.u_act_fill.u_pf.mem_lb_n, Q = \u_arbiter.pending_lb_n [4]). +Adding SRST signal on $flatten\u_arbiter.$procdff$20112 ($dff) from module fpga_neural_v2_top (D = { $flatten\u_arbiter.$procmux$8097_Y $flatten\u_arbiter.$procmux$7936_Y $flatten\u_arbiter.$procmux$7972_Y $flatten\u_arbiter.$procmux$8008_Y $flatten\u_arbiter.$procmux$8044_Y }, Q = \u_arbiter.pending_wr, rval = 5'00000). +Adding EN signal on $auto$ff.cc:337:slice$24633 ($sdff) from module fpga_neural_v2_top (D = 1'1, Q = \u_arbiter.pending_wr [3]). +Adding EN signal on $auto$ff.cc:337:slice$24633 ($sdff) from module fpga_neural_v2_top (D = 1'1, Q = \u_arbiter.pending_wr [2]). +Adding EN signal on $auto$ff.cc:337:slice$24633 ($sdff) from module fpga_neural_v2_top (D = 1'1, Q = \u_arbiter.pending_wr [1]). +Adding EN signal on $auto$ff.cc:337:slice$24633 ($sdff) from module fpga_neural_v2_top (D = 1'1, Q = \u_arbiter.pending_wr [0]). +Adding EN signal on $auto$ff.cc:337:slice$24633 ($sdff) from module fpga_neural_v2_top (D = \u_dataflow_core.u_act_fill.u_pf.mem_wr, Q = \u_arbiter.pending_wr [4]). +Adding SRST signal on $flatten\u_arbiter.$procdff$20111 ($dff) from module fpga_neural_v2_top (D = { $flatten\u_arbiter.$procmux$7906_Y $flatten\u_arbiter.$procmux$7912_Y $flatten\u_arbiter.$procmux$7948_Y $flatten\u_arbiter.$procmux$7984_Y $flatten\u_arbiter.$procmux$8020_Y }, Q = \u_arbiter.pending_wdata, rval = 80'00000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:337:slice$24639 ($sdff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[3].u_mm.wr_mem_wdata, Q = \u_arbiter.pending_wdata [63:48]). +Adding EN signal on $auto$ff.cc:337:slice$24639 ($sdff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[2].u_mm.wr_mem_wdata, Q = \u_arbiter.pending_wdata [47:32]). +Adding EN signal on $auto$ff.cc:337:slice$24639 ($sdff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[1].u_mm.wr_mem_wdata, Q = \u_arbiter.pending_wdata [31:16]). +Adding EN signal on $auto$ff.cc:337:slice$24639 ($sdff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[0].u_mm.wr_mem_wdata, Q = \u_arbiter.pending_wdata [15:0]). +Adding EN signal on $auto$ff.cc:337:slice$24639 ($sdff) from module fpga_neural_v2_top (D = \u_dataflow_core.u_act_fill.u_pf.mem_wdata, Q = \u_arbiter.pending_wdata [79:64]). +Adding SRST signal on $flatten\u_arbiter.$procdff$20110 ($dff) from module fpga_neural_v2_top (D = { $flatten\u_arbiter.$procmux$7942_Y $flatten\u_arbiter.$procmux$7918_Y $flatten\u_arbiter.$procmux$7954_Y $flatten\u_arbiter.$procmux$7990_Y $flatten\u_arbiter.$procmux$8026_Y }, Q = \u_arbiter.pending_addr, rval = 115'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:337:slice$24645 ($sdff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[3].u_mm.wr_mem_addr, Q = \u_arbiter.pending_addr [91:69]). +Adding EN signal on $auto$ff.cc:337:slice$24645 ($sdff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[2].u_mm.wr_mem_addr, Q = \u_arbiter.pending_addr [68:46]). +Adding EN signal on $auto$ff.cc:337:slice$24645 ($sdff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[1].u_mm.wr_mem_addr, Q = \u_arbiter.pending_addr [45:23]). +Adding EN signal on $auto$ff.cc:337:slice$24645 ($sdff) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[0].u_mm.wr_mem_addr, Q = \u_arbiter.pending_addr [22:0]). +Adding EN signal on $auto$ff.cc:337:slice$24645 ($sdff) from module fpga_neural_v2_top (D = \u_dataflow_core.u_act_fill.u_pf.mem_addr, Q = \u_arbiter.pending_addr [114:92]). +Adding SRST signal on $flatten\u_arbiter.$procdff$20109 ($dff) from module fpga_neural_v2_top (D = $flatten\u_arbiter.$7$lookahead\pending$7146[4:0]$7159, Q = \u_arbiter.pending, rval = 5'00000). +Adding SRST signal on $flatten\u_arbiter.$procdff$20108 ($dff) from module fpga_neural_v2_top (D = $flatten\u_arbiter.$procmux$8115_Y, Q = \u_arbiter.owner, rval = 3'000). +Adding EN signal on $auto$ff.cc:337:slice$24652 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_arbiter.$procmux$8115_Y, Q = \u_arbiter.owner). +Adding SRST signal on $flatten\u_arbiter.$procdff$20107 ($dff) from module fpga_neural_v2_top (D = $flatten\u_arbiter.$procmux$8124_Y, Q = \u_arbiter.m_ub_n, rval = 1'1). +Adding EN signal on $auto$ff.cc:337:slice$24660 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_arbiter.$shiftx$hardware/v2/rtl/slot_mem_arbiter.v:161$7165_Y, Q = \u_arbiter.m_ub_n). +Adding SRST signal on $flatten\u_arbiter.$procdff$20106 ($dff) from module fpga_neural_v2_top (D = $flatten\u_arbiter.$procmux$8133_Y, Q = \u_arbiter.m_lb_n, rval = 1'1). +Adding EN signal on $auto$ff.cc:337:slice$24664 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_arbiter.$shiftx$hardware/v2/rtl/slot_mem_arbiter.v:160$7164_Y, Q = \u_arbiter.m_lb_n). +Adding SRST signal on $flatten\u_arbiter.$procdff$20105 ($dff) from module fpga_neural_v2_top (D = $flatten\u_arbiter.$procmux$8142_Y, Q = \u_arbiter.m_wdata, rval = 16'0000000000000000). +Adding EN signal on $auto$ff.cc:337:slice$24668 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_arbiter.$shiftx$hardware/v2/rtl/slot_mem_arbiter.v:163$7171_Y, Q = \u_arbiter.m_wdata). +Adding SRST signal on $flatten\u_arbiter.$procdff$20104 ($dff) from module fpga_neural_v2_top (D = $flatten\u_arbiter.$procmux$8151_Y, Q = \u_arbiter.m_addr, rval = 23'00000000000000000000000). +Adding EN signal on $auto$ff.cc:337:slice$24672 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_arbiter.$shiftx$hardware/v2/rtl/slot_mem_arbiter.v:162$7168_Y, Q = \u_arbiter.m_addr). +Adding SRST signal on $flatten\u_arbiter.$procdff$20103 ($dff) from module fpga_neural_v2_top (D = $flatten\u_arbiter.$procmux$8160_Y, Q = \u_arbiter.m_wr, rval = 1'0). +Adding EN signal on $auto$ff.cc:337:slice$24676 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_arbiter.$shiftx$hardware/v2/rtl/slot_mem_arbiter.v:159$7163_Y, Q = \u_arbiter.m_wr). +Adding SRST signal on $flatten\u_arbiter.$procdff$20102 ($dff) from module fpga_neural_v2_top (D = $flatten\u_arbiter.$procmux$8062_Y, Q = \u_arbiter.m_req, rval = 1'0). +Adding SRST signal on $flatten\u_arbiter.$procdff$20101 ($dff) from module fpga_neural_v2_top (D = { $flatten\u_arbiter.$procmux$7765_Y $flatten\u_arbiter.$procmux$7776_Y $flatten\u_arbiter.$procmux$7798_Y $flatten\u_arbiter.$procmux$7820_Y $flatten\u_arbiter.$procmux$7842_Y }, Q = \u_arbiter.s_ready, rval = 5'00000). +Adding SRST signal on $flatten\u_arbiter.$procdff$20100 ($dff) from module fpga_neural_v2_top (D = { $flatten\u_arbiter.$procmux$8055_Y $flatten\u_arbiter.$procmux$7792_Y $flatten\u_arbiter.$procmux$7814_Y $flatten\u_arbiter.$procmux$7836_Y $flatten\u_arbiter.$procmux$7858_Y }, Q = \u_arbiter.s_rdata, rval = 80'00000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:337:slice$24690 ($sdff) from module fpga_neural_v2_top (D = \u_host_arb.s_rdata [15:0], Q = \u_arbiter.s_rdata [79:64]). +Adding EN signal on $auto$ff.cc:337:slice$24690 ($sdff) from module fpga_neural_v2_top (D = \u_host_arb.s_rdata [15:0], Q = \u_arbiter.s_rdata [63:48]). +Adding EN signal on $auto$ff.cc:337:slice$24690 ($sdff) from module fpga_neural_v2_top (D = \u_host_arb.s_rdata [15:0], Q = \u_arbiter.s_rdata [47:32]). +Adding EN signal on $auto$ff.cc:337:slice$24690 ($sdff) from module fpga_neural_v2_top (D = \u_host_arb.s_rdata [15:0], Q = \u_arbiter.s_rdata [31:16]). +Adding EN signal on $auto$ff.cc:337:slice$24690 ($sdff) from module fpga_neural_v2_top (D = \u_host_arb.s_rdata [15:0], Q = \u_arbiter.s_rdata [15:0]). +Adding SRST signal on $flatten\u_arbiter_wide.$procdff$20136 ($dff) from module fpga_neural_v2_top (D = { $flatten\u_arbiter_wide.$procmux$8683_Y $flatten\u_arbiter_wide.$procmux$8478_Y $flatten\u_arbiter_wide.$procmux$8500_Y $flatten\u_arbiter_wide.$procmux$8522_Y }, Q = \u_arbiter_wide.s_rdata, rval = 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:337:slice$24716 ($sdff) from module fpga_neural_v2_top (D = \u_sdram_backend.w_rdata, Q = \u_arbiter_wide.s_rdata [255:192]). +Adding EN signal on $auto$ff.cc:337:slice$24716 ($sdff) from module fpga_neural_v2_top (D = \u_sdram_backend.w_rdata, Q = \u_arbiter_wide.s_rdata [191:128]). +Adding EN signal on $auto$ff.cc:337:slice$24716 ($sdff) from module fpga_neural_v2_top (D = \u_sdram_backend.w_rdata, Q = \u_arbiter_wide.s_rdata [127:64]). +Adding EN signal on $auto$ff.cc:337:slice$24716 ($sdff) from module fpga_neural_v2_top (D = \u_sdram_backend.w_rdata, Q = \u_arbiter_wide.s_rdata [63:0]). +Adding SRST signal on $flatten\u_dataflow_core.\u_dep_mgr.$procdff$20249 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\u_dep_mgr.$procmux$18029_Y, Q = \u_dataflow_core.u_dep_mgr.ready_valid, rval = 1'0). +Adding EN signal on $auto$ff.cc:337:slice$24737 ($sdff) from module fpga_neural_v2_top (D = 1'1, Q = \u_dataflow_core.u_dep_mgr.ready_valid). +Adding EN signal on $flatten\u_dataflow_core.\u_dep_mgr.$procdff$20250 ($dff) from module fpga_neural_v2_top (D = \u_dataflow_core.u_dep_mgr.first_ready_idx, Q = \u_dataflow_core.u_dep_mgr.ready_node_id). +Adding EN signal on $flatten\u_dataflow_core.\u_dep_mgr.$procdff$20251 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_x_base$hardware/v2/rtl/dependency_manager.v:184$6650_DATA, Q = \u_dataflow_core.u_dep_mgr.ready_x_base). +Adding EN signal on $flatten\u_dataflow_core.\u_dep_mgr.$procdff$20252 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_w_base$hardware/v2/rtl/dependency_manager.v:185$6651_DATA, Q = \u_dataflow_core.u_dep_mgr.ready_w_base). +Adding EN signal on $flatten\u_dataflow_core.\u_dep_mgr.$procdff$20253 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_n_tiles$hardware/v2/rtl/dependency_manager.v:186$6652_DATA, Q = \u_dataflow_core.u_dep_mgr.ready_n_tiles). +Adding EN signal on $flatten\u_dataflow_core.\u_dep_mgr.$procdff$20254 ($dff) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_result_addr$hardware/v2/rtl/dependency_manager.v:187$6653_DATA, Q = \u_dataflow_core.u_dep_mgr.ready_result_addr). +Adding SRST signal on $flatten\u_host_arb.$procdff$20132 ($dff) from module fpga_neural_v2_top (D = { $flatten\u_host_arb.$procmux$8368_Y $flatten\u_host_arb.$procmux$8297_Y }, Q = \u_host_arb.pending_ub_n, rval = 2'11). +Adding EN signal on $auto$ff.cc:337:slice$24776 ($sdff) from module fpga_neural_v2_top (D = \u_spi_bridge.mem_ub_n, Q = \u_host_arb.pending_ub_n [1]). +Adding EN signal on $auto$ff.cc:337:slice$24776 ($sdff) from module fpga_neural_v2_top (D = \u_arbiter.m_ub_n, Q = \u_host_arb.pending_ub_n [0]). +Adding SRST signal on $flatten\u_host_arb.$procdff$20131 ($dff) from module fpga_neural_v2_top (D = { $flatten\u_host_arb.$procmux$8344_Y $flatten\u_host_arb.$procmux$8303_Y }, Q = \u_host_arb.pending_lb_n, rval = 2'11). +Adding EN signal on $auto$ff.cc:337:slice$24779 ($sdff) from module fpga_neural_v2_top (D = \u_spi_bridge.mem_lb_n, Q = \u_host_arb.pending_lb_n [1]). +Adding EN signal on $auto$ff.cc:337:slice$24779 ($sdff) from module fpga_neural_v2_top (D = \u_arbiter.m_lb_n, Q = \u_host_arb.pending_lb_n [0]). +Adding SRST signal on $flatten\u_host_arb.$procdff$20130 ($dff) from module fpga_neural_v2_top (D = { $flatten\u_host_arb.$procmux$8350_Y $flatten\u_host_arb.$procmux$8309_Y }, Q = \u_host_arb.pending_wr, rval = 2'00). +Adding EN signal on $auto$ff.cc:337:slice$24782 ($sdff) from module fpga_neural_v2_top (D = \u_spi_bridge.mem_wr, Q = \u_host_arb.pending_wr [1]). +Adding EN signal on $auto$ff.cc:337:slice$24782 ($sdff) from module fpga_neural_v2_top (D = \u_arbiter.m_wr, Q = \u_host_arb.pending_wr [0]). +Adding SRST signal on $flatten\u_host_arb.$procdff$20129 ($dff) from module fpga_neural_v2_top (D = { $flatten\u_host_arb.$procmux$8279_Y $flatten\u_host_arb.$procmux$8285_Y }, Q = \u_host_arb.pending_wdata, rval = 0). +Adding EN signal on $auto$ff.cc:337:slice$24785 ($sdff) from module fpga_neural_v2_top (D = \u_spi_bridge.mem_wdata, Q = \u_host_arb.pending_wdata [31:16]). +Adding EN signal on $auto$ff.cc:337:slice$24785 ($sdff) from module fpga_neural_v2_top (D = \u_arbiter.m_wdata, Q = \u_host_arb.pending_wdata [15:0]). +Adding SRST signal on $flatten\u_host_arb.$procdff$20128 ($dff) from module fpga_neural_v2_top (D = { $flatten\u_host_arb.$procmux$8362_Y $flatten\u_host_arb.$procmux$8291_Y }, Q = \u_host_arb.pending_addr, rval = 46'0000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:337:slice$24788 ($sdff) from module fpga_neural_v2_top (D = \u_spi_bridge.mem_addr, Q = \u_host_arb.pending_addr [45:23]). +Adding EN signal on $auto$ff.cc:337:slice$24788 ($sdff) from module fpga_neural_v2_top (D = \u_arbiter.m_addr, Q = \u_host_arb.pending_addr [22:0]). +Adding SRST signal on $flatten\u_host_arb.$procdff$20127 ($dff) from module fpga_neural_v2_top (D = $flatten\u_host_arb.$4$lookahead\pending$7112[1:0]$7122, Q = \u_host_arb.pending, rval = 2'00). +Adding SRST signal on $flatten\u_host_arb.$procdff$20126 ($dff) from module fpga_neural_v2_top (D = $flatten\u_host_arb.$procmux$8380_Y, Q = \u_host_arb.owner, rval = 2'00). +Adding EN signal on $auto$ff.cc:337:slice$24792 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_host_arb.$procmux$8380_Y, Q = \u_host_arb.owner). +Adding SRST signal on $flatten\u_host_arb.$procdff$20125 ($dff) from module fpga_neural_v2_top (D = $flatten\u_host_arb.$procmux$8389_Y, Q = \u_host_arb.m_ub_n, rval = 1'1). +Adding EN signal on $auto$ff.cc:337:slice$24800 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_host_arb.$shiftx$hardware/v2/rtl/slot_mem_arbiter.v:161$7128_Y, Q = \u_host_arb.m_ub_n). +Adding SRST signal on $flatten\u_host_arb.$procdff$20124 ($dff) from module fpga_neural_v2_top (D = $flatten\u_host_arb.$procmux$8398_Y, Q = \u_host_arb.m_lb_n, rval = 1'1). +Adding EN signal on $auto$ff.cc:337:slice$24804 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_host_arb.$shiftx$hardware/v2/rtl/slot_mem_arbiter.v:160$7127_Y, Q = \u_host_arb.m_lb_n). +Adding SRST signal on $flatten\u_host_arb.$procdff$20123 ($dff) from module fpga_neural_v2_top (D = $flatten\u_host_arb.$procmux$8407_Y, Q = \u_host_arb.m_wdata, rval = 16'0000000000000000). +Adding EN signal on $auto$ff.cc:337:slice$24808 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_host_arb.$shiftx$hardware/v2/rtl/slot_mem_arbiter.v:163$7134_Y, Q = \u_host_arb.m_wdata). +Adding SRST signal on $flatten\u_host_arb.$procdff$20122 ($dff) from module fpga_neural_v2_top (D = $flatten\u_host_arb.$procmux$8416_Y, Q = \u_host_arb.m_addr, rval = 23'00000000000000000000000). +Adding EN signal on $auto$ff.cc:337:slice$24812 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_host_arb.$shiftx$hardware/v2/rtl/slot_mem_arbiter.v:162$7131_Y, Q = \u_host_arb.m_addr). +Adding SRST signal on $flatten\u_host_arb.$procdff$20121 ($dff) from module fpga_neural_v2_top (D = $flatten\u_host_arb.$procmux$8425_Y, Q = \u_host_arb.m_wr, rval = 1'0). +Adding EN signal on $auto$ff.cc:337:slice$24816 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_host_arb.$shiftx$hardware/v2/rtl/slot_mem_arbiter.v:159$7126_Y, Q = \u_host_arb.m_wr). +Adding SRST signal on $flatten\u_host_arb.$procdff$20120 ($dff) from module fpga_neural_v2_top (D = $flatten\u_host_arb.$procmux$8327_Y, Q = \u_host_arb.m_req, rval = 1'0). +Adding SRST signal on $flatten\u_host_arb.$procdff$20119 ($dff) from module fpga_neural_v2_top (D = { $flatten\u_host_arb.$procmux$8204_Y $flatten\u_host_arb.$procmux$8215_Y }, Q = \u_host_arb.s_ready, rval = 2'00). +Adding SRST signal on $flatten\u_host_arb.$procdff$20118 ($dff) from module fpga_neural_v2_top (D = { $flatten\u_host_arb.$procmux$8320_Y $flatten\u_host_arb.$procmux$8231_Y }, Q = \u_host_arb.s_rdata, rval = 0). +Adding EN signal on $auto$ff.cc:337:slice$24830 ($sdff) from module fpga_neural_v2_top (D = \u_sdram_backend.ar_rdata, Q = \u_host_arb.s_rdata [31:16]). +Adding EN signal on $auto$ff.cc:337:slice$24830 ($sdff) from module fpga_neural_v2_top (D = \u_sdram_backend.ar_rdata, Q = \u_host_arb.s_rdata [15:0]). +Setting constant 1-bit at position 0 on $auto$ff.cc:337:slice$24572 ($dffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$24389 ($dffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 1 on $auto$ff.cc:337:slice$24389 ($dffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 2 on $auto$ff.cc:337:slice$24389 ($dffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 3 on $auto$ff.cc:337:slice$24389 ($dffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 4 on $auto$ff.cc:337:slice$24389 ($dffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 5 on $auto$ff.cc:337:slice$24389 ($dffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 6 on $auto$ff.cc:337:slice$24389 ($dffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 7 on $auto$ff.cc:337:slice$24389 ($dffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 8 on $auto$ff.cc:337:slice$24389 ($dffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 9 on $auto$ff.cc:337:slice$24389 ($dffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 10 on $auto$ff.cc:337:slice$24389 ($dffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 11 on $auto$ff.cc:337:slice$24389 ($dffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 12 on $auto$ff.cc:337:slice$24389 ($dffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 13 on $auto$ff.cc:337:slice$24389 ($dffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 14 on $auto$ff.cc:337:slice$24389 ($dffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 15 on $auto$ff.cc:337:slice$24389 ($dffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 22 on $auto$ff.cc:337:slice$24084 ($dffe) from module fpga_neural_v2_top. +Setting constant 1-bit at position 0 on $auto$ff.cc:337:slice$23900 ($sdffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 1 on $auto$ff.cc:337:slice$23900 ($sdffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$23896 ($sdffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 1 on $auto$ff.cc:337:slice$23896 ($sdffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 2 on $auto$ff.cc:337:slice$23896 ($sdffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 3 on $auto$ff.cc:337:slice$23896 ($sdffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 4 on $auto$ff.cc:337:slice$23896 ($sdffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 5 on $auto$ff.cc:337:slice$23896 ($sdffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 6 on $auto$ff.cc:337:slice$23896 ($sdffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 7 on $auto$ff.cc:337:slice$23896 ($sdffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 22 on $auto$ff.cc:337:slice$23748 ($dffe) from module fpga_neural_v2_top. +Setting constant 1-bit at position 0 on $auto$ff.cc:337:slice$23555 ($sdffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 1 on $auto$ff.cc:337:slice$23555 ($sdffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$23551 ($sdffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 1 on $auto$ff.cc:337:slice$23551 ($sdffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 2 on $auto$ff.cc:337:slice$23551 ($sdffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 3 on $auto$ff.cc:337:slice$23551 ($sdffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 4 on $auto$ff.cc:337:slice$23551 ($sdffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 5 on $auto$ff.cc:337:slice$23551 ($sdffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 6 on $auto$ff.cc:337:slice$23551 ($sdffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 7 on $auto$ff.cc:337:slice$23551 ($sdffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 22 on $auto$ff.cc:337:slice$23389 ($dffe) from module fpga_neural_v2_top. +Setting constant 1-bit at position 0 on $auto$ff.cc:337:slice$23205 ($sdffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 1 on $auto$ff.cc:337:slice$23205 ($sdffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$23201 ($sdffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 1 on $auto$ff.cc:337:slice$23201 ($sdffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 2 on $auto$ff.cc:337:slice$23201 ($sdffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 3 on $auto$ff.cc:337:slice$23201 ($sdffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 4 on $auto$ff.cc:337:slice$23201 ($sdffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 5 on $auto$ff.cc:337:slice$23201 ($sdffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 6 on $auto$ff.cc:337:slice$23201 ($sdffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 7 on $auto$ff.cc:337:slice$23201 ($sdffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 22 on $auto$ff.cc:337:slice$23053 ($dffe) from module fpga_neural_v2_top. +Setting constant 1-bit at position 0 on $auto$ff.cc:337:slice$22869 ($sdffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 1 on $auto$ff.cc:337:slice$22869 ($sdffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$22865 ($sdffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 1 on $auto$ff.cc:337:slice$22865 ($sdffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 2 on $auto$ff.cc:337:slice$22865 ($sdffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 3 on $auto$ff.cc:337:slice$22865 ($sdffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 4 on $auto$ff.cc:337:slice$22865 ($sdffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 5 on $auto$ff.cc:337:slice$22865 ($sdffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 6 on $auto$ff.cc:337:slice$22865 ($sdffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 7 on $auto$ff.cc:337:slice$22865 ($sdffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$22741 ($sdffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$22735 ($sdffe) from module fpga_neural_v2_top. + +19.14.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \fpga_neural_v2_top.. +Removed 1135 unused cells and 1320 unused wires. + + +19.14.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module fpga_neural_v2_top. + + +19.14.9. Rerunning OPT passes. (Maybe there is more to do..) + +19.14.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \fpga_neural_v2_top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. + dead port 1/2 on $mux $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$ternary$hardware/v2/rtl/neural_processor.v:263$3699. + dead port 2/2 on $mux $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$ternary$hardware/v2/rtl/neural_processor.v:263$3699. + dead port 1/2 on $mux $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$ternary$hardware/v2/rtl/neural_processor.v:264$3698. + dead port 2/2 on $mux $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$ternary$hardware/v2/rtl/neural_processor.v:264$3698. + dead port 1/2 on $mux $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$ternary$hardware/v2/rtl/neural_processor.v:263$3699. + dead port 2/2 on $mux $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$ternary$hardware/v2/rtl/neural_processor.v:263$3699. + dead port 1/2 on $mux $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$ternary$hardware/v2/rtl/neural_processor.v:264$3698. + dead port 2/2 on $mux $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$ternary$hardware/v2/rtl/neural_processor.v:264$3698. + dead port 1/2 on $mux $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$ternary$hardware/v2/rtl/neural_processor.v:263$3699. + dead port 2/2 on $mux $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$ternary$hardware/v2/rtl/neural_processor.v:263$3699. + dead port 1/2 on $mux $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$ternary$hardware/v2/rtl/neural_processor.v:264$3698. + dead port 2/2 on $mux $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$ternary$hardware/v2/rtl/neural_processor.v:264$3698. + dead port 1/2 on $mux $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$ternary$hardware/v2/rtl/neural_processor.v:263$3699. + dead port 2/2 on $mux $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$ternary$hardware/v2/rtl/neural_processor.v:263$3699. + dead port 1/2 on $mux $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$ternary$hardware/v2/rtl/neural_processor.v:264$3698. + dead port 2/2 on $mux $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$ternary$hardware/v2/rtl/neural_processor.v:264$3698. +Removed 16 multiplexer ports. + + +19.14.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \fpga_neural_v2_top. +Performed a total of 0 changes. + +19.14.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\fpga_neural_v2_top'. +Computing hashes of 4628 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. +Computing hashes of 4309 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. +Computing hashes of 4177 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. +Computing hashes of 4171 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. +Computing hashes of 4170 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. +Computing hashes of 4169 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. + +Removed a total of 459 cells. + +19.14.13. Executing OPT_DFF pass (perform DFF optimizations). +Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$24644 ($sdffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 1 on $auto$ff.cc:337:slice$24644 ($sdffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 2 on $auto$ff.cc:337:slice$24644 ($sdffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 3 on $auto$ff.cc:337:slice$24644 ($sdffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 4 on $auto$ff.cc:337:slice$24644 ($sdffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 5 on $auto$ff.cc:337:slice$24644 ($sdffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 6 on $auto$ff.cc:337:slice$24644 ($sdffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 7 on $auto$ff.cc:337:slice$24644 ($sdffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 8 on $auto$ff.cc:337:slice$24644 ($sdffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 9 on $auto$ff.cc:337:slice$24644 ($sdffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 10 on $auto$ff.cc:337:slice$24644 ($sdffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 11 on $auto$ff.cc:337:slice$24644 ($sdffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 12 on $auto$ff.cc:337:slice$24644 ($sdffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 13 on $auto$ff.cc:337:slice$24644 ($sdffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 14 on $auto$ff.cc:337:slice$24644 ($sdffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 15 on $auto$ff.cc:337:slice$24644 ($sdffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 22 on $auto$ff.cc:337:slice$24646 ($sdffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 22 on $auto$ff.cc:337:slice$24647 ($sdffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 22 on $auto$ff.cc:337:slice$24648 ($sdffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 22 on $auto$ff.cc:337:slice$24649 ($sdffe) from module fpga_neural_v2_top. + +19.14.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \fpga_neural_v2_top.. +Removed 12 unused cells and 484 unused wires. + + +19.14.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module fpga_neural_v2_top. + +19.14.16. Rerunning OPT passes. (Maybe there is more to do..) + +19.14.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \fpga_neural_v2_top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +19.14.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \fpga_neural_v2_top. +Performed a total of 0 changes. + +19.14.19. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\fpga_neural_v2_top'. +Computing hashes of 4152 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. +Removed a total of 0 cells. + +19.14.20. Executing OPT_DFF pass (perform DFF optimizations). +Adding SRST signal on $auto$ff.cc:337:slice$22873 ($dffe) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$ternary$hardware/v2/rtl/neural_processor.v:269$3700_Y [6:0], Q = \u_dataflow_core.GEN_SLOT[3].u_np.y7 [6:0], rval = 7'0000000). +Adding SRST signal on $auto$ff.cc:337:slice$22873 ($dffe) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[3].u_np.final_acc_reg [7], Q = \u_dataflow_core.GEN_SLOT[3].u_np.y7 [7], rval = 1'0). +Adding SRST signal on $auto$ff.cc:337:slice$23209 ($dffe) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$ternary$hardware/v2/rtl/neural_processor.v:269$3700_Y [6:0], Q = \u_dataflow_core.GEN_SLOT[2].u_np.y7 [6:0], rval = 7'0000000). +Adding SRST signal on $auto$ff.cc:337:slice$23209 ($dffe) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[2].u_np.final_acc_reg [7], Q = \u_dataflow_core.GEN_SLOT[2].u_np.y7 [7], rval = 1'0). +Adding SRST signal on $auto$ff.cc:337:slice$23559 ($dffe) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$ternary$hardware/v2/rtl/neural_processor.v:269$3700_Y [6:0], Q = \u_dataflow_core.GEN_SLOT[1].u_np.y7 [6:0], rval = 7'0000000). +Adding SRST signal on $auto$ff.cc:337:slice$23559 ($dffe) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[1].u_np.final_acc_reg [7], Q = \u_dataflow_core.GEN_SLOT[1].u_np.y7 [7], rval = 1'0). +Adding SRST signal on $auto$ff.cc:337:slice$23904 ($dffe) from module fpga_neural_v2_top (D = $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$ternary$hardware/v2/rtl/neural_processor.v:269$3700_Y [6:0], Q = \u_dataflow_core.GEN_SLOT[0].u_np.y7 [6:0], rval = 7'0000000). +Adding SRST signal on $auto$ff.cc:337:slice$23904 ($dffe) from module fpga_neural_v2_top (D = \u_dataflow_core.GEN_SLOT[0].u_np.final_acc_reg [7], Q = \u_dataflow_core.GEN_SLOT[0].u_np.y7 [7], rval = 1'0). + +19.14.21. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \fpga_neural_v2_top.. +Removed 4 unused cells and 4 unused wires. + + +19.14.22. Executing OPT_EXPR pass (perform const folding). +Optimizing module fpga_neural_v2_top. + +19.14.23. Rerunning OPT passes. (Maybe there is more to do..) + +19.14.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \fpga_neural_v2_top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +19.14.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \fpga_neural_v2_top. + New input vector for $reduce_or cell $auto$opt_dff.cc:362:combine_resets$24864: { \u_dataflow_core.GEN_SLOT[0].u_np.final_acc_le_zero \u_dataflow_core.GEN_SLOT[0].u_np.final_acc_reg [31:7] } + New input vector for $reduce_or cell $auto$opt_dff.cc:362:combine_resets$24860: { \u_dataflow_core.GEN_SLOT[1].u_np.final_acc_le_zero \u_dataflow_core.GEN_SLOT[1].u_np.final_acc_reg [31:7] } + New input vector for $reduce_or cell $auto$opt_dff.cc:362:combine_resets$24852: { \u_dataflow_core.GEN_SLOT[3].u_np.final_acc_le_zero \u_dataflow_core.GEN_SLOT[3].u_np.final_acc_reg [31:7] } + New input vector for $reduce_or cell $auto$opt_dff.cc:362:combine_resets$24856: { \u_dataflow_core.GEN_SLOT[2].u_np.final_acc_le_zero \u_dataflow_core.GEN_SLOT[2].u_np.final_acc_reg [31:7] } + Optimizing cells in module \fpga_neural_v2_top. +Performed a total of 4 changes. + +19.14.26. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\fpga_neural_v2_top'. +Computing hashes of 4156 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. +Removed a total of 0 cells. + +19.14.27. Executing OPT_DFF pass (perform DFF optimizations). + +19.14.28. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \fpga_neural_v2_top.. + +19.14.29. Executing OPT_EXPR pass (perform const folding). +Optimizing module fpga_neural_v2_top. + +19.14.30. Rerunning OPT passes. (Maybe there is more to do..) + +19.14.31. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \fpga_neural_v2_top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +19.14.32. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \fpga_neural_v2_top. +Performed a total of 0 changes. + +19.14.33. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\fpga_neural_v2_top'. +Computing hashes of 4156 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. +Removed a total of 0 cells. + +19.14.34. Executing OPT_DFF pass (perform DFF optimizations). + +19.14.35. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \fpga_neural_v2_top.. + +19.14.36. Executing OPT_EXPR pass (perform const folding). +Optimizing module fpga_neural_v2_top. + +19.14.37. Finished fast OPT passes. (There is nothing left to do.) + +19.15. Executing WREDUCE pass (reducing word size of cells). +Removed top 28 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$6643 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_required$hardware/v2/rtl/dependency_manager.v:152$6640 (u_dataflow_core.u_dep_mgr.node_required). +Removed top 26 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$6632 (u_dataflow_core.u_dep_mgr.node_producer_ids). +Removed top 26 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$6617 (u_dataflow_core.u_dep_mgr.node_producer_ids). +Removed top 26 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$6602 (u_dataflow_core.u_dep_mgr.node_producer_ids). +Removed top 26 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$6587 (u_dataflow_core.u_dep_mgr.node_producer_ids). +Removed top 28 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_state$hardware/v2/rtl/dependency_manager.v:148$6571 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$6569 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_required$hardware/v2/rtl/dependency_manager.v:152$6566 (u_dataflow_core.u_dep_mgr.node_required). +Removed top 26 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$6558 (u_dataflow_core.u_dep_mgr.node_producer_ids). +Removed top 26 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$6543 (u_dataflow_core.u_dep_mgr.node_producer_ids). +Removed top 26 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$6528 (u_dataflow_core.u_dep_mgr.node_producer_ids). +Removed top 26 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$6513 (u_dataflow_core.u_dep_mgr.node_producer_ids). +Removed top 28 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_state$hardware/v2/rtl/dependency_manager.v:148$6497 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$6495 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_required$hardware/v2/rtl/dependency_manager.v:152$6492 (u_dataflow_core.u_dep_mgr.node_required). +Removed top 26 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$6484 (u_dataflow_core.u_dep_mgr.node_producer_ids). +Removed top 26 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$6469 (u_dataflow_core.u_dep_mgr.node_producer_ids). +Removed top 26 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$6454 (u_dataflow_core.u_dep_mgr.node_producer_ids). +Removed top 26 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$6439 (u_dataflow_core.u_dep_mgr.node_producer_ids). +Removed top 28 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_state$hardware/v2/rtl/dependency_manager.v:148$6423 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$6421 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_required$hardware/v2/rtl/dependency_manager.v:152$6418 (u_dataflow_core.u_dep_mgr.node_required). +Removed top 26 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$6410 (u_dataflow_core.u_dep_mgr.node_producer_ids). +Removed top 26 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$6395 (u_dataflow_core.u_dep_mgr.node_producer_ids). +Removed top 26 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$6380 (u_dataflow_core.u_dep_mgr.node_producer_ids). +Removed top 26 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$6365 (u_dataflow_core.u_dep_mgr.node_producer_ids). +Removed top 28 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_state$hardware/v2/rtl/dependency_manager.v:148$6349 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$6347 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_required$hardware/v2/rtl/dependency_manager.v:152$6344 (u_dataflow_core.u_dep_mgr.node_required). +Removed top 26 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$6336 (u_dataflow_core.u_dep_mgr.node_producer_ids). +Removed top 26 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$6321 (u_dataflow_core.u_dep_mgr.node_producer_ids). +Removed top 26 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$6306 (u_dataflow_core.u_dep_mgr.node_producer_ids). +Removed top 26 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$6291 (u_dataflow_core.u_dep_mgr.node_producer_ids). +Removed top 28 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_state$hardware/v2/rtl/dependency_manager.v:148$6275 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$6273 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_required$hardware/v2/rtl/dependency_manager.v:152$6270 (u_dataflow_core.u_dep_mgr.node_required). +Removed top 26 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$6262 (u_dataflow_core.u_dep_mgr.node_producer_ids). +Removed top 26 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$6247 (u_dataflow_core.u_dep_mgr.node_producer_ids). +Removed top 26 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$6232 (u_dataflow_core.u_dep_mgr.node_producer_ids). +Removed top 26 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$6217 (u_dataflow_core.u_dep_mgr.node_producer_ids). +Removed top 28 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_state$hardware/v2/rtl/dependency_manager.v:148$6201 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$6199 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_required$hardware/v2/rtl/dependency_manager.v:152$6196 (u_dataflow_core.u_dep_mgr.node_required). +Removed top 26 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$6188 (u_dataflow_core.u_dep_mgr.node_producer_ids). +Removed top 26 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$6173 (u_dataflow_core.u_dep_mgr.node_producer_ids). +Removed top 26 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$6158 (u_dataflow_core.u_dep_mgr.node_producer_ids). +Removed top 26 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$6143 (u_dataflow_core.u_dep_mgr.node_producer_ids). +Removed top 28 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_state$hardware/v2/rtl/dependency_manager.v:148$6127 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$6125 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_required$hardware/v2/rtl/dependency_manager.v:152$6122 (u_dataflow_core.u_dep_mgr.node_required). +Removed top 26 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$6114 (u_dataflow_core.u_dep_mgr.node_producer_ids). +Removed top 26 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$6099 (u_dataflow_core.u_dep_mgr.node_producer_ids). +Removed top 26 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$6084 (u_dataflow_core.u_dep_mgr.node_producer_ids). +Removed top 26 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$6069 (u_dataflow_core.u_dep_mgr.node_producer_ids). +Removed top 28 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_state$hardware/v2/rtl/dependency_manager.v:148$6053 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$6051 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_required$hardware/v2/rtl/dependency_manager.v:152$6048 (u_dataflow_core.u_dep_mgr.node_required). +Removed top 26 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$6040 (u_dataflow_core.u_dep_mgr.node_producer_ids). +Removed top 26 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$6025 (u_dataflow_core.u_dep_mgr.node_producer_ids). +Removed top 26 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$6010 (u_dataflow_core.u_dep_mgr.node_producer_ids). +Removed top 26 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$5995 (u_dataflow_core.u_dep_mgr.node_producer_ids). +Removed top 28 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_state$hardware/v2/rtl/dependency_manager.v:148$5979 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$5977 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_required$hardware/v2/rtl/dependency_manager.v:152$5974 (u_dataflow_core.u_dep_mgr.node_required). +Removed top 26 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$5966 (u_dataflow_core.u_dep_mgr.node_producer_ids). +Removed top 26 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$5951 (u_dataflow_core.u_dep_mgr.node_producer_ids). +Removed top 26 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$5936 (u_dataflow_core.u_dep_mgr.node_producer_ids). +Removed top 26 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$5921 (u_dataflow_core.u_dep_mgr.node_producer_ids). +Removed top 28 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_state$hardware/v2/rtl/dependency_manager.v:148$5905 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$5903 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_required$hardware/v2/rtl/dependency_manager.v:152$5900 (u_dataflow_core.u_dep_mgr.node_required). +Removed top 26 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$5892 (u_dataflow_core.u_dep_mgr.node_producer_ids). +Removed top 26 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$5877 (u_dataflow_core.u_dep_mgr.node_producer_ids). +Removed top 26 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$5862 (u_dataflow_core.u_dep_mgr.node_producer_ids). +Removed top 26 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$5847 (u_dataflow_core.u_dep_mgr.node_producer_ids). +Removed top 28 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_state$hardware/v2/rtl/dependency_manager.v:148$5831 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$5829 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_required$hardware/v2/rtl/dependency_manager.v:152$5826 (u_dataflow_core.u_dep_mgr.node_required). +Removed top 26 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$5818 (u_dataflow_core.u_dep_mgr.node_producer_ids). +Removed top 26 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$5803 (u_dataflow_core.u_dep_mgr.node_producer_ids). +Removed top 26 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$5788 (u_dataflow_core.u_dep_mgr.node_producer_ids). +Removed top 26 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$5773 (u_dataflow_core.u_dep_mgr.node_producer_ids). +Removed top 28 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_state$hardware/v2/rtl/dependency_manager.v:148$5757 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$5755 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_required$hardware/v2/rtl/dependency_manager.v:152$5752 (u_dataflow_core.u_dep_mgr.node_required). +Removed top 26 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$5744 (u_dataflow_core.u_dep_mgr.node_producer_ids). +Removed top 26 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$5729 (u_dataflow_core.u_dep_mgr.node_producer_ids). +Removed top 26 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$5714 (u_dataflow_core.u_dep_mgr.node_producer_ids). +Removed top 26 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$5699 (u_dataflow_core.u_dep_mgr.node_producer_ids). +Removed top 28 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_state$hardware/v2/rtl/dependency_manager.v:148$5683 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$5681 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_required$hardware/v2/rtl/dependency_manager.v:152$5678 (u_dataflow_core.u_dep_mgr.node_required). +Removed top 26 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$5670 (u_dataflow_core.u_dep_mgr.node_producer_ids). +Removed top 26 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$5655 (u_dataflow_core.u_dep_mgr.node_producer_ids). +Removed top 26 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$5640 (u_dataflow_core.u_dep_mgr.node_producer_ids). +Removed top 26 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$5625 (u_dataflow_core.u_dep_mgr.node_producer_ids). +Removed top 28 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_state$hardware/v2/rtl/dependency_manager.v:148$5609 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$5607 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_required$hardware/v2/rtl/dependency_manager.v:152$5604 (u_dataflow_core.u_dep_mgr.node_required). +Removed top 26 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$5596 (u_dataflow_core.u_dep_mgr.node_producer_ids). +Removed top 26 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$5581 (u_dataflow_core.u_dep_mgr.node_producer_ids). +Removed top 26 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$5566 (u_dataflow_core.u_dep_mgr.node_producer_ids). +Removed top 26 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$5551 (u_dataflow_core.u_dep_mgr.node_producer_ids). +Removed top 28 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_state$hardware/v2/rtl/dependency_manager.v:148$5535 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_resolved$hardware/v2/rtl/dependency_manager.v:154$5533 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_required$hardware/v2/rtl/dependency_manager.v:152$5530 (u_dataflow_core.u_dep_mgr.node_required). +Removed top 26 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$5522 (u_dataflow_core.u_dep_mgr.node_producer_ids). +Removed top 26 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$5507 (u_dataflow_core.u_dep_mgr.node_producer_ids). +Removed top 26 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$5492 (u_dataflow_core.u_dep_mgr.node_producer_ids). +Removed top 26 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:151$5477 (u_dataflow_core.u_dep_mgr.node_producer_ids). +Removed top 28 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$memrd$\node_state$hardware/v2/rtl/dependency_manager.v:148$5461 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20960 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20959 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20958 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20957 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20956 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20955 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20954 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20953 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20952 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20951 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20950 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20949 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20948 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20947 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20946 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20945 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20944 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20943 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20942 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20941 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20940 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20939 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20938 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20937 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20936 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20935 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20934 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20933 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20932 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20931 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20930 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20929 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 30 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_sdram_backend.$auto$proc_memwr.cc:45:proc_memwr$20767 (u_sdram_backend.w_cache_valid). +Removed top 30 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_sdram_backend.$auto$proc_memwr.cc:45:proc_memwr$20766 (u_sdram_backend.w_cache_valid). +Removed top 30 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_sdram_backend.$auto$proc_memwr.cc:45:proc_memwr$20765 (u_sdram_backend.w_cache_valid). +Removed top 30 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_sdram_backend.$auto$proc_memwr.cc:45:proc_memwr$20764 (u_sdram_backend.w_cache_valid). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20928 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20927 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20926 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20925 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20924 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20923 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20922 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20921 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20920 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20919 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20918 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20917 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20916 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20915 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20914 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20913 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20912 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20911 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20910 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20909 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20908 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20907 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20906 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20905 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20904 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20903 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20902 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20901 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20900 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20899 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20898 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20897 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20896 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20895 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20894 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20893 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20892 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20891 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20890 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20889 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20888 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20887 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20886 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20885 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20884 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20883 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20882 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20881 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20880 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20879 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20878 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20877 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20876 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20875 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20874 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20873 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20872 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20871 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20870 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20869 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20868 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20867 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20866 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20865 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20864 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20863 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20862 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20861 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20860 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20859 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20858 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20857 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20856 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20855 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20854 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20853 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20852 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20851 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20850 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20849 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20848 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20847 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20846 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20845 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20844 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20843 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20842 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20841 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20840 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20839 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20838 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20837 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20836 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20835 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20834 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20833 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 26 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20831 (u_dataflow_core.u_dep_mgr.node_producer_ids). +Removed top 26 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20830 (u_dataflow_core.u_dep_mgr.node_producer_ids). +Removed top 26 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20829 (u_dataflow_core.u_dep_mgr.node_producer_ids). +Removed top 26 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20828 (u_dataflow_core.u_dep_mgr.node_producer_ids). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20821 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20820 (u_dataflow_core.u_dep_mgr.node_required). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20819 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20818 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20817 (u_dataflow_core.u_dep_mgr.node_required). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20816 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20815 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20814 (u_dataflow_core.u_dep_mgr.node_required). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20813 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 30 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_sdram_backend.$memrd$\w_cache_valid$hardware/v2/nms/rtl/sdram_unified_backend.v:119$6955 (u_sdram_backend.w_cache_valid). +Removed top 30 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_sdram_backend.$memrd$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:119$6956 (u_sdram_backend.w_cache_addr). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20812 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20811 (u_dataflow_core.u_dep_mgr.node_required). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20810 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20809 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20808 (u_dataflow_core.u_dep_mgr.node_required). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20807 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20806 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20805 (u_dataflow_core.u_dep_mgr.node_required). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20804 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20803 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20802 (u_dataflow_core.u_dep_mgr.node_required). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20801 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20800 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20799 (u_dataflow_core.u_dep_mgr.node_required). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20798 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20797 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20796 (u_dataflow_core.u_dep_mgr.node_required). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20795 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20794 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20793 (u_dataflow_core.u_dep_mgr.node_required). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20792 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20791 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20790 (u_dataflow_core.u_dep_mgr.node_required). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20789 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20788 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20787 (u_dataflow_core.u_dep_mgr.node_required). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20786 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20785 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20784 (u_dataflow_core.u_dep_mgr.node_required). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20783 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20782 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20781 (u_dataflow_core.u_dep_mgr.node_required). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20780 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20779 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20778 (u_dataflow_core.u_dep_mgr.node_required). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20777 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20776 (u_dataflow_core.u_dep_mgr.node_resolved). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20775 (u_dataflow_core.u_dep_mgr.node_required). +Removed top 28 address bits (of 32) from memory init port fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$auto$proc_memwr.cc:45:proc_memwr$20774 (u_dataflow_core.u_dep_mgr.node_state). +Removed top 30 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_sdram_backend.$memrd$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:119$6952 (u_sdram_backend.w_cache_addr). +Removed top 30 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_sdram_backend.$memrd$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:119$6948 (u_sdram_backend.w_cache_addr). +Removed top 30 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_sdram_backend.$memrd$\w_cache_valid$hardware/v2/nms/rtl/sdram_unified_backend.v:119$6951 (u_sdram_backend.w_cache_valid). +Removed top 30 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_sdram_backend.$memrd$\w_cache_valid$hardware/v2/nms/rtl/sdram_unified_backend.v:119$6947 (u_sdram_backend.w_cache_valid). +Removed top 30 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_sdram_backend.$memrd$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:119$6944 (u_sdram_backend.w_cache_addr). +Removed top 30 address bits (of 32) from memory read port fpga_neural_v2_top.$flatten\u_sdram_backend.$memrd$\w_cache_valid$hardware/v2/nms/rtl/sdram_unified_backend.v:119$6943 (u_sdram_backend.w_cache_valid). +Removed top 1 bits (of 2) from port B of cell fpga_neural_v2_top.$auto$opt_dff.cc:320:make_patterns_logic$24797 ($ne). +Removed top 1 bits (of 2) from port B of cell fpga_neural_v2_top.$auto$opt_dff.cc:320:make_patterns_logic$24657 ($ne). +Removed top 1 bits (of 2) from port B of cell fpga_neural_v2_top.$auto$opt_dff.cc:320:make_patterns_logic$24535 ($ne). +Removed top 2 bits (of 3) from port B of cell fpga_neural_v2_top.$auto$opt_dff.cc:320:make_patterns_logic$24501 ($ne). +Removed top 1 bits (of 3) from port B of cell fpga_neural_v2_top.$auto$opt_dff.cc:320:make_patterns_logic$24499 ($ne). +Removed top 1 bits (of 2) from port B of cell fpga_neural_v2_top.$auto$opt_dff.cc:320:make_patterns_logic$24497 ($ne). +Removed top 1 bits (of 2) from port B of cell fpga_neural_v2_top.$auto$opt_dff.cc:320:make_patterns_logic$24493 ($ne). +Removed top 1 bits (of 2) from port B of cell fpga_neural_v2_top.$auto$opt_dff.cc:320:make_patterns_logic$24437 ($ne). +Removed top 1 bits (of 2) from port B of cell fpga_neural_v2_top.$auto$opt_dff.cc:320:make_patterns_logic$24433 ($ne). +Removed top 1 bits (of 2) from port B of cell fpga_neural_v2_top.$auto$opt_dff.cc:320:make_patterns_logic$24362 ($ne). +Removed top 1 bits (of 2) from port B of cell fpga_neural_v2_top.$auto$opt_dff.cc:320:make_patterns_logic$24218 ($ne). +Removed top 1 bits (of 3) from port B of cell fpga_neural_v2_top.$auto$opt_dff.cc:320:make_patterns_logic$24201 ($ne). +Removed top 2 bits (of 3) from port B of cell fpga_neural_v2_top.$auto$opt_dff.cc:320:make_patterns_logic$24124 ($ne). +Removed top 1 bits (of 2) from port B of cell fpga_neural_v2_top.$auto$opt_dff.cc:320:make_patterns_logic$24077 ($ne). +Removed top 1 bits (of 2) from port B of cell fpga_neural_v2_top.$auto$opt_dff.cc:320:make_patterns_logic$24035 ($ne). +Removed top 1 bits (of 2) from port B of cell fpga_neural_v2_top.$auto$opt_dff.cc:320:make_patterns_logic$24033 ($ne). +Removed top 1 bits (of 2) from port B of cell fpga_neural_v2_top.$auto$opt_dff.cc:320:make_patterns_logic$24031 ($ne). +Removed top 16 bits (of 32) from FF cell fpga_neural_v2_top.$auto$ff.cc:337:slice$23923 ($dffe). +Removed top 16 bits (of 32) from FF cell fpga_neural_v2_top.$auto$ff.cc:337:slice$23922 ($dffe). +Removed top 16 bits (of 32) from FF cell fpga_neural_v2_top.$auto$ff.cc:337:slice$23921 ($dffe). +Removed top 16 bits (of 32) from FF cell fpga_neural_v2_top.$auto$ff.cc:337:slice$23920 ($dffe). +Removed top 16 bits (of 32) from FF cell fpga_neural_v2_top.$auto$ff.cc:337:slice$23919 ($dffe). +Removed top 16 bits (of 32) from FF cell fpga_neural_v2_top.$auto$ff.cc:337:slice$23918 ($dffe). +Removed top 16 bits (of 32) from FF cell fpga_neural_v2_top.$auto$ff.cc:337:slice$23917 ($dffe). +Removed top 16 bits (of 32) from FF cell fpga_neural_v2_top.$auto$ff.cc:337:slice$23916 ($dffe). +Removed top 1 bits (of 2) from port B of cell fpga_neural_v2_top.$auto$opt_dff.cc:320:make_patterns_logic$23888 ($ne). +Removed top 1 bits (of 2) from port B of cell fpga_neural_v2_top.$auto$opt_dff.cc:320:make_patterns_logic$23886 ($ne). +Removed top 1 bits (of 3) from port B of cell fpga_neural_v2_top.$auto$opt_dff.cc:320:make_patterns_logic$23865 ($ne). +Removed top 2 bits (of 3) from port B of cell fpga_neural_v2_top.$auto$opt_dff.cc:320:make_patterns_logic$23788 ($ne). +Removed top 1 bits (of 2) from port B of cell fpga_neural_v2_top.$auto$opt_dff.cc:320:make_patterns_logic$23741 ($ne). +Removed top 1 bits (of 2) from port B of cell fpga_neural_v2_top.$auto$opt_dff.cc:320:make_patterns_logic$23699 ($ne). +Removed top 1 bits (of 2) from port B of cell fpga_neural_v2_top.$auto$opt_dff.cc:320:make_patterns_logic$23697 ($ne). +Removed top 1 bits (of 2) from port B of cell fpga_neural_v2_top.$auto$opt_dff.cc:320:make_patterns_logic$23695 ($ne). +Removed top 16 bits (of 32) from FF cell fpga_neural_v2_top.$auto$ff.cc:337:slice$23578 ($dffe). +Removed top 16 bits (of 32) from FF cell fpga_neural_v2_top.$auto$ff.cc:337:slice$23577 ($dffe). +Removed top 16 bits (of 32) from FF cell fpga_neural_v2_top.$auto$ff.cc:337:slice$23576 ($dffe). +Removed top 16 bits (of 32) from FF cell fpga_neural_v2_top.$auto$ff.cc:337:slice$23575 ($dffe). +Removed top 16 bits (of 32) from FF cell fpga_neural_v2_top.$auto$ff.cc:337:slice$23574 ($dffe). +Removed top 16 bits (of 32) from FF cell fpga_neural_v2_top.$auto$ff.cc:337:slice$23573 ($dffe). +Removed top 16 bits (of 32) from FF cell fpga_neural_v2_top.$auto$ff.cc:337:slice$23572 ($dffe). +Removed top 16 bits (of 32) from FF cell fpga_neural_v2_top.$auto$ff.cc:337:slice$23571 ($dffe). +Removed top 1 bits (of 2) from port B of cell fpga_neural_v2_top.$auto$opt_dff.cc:320:make_patterns_logic$23543 ($ne). +Removed top 1 bits (of 2) from port B of cell fpga_neural_v2_top.$auto$opt_dff.cc:320:make_patterns_logic$23541 ($ne). +Removed top 1 bits (of 2) from port B of cell fpga_neural_v2_top.$auto$opt_dff.cc:320:make_patterns_logic$23527 ($ne). +Removed top 1 bits (of 3) from port B of cell fpga_neural_v2_top.$auto$opt_dff.cc:320:make_patterns_logic$23506 ($ne). +Removed top 2 bits (of 3) from port B of cell fpga_neural_v2_top.$auto$opt_dff.cc:320:make_patterns_logic$23429 ($ne). +Removed top 1 bits (of 2) from port B of cell fpga_neural_v2_top.$auto$opt_dff.cc:320:make_patterns_logic$23382 ($ne). +Removed top 1 bits (of 2) from port B of cell fpga_neural_v2_top.$auto$opt_dff.cc:320:make_patterns_logic$23340 ($ne). +Removed top 1 bits (of 2) from port B of cell fpga_neural_v2_top.$auto$opt_dff.cc:320:make_patterns_logic$23338 ($ne). +Removed top 1 bits (of 2) from port B of cell fpga_neural_v2_top.$auto$opt_dff.cc:320:make_patterns_logic$23336 ($ne). +Removed top 16 bits (of 32) from FF cell fpga_neural_v2_top.$auto$ff.cc:337:slice$23228 ($dffe). +Removed top 16 bits (of 32) from FF cell fpga_neural_v2_top.$auto$ff.cc:337:slice$23227 ($dffe). +Removed top 16 bits (of 32) from FF cell fpga_neural_v2_top.$auto$ff.cc:337:slice$23226 ($dffe). +Removed top 16 bits (of 32) from FF cell fpga_neural_v2_top.$auto$ff.cc:337:slice$23225 ($dffe). +Removed top 16 bits (of 32) from FF cell fpga_neural_v2_top.$auto$ff.cc:337:slice$23224 ($dffe). +Removed top 16 bits (of 32) from FF cell fpga_neural_v2_top.$auto$ff.cc:337:slice$23223 ($dffe). +Removed top 16 bits (of 32) from FF cell fpga_neural_v2_top.$auto$ff.cc:337:slice$23222 ($dffe). +Removed top 16 bits (of 32) from FF cell fpga_neural_v2_top.$auto$ff.cc:337:slice$23221 ($dffe). +Removed top 1 bits (of 2) from port B of cell fpga_neural_v2_top.$auto$opt_dff.cc:320:make_patterns_logic$23193 ($ne). +Removed top 1 bits (of 2) from port B of cell fpga_neural_v2_top.$auto$opt_dff.cc:320:make_patterns_logic$23191 ($ne). +Removed top 1 bits (of 3) from port B of cell fpga_neural_v2_top.$auto$opt_dff.cc:320:make_patterns_logic$23170 ($ne). +Removed top 2 bits (of 3) from port B of cell fpga_neural_v2_top.$auto$opt_dff.cc:320:make_patterns_logic$23093 ($ne). +Removed top 1 bits (of 2) from port B of cell fpga_neural_v2_top.$auto$opt_dff.cc:320:make_patterns_logic$23046 ($ne). +Removed top 1 bits (of 2) from port B of cell fpga_neural_v2_top.$auto$opt_dff.cc:320:make_patterns_logic$23004 ($ne). +Removed top 1 bits (of 2) from port B of cell fpga_neural_v2_top.$auto$opt_dff.cc:320:make_patterns_logic$23002 ($ne). +Removed top 1 bits (of 2) from port B of cell fpga_neural_v2_top.$auto$opt_dff.cc:320:make_patterns_logic$23000 ($ne). +Removed top 16 bits (of 32) from FF cell fpga_neural_v2_top.$auto$ff.cc:337:slice$22892 ($dffe). +Removed top 16 bits (of 32) from FF cell fpga_neural_v2_top.$auto$ff.cc:337:slice$22891 ($dffe). +Removed top 16 bits (of 32) from FF cell fpga_neural_v2_top.$auto$ff.cc:337:slice$22890 ($dffe). +Removed top 16 bits (of 32) from FF cell fpga_neural_v2_top.$auto$ff.cc:337:slice$22889 ($dffe). +Removed top 16 bits (of 32) from FF cell fpga_neural_v2_top.$auto$ff.cc:337:slice$22888 ($dffe). +Removed top 16 bits (of 32) from FF cell fpga_neural_v2_top.$auto$ff.cc:337:slice$22887 ($dffe). +Removed top 16 bits (of 32) from FF cell fpga_neural_v2_top.$auto$ff.cc:337:slice$22886 ($dffe). +Removed top 16 bits (of 32) from FF cell fpga_neural_v2_top.$auto$ff.cc:337:slice$22885 ($dffe). +Removed top 1 bits (of 2) from port B of cell fpga_neural_v2_top.$auto$opt_dff.cc:320:make_patterns_logic$22857 ($ne). +Removed top 1 bits (of 2) from port B of cell fpga_neural_v2_top.$auto$opt_dff.cc:320:make_patterns_logic$22855 ($ne). +Removed top 1 bits (of 8) from FF cell fpga_neural_v2_top.$auto$ff.cc:337:slice$22671 ($sdffe). +Removed top 1 bits (of 3) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$22600 ($eq). +Removed top 1 bits (of 3) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$22500 ($eq). +Removed top 1 bits (of 3) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$22404 ($eq). +Removed top 1 bits (of 3) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$22284 ($eq). +Removed top 1 bits (of 3) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$22159 ($eq). +Removed top 3 bits (of 5) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$22117 ($eq). +Removed top 1 bits (of 3) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$22108 ($eq). +Removed top 2 bits (of 4) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$22099 ($eq). +Removed top 2 bits (of 4) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$22064 ($eq). +Removed top 3 bits (of 5) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$22062 ($eq). +Removed top 2 bits (of 6) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$22042 ($eq). +Removed top 3 bits (of 10) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$22038 ($eq). +Removed top 4 bits (of 7) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$22034 ($eq). +Removed top 3 bits (of 11) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$22030 ($eq). +Removed top 2 bits (of 7) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$22026 ($eq). +Removed top 3 bits (of 11) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$22022 ($eq). +Removed top 7 bits (of 8) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$22018 ($eq). +Removed top 3 bits (of 12) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$22014 ($eq). +Removed top 1 bits (of 9) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$22009 ($eq). +Removed top 1 bits (of 10) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$22005 ($eq). +Removed top 1 bits (of 10) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$22001 ($eq). +Removed top 1 bits (of 11) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21997 ($eq). +Removed top 4 bits (of 8) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21993 ($eq). +Removed top 6 bits (of 9) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21989 ($eq). +Removed top 4 bits (of 9) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21985 ($eq). +Removed top 9 bits (of 10) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21981 ($eq). +Removed top 1 bits (of 10) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21977 ($eq). +Removed top 1 bits (of 11) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21973 ($eq). +Removed top 1 bits (of 11) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21969 ($eq). +Removed top 1 bits (of 12) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21965 ($eq). +Removed top 2 bits (of 9) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21961 ($eq). +Removed top 2 bits (of 10) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21957 ($eq). +Removed top 2 bits (of 10) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21953 ($eq). +Removed top 2 bits (of 11) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21949 ($eq). +Removed top 1 bits (of 10) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21945 ($eq). +Removed top 1 bits (of 11) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21941 ($eq). +Removed top 1 bits (of 11) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21937 ($eq). +Removed top 1 bits (of 12) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21933 ($eq). +Removed top 2 bits (of 9) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21929 ($eq). +Removed top 2 bits (of 10) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21925 ($eq). +Removed top 2 bits (of 10) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21921 ($eq). +Removed top 2 bits (of 11) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21917 ($eq). +Removed top 1 bits (of 8) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21912 ($eq). +Removed top 1 bits (of 9) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21908 ($eq). +Removed top 1 bits (of 9) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21904 ($eq). +Removed top 1 bits (of 10) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21900 ($eq). +Removed top 1 bits (of 8) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21884 ($eq). +Removed top 1 bits (of 9) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21868 ($eq). +Removed top 3 bits (of 10) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21860 ($eq). +Removed top 3 bits (of 11) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21852 ($eq). +Removed top 1 bits (of 6) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21846 ($eq). +Removed top 2 bits (of 7) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21844 ($eq). +Removed top 3 bits (of 11) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21836 ($eq). +Removed top 3 bits (of 12) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21828 ($eq). +Removed top 1 bits (of 7) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21822 ($eq). +Removed top 2 bits (of 8) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21820 ($eq). +Removed top 1 bits (of 4) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21813 ($eq). +Removed top 2 bits (of 5) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21811 ($eq). +Removed top 1 bits (of 7) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21803 ($eq). +Removed top 1 bits (of 8) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21799 ($eq). +Removed top 1 bits (of 8) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21791 ($eq). +Removed top 1 bits (of 9) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21787 ($eq). +Removed top 1 bits (of 8) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21779 ($eq). +Removed top 1 bits (of 8) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21771 ($eq). +Removed top 1 bits (of 9) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21767 ($eq). +Removed top 1 bits (of 9) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21759 ($eq). +Removed top 1 bits (of 10) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21755 ($eq). +Removed top 1 bits (of 9) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21747 ($eq). +Removed top 1 bits (of 6) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21739 ($eq). +Removed top 3 bits (of 7) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21735 ($eq). +Removed top 1 bits (of 7) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21727 ($eq). +Removed top 5 bits (of 8) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21723 ($eq). +Removed top 1 bits (of 6) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21717 ($eq). +Removed top 2 bits (of 7) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21715 ($eq). +Removed top 1 bits (of 7) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21707 ($eq). +Removed top 3 bits (of 8) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21703 ($eq). +Removed top 1 bits (of 8) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21695 ($eq). +Removed top 8 bits (of 9) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21691 ($eq). +Removed top 1 bits (of 7) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21685 ($eq). +Removed top 2 bits (of 8) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21683 ($eq). +Removed top 1 bits (of 11) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21679 ($eq). +Removed top 1 bits (of 12) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21675 ($eq). +Removed top 1 bits (of 12) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21671 ($eq). +Removed top 1 bits (of 13) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21667 ($eq). +Removed top 2 bits (of 10) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21663 ($eq). +Removed top 2 bits (of 11) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21659 ($eq). +Removed top 2 bits (of 11) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21655 ($eq). +Removed top 2 bits (of 12) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21651 ($eq). +Removed top 1 bits (of 10) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21614 ($eq). +Removed top 1 bits (of 11) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21610 ($eq). +Removed top 1 bits (of 11) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21606 ($eq). +Removed top 1 bits (of 12) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21602 ($eq). +Removed top 2 bits (of 9) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21598 ($eq). +Removed top 2 bits (of 10) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21594 ($eq). +Removed top 2 bits (of 10) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21590 ($eq). +Removed top 2 bits (of 11) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21586 ($eq). +Removed top 1 bits (of 10) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21582 ($eq). +Removed top 1 bits (of 11) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21578 ($eq). +Removed top 1 bits (of 11) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21574 ($eq). +Removed top 1 bits (of 12) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21570 ($eq). +Removed top 2 bits (of 9) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21566 ($eq). +Removed top 2 bits (of 10) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21562 ($eq). +Removed top 2 bits (of 10) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21558 ($eq). +Removed top 2 bits (of 11) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21554 ($eq). +Removed top 3 bits (of 9) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21529 ($eq). +Removed top 3 bits (of 10) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21521 ($eq). +Removed top 3 bits (of 10) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21513 ($eq). +Removed top 3 bits (of 11) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21505 ($eq). +Removed top 1 bits (of 10) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21468 ($eq). +Removed top 1 bits (of 11) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21464 ($eq). +Removed top 1 bits (of 11) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21460 ($eq). +Removed top 1 bits (of 12) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21456 ($eq). +Removed top 2 bits (of 9) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21452 ($eq). +Removed top 2 bits (of 10) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21448 ($eq). +Removed top 2 bits (of 10) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21444 ($eq). +Removed top 2 bits (of 11) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21440 ($eq). +Removed top 1 bits (of 10) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21387 ($eq). +Removed top 1 bits (of 11) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21383 ($eq). +Removed top 1 bits (of 11) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21379 ($eq). +Removed top 1 bits (of 12) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21375 ($eq). +Removed top 2 bits (of 9) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21371 ($eq). +Removed top 2 bits (of 10) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21367 ($eq). +Removed top 2 bits (of 10) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21363 ($eq). +Removed top 2 bits (of 11) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21359 ($eq). +Removed top 1 bits (of 6) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21342 ($eq). +Removed top 1 bits (of 4) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21320 ($eq). +Removed top 2 bits (of 5) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21318 ($eq). +Removed top 1 bits (of 8) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21295 ($eq). +Removed top 1 bits (of 9) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21283 ($eq). +Removed top 1 bits (of 9) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21271 ($eq). +Removed top 1 bits (of 10) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21259 ($eq). +Removed top 1 bits (of 7) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21247 ($eq). +Removed top 1 bits (of 8) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21235 ($eq). +Removed top 1 bits (of 8) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21223 ($eq). +Removed top 1 bits (of 9) from port B of cell fpga_neural_v2_top.$auto$fsm_map.cc:77:implement_pattern_cache$21211 ($eq). +Removed top 1 bits (of 4) from port B of cell fpga_neural_v2_top.$flatten\u_spi_bridge.$procmux$18747_CMP0 ($eq). +Removed top 3 bits (of 8) from port B of cell fpga_neural_v2_top.$flatten\u_spi_bridge.$procmux$18614_CMP0 ($eq). +Removed top 7 bits (of 8) from port B of cell fpga_neural_v2_top.$flatten\u_spi_bridge.$procmux$18613_CMP0 ($eq). +Removed top 6 bits (of 8) from port B of cell fpga_neural_v2_top.$flatten\u_spi_bridge.$procmux$18612_CMP0 ($eq). +Removed top 3 bits (of 4) from mux cell fpga_neural_v2_top.$flatten\u_spi_bridge.$procmux$18546 ($mux). +Removed top 2 bits (of 4) from port B of cell fpga_neural_v2_top.$flatten\u_spi_bridge.$procmux$18427_CMP0 ($eq). +Removed top 1 bits (of 4) from port B of cell fpga_neural_v2_top.$flatten\u_spi_bridge.$procmux$18401_CMP0 ($eq). +Removed top 1 bits (of 4) from port B of cell fpga_neural_v2_top.$flatten\u_spi_bridge.$procmux$18376_CMP0 ($eq). +Removed top 1 bits (of 4) from port B of cell fpga_neural_v2_top.$flatten\u_spi_bridge.$procmux$18353_CMP0 ($eq). +Removed top 2 bits (of 4) from port B of cell fpga_neural_v2_top.$flatten\u_spi_bridge.$procmux$18251_CMP0 ($eq). +Removed top 3 bits (of 4) from port B of cell fpga_neural_v2_top.$flatten\u_spi_bridge.$procmux$18195_CMP0 ($eq). +Removed top 4 bits (of 8) from port B of cell fpga_neural_v2_top.$flatten\u_spi_bridge.$eq$hardware/v2/rtl/spi_host_bridge.v:428$7393 ($eq). +Removed top 15 bits (of 16) from port B of cell fpga_neural_v2_top.$flatten\u_spi_bridge.$eq$hardware/v2/rtl/spi_host_bridge.v:394$7375 ($eq). +Removed top 7 bits (of 8) from port B of cell fpga_neural_v2_top.$flatten\u_spi_bridge.$eq$hardware/v2/rtl/spi_host_bridge.v:357$7359 ($eq). +Removed top 2 bits (of 4) from port B of cell fpga_neural_v2_top.$flatten\u_spi_bridge.$ne$hardware/v2/rtl/spi_host_bridge.v:345$7356 ($ne). +Removed top 3 bits (of 4) from port B of cell fpga_neural_v2_top.$flatten\u_spi_bridge.$add$hardware/v2/rtl/spi_host_bridge.v:333$7355 ($add). +Removed top 6 bits (of 8) from port B of cell fpga_neural_v2_top.$flatten\u_spi_bridge.$eq$hardware/v2/rtl/spi_host_bridge.v:254$7340 ($eq). +Removed top 2 bits (of 8) from port B of cell fpga_neural_v2_top.$flatten\u_spi_bridge.$eq$hardware/v2/rtl/spi_host_bridge.v:252$7339 ($eq). +Removed top 2 bits (of 3) from port B of cell fpga_neural_v2_top.$flatten\u_spi_bridge.$add$hardware/v2/rtl/spi_host_bridge.v:208$7333 ($add). +Removed top 1 bits (of 8) from mux cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$ternary$hardware/v2/rtl/neural_processor.v:269$3700 ($mux). +Converting cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3719 ($add) from unsigned to signed. +Removed top 16 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3719 ($add). +Removed top 16 bits (of 32) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3719 ($add). +Removed top 15 bits (of 32) from port Y of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3719 ($add). +Converting cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3721 ($add) from unsigned to signed. +Removed top 16 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3721 ($add). +Removed top 16 bits (of 32) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3721 ($add). +Removed top 15 bits (of 32) from port Y of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3721 ($add). +Converting cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3723 ($add) from unsigned to signed. +Removed top 16 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3723 ($add). +Removed top 16 bits (of 32) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3723 ($add). +Removed top 15 bits (of 32) from port Y of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3723 ($add). +Converting cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3725 ($add) from unsigned to signed. +Removed top 16 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3725 ($add). +Removed top 16 bits (of 32) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3725 ($add). +Removed top 15 bits (of 32) from port Y of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3725 ($add). +Removed top 15 bits (of 32) from FF cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procdff$20048 ($dff). +Removed top 15 bits (of 32) from FF cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procdff$20049 ($dff). +Removed top 15 bits (of 32) from FF cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procdff$20050 ($dff). +Removed top 15 bits (of 32) from FF cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$procdff$20051 ($dff). +Removed top 11 bits (of 16) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$lt$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:171$3760 ($lt). +Removed top 11 bits (of 16) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$add$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:247$3774 ($add). +Removed top 15 bits (of 16) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$add$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:247$3774 ($add). +Removed top 10 bits (of 16) from port Y of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$add$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:247$3774 ($add). +Removed top 10 bits (of 16) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$eq$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:247$3775 ($eq). +Removed top 15 bits (of 16) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$sub$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:263$3777 ($sub). +Removed top 11 bits (of 16) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$eq$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:263$3778 ($eq). +Removed top 27 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:103$6790 ($add). +Removed top 28 bits (of 32) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:103$6790 ($add). +Removed top 26 bits (of 32) from port Y of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:103$6790 ($add). +Removed top 22 bits (of 23) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:151$6830 ($add). +Removed top 21 bits (of 23) from port Y of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:151$6830 ($add). +Removed top 15 bits (of 23) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:150$6829 ($add). +Removed top 17 bits (of 23) from port Y of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:139$6824 ($add). +Removed top 27 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$lt$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:137$6822 ($lt). +Removed top 26 bits (of 32) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$lt$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:137$6822 ($lt). +Removed top 11 bits (of 16) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$lt$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:136$6820 ($lt). +Removed top 27 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$lt$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:106$6793 ($lt). +Removed top 26 bits (of 32) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$lt$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:106$6793 ($lt). +Removed top 11 bits (of 16) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$lt$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:105$6791 ($lt). +Removed top 1 bits (of 8) from mux cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$ternary$hardware/v2/rtl/neural_processor.v:269$3700 ($mux). +Converting cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3719 ($add) from unsigned to signed. +Removed top 16 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3719 ($add). +Removed top 16 bits (of 32) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3719 ($add). +Removed top 15 bits (of 32) from port Y of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3719 ($add). +Converting cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3721 ($add) from unsigned to signed. +Removed top 16 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3721 ($add). +Removed top 16 bits (of 32) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3721 ($add). +Removed top 15 bits (of 32) from port Y of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3721 ($add). +Converting cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3723 ($add) from unsigned to signed. +Removed top 16 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3723 ($add). +Removed top 16 bits (of 32) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3723 ($add). +Removed top 15 bits (of 32) from port Y of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3723 ($add). +Converting cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3725 ($add) from unsigned to signed. +Removed top 16 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3725 ($add). +Removed top 16 bits (of 32) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3725 ($add). +Removed top 15 bits (of 32) from port Y of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3725 ($add). +Removed top 15 bits (of 32) from FF cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procdff$20048 ($dff). +Removed top 15 bits (of 32) from FF cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procdff$20049 ($dff). +Removed top 15 bits (of 32) from FF cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procdff$20050 ($dff). +Removed top 15 bits (of 32) from FF cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$procdff$20051 ($dff). +Removed top 11 bits (of 16) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$lt$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:171$3760 ($lt). +Removed top 11 bits (of 16) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$add$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:247$3774 ($add). +Removed top 15 bits (of 16) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$add$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:247$3774 ($add). +Removed top 10 bits (of 16) from port Y of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$add$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:247$3774 ($add). +Removed top 10 bits (of 16) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$eq$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:247$3775 ($eq). +Removed top 15 bits (of 16) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$sub$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:263$3777 ($sub). +Removed top 11 bits (of 16) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$eq$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:263$3778 ($eq). +Removed top 27 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:103$6790 ($add). +Removed top 28 bits (of 32) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:103$6790 ($add). +Removed top 26 bits (of 32) from port Y of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:103$6790 ($add). +Removed top 22 bits (of 23) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:151$6830 ($add). +Removed top 21 bits (of 23) from port Y of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:151$6830 ($add). +Removed top 15 bits (of 23) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:150$6829 ($add). +Removed top 17 bits (of 23) from port Y of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:139$6824 ($add). +Removed top 27 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$lt$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:137$6822 ($lt). +Removed top 26 bits (of 32) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$lt$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:137$6822 ($lt). +Removed top 11 bits (of 16) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$lt$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:136$6820 ($lt). +Removed top 27 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$lt$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:106$6793 ($lt). +Removed top 26 bits (of 32) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$lt$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:106$6793 ($lt). +Removed top 11 bits (of 16) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$lt$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:105$6791 ($lt). +Removed top 1 bits (of 8) from mux cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$ternary$hardware/v2/rtl/neural_processor.v:269$3700 ($mux). +Converting cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3719 ($add) from unsigned to signed. +Removed top 16 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3719 ($add). +Removed top 16 bits (of 32) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3719 ($add). +Removed top 15 bits (of 32) from port Y of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3719 ($add). +Converting cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3721 ($add) from unsigned to signed. +Removed top 16 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3721 ($add). +Removed top 16 bits (of 32) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3721 ($add). +Removed top 15 bits (of 32) from port Y of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3721 ($add). +Converting cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3723 ($add) from unsigned to signed. +Removed top 16 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3723 ($add). +Removed top 16 bits (of 32) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3723 ($add). +Removed top 15 bits (of 32) from port Y of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3723 ($add). +Converting cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3725 ($add) from unsigned to signed. +Removed top 16 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3725 ($add). +Removed top 16 bits (of 32) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3725 ($add). +Removed top 15 bits (of 32) from port Y of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3725 ($add). +Removed top 15 bits (of 32) from FF cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procdff$20048 ($dff). +Removed top 15 bits (of 32) from FF cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procdff$20049 ($dff). +Removed top 15 bits (of 32) from FF cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procdff$20050 ($dff). +Removed top 15 bits (of 32) from FF cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$procdff$20051 ($dff). +Removed top 11 bits (of 16) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$lt$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:171$3760 ($lt). +Removed top 11 bits (of 16) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$add$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:247$3774 ($add). +Removed top 15 bits (of 16) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$add$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:247$3774 ($add). +Removed top 10 bits (of 16) from port Y of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$add$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:247$3774 ($add). +Removed top 10 bits (of 16) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$eq$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:247$3775 ($eq). +Removed top 15 bits (of 16) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$sub$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:263$3777 ($sub). +Removed top 11 bits (of 16) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$eq$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:263$3778 ($eq). +Removed top 27 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:103$6790 ($add). +Removed top 28 bits (of 32) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:103$6790 ($add). +Removed top 26 bits (of 32) from port Y of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:103$6790 ($add). +Removed top 22 bits (of 23) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:151$6830 ($add). +Removed top 21 bits (of 23) from port Y of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:151$6830 ($add). +Removed top 15 bits (of 23) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:150$6829 ($add). +Removed top 17 bits (of 23) from port Y of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:139$6824 ($add). +Removed top 27 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$lt$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:137$6822 ($lt). +Removed top 26 bits (of 32) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$lt$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:137$6822 ($lt). +Removed top 11 bits (of 16) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$lt$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:136$6820 ($lt). +Removed top 27 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$lt$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:106$6793 ($lt). +Removed top 26 bits (of 32) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$lt$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:106$6793 ($lt). +Removed top 11 bits (of 16) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$lt$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:105$6791 ($lt). +Removed top 1 bits (of 8) from mux cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$ternary$hardware/v2/rtl/neural_processor.v:269$3700 ($mux). +Converting cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3719 ($add) from unsigned to signed. +Removed top 16 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3719 ($add). +Removed top 16 bits (of 32) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3719 ($add). +Removed top 15 bits (of 32) from port Y of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3719 ($add). +Converting cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3721 ($add) from unsigned to signed. +Removed top 16 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3721 ($add). +Removed top 16 bits (of 32) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3721 ($add). +Removed top 15 bits (of 32) from port Y of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3721 ($add). +Converting cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3723 ($add) from unsigned to signed. +Removed top 16 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3723 ($add). +Removed top 16 bits (of 32) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3723 ($add). +Removed top 15 bits (of 32) from port Y of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3723 ($add). +Converting cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3725 ($add) from unsigned to signed. +Removed top 16 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3725 ($add). +Removed top 16 bits (of 32) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3725 ($add). +Removed top 15 bits (of 32) from port Y of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3725 ($add). +Removed top 15 bits (of 32) from FF cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procdff$20048 ($dff). +Removed top 15 bits (of 32) from FF cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procdff$20049 ($dff). +Removed top 15 bits (of 32) from FF cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procdff$20050 ($dff). +Removed top 15 bits (of 32) from FF cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$procdff$20051 ($dff). +Removed top 11 bits (of 16) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$lt$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:171$3760 ($lt). +Removed top 11 bits (of 16) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$add$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:247$3774 ($add). +Removed top 15 bits (of 16) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$add$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:247$3774 ($add). +Removed top 10 bits (of 16) from port Y of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$add$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:247$3774 ($add). +Removed top 10 bits (of 16) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$eq$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:247$3775 ($eq). +Removed top 15 bits (of 16) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$sub$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:263$3777 ($sub). +Removed top 11 bits (of 16) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$eq$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:263$3778 ($eq). +Removed top 27 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:103$6790 ($add). +Removed top 28 bits (of 32) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:103$6790 ($add). +Removed top 26 bits (of 32) from port Y of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:103$6790 ($add). +Removed top 22 bits (of 23) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:151$6830 ($add). +Removed top 21 bits (of 23) from port Y of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:151$6830 ($add). +Removed top 15 bits (of 23) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:150$6829 ($add). +Removed top 17 bits (of 23) from port Y of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:139$6824 ($add). +Removed top 27 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$lt$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:137$6822 ($lt). +Removed top 26 bits (of 32) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$lt$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:137$6822 ($lt). +Removed top 11 bits (of 16) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$lt$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:136$6820 ($lt). +Removed top 27 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$lt$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:106$6793 ($lt). +Removed top 26 bits (of 32) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$lt$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:106$6793 ($lt). +Removed top 11 bits (of 16) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$lt$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:105$6791 ($lt). +Removed top 15 bits (of 23) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_act_fill.$add$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:207$4192 ($add). +Removed top 1 bits (of 23) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_act_fill.\u_pf.$add$hardware/v2/rtl/prefetch_engine.v:122$6859 ($add). +Removed top 1 bits (of 3) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_act_fill.\u_pf.$eq$hardware/v2/rtl/prefetch_engine.v:116$6857 ($eq). +Removed top 25 bits (of 33) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_act_fill.\u_pf.$neg$hardware/v2/rtl/prefetch_engine.v:115$6850 ($neg). +Converting cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_act_fill.\u_pf.$neg$hardware/v2/rtl/prefetch_engine.v:115$6850 ($neg) from signed to unsigned. +Removed top 1 bits (of 8) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_act_fill.\u_pf.$neg$hardware/v2/rtl/prefetch_engine.v:115$6850 ($neg). +Removed top 27 bits (of 32) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_director.$mul$hardware/v2/rtl/neural_director.v:210$4417 ($mul). +Removed top 25 bits (of 32) from port Y of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_director.$mul$hardware/v2/rtl/neural_director.v:210$4417 ($mul). +Removed top 25 bits (of 33) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_director.$neg$hardware/v2/rtl/neural_director.v:210$4424 ($neg). +Converting cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_director.$neg$hardware/v2/rtl/neural_director.v:210$4424 ($neg) from signed to unsigned. +Removed top 1 bits (of 8) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_director.$neg$hardware/v2/rtl/neural_director.v:210$4424 ($neg). +Removed top 26 bits (of 33) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_director.$neg$hardware/v2/rtl/neural_director.v:211$4434 ($neg). +Converting cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_director.$neg$hardware/v2/rtl/neural_director.v:211$4434 ($neg) from signed to unsigned. +Removed top 1 bits (of 7) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_director.$neg$hardware/v2/rtl/neural_director.v:211$4434 ($neg). +Converting cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_director.$neg$hardware/v2/rtl/neural_director.v:212$4441 ($neg) from signed to unsigned. +Removed top 1 bits (of 3) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_director.$neg$hardware/v2/rtl/neural_director.v:212$4441 ($neg). +Removed top 1 bits (of 2) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_director.$procmux$19168_CMP0 ($eq). +Removed top 26 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:136$5262 ($add). +Removed top 31 bits (of 32) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:136$5262 ($add). +Removed top 25 bits (of 32) from port Y of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:136$5262 ($add). +Removed top 26 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:136$5264 ($add). +Removed top 30 bits (of 32) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:136$5264 ($add). +Removed top 25 bits (of 32) from port Y of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:136$5264 ($add). +Removed top 26 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:136$5266 ($add). +Removed top 30 bits (of 32) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:136$5266 ($add). +Removed top 25 bits (of 32) from port Y of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:136$5266 ($add). +Removed top 1 bits (of 2) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$eq$hardware/v2/rtl/dependency_manager.v:148$5462 ($eq). +Removed top 31 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$lt$hardware/v2/rtl/dependency_manager.v:150$5476 ($lt). +Removed top 31 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$lt$hardware/v2/rtl/dependency_manager.v:150$5491 ($lt). +Removed top 30 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$lt$hardware/v2/rtl/dependency_manager.v:150$5506 ($lt). +Removed top 30 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$lt$hardware/v2/rtl/dependency_manager.v:150$5521 ($lt). +Removed top 1 bits (of 2) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$eq$hardware/v2/rtl/dependency_manager.v:148$5536 ($eq). +Removed top 31 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$lt$hardware/v2/rtl/dependency_manager.v:150$5550 ($lt). +Removed top 31 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$lt$hardware/v2/rtl/dependency_manager.v:150$5565 ($lt). +Removed top 30 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$lt$hardware/v2/rtl/dependency_manager.v:150$5580 ($lt). +Removed top 30 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$lt$hardware/v2/rtl/dependency_manager.v:150$5595 ($lt). +Removed top 1 bits (of 2) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$eq$hardware/v2/rtl/dependency_manager.v:148$5610 ($eq). +Removed top 31 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$lt$hardware/v2/rtl/dependency_manager.v:150$5624 ($lt). +Removed top 31 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$lt$hardware/v2/rtl/dependency_manager.v:150$5639 ($lt). +Removed top 30 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$lt$hardware/v2/rtl/dependency_manager.v:150$5654 ($lt). +Removed top 30 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$lt$hardware/v2/rtl/dependency_manager.v:150$5669 ($lt). +Removed top 1 bits (of 2) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$eq$hardware/v2/rtl/dependency_manager.v:148$5684 ($eq). +Removed top 31 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$lt$hardware/v2/rtl/dependency_manager.v:150$5698 ($lt). +Removed top 31 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$lt$hardware/v2/rtl/dependency_manager.v:150$5713 ($lt). +Removed top 30 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$lt$hardware/v2/rtl/dependency_manager.v:150$5728 ($lt). +Removed top 30 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$lt$hardware/v2/rtl/dependency_manager.v:150$5743 ($lt). +Removed top 1 bits (of 2) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$eq$hardware/v2/rtl/dependency_manager.v:148$5758 ($eq). +Removed top 31 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$lt$hardware/v2/rtl/dependency_manager.v:150$5772 ($lt). +Removed top 31 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$lt$hardware/v2/rtl/dependency_manager.v:150$5787 ($lt). +Removed top 30 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$lt$hardware/v2/rtl/dependency_manager.v:150$5802 ($lt). +Removed top 30 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$lt$hardware/v2/rtl/dependency_manager.v:150$5817 ($lt). +Removed top 1 bits (of 2) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$eq$hardware/v2/rtl/dependency_manager.v:148$5832 ($eq). +Removed top 31 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$lt$hardware/v2/rtl/dependency_manager.v:150$5846 ($lt). +Removed top 31 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$lt$hardware/v2/rtl/dependency_manager.v:150$5861 ($lt). +Removed top 30 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$lt$hardware/v2/rtl/dependency_manager.v:150$5876 ($lt). +Removed top 30 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$lt$hardware/v2/rtl/dependency_manager.v:150$5891 ($lt). +Removed top 1 bits (of 2) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$eq$hardware/v2/rtl/dependency_manager.v:148$5906 ($eq). +Removed top 31 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$lt$hardware/v2/rtl/dependency_manager.v:150$5920 ($lt). +Removed top 31 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$lt$hardware/v2/rtl/dependency_manager.v:150$5935 ($lt). +Removed top 30 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$lt$hardware/v2/rtl/dependency_manager.v:150$5950 ($lt). +Removed top 30 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$lt$hardware/v2/rtl/dependency_manager.v:150$5965 ($lt). +Removed top 1 bits (of 2) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$eq$hardware/v2/rtl/dependency_manager.v:148$5980 ($eq). +Removed top 31 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$lt$hardware/v2/rtl/dependency_manager.v:150$5994 ($lt). +Removed top 31 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$lt$hardware/v2/rtl/dependency_manager.v:150$6009 ($lt). +Removed top 30 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$lt$hardware/v2/rtl/dependency_manager.v:150$6024 ($lt). +Removed top 30 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$lt$hardware/v2/rtl/dependency_manager.v:150$6039 ($lt). +Removed top 1 bits (of 2) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$eq$hardware/v2/rtl/dependency_manager.v:148$6054 ($eq). +Removed top 31 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$lt$hardware/v2/rtl/dependency_manager.v:150$6068 ($lt). +Removed top 31 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$lt$hardware/v2/rtl/dependency_manager.v:150$6083 ($lt). +Removed top 30 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$lt$hardware/v2/rtl/dependency_manager.v:150$6098 ($lt). +Removed top 30 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$lt$hardware/v2/rtl/dependency_manager.v:150$6113 ($lt). +Removed top 1 bits (of 2) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$eq$hardware/v2/rtl/dependency_manager.v:148$6128 ($eq). +Removed top 31 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$lt$hardware/v2/rtl/dependency_manager.v:150$6142 ($lt). +Removed top 31 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$lt$hardware/v2/rtl/dependency_manager.v:150$6157 ($lt). +Removed top 30 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$lt$hardware/v2/rtl/dependency_manager.v:150$6172 ($lt). +Removed top 30 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$lt$hardware/v2/rtl/dependency_manager.v:150$6187 ($lt). +Removed top 1 bits (of 2) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$eq$hardware/v2/rtl/dependency_manager.v:148$6202 ($eq). +Removed top 31 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$lt$hardware/v2/rtl/dependency_manager.v:150$6216 ($lt). +Removed top 31 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$lt$hardware/v2/rtl/dependency_manager.v:150$6231 ($lt). +Removed top 30 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$lt$hardware/v2/rtl/dependency_manager.v:150$6246 ($lt). +Removed top 30 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$lt$hardware/v2/rtl/dependency_manager.v:150$6261 ($lt). +Removed top 1 bits (of 2) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$eq$hardware/v2/rtl/dependency_manager.v:148$6276 ($eq). +Removed top 31 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$lt$hardware/v2/rtl/dependency_manager.v:150$6290 ($lt). +Removed top 31 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$lt$hardware/v2/rtl/dependency_manager.v:150$6305 ($lt). +Removed top 30 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$lt$hardware/v2/rtl/dependency_manager.v:150$6320 ($lt). +Removed top 30 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$lt$hardware/v2/rtl/dependency_manager.v:150$6335 ($lt). +Removed top 1 bits (of 2) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$eq$hardware/v2/rtl/dependency_manager.v:148$6350 ($eq). +Removed top 31 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$lt$hardware/v2/rtl/dependency_manager.v:150$6364 ($lt). +Removed top 31 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$lt$hardware/v2/rtl/dependency_manager.v:150$6379 ($lt). +Removed top 30 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$lt$hardware/v2/rtl/dependency_manager.v:150$6394 ($lt). +Removed top 30 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$lt$hardware/v2/rtl/dependency_manager.v:150$6409 ($lt). +Removed top 1 bits (of 2) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$eq$hardware/v2/rtl/dependency_manager.v:148$6424 ($eq). +Removed top 31 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$lt$hardware/v2/rtl/dependency_manager.v:150$6438 ($lt). +Removed top 31 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$lt$hardware/v2/rtl/dependency_manager.v:150$6453 ($lt). +Removed top 30 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$lt$hardware/v2/rtl/dependency_manager.v:150$6468 ($lt). +Removed top 30 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$lt$hardware/v2/rtl/dependency_manager.v:150$6483 ($lt). +Removed top 1 bits (of 2) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$eq$hardware/v2/rtl/dependency_manager.v:148$6498 ($eq). +Removed top 31 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$lt$hardware/v2/rtl/dependency_manager.v:150$6512 ($lt). +Removed top 31 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$lt$hardware/v2/rtl/dependency_manager.v:150$6527 ($lt). +Removed top 30 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$lt$hardware/v2/rtl/dependency_manager.v:150$6542 ($lt). +Removed top 30 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$lt$hardware/v2/rtl/dependency_manager.v:150$6557 ($lt). +Removed top 1 bits (of 2) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$eq$hardware/v2/rtl/dependency_manager.v:148$6572 ($eq). +Removed top 31 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$lt$hardware/v2/rtl/dependency_manager.v:150$6586 ($lt). +Removed top 31 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$lt$hardware/v2/rtl/dependency_manager.v:150$6601 ($lt). +Removed top 30 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$lt$hardware/v2/rtl/dependency_manager.v:150$6616 ($lt). +Removed top 30 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$lt$hardware/v2/rtl/dependency_manager.v:150$6631 ($lt). +Removed top 26 bits (of 32) from mux cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$procmux$17906 ($mux). +Removed top 26 bits (of 32) from mux cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$procmux$17915 ($mux). +Removed top 26 bits (of 32) from mux cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$procmux$17924 ($mux). +Removed top 26 bits (of 32) from mux cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$procmux$17933 ($mux). +Removed top 15 bits (of 16) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_act_fill.$gt$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:129$4170 ($gt). +Removed top 25 bits (of 32) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.$shiftx$hardware/v2/nms/rtl/nms_dataflow_core_sdram.v:154$7306 ($shiftx). +Removed top 12 bits (of 16) from port Y of cell fpga_neural_v2_top.$flatten\u_dataflow_core.$shiftx$hardware/v2/nms/rtl/nms_dataflow_core_sdram.v:154$7306 ($shiftx). +Removed top 1 bits (of 3) from port B of cell fpga_neural_v2_top.$flatten\u_arbiter.$eq$hardware/v2/rtl/slot_mem_arbiter.v:173$7181 ($eq). +Removed top 1 bits (of 3) from port B of cell fpga_neural_v2_top.$flatten\u_arbiter.$eq$hardware/v2/rtl/slot_mem_arbiter.v:173$7180 ($eq). +Removed top 2 bits (of 3) from port B of cell fpga_neural_v2_top.$flatten\u_arbiter.$eq$hardware/v2/rtl/slot_mem_arbiter.v:173$7179 ($eq). +Converting cell fpga_neural_v2_top.$flatten\u_arbiter.$neg$hardware/v2/rtl/slot_mem_arbiter.v:164$7172 ($neg) from signed to unsigned. +Removed top 1 bits (of 4) from port A of cell fpga_neural_v2_top.$flatten\u_arbiter.$neg$hardware/v2/rtl/slot_mem_arbiter.v:164$7172 ($neg). +Removed top 24 bits (of 32) from port B of cell fpga_neural_v2_top.$flatten\u_arbiter.$shiftx$hardware/v2/rtl/slot_mem_arbiter.v:163$7171 ($shiftx). +Removed top 27 bits (of 32) from port B of cell fpga_neural_v2_top.$flatten\u_arbiter.$mul$hardware/v2/rtl/slot_mem_arbiter.v:162$7166 ($mul). +Removed top 24 bits (of 32) from port Y of cell fpga_neural_v2_top.$flatten\u_arbiter.$mul$hardware/v2/rtl/slot_mem_arbiter.v:162$7166 ($mul). +Removed top 1 bits (of 2) from mux cell fpga_neural_v2_top.$flatten\u_host_arb.$procmux$8448 ($mux). +Removed top 1 bits (of 2) from mux cell fpga_neural_v2_top.$flatten\u_host_arb.$procmux$8442 ($mux). +Removed top 1 bits (of 2) from port B of cell fpga_neural_v2_top.$flatten\u_host_arb.$eq$hardware/v2/rtl/slot_mem_arbiter.v:173$7142 ($eq). +Removed top 1 bits (of 3) from port A of cell fpga_neural_v2_top.$flatten\u_host_arb.$neg$hardware/v2/rtl/slot_mem_arbiter.v:164$7135 ($neg). +Converting cell fpga_neural_v2_top.$flatten\u_host_arb.$neg$hardware/v2/rtl/slot_mem_arbiter.v:164$7135 ($neg) from signed to unsigned. +Removed top 1 bits (of 2) from port A of cell fpga_neural_v2_top.$flatten\u_host_arb.$neg$hardware/v2/rtl/slot_mem_arbiter.v:164$7135 ($neg). +Removed top 26 bits (of 32) from port B of cell fpga_neural_v2_top.$flatten\u_host_arb.$shiftx$hardware/v2/rtl/slot_mem_arbiter.v:163$7134 ($shiftx). +Removed top 1 bits (of 2) from port A of cell fpga_neural_v2_top.$flatten\u_host_arb.$mul$hardware/v2/rtl/slot_mem_arbiter.v:162$7129 ($mul). +Removed top 27 bits (of 32) from port B of cell fpga_neural_v2_top.$flatten\u_host_arb.$mul$hardware/v2/rtl/slot_mem_arbiter.v:162$7129 ($mul). +Removed top 26 bits (of 32) from port Y of cell fpga_neural_v2_top.$flatten\u_host_arb.$mul$hardware/v2/rtl/slot_mem_arbiter.v:162$7129 ($mul). +Removed top 1 bits (of 2) from port B of cell fpga_neural_v2_top.$flatten\u_host_arb.$shiftx$hardware/v2/rtl/slot_mem_arbiter.v:161$7128 ($shiftx). +Removed top 1 bits (of 2) from port B of cell fpga_neural_v2_top.$flatten\u_host_arb.$shiftx$hardware/v2/rtl/slot_mem_arbiter.v:160$7127 ($shiftx). +Removed top 1 bits (of 2) from port B of cell fpga_neural_v2_top.$flatten\u_host_arb.$shiftx$hardware/v2/rtl/slot_mem_arbiter.v:159$7126 ($shiftx). +Removed top 1 bits (of 2) from port A of cell fpga_neural_v2_top.$flatten\u_host_arb.$add$hardware/v2/rtl/slot_mem_arbiter.v:157$7125 ($add). +Removed top 1 bits (of 3) from mux cell fpga_neural_v2_top.$flatten\u_arbiter_wide.$procmux$8823 ($mux). +Removed top 1 bits (of 3) from mux cell fpga_neural_v2_top.$flatten\u_arbiter_wide.$procmux$8817 ($mux). +Removed top 1 bits (of 3) from mux cell fpga_neural_v2_top.$flatten\u_arbiter_wide.$procmux$8811 ($mux). +Removed top 1 bits (of 3) from mux cell fpga_neural_v2_top.$flatten\u_arbiter_wide.$procmux$8805 ($mux). +Removed top 1 bits (of 3) from port B of cell fpga_neural_v2_top.$flatten\u_arbiter_wide.$eq$hardware/v2/rtl/slot_mem_arbiter_wide.v:174$7108 ($eq). +Removed top 1 bits (of 3) from port B of cell fpga_neural_v2_top.$flatten\u_arbiter_wide.$eq$hardware/v2/rtl/slot_mem_arbiter_wide.v:174$7107 ($eq). +Removed top 2 bits (of 3) from port B of cell fpga_neural_v2_top.$flatten\u_arbiter_wide.$eq$hardware/v2/rtl/slot_mem_arbiter_wide.v:174$7106 ($eq). +Removed top 1 bits (of 4) from port A of cell fpga_neural_v2_top.$flatten\u_arbiter_wide.$neg$hardware/v2/rtl/slot_mem_arbiter_wide.v:165$7103 ($neg). +Converting cell fpga_neural_v2_top.$flatten\u_arbiter_wide.$neg$hardware/v2/rtl/slot_mem_arbiter_wide.v:165$7103 ($neg) from signed to unsigned. +Removed top 1 bits (of 3) from port A of cell fpga_neural_v2_top.$flatten\u_arbiter_wide.$neg$hardware/v2/rtl/slot_mem_arbiter_wide.v:165$7103 ($neg). +Removed top 1 bits (of 3) from port A of cell fpga_neural_v2_top.$flatten\u_arbiter_wide.$mul$hardware/v2/rtl/slot_mem_arbiter_wide.v:163$7093 ($mul). +Removed top 27 bits (of 32) from port B of cell fpga_neural_v2_top.$flatten\u_arbiter_wide.$mul$hardware/v2/rtl/slot_mem_arbiter_wide.v:163$7093 ($mul). +Removed top 25 bits (of 32) from port Y of cell fpga_neural_v2_top.$flatten\u_arbiter_wide.$mul$hardware/v2/rtl/slot_mem_arbiter_wide.v:163$7093 ($mul). +Removed top 1 bits (of 3) from port A of cell fpga_neural_v2_top.$flatten\u_arbiter_wide.$add$hardware/v2/rtl/slot_mem_arbiter_wide.v:158$7089 ($add). +Removed top 1 bits (of 4) from port B of cell fpga_neural_v2_top.$flatten\u_sdram_backend.\u_sdram_ctrl.$lt$hardware/v2/nms/rtl/sdram_controller.v:279$7432 ($lt). +Removed top 25 bits (of 33) from port A of cell fpga_neural_v2_top.$flatten\u_sdram_backend.\u_sdram_ctrl.$neg$hardware/v2/nms/rtl/sdram_controller.v:410$7449 ($neg). +Converting cell fpga_neural_v2_top.$flatten\u_sdram_backend.\u_sdram_ctrl.$neg$hardware/v2/nms/rtl/sdram_controller.v:410$7449 ($neg) from signed to unsigned. +Removed top 1 bits (of 8) from port A of cell fpga_neural_v2_top.$flatten\u_sdram_backend.\u_sdram_ctrl.$neg$hardware/v2/nms/rtl/sdram_controller.v:410$7449 ($neg). +Removed top 28 bits (of 32) from port Y of cell fpga_neural_v2_top.$flatten\u_sdram_backend.\u_sdram_ctrl.$add$hardware/v2/nms/rtl/sdram_controller.v:426$7460 ($add). +Removed top 23 bits (of 32) from port B of cell fpga_neural_v2_top.$flatten\u_sdram_backend.\u_sdram_ctrl.$shiftx$hardware/v2/nms/rtl/sdram_controller.v:426$7463 ($shiftx). +Removed top 26 bits (of 32) from port B of cell fpga_neural_v2_top.$flatten\u_sdram_backend.\u_sdram_ctrl.$shiftx$hardware/v2/nms/rtl/sdram_controller.v:427$7467 ($shiftx). +Removed top 1 bits (of 2) from mux cell fpga_neural_v2_top.$flatten\u_sdram_backend.$procmux$9685 ($mux). +Removed top 24 bits (of 32) from port B of cell fpga_neural_v2_top.$flatten\u_sdram_backend.$shiftx$hardware/v2/nms/rtl/sdram_unified_backend.v:306$7071 ($shiftx). +Removed top 19 bits (of 23) from port B of cell fpga_neural_v2_top.$flatten\u_sdram_backend.$add$hardware/v2/nms/rtl/sdram_unified_backend.v:296$7065 ($add). +Removed top 19 bits (of 23) from port B of cell fpga_neural_v2_top.$flatten\u_sdram_backend.$sub$hardware/v2/nms/rtl/sdram_unified_backend.v:292$7064 ($sub). +Removed top 14 bits (of 16) from port A of cell fpga_neural_v2_top.$flatten\u_sdram_backend.$shl$hardware/v2/nms/rtl/sdram_unified_backend.v:282$7036 ($shl). +Removed top 28 bits (of 32) from port B of cell fpga_neural_v2_top.$flatten\u_sdram_backend.$shl$hardware/v2/nms/rtl/sdram_unified_backend.v:282$7036 ($shl). +Removed top 14 bits (of 16) from port A of cell fpga_neural_v2_top.$flatten\u_sdram_backend.$shl$hardware/v2/nms/rtl/sdram_unified_backend.v:282$7032 ($shl). +Removed top 28 bits (of 32) from port B of cell fpga_neural_v2_top.$flatten\u_sdram_backend.$shl$hardware/v2/nms/rtl/sdram_unified_backend.v:282$7032 ($shl). +Removed top 1 bits (of 23) from mux cell fpga_neural_v2_top.$flatten\u_sdram_backend.$ternary$hardware/v2/nms/rtl/sdram_unified_backend.v:189$6964 ($mux). +Removed cell fpga_neural_v2_top.$auto$ff.cc:337:slice$24299 ($sdffe). +Converting cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$add$hardware/v2/rtl/neural_processor.v:197$3728 ($add) from unsigned to signed. +Removed top 15 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$add$hardware/v2/rtl/neural_processor.v:197$3728 ($add). +Removed top 15 bits (of 32) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$add$hardware/v2/rtl/neural_processor.v:197$3728 ($add). +Removed top 14 bits (of 32) from port Y of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$add$hardware/v2/rtl/neural_processor.v:197$3728 ($add). +Converting cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$add$hardware/v2/rtl/neural_processor.v:197$3730 ($add) from unsigned to signed. +Removed top 15 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$add$hardware/v2/rtl/neural_processor.v:197$3730 ($add). +Removed top 15 bits (of 32) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$add$hardware/v2/rtl/neural_processor.v:197$3730 ($add). +Removed top 14 bits (of 32) from port Y of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$add$hardware/v2/rtl/neural_processor.v:197$3730 ($add). +Converting cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$add$hardware/v2/rtl/neural_processor.v:197$3728 ($add) from unsigned to signed. +Removed top 15 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$add$hardware/v2/rtl/neural_processor.v:197$3728 ($add). +Removed top 15 bits (of 32) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$add$hardware/v2/rtl/neural_processor.v:197$3728 ($add). +Removed top 14 bits (of 32) from port Y of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$add$hardware/v2/rtl/neural_processor.v:197$3728 ($add). +Converting cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$add$hardware/v2/rtl/neural_processor.v:197$3730 ($add) from unsigned to signed. +Removed top 15 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$add$hardware/v2/rtl/neural_processor.v:197$3730 ($add). +Removed top 15 bits (of 32) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$add$hardware/v2/rtl/neural_processor.v:197$3730 ($add). +Removed top 14 bits (of 32) from port Y of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$add$hardware/v2/rtl/neural_processor.v:197$3730 ($add). +Converting cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$add$hardware/v2/rtl/neural_processor.v:197$3728 ($add) from unsigned to signed. +Removed top 15 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$add$hardware/v2/rtl/neural_processor.v:197$3728 ($add). +Removed top 15 bits (of 32) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$add$hardware/v2/rtl/neural_processor.v:197$3728 ($add). +Removed top 14 bits (of 32) from port Y of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$add$hardware/v2/rtl/neural_processor.v:197$3728 ($add). +Converting cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$add$hardware/v2/rtl/neural_processor.v:197$3730 ($add) from unsigned to signed. +Removed top 15 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$add$hardware/v2/rtl/neural_processor.v:197$3730 ($add). +Removed top 15 bits (of 32) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$add$hardware/v2/rtl/neural_processor.v:197$3730 ($add). +Removed top 14 bits (of 32) from port Y of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$add$hardware/v2/rtl/neural_processor.v:197$3730 ($add). +Converting cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$add$hardware/v2/rtl/neural_processor.v:197$3728 ($add) from unsigned to signed. +Removed top 15 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$add$hardware/v2/rtl/neural_processor.v:197$3728 ($add). +Removed top 15 bits (of 32) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$add$hardware/v2/rtl/neural_processor.v:197$3728 ($add). +Removed top 14 bits (of 32) from port Y of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$add$hardware/v2/rtl/neural_processor.v:197$3728 ($add). +Converting cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$add$hardware/v2/rtl/neural_processor.v:197$3730 ($add) from unsigned to signed. +Removed top 15 bits (of 32) from port A of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$add$hardware/v2/rtl/neural_processor.v:197$3730 ($add). +Removed top 15 bits (of 32) from port B of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$add$hardware/v2/rtl/neural_processor.v:197$3730 ($add). +Removed top 14 bits (of 32) from port Y of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$add$hardware/v2/rtl/neural_processor.v:197$3730 ($add). +Removed top 26 bits (of 32) from mux cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$procmux$17000 ($mux). +Removed top 26 bits (of 32) from mux cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$procmux$17018 ($mux). +Removed top 26 bits (of 32) from mux cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$procmux$17036 ($mux). +Removed top 26 bits (of 32) from mux cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$procmux$17054 ($mux). +Removed top 1 bits (of 7) from port Y of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:136$5262 ($add). +Removed top 1 bits (of 7) from port Y of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:136$5264 ($add). +Removed top 1 bits (of 7) from port Y of cell fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:136$5266 ($add). +Removed top 17 bits (of 23) from wire fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:139$6824_Y. +Removed top 21 bits (of 23) from wire fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:151$6830_Y. +Removed top 10 bits (of 16) from wire fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$add$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:247$3774_Y. +Removed top 26 bits (of 32) from wire fpga_neural_v2_top.$flatten\u_host_arb.$add$hardware/v2/rtl/slot_mem_arbiter.v:162$7130_Y. +Removed top 1 bits (of 2) from wire fpga_neural_v2_top.$flatten\u_host_arb.$1\grant_idx[1:0]. +Removed top 1 bits (of 8) from wire fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$ternary$hardware/v2/rtl/neural_processor.v:269$3700_Y. +Removed top 17 bits (of 23) from wire fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:139$6824_Y. +Removed top 21 bits (of 23) from wire fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:151$6830_Y. +Removed top 25 bits (of 32) from wire fpga_neural_v2_top.$flatten\u_arbiter_wide.$add$hardware/v2/rtl/slot_mem_arbiter_wide.v:163$7094_Y. +Removed top 10 bits (of 16) from wire fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$add$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:247$3774_Y. +Removed top 1 bits (of 3) from wire fpga_neural_v2_top.$flatten\u_arbiter_wide.$3\grant_idx[2:0]. +Removed top 1 bits (of 3) from wire fpga_neural_v2_top.$flatten\u_arbiter_wide.$2\grant_idx[2:0]. +Removed top 1 bits (of 3) from wire fpga_neural_v2_top.$flatten\u_arbiter_wide.$1\grant_idx[2:0]. +Removed top 24 bits (of 32) from wire fpga_neural_v2_top.$flatten\u_arbiter.$add$hardware/v2/rtl/slot_mem_arbiter.v:162$7167_Y. +Removed top 25 bits (of 32) from wire fpga_neural_v2_top.$flatten\u_dataflow_core.\u_director.$add$hardware/v2/rtl/neural_director.v:207$4388_Y. +Removed top 112 bits (of 128) from wire fpga_neural_v2_top.$flatten\u_sdram_backend.\u_sdram_ctrl.$2$lookahead\rdata$7416[127:0]$7425. +Removed top 28 bits (of 32) from wire fpga_neural_v2_top.$flatten\u_sdram_backend.\u_sdram_ctrl.$add$hardware/v2/nms/rtl/sdram_controller.v:426$7460_Y. +Removed top 1 bits (of 8) from wire fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$ternary$hardware/v2/rtl/neural_processor.v:269$3700_Y. +Removed top 26 bits (of 32) from wire fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$4508_ADDR[31:0]$5244. +Removed top 26 bits (of 32) from wire fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$4509_ADDR[31:0]$5247. +Removed top 26 bits (of 32) from wire fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$4510_ADDR[31:0]$5250. +Removed top 26 bits (of 32) from wire fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$2$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$4511_ADDR[31:0]$5253. +Removed top 17 bits (of 23) from wire fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:139$6824_Y. +Removed top 21 bits (of 23) from wire fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:151$6830_Y. +Removed top 26 bits (of 32) from wire fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:136$5262_Y. +Removed top 26 bits (of 32) from wire fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:136$5264_Y. +Removed top 26 bits (of 32) from wire fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:136$5266_Y. +Removed top 10 bits (of 16) from wire fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$add$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:247$3774_Y. +Removed top 26 bits (of 32) from wire fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$4511_ADDR[31:0]$4752. +Removed top 26 bits (of 32) from wire fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$4510_ADDR[31:0]$4749. +Removed top 26 bits (of 32) from wire fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$4509_ADDR[31:0]$4746. +Removed top 26 bits (of 32) from wire fpga_neural_v2_top.$flatten\u_dataflow_core.\u_dep_mgr.$0$memwr$\node_producer_ids$hardware/v2/rtl/dependency_manager.v:136$4508_ADDR[31:0]$4743. +Removed top 1 bits (of 8) from wire fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$ternary$hardware/v2/rtl/neural_processor.v:269$3700_Y. +Removed top 17 bits (of 23) from wire fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:139$6824_Y. +Removed top 21 bits (of 23) from wire fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:151$6830_Y. +Removed top 10 bits (of 16) from wire fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$add$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:247$3774_Y. +Removed top 1 bits (of 8) from wire fpga_neural_v2_top.$flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$ternary$hardware/v2/rtl/neural_processor.v:269$3700_Y. +Removed top 3 bits (of 4) from wire fpga_neural_v2_top.$flatten\u_spi_bridge.$procmux$18546_Y. +Removed top 1 bits (of 2) from wire fpga_neural_v2_top.$flatten\u_sdram_backend.$2\w_hit_idx_c[1:0]. +Removed top 16 bits (of 80) from wire fpga_neural_v2_top.slot_mem_wdata. + +19.16. Executing PEEPOPT pass (run peephole optimizers). +shiftadd pattern in fpga_neural_v2_top: shift=$flatten\u_sdram_backend.\u_sdram_ctrl.$shiftx$hardware/v2/nms/rtl/sdram_controller.v:426$7463, add/sub=$flatten\u_sdram_backend.\u_sdram_ctrl.$add$hardware/v2/nms/rtl/sdram_controller.v:426$7460, offset: 16 +right shiftmul pattern in fpga_neural_v2_top: shift=$flatten\u_arbiter.$shiftx$hardware/v2/rtl/slot_mem_arbiter.v:162$7168, mul=$flatten\u_arbiter.$mul$hardware/v2/rtl/slot_mem_arbiter.v:162$7166 +right shiftmul pattern in fpga_neural_v2_top: shift=$flatten\u_arbiter_wide.$shiftx$hardware/v2/rtl/slot_mem_arbiter_wide.v:163$7095, mul=$flatten\u_arbiter_wide.$mul$hardware/v2/rtl/slot_mem_arbiter_wide.v:163$7093 +right shiftmul pattern in fpga_neural_v2_top: shift=$flatten\u_host_arb.$shiftx$hardware/v2/rtl/slot_mem_arbiter.v:162$7131, mul=$flatten\u_host_arb.$mul$hardware/v2/rtl/slot_mem_arbiter.v:162$7129 +left shiftmul pattern in fpga_neural_v2_top: shift=$flatten\u_dataflow_core.\u_director.$shift$hardware/v2/rtl/neural_director.v:210$4425, mul=$flatten\u_dataflow_core.\u_director.$mul$hardware/v2/rtl/neural_director.v:210$4417 +left shiftmul pattern in fpga_neural_v2_top: shift=$flatten\u_dataflow_core.\u_director.$shift$hardware/v2/rtl/neural_director.v:210$4420, mul=$flatten\u_dataflow_core.\u_director.$mul$hardware/v2/rtl/neural_director.v:210$4417 +left shiftmul pattern in fpga_neural_v2_top: shift=$flatten\u_dataflow_core.\u_director.$shift$hardware/v2/rtl/neural_director.v:208$4405, mul=$flatten\u_dataflow_core.\u_director.$mul$hardware/v2/rtl/neural_director.v:210$4417 +left shiftmul pattern in fpga_neural_v2_top: shift=$flatten\u_dataflow_core.\u_director.$shift$hardware/v2/rtl/neural_director.v:207$4395, mul=$flatten\u_dataflow_core.\u_director.$mul$hardware/v2/rtl/neural_director.v:210$4417 +shiftpow2 pattern in fpga_neural_v2_top: shift=$flatten\u_host_arb.$shiftx$hardware/v2/rtl/slot_mem_arbiter.v:163$7134, index=\u_host_arb.grant_idx [0], stride=16, width=16, ways=2 +shiftpow2 pattern in fpga_neural_v2_top: shift=$flatten\u_arbiter.$shiftx$hardware/v2/rtl/slot_mem_arbiter.v:163$7171, index=\u_arbiter.grant_idx, stride=16, width=16, ways=8 +shiftpow2 pattern in fpga_neural_v2_top: shift=$flatten\u_dataflow_core.$shiftx$hardware/v2/nms/rtl/nms_dataflow_core_sdram.v:154$7306, index=\u_dataflow_core.u_director.job_out_slot, stride=16, width=4, ways=4 +shiftpow2 pattern in fpga_neural_v2_top: shift=$flatten\u_sdram_backend.\u_sdram_ctrl.$shiftx$hardware/v2/nms/rtl/sdram_controller.v:426$7463, index=\u_sdram_backend.u_sdram_ctrl.burst_idx, stride=16, width=16, ways=8 +shiftpow2 pattern in fpga_neural_v2_top: shift=$flatten\u_sdram_backend.\u_sdram_ctrl.$shiftx$hardware/v2/nms/rtl/sdram_controller.v:427$7467, index=$auto$wreduce.cc:514:run$24881 [3:0], stride=2, width=2, ways=16 +shiftpow2 pattern in fpga_neural_v2_top: shift=$flatten\u_sdram_backend.$shiftx$hardware/v2/nms/rtl/sdram_unified_backend.v:306$7071, index=\u_sdram_backend.ar_pending_word, stride=16, width=16, ways=8 +shiftpow2 pattern in fpga_neural_v2_top: shift=$flatten\u_arbiter.$shiftx$hardware/v2/rtl/slot_mem_arbiter.v:162$7168, index=\u_arbiter.grant_idx, stride=32, width=23, ways=8 +shiftpow2 pattern in fpga_neural_v2_top: shift=$flatten\u_arbiter_wide.$shiftx$hardware/v2/rtl/slot_mem_arbiter_wide.v:163$7095, index=\u_arbiter_wide.grant_idx [1:0], stride=32, width=23, ways=4 +shiftpow2 pattern in fpga_neural_v2_top: shift=$flatten\u_host_arb.$shiftx$hardware/v2/rtl/slot_mem_arbiter.v:162$7131, index=\u_host_arb.grant_idx [0], stride=32, width=23, ways=2 + +19.17. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \fpga_neural_v2_top.. +Removed 5 unused cells and 45 unused wires. + + +19.18. Executing SHARE pass (SAT-based resource sharing). +Found 39 cells in module fpga_neural_v2_top that may be considered for resource sharing. + Analyzing resource sharing options for $flatten\u_sdram_backend.$shl$hardware/v2/nms/rtl/sdram_unified_backend.v:282$7036 ($shl): + Found 1 activation_patterns using ctrl signal { \u_sdram_backend.w_eff_req $flatten\u_sdram_backend.$logic_and$hardware/v2/nms/rtl/sdram_unified_backend.v:264$7029_Y $flatten\u_sdram_backend.$logic_and$hardware/v2/nms/rtl/sdram_unified_backend.v:272$7030_Y }. + Found 1 candidates: $flatten\u_sdram_backend.$shl$hardware/v2/nms/rtl/sdram_unified_backend.v:282$7032 + Analyzing resource sharing with $flatten\u_sdram_backend.$shl$hardware/v2/nms/rtl/sdram_unified_backend.v:282$7032 ($shl): + Found 1 activation_patterns using ctrl signal { \u_sdram_backend.w_eff_req $flatten\u_sdram_backend.$logic_and$hardware/v2/nms/rtl/sdram_unified_backend.v:264$7029_Y $flatten\u_sdram_backend.$logic_and$hardware/v2/nms/rtl/sdram_unified_backend.v:272$7030_Y }. + Activation pattern for cell $flatten\u_sdram_backend.$shl$hardware/v2/nms/rtl/sdram_unified_backend.v:282$7036: { \u_sdram_backend.w_eff_req $flatten\u_sdram_backend.$logic_and$hardware/v2/nms/rtl/sdram_unified_backend.v:264$7029_Y $flatten\u_sdram_backend.$logic_and$hardware/v2/nms/rtl/sdram_unified_backend.v:272$7030_Y } = 3'001 + Activation pattern for cell $flatten\u_sdram_backend.$shl$hardware/v2/nms/rtl/sdram_unified_backend.v:282$7032: { \u_sdram_backend.w_eff_req $flatten\u_sdram_backend.$logic_and$hardware/v2/nms/rtl/sdram_unified_backend.v:264$7029_Y $flatten\u_sdram_backend.$logic_and$hardware/v2/nms/rtl/sdram_unified_backend.v:272$7030_Y } = 3'001 + Size of SAT problem: 6 cells, 46 variables, 106 clauses + According to the SAT solver this pair of cells can not be shared. + Model from SAT solver: { \u_sdram_backend.w_eff_req $flatten\u_sdram_backend.$logic_and$hardware/v2/nms/rtl/sdram_unified_backend.v:264$7029_Y $flatten\u_sdram_backend.$logic_and$hardware/v2/nms/rtl/sdram_unified_backend.v:272$7030_Y } = 3'001 + Analyzing resource sharing options for $flatten\u_sdram_backend.$shl$hardware/v2/nms/rtl/sdram_unified_backend.v:282$7032 ($shl): + Found 1 activation_patterns using ctrl signal { \u_sdram_backend.w_eff_req $flatten\u_sdram_backend.$logic_and$hardware/v2/nms/rtl/sdram_unified_backend.v:264$7029_Y $flatten\u_sdram_backend.$logic_and$hardware/v2/nms/rtl/sdram_unified_backend.v:272$7030_Y }. + No candidates found. + Analyzing resource sharing options for $flatten\u_dataflow_core.\u_wgt_mem.$memrd$\GEN_SLOT[0].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:65$3825 ($memrd): + Found 1 activation_patterns using ctrl signal \u_dataflow_core.u_wgt_mem.GEN_SLOT[0].GEN_LANE[0].rd_bypass. + No candidates found. + Analyzing resource sharing options for $flatten\u_dataflow_core.\u_wgt_mem.$memrd$\GEN_SLOT[0].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:65$3836 ($memrd): + Found 1 activation_patterns using ctrl signal \u_dataflow_core.u_wgt_mem.GEN_SLOT[0].GEN_LANE[0].rd_bypass. + No candidates found. + Analyzing resource sharing options for $flatten\u_dataflow_core.\u_wgt_mem.$memrd$\GEN_SLOT[0].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:65$3847 ($memrd): + Found 1 activation_patterns using ctrl signal \u_dataflow_core.u_wgt_mem.GEN_SLOT[0].GEN_LANE[0].rd_bypass. + No candidates found. + Analyzing resource sharing options for $flatten\u_dataflow_core.\u_wgt_mem.$memrd$\GEN_SLOT[0].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:65$3858 ($memrd): + Found 1 activation_patterns using ctrl signal \u_dataflow_core.u_wgt_mem.GEN_SLOT[0].GEN_LANE[0].rd_bypass. + No candidates found. + Analyzing resource sharing options for $flatten\u_dataflow_core.\u_wgt_mem.$memrd$\GEN_SLOT[0].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:65$3869 ($memrd): + Found 1 activation_patterns using ctrl signal \u_dataflow_core.u_wgt_mem.GEN_SLOT[0].GEN_LANE[0].rd_bypass. + No candidates found. + Analyzing resource sharing options for $flatten\u_dataflow_core.\u_wgt_mem.$memrd$\GEN_SLOT[0].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:65$3880 ($memrd): + Found 1 activation_patterns using ctrl signal \u_dataflow_core.u_wgt_mem.GEN_SLOT[0].GEN_LANE[0].rd_bypass. + No candidates found. + Analyzing resource sharing options for $flatten\u_dataflow_core.\u_wgt_mem.$memrd$\GEN_SLOT[0].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:65$3891 ($memrd): + Found 1 activation_patterns using ctrl signal \u_dataflow_core.u_wgt_mem.GEN_SLOT[0].GEN_LANE[0].rd_bypass. + No candidates found. + Analyzing resource sharing options for $flatten\u_dataflow_core.\u_wgt_mem.$memrd$\GEN_SLOT[0].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:65$3902 ($memrd): + Found 1 activation_patterns using ctrl signal \u_dataflow_core.u_wgt_mem.GEN_SLOT[0].GEN_LANE[0].rd_bypass. + No candidates found. + Analyzing resource sharing options for $flatten\u_dataflow_core.\u_wgt_mem.$memrd$\GEN_SLOT[1].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:65$3913 ($memrd): + Found 1 activation_patterns using ctrl signal \u_dataflow_core.u_wgt_mem.GEN_SLOT[1].GEN_LANE[0].rd_bypass. + No candidates found. + Analyzing resource sharing options for $flatten\u_dataflow_core.\u_wgt_mem.$memrd$\GEN_SLOT[1].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:65$3924 ($memrd): + Found 1 activation_patterns using ctrl signal \u_dataflow_core.u_wgt_mem.GEN_SLOT[1].GEN_LANE[0].rd_bypass. + No candidates found. + Analyzing resource sharing options for $flatten\u_dataflow_core.\u_wgt_mem.$memrd$\GEN_SLOT[1].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:65$3935 ($memrd): + Found 1 activation_patterns using ctrl signal \u_dataflow_core.u_wgt_mem.GEN_SLOT[1].GEN_LANE[0].rd_bypass. + No candidates found. + Analyzing resource sharing options for $flatten\u_dataflow_core.\u_wgt_mem.$memrd$\GEN_SLOT[1].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:65$3946 ($memrd): + Found 1 activation_patterns using ctrl signal \u_dataflow_core.u_wgt_mem.GEN_SLOT[1].GEN_LANE[0].rd_bypass. + No candidates found. + Analyzing resource sharing options for $flatten\u_dataflow_core.\u_wgt_mem.$memrd$\GEN_SLOT[1].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:65$3957 ($memrd): + Found 1 activation_patterns using ctrl signal \u_dataflow_core.u_wgt_mem.GEN_SLOT[1].GEN_LANE[0].rd_bypass. + No candidates found. + Analyzing resource sharing options for $flatten\u_dataflow_core.\u_wgt_mem.$memrd$\GEN_SLOT[1].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:65$3968 ($memrd): + Found 1 activation_patterns using ctrl signal \u_dataflow_core.u_wgt_mem.GEN_SLOT[1].GEN_LANE[0].rd_bypass. + No candidates found. + Analyzing resource sharing options for $flatten\u_dataflow_core.\u_wgt_mem.$memrd$\GEN_SLOT[1].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:65$3979 ($memrd): + Found 1 activation_patterns using ctrl signal \u_dataflow_core.u_wgt_mem.GEN_SLOT[1].GEN_LANE[0].rd_bypass. + No candidates found. + Analyzing resource sharing options for $flatten\u_dataflow_core.\u_wgt_mem.$memrd$\GEN_SLOT[1].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:65$3990 ($memrd): + Found 1 activation_patterns using ctrl signal \u_dataflow_core.u_wgt_mem.GEN_SLOT[1].GEN_LANE[0].rd_bypass. + No candidates found. + Analyzing resource sharing options for $flatten\u_dataflow_core.\u_wgt_mem.$memrd$\GEN_SLOT[2].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:65$4001 ($memrd): + Found 1 activation_patterns using ctrl signal \u_dataflow_core.u_wgt_mem.GEN_SLOT[2].GEN_LANE[0].rd_bypass. + No candidates found. + Analyzing resource sharing options for $flatten\u_dataflow_core.\u_wgt_mem.$memrd$\GEN_SLOT[2].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:65$4012 ($memrd): + Found 1 activation_patterns using ctrl signal \u_dataflow_core.u_wgt_mem.GEN_SLOT[2].GEN_LANE[0].rd_bypass. + No candidates found. + Analyzing resource sharing options for $flatten\u_dataflow_core.\u_wgt_mem.$memrd$\GEN_SLOT[2].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:65$4023 ($memrd): + Found 1 activation_patterns using ctrl signal \u_dataflow_core.u_wgt_mem.GEN_SLOT[2].GEN_LANE[0].rd_bypass. + No candidates found. + Analyzing resource sharing options for $flatten\u_dataflow_core.\u_wgt_mem.$memrd$\GEN_SLOT[2].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:65$4034 ($memrd): + Found 1 activation_patterns using ctrl signal \u_dataflow_core.u_wgt_mem.GEN_SLOT[2].GEN_LANE[0].rd_bypass. + No candidates found. + Analyzing resource sharing options for $flatten\u_dataflow_core.\u_wgt_mem.$memrd$\GEN_SLOT[2].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:65$4045 ($memrd): + Found 1 activation_patterns using ctrl signal \u_dataflow_core.u_wgt_mem.GEN_SLOT[2].GEN_LANE[0].rd_bypass. + No candidates found. + Analyzing resource sharing options for $flatten\u_dataflow_core.\u_wgt_mem.$memrd$\GEN_SLOT[2].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:65$4056 ($memrd): + Found 1 activation_patterns using ctrl signal \u_dataflow_core.u_wgt_mem.GEN_SLOT[2].GEN_LANE[0].rd_bypass. + No candidates found. + Analyzing resource sharing options for $flatten\u_dataflow_core.\u_wgt_mem.$memrd$\GEN_SLOT[2].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:65$4067 ($memrd): + Found 1 activation_patterns using ctrl signal \u_dataflow_core.u_wgt_mem.GEN_SLOT[2].GEN_LANE[0].rd_bypass. + No candidates found. + Analyzing resource sharing options for $flatten\u_dataflow_core.\u_wgt_mem.$memrd$\GEN_SLOT[2].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:65$4078 ($memrd): + Found 1 activation_patterns using ctrl signal \u_dataflow_core.u_wgt_mem.GEN_SLOT[2].GEN_LANE[0].rd_bypass. + No candidates found. + Analyzing resource sharing options for $flatten\u_dataflow_core.\u_wgt_mem.$memrd$\GEN_SLOT[3].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:65$4089 ($memrd): + Found 1 activation_patterns using ctrl signal \u_dataflow_core.u_wgt_mem.GEN_SLOT[3].GEN_LANE[0].rd_bypass. + No candidates found. + Analyzing resource sharing options for $flatten\u_dataflow_core.\u_wgt_mem.$memrd$\GEN_SLOT[3].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:65$4100 ($memrd): + Found 1 activation_patterns using ctrl signal \u_dataflow_core.u_wgt_mem.GEN_SLOT[3].GEN_LANE[0].rd_bypass. + No candidates found. + Analyzing resource sharing options for $flatten\u_dataflow_core.\u_wgt_mem.$memrd$\GEN_SLOT[3].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:65$4111 ($memrd): + Found 1 activation_patterns using ctrl signal \u_dataflow_core.u_wgt_mem.GEN_SLOT[3].GEN_LANE[0].rd_bypass. + No candidates found. + Analyzing resource sharing options for $flatten\u_dataflow_core.\u_wgt_mem.$memrd$\GEN_SLOT[3].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:65$4122 ($memrd): + Found 1 activation_patterns using ctrl signal \u_dataflow_core.u_wgt_mem.GEN_SLOT[3].GEN_LANE[0].rd_bypass. + No candidates found. + Analyzing resource sharing options for $flatten\u_dataflow_core.\u_wgt_mem.$memrd$\GEN_SLOT[3].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:65$4133 ($memrd): + Found 1 activation_patterns using ctrl signal \u_dataflow_core.u_wgt_mem.GEN_SLOT[3].GEN_LANE[0].rd_bypass. + No candidates found. + Analyzing resource sharing options for $flatten\u_dataflow_core.\u_wgt_mem.$memrd$\GEN_SLOT[3].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:65$4144 ($memrd): + Found 1 activation_patterns using ctrl signal \u_dataflow_core.u_wgt_mem.GEN_SLOT[3].GEN_LANE[0].rd_bypass. + No candidates found. + Analyzing resource sharing options for $flatten\u_dataflow_core.\u_wgt_mem.$memrd$\GEN_SLOT[3].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:65$4155 ($memrd): + Found 1 activation_patterns using ctrl signal \u_dataflow_core.u_wgt_mem.GEN_SLOT[3].GEN_LANE[0].rd_bypass. + No candidates found. + Analyzing resource sharing options for $flatten\u_dataflow_core.\u_wgt_mem.$memrd$\GEN_SLOT[3].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:65$4166 ($memrd): + Found 1 activation_patterns using ctrl signal \u_dataflow_core.u_wgt_mem.GEN_SLOT[3].GEN_LANE[0].rd_bypass. + No candidates found. + Analyzing resource sharing options for $flatten\u_dataflow_core.\u_act_mem.$memrd$\GEN_COPY[0].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:77$4222 ($memrd): + Found 1 activation_patterns using ctrl signal \u_dataflow_core.u_act_mem.GEN_COPY[0].rd_bypass. + No candidates found. + Analyzing resource sharing options for $flatten\u_dataflow_core.\u_act_mem.$memrd$\GEN_COPY[1].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:77$4233 ($memrd): + Found 1 activation_patterns using ctrl signal \u_dataflow_core.u_act_mem.GEN_COPY[1].rd_bypass. + No candidates found. + Analyzing resource sharing options for $flatten\u_dataflow_core.\u_act_mem.$memrd$\GEN_COPY[2].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:77$4244 ($memrd): + Found 1 activation_patterns using ctrl signal \u_dataflow_core.u_act_mem.GEN_COPY[2].rd_bypass. + No candidates found. + Analyzing resource sharing options for $flatten\u_dataflow_core.\u_act_mem.$memrd$\GEN_COPY[3].mem$hardware/v2/nms/rtl/nms_activation_replicated.v:77$4255 ($memrd): + Found 1 activation_patterns using ctrl signal \u_dataflow_core.u_act_mem.GEN_COPY[3].rd_bypass. + No candidates found. + Analyzing resource sharing options for $flatten\u_sdram_backend.$memrd$\w_cache_data$hardware/v2/nms/rtl/sdram_unified_backend.v:251$7027 ($memrd): + Found 1 activation_patterns using ctrl signal { \u_sdram_backend.w_cache_hit \u_sdram_backend.state [0] }. + No candidates found. + +19.19. Executing TECHMAP pass (map to technology primitives). + +19.19.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/cmp2lut.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/cmp2lut.v' to AST representation. +Generating RTLIL representation for module `\_90_lut_cmp_'. +Successfully finished Verilog frontend. + +19.19.2. Continuing TECHMAP pass. +Using template $paramod$4a6470414f44d7bfc80a561af8ae86943c9d8e44\_90_lut_cmp_ for cells of type $lt. +Using template $paramod$b33ffabab7f76e9eea93de0eb72e92e30b4f65b6\_90_lut_cmp_ for cells of type $lt. +Using template $paramod$00b6cfa7627efb096a4db0169df5297bfaf657d7\_90_lut_cmp_ for cells of type $lt. +Using template $paramod$21bd1e49a66742dbdaaf45a85521ce9d28e5f3df\_90_lut_cmp_ for cells of type $lt. +Using template $paramod$abbd0fbc0c55d077183371692babaf3e6a982c6e\_90_lut_cmp_ for cells of type $lt. +Using template $paramod$254ef1516958dd5ebf9155b08a85a11a24f732fb\_90_lut_cmp_ for cells of type $lt. +No more expansions possible. + + +19.20. Executing OPT_EXPR pass (perform const folding). +Optimizing module fpga_neural_v2_top. + +19.21. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \fpga_neural_v2_top.. +Removed 0 unused cells and 198 unused wires. + + +19.22. Executing TECHMAP pass (map to technology primitives). + +19.22.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/mul2dsp.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/mul2dsp.v' to AST representation. +Generating RTLIL representation for module `\_80_mul'. +Generating RTLIL representation for module `\_90_soft_mul'. +Successfully finished Verilog frontend. + +19.22.2. Continuing TECHMAP pass. +Using template $paramod$cc733e0dbb038034434917c1e0de96998ec4103f\_80_mul for cells of type $mul. +No more expansions possible. + + +19.23. Executing TECHMAP pass (map to technology primitives). + +19.23.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v' to AST representation. +Generating RTLIL representation for module `$__MUL18X18'. +Successfully finished Verilog frontend. + +19.23.2. Continuing TECHMAP pass. +Using template $paramod$ea686d7c43b0ae12a4f0d39aec4e01bcc4449b23$__MUL18X18 for cells of type $__MUL18X18. +No more expansions possible. + + +19.24. Executing ALUMACC pass (create $alu and $macc cells). +Extracting $alu and $macc cells in module fpga_neural_v2_top: + creating $macc model for $flatten\u_sdram_backend.$sub$hardware/v2/nms/rtl/sdram_unified_backend.v:292$7064 ($sub). + creating $macc model for $flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:154$6644 ($add). + creating $macc model for $flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:154$6570 ($add). + creating $macc model for $flatten\u_arbiter.$add$hardware/v2/rtl/slot_mem_arbiter.v:157$7162 ($add). + creating $macc model for $auto$peepopt_pm.h:1040:block_9$24910 ($neg). + creating $macc model for $flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:154$6496 ($add). + creating $macc model for $flatten\u_arbiter.$neg$hardware/v2/rtl/slot_mem_arbiter.v:164$7172 ($neg). + creating $macc model for $flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:154$6422 ($add). + creating $macc model for $flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:154$6348 ($add). + creating $macc model for $flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:154$6274 ($add). + creating $macc model for $flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:154$6200 ($add). + creating $macc model for $flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:154$6126 ($add). + creating $macc model for $flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:154$6052 ($add). + creating $macc model for $flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:154$5978 ($add). + creating $macc model for $flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:154$5904 ($add). + creating $macc model for $flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:154$5830 ($add). + creating $macc model for $flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:154$5756 ($add). + creating $macc model for $flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:154$5682 ($add). + creating $macc model for $flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:154$5608 ($add). + creating $macc model for $flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:154$5534 ($add). + creating $macc model for $flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:136$5266 ($add). + creating $macc model for $flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:136$5264 ($add). + creating $macc model for $flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:136$5262 ($add). + creating $macc model for $flatten\u_host_arb.$neg$hardware/v2/rtl/slot_mem_arbiter.v:164$7135 ($neg). + creating $macc model for $flatten\u_dataflow_core.\u_director.$sub$hardware/v2/rtl/neural_director.v:231$4453 ($sub). + creating $macc model for $flatten\u_dataflow_core.\u_director.$add$hardware/v2/rtl/neural_director.v:230$4452 ($add). + creating $macc model for $flatten\u_dataflow_core.\u_director.$add$hardware/v2/rtl/neural_director.v:213$4445 ($add). + creating $macc model for $flatten\u_dataflow_core.\u_director.$neg$hardware/v2/rtl/neural_director.v:212$4441 ($neg). + creating $macc model for $flatten\u_dataflow_core.\u_director.$neg$hardware/v2/rtl/neural_director.v:211$4434 ($neg). + creating $macc model for $auto$peepopt_pm.h:1040:block_9$24913 ($neg). + creating $macc model for $auto$peepopt_pm.h:1040:block_9$24916 ($neg). + creating $macc model for $flatten\u_dataflow_core.\u_director.$add$hardware/v2/rtl/neural_director.v:168$4359 ($add). + creating $macc model for $flatten\u_dataflow_core.\u_act_fill.\u_pf.$neg$hardware/v2/rtl/prefetch_engine.v:115$6850 ($neg). + creating $macc model for $flatten\u_dataflow_core.\u_act_fill.\u_pf.$add$hardware/v2/rtl/prefetch_engine.v:119$6858 ($add). + creating $macc model for $flatten\u_dataflow_core.\u_act_fill.\u_pf.$add$hardware/v2/rtl/prefetch_engine.v:122$6859 ($add). + creating $macc model for $flatten\u_dataflow_core.\u_act_fill.\u_pf.$add$hardware/v2/rtl/prefetch_engine.v:122$6860 ($add). + creating $macc model for $flatten\u_dataflow_core.\u_act_fill.$add$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:207$4192 ($add). + creating $macc model for $flatten\u_dataflow_core.\u_act_fill.$add$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:181$4176 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:133$6817 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:134$6818 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:139$6824 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:139$6826 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:143$6827 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:150$6829 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:151$6830 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:150$6832 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:103$6790 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$add$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:264$3779 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$sub$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:263$3777 ($sub). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$add$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:251$3776 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$add$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:247$3774 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$add$hardware/v2/rtl/neural_processor.v:197$3733 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$add$hardware/v2/rtl/neural_processor.v:197$3730 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$add$hardware/v2/rtl/neural_processor.v:197$3728 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3725 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3723 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3721 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3719 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$add$hardware/v2/rtl/neural_processor.v:226$3688 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:133$6817 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:134$6818 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:139$6824 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:139$6826 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:143$6827 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:150$6829 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:151$6830 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:150$6832 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:103$6790 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$add$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:264$3779 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$sub$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:263$3777 ($sub). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$add$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:251$3776 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$add$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:247$3774 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$add$hardware/v2/rtl/neural_processor.v:197$3733 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$add$hardware/v2/rtl/neural_processor.v:197$3730 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$add$hardware/v2/rtl/neural_processor.v:197$3728 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3725 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3723 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3721 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3719 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$add$hardware/v2/rtl/neural_processor.v:226$3688 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:133$6817 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:134$6818 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:139$6824 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:139$6826 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:143$6827 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:150$6829 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:151$6830 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:150$6832 ($add). + creating $macc model for $flatten\u_arbiter_wide.$neg$hardware/v2/rtl/slot_mem_arbiter_wide.v:165$7103 ($neg). + creating $macc model for $flatten\u_sdram_backend.$add$hardware/v2/nms/rtl/sdram_unified_backend.v:296$7065 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:103$6790 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$add$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:264$3779 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$sub$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:263$3777 ($sub). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$add$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:251$3776 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$add$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:247$3774 ($add). + creating $macc model for $flatten\u_arbiter_wide.$add$hardware/v2/rtl/slot_mem_arbiter_wide.v:158$7089 ($add). + creating $macc model for $flatten\u_sdram_backend.\u_sdram_ctrl.$sub$hardware/v2/nms/rtl/sdram_controller.v:224$7423 ($sub). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$add$hardware/v2/rtl/neural_processor.v:197$3733 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$add$hardware/v2/rtl/neural_processor.v:197$3730 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$add$hardware/v2/rtl/neural_processor.v:197$3728 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3725 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3723 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3721 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3719 ($add). + creating $macc model for $flatten\u_sdram_backend.\u_sdram_ctrl.$sub$hardware/v2/nms/rtl/sdram_controller.v:256$7427 ($sub). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$add$hardware/v2/rtl/neural_processor.v:226$3688 ($add). + creating $macc model for $flatten\u_sdram_backend.\u_sdram_ctrl.$add$hardware/v2/nms/rtl/sdram_controller.v:280$7433 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:133$6817 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:134$6818 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:139$6824 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:139$6826 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:143$6827 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:150$6829 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:151$6830 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:150$6832 ($add). + creating $macc model for $flatten\u_sdram_backend.\u_sdram_ctrl.$add$hardware/v2/nms/rtl/sdram_controller.v:397$7446 ($add). + creating $macc model for $flatten\u_sdram_backend.\u_sdram_ctrl.$neg$hardware/v2/nms/rtl/sdram_controller.v:410$7449 ($neg). + creating $macc model for $flatten\u_sdram_backend.\u_sdram_ctrl.$add$hardware/v2/nms/rtl/sdram_controller.v:426$7460 ($add). + creating $macc model for $flatten\u_sdram_backend.$add$hardware/v2/nms/rtl/sdram_unified_backend.v:299$7067 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:103$6790 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$add$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:264$3779 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$sub$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:263$3777 ($sub). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$add$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:251$3776 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$add$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:247$3774 ($add). + creating $macc model for $auto$peepopt_pm.h:1040:block_9$24907 ($neg). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$add$hardware/v2/rtl/neural_processor.v:197$3733 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$add$hardware/v2/rtl/neural_processor.v:197$3730 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$add$hardware/v2/rtl/neural_processor.v:197$3728 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3725 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3723 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3721 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3719 ($add). + creating $macc model for $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$add$hardware/v2/rtl/neural_processor.v:226$3688 ($add). + creating $macc model for $flatten\u_spi_bridge.$add$hardware/v2/rtl/spi_host_bridge.v:208$7333 ($add). + creating $macc model for $flatten\u_spi_bridge.$sub$hardware/v2/rtl/spi_host_bridge.v:211$7336 ($sub). + creating $macc model for $flatten\u_spi_bridge.$add$hardware/v2/rtl/spi_host_bridge.v:333$7355 ($add). + creating $macc model for $flatten\u_spi_bridge.$add$hardware/v2/rtl/spi_host_bridge.v:391$7373 ($add). + creating $macc model for $flatten\u_spi_bridge.$sub$hardware/v2/rtl/spi_host_bridge.v:392$7374 ($sub). + creating $macc model for $flatten\u_host_arb.$add$hardware/v2/rtl/slot_mem_arbiter.v:157$7125 ($add). + merging $macc model for $flatten\u_dataflow_core.\u_act_fill.\u_pf.$add$hardware/v2/rtl/prefetch_engine.v:122$6859 into $flatten\u_dataflow_core.\u_act_fill.\u_pf.$add$hardware/v2/rtl/prefetch_engine.v:122$6860. + creating $alu model for $macc $flatten\u_spi_bridge.$sub$hardware/v2/rtl/spi_host_bridge.v:392$7374. + creating $alu model for $macc $flatten\u_spi_bridge.$add$hardware/v2/rtl/spi_host_bridge.v:391$7373. + creating $alu model for $macc $flatten\u_spi_bridge.$add$hardware/v2/rtl/spi_host_bridge.v:333$7355. + creating $alu model for $macc $flatten\u_spi_bridge.$sub$hardware/v2/rtl/spi_host_bridge.v:211$7336. + creating $alu model for $macc $flatten\u_spi_bridge.$add$hardware/v2/rtl/spi_host_bridge.v:208$7333. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$add$hardware/v2/rtl/neural_processor.v:226$3688. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3719. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3721. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3723. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3725. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$add$hardware/v2/rtl/neural_processor.v:197$3728. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$add$hardware/v2/rtl/neural_processor.v:197$3730. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$add$hardware/v2/rtl/neural_processor.v:197$3733. + creating $alu model for $macc $auto$peepopt_pm.h:1040:block_9$24907. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$add$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:247$3774. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$add$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:251$3776. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$sub$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:263$3777. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$add$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:264$3779. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:103$6790. + creating $alu model for $macc $flatten\u_sdram_backend.$add$hardware/v2/nms/rtl/sdram_unified_backend.v:299$7067. + creating $alu model for $macc $flatten\u_sdram_backend.\u_sdram_ctrl.$add$hardware/v2/nms/rtl/sdram_controller.v:426$7460. + creating $alu model for $macc $flatten\u_sdram_backend.\u_sdram_ctrl.$neg$hardware/v2/nms/rtl/sdram_controller.v:410$7449. + creating $alu model for $macc $flatten\u_sdram_backend.\u_sdram_ctrl.$add$hardware/v2/nms/rtl/sdram_controller.v:397$7446. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:150$6832. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:151$6830. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:150$6829. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:143$6827. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:139$6826. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:139$6824. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:134$6818. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:133$6817. + creating $alu model for $macc $flatten\u_sdram_backend.\u_sdram_ctrl.$add$hardware/v2/nms/rtl/sdram_controller.v:280$7433. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$add$hardware/v2/rtl/neural_processor.v:226$3688. + creating $alu model for $macc $flatten\u_sdram_backend.\u_sdram_ctrl.$sub$hardware/v2/nms/rtl/sdram_controller.v:256$7427. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3719. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3721. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3723. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3725. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$add$hardware/v2/rtl/neural_processor.v:197$3728. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$add$hardware/v2/rtl/neural_processor.v:197$3730. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$add$hardware/v2/rtl/neural_processor.v:197$3733. + creating $alu model for $macc $flatten\u_sdram_backend.\u_sdram_ctrl.$sub$hardware/v2/nms/rtl/sdram_controller.v:224$7423. + creating $alu model for $macc $flatten\u_arbiter_wide.$add$hardware/v2/rtl/slot_mem_arbiter_wide.v:158$7089. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$add$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:247$3774. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$add$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:251$3776. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$sub$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:263$3777. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$add$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:264$3779. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:103$6790. + creating $alu model for $macc $flatten\u_sdram_backend.$add$hardware/v2/nms/rtl/sdram_unified_backend.v:296$7065. + creating $alu model for $macc $flatten\u_arbiter_wide.$neg$hardware/v2/rtl/slot_mem_arbiter_wide.v:165$7103. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:150$6832. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:151$6830. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:150$6829. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:143$6827. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:139$6826. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:139$6824. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:134$6818. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:133$6817. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$add$hardware/v2/rtl/neural_processor.v:226$3688. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3719. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3721. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3723. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3725. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$add$hardware/v2/rtl/neural_processor.v:197$3728. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$add$hardware/v2/rtl/neural_processor.v:197$3730. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$add$hardware/v2/rtl/neural_processor.v:197$3733. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$add$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:247$3774. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$add$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:251$3776. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$sub$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:263$3777. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$add$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:264$3779. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:103$6790. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:150$6832. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:151$6830. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:150$6829. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:143$6827. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:139$6826. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:139$6824. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:134$6818. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:133$6817. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$add$hardware/v2/rtl/neural_processor.v:226$3688. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3719. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3721. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3723. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3725. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$add$hardware/v2/rtl/neural_processor.v:197$3728. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$add$hardware/v2/rtl/neural_processor.v:197$3730. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$add$hardware/v2/rtl/neural_processor.v:197$3733. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$add$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:247$3774. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$add$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:251$3776. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$sub$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:263$3777. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$add$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:264$3779. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:103$6790. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:150$6832. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:151$6830. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:150$6829. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:143$6827. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:139$6826. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:139$6824. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:134$6818. + creating $alu model for $macc $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:133$6817. + creating $alu model for $macc $flatten\u_dataflow_core.\u_act_fill.$add$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:181$4176. + creating $alu model for $macc $flatten\u_dataflow_core.\u_act_fill.$add$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:207$4192. + creating $alu model for $macc $flatten\u_dataflow_core.\u_act_fill.\u_pf.$add$hardware/v2/rtl/prefetch_engine.v:122$6860. + creating $alu model for $macc $flatten\u_host_arb.$add$hardware/v2/rtl/slot_mem_arbiter.v:157$7125. + creating $alu model for $macc $flatten\u_dataflow_core.\u_act_fill.\u_pf.$add$hardware/v2/rtl/prefetch_engine.v:119$6858. + creating $alu model for $macc $flatten\u_dataflow_core.\u_act_fill.\u_pf.$neg$hardware/v2/rtl/prefetch_engine.v:115$6850. + creating $alu model for $macc $flatten\u_dataflow_core.\u_director.$add$hardware/v2/rtl/neural_director.v:168$4359. + creating $alu model for $macc $auto$peepopt_pm.h:1040:block_9$24916. + creating $alu model for $macc $auto$peepopt_pm.h:1040:block_9$24913. + creating $alu model for $macc $flatten\u_dataflow_core.\u_director.$neg$hardware/v2/rtl/neural_director.v:211$4434. + creating $alu model for $macc $flatten\u_dataflow_core.\u_director.$neg$hardware/v2/rtl/neural_director.v:212$4441. + creating $alu model for $macc $flatten\u_dataflow_core.\u_director.$add$hardware/v2/rtl/neural_director.v:213$4445. + creating $alu model for $macc $flatten\u_dataflow_core.\u_director.$add$hardware/v2/rtl/neural_director.v:230$4452. + creating $alu model for $macc $flatten\u_dataflow_core.\u_director.$sub$hardware/v2/rtl/neural_director.v:231$4453. + creating $alu model for $macc $flatten\u_host_arb.$neg$hardware/v2/rtl/slot_mem_arbiter.v:164$7135. + creating $alu model for $macc $flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:136$5262. + creating $alu model for $macc $flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:136$5264. + creating $alu model for $macc $flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:136$5266. + creating $alu model for $macc $flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:154$5534. + creating $alu model for $macc $flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:154$5608. + creating $alu model for $macc $flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:154$5682. + creating $alu model for $macc $flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:154$5756. + creating $alu model for $macc $flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:154$5830. + creating $alu model for $macc $flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:154$5904. + creating $alu model for $macc $flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:154$5978. + creating $alu model for $macc $flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:154$6052. + creating $alu model for $macc $flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:154$6126. + creating $alu model for $macc $flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:154$6200. + creating $alu model for $macc $flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:154$6274. + creating $alu model for $macc $flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:154$6348. + creating $alu model for $macc $flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:154$6422. + creating $alu model for $macc $flatten\u_arbiter.$neg$hardware/v2/rtl/slot_mem_arbiter.v:164$7172. + creating $alu model for $macc $flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:154$6496. + creating $alu model for $macc $auto$peepopt_pm.h:1040:block_9$24910. + creating $alu model for $macc $flatten\u_arbiter.$add$hardware/v2/rtl/slot_mem_arbiter.v:157$7162. + creating $alu model for $macc $flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:154$6570. + creating $alu model for $macc $flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:154$6644. + creating $alu model for $macc $flatten\u_sdram_backend.$sub$hardware/v2/nms/rtl/sdram_unified_backend.v:292$7064. + creating $alu model for $flatten\u_dataflow_core.\u_dep_mgr.$ge$hardware/v2/rtl/dependency_manager.v:152$6641 ($ge): new $alu + creating $alu model for $flatten\u_dataflow_core.\u_dep_mgr.$ge$hardware/v2/rtl/dependency_manager.v:152$6567 ($ge): new $alu + creating $alu model for $flatten\u_dataflow_core.\u_dep_mgr.$ge$hardware/v2/rtl/dependency_manager.v:152$6493 ($ge): new $alu + creating $alu model for $flatten\u_dataflow_core.\u_dep_mgr.$ge$hardware/v2/rtl/dependency_manager.v:152$6419 ($ge): new $alu + creating $alu model for $flatten\u_dataflow_core.\u_dep_mgr.$ge$hardware/v2/rtl/dependency_manager.v:152$6345 ($ge): new $alu + creating $alu model for $flatten\u_dataflow_core.\u_dep_mgr.$ge$hardware/v2/rtl/dependency_manager.v:152$6271 ($ge): new $alu + creating $alu model for $flatten\u_dataflow_core.\u_dep_mgr.$ge$hardware/v2/rtl/dependency_manager.v:152$6197 ($ge): new $alu + creating $alu model for $flatten\u_dataflow_core.\u_dep_mgr.$ge$hardware/v2/rtl/dependency_manager.v:152$6123 ($ge): new $alu + creating $alu model for $flatten\u_dataflow_core.\u_dep_mgr.$ge$hardware/v2/rtl/dependency_manager.v:152$6049 ($ge): new $alu + creating $alu model for $flatten\u_dataflow_core.\u_dep_mgr.$ge$hardware/v2/rtl/dependency_manager.v:152$5975 ($ge): new $alu + creating $alu model for $flatten\u_dataflow_core.\u_dep_mgr.$ge$hardware/v2/rtl/dependency_manager.v:152$5901 ($ge): new $alu + creating $alu model for $flatten\u_dataflow_core.\u_dep_mgr.$ge$hardware/v2/rtl/dependency_manager.v:152$5827 ($ge): new $alu + creating $alu model for $flatten\u_dataflow_core.\u_dep_mgr.$ge$hardware/v2/rtl/dependency_manager.v:152$5753 ($ge): new $alu + creating $alu model for $flatten\u_dataflow_core.\u_dep_mgr.$ge$hardware/v2/rtl/dependency_manager.v:152$5679 ($ge): new $alu + creating $alu model for $flatten\u_dataflow_core.\u_dep_mgr.$ge$hardware/v2/rtl/dependency_manager.v:152$5605 ($ge): new $alu + creating $alu model for $flatten\u_dataflow_core.\u_dep_mgr.$ge$hardware/v2/rtl/dependency_manager.v:152$5531 ($ge): new $alu + creating $alu model for $flatten\u_dataflow_core.\u_act_fill.$gt$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:129$4170 ($gt): new $alu + creating $alu model for $flatten\u_dataflow_core.\u_act_fill.$lt$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:204$4186 ($lt): new $alu + creating $alu model for $flatten\u_dataflow_core.\u_act_fill.$gt$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:129$4173 ($gt): new $alu + creating $alu model for $flatten\u_dataflow_core.\u_act_fill.$gt$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:129$4172 ($gt): new $alu + creating $alu model for $flatten\u_dataflow_core.\u_act_fill.$gt$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:129$4171 ($gt): new $alu + creating $alu model for $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$lt$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:105$6791 ($lt): new $alu + creating $alu model for $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$lt$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:106$6793 ($lt): new $alu + creating $alu model for $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$lt$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:136$6820 ($lt): new $alu + creating $alu model for $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$lt$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:137$6822 ($lt): new $alu + creating $alu model for $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$lt$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:173$3763 ($lt): new $alu + creating $alu model for $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$lt$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:172$3761 ($lt): new $alu + creating $alu model for $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$lt$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:171$3760 ($lt): new $alu + creating $alu model for $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$lt$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:105$6791 ($lt): new $alu + creating $alu model for $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$lt$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:106$6793 ($lt): new $alu + creating $alu model for $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$lt$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:136$6820 ($lt): new $alu + creating $alu model for $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$lt$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:137$6822 ($lt): new $alu + creating $alu model for $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$lt$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:173$3763 ($lt): new $alu + creating $alu model for $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$lt$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:172$3761 ($lt): new $alu + creating $alu model for $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$lt$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:171$3760 ($lt): new $alu + creating $alu model for $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$lt$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:105$6791 ($lt): new $alu + creating $alu model for $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$lt$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:106$6793 ($lt): new $alu + creating $alu model for $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$lt$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:136$6820 ($lt): new $alu + creating $alu model for $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$lt$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:137$6822 ($lt): new $alu + creating $alu model for $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$lt$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:173$3763 ($lt): new $alu + creating $alu model for $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$lt$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:172$3761 ($lt): new $alu + creating $alu model for $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$lt$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:171$3760 ($lt): new $alu + creating $alu model for $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$lt$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:105$6791 ($lt): new $alu + creating $alu model for $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$lt$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:106$6793 ($lt): new $alu + creating $alu model for $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$lt$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:136$6820 ($lt): new $alu + creating $alu model for $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$lt$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:137$6822 ($lt): new $alu + creating $alu model for $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$lt$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:173$3763 ($lt): new $alu + creating $alu model for $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$lt$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:172$3761 ($lt): new $alu + creating $alu model for $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$lt$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:171$3760 ($lt): new $alu + creating $alu model for $flatten\u_spi_bridge.$eq$hardware/v2/rtl/spi_host_bridge.v:203$7332 ($eq): merged with $flatten\u_spi_bridge.$sub$hardware/v2/rtl/spi_host_bridge.v:211$7336. + creating $alu model for $flatten\u_spi_bridge.$eq$hardware/v2/rtl/spi_host_bridge.v:394$7375 ($eq): merged with $flatten\u_spi_bridge.$sub$hardware/v2/rtl/spi_host_bridge.v:392$7374. + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$lt$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:171$3760: $auto$alumacc.cc:548:replace_alu$25112 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$lt$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:172$3761: $auto$alumacc.cc:548:replace_alu$25117 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$lt$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:173$3763: $auto$alumacc.cc:548:replace_alu$25122 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$lt$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:137$6822: $auto$alumacc.cc:548:replace_alu$25127 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$lt$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:136$6820: $auto$alumacc.cc:548:replace_alu$25132 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$lt$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:106$6793: $auto$alumacc.cc:548:replace_alu$25137 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$lt$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:105$6791: $auto$alumacc.cc:548:replace_alu$25142 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$lt$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:171$3760: $auto$alumacc.cc:548:replace_alu$25147 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$lt$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:172$3761: $auto$alumacc.cc:548:replace_alu$25152 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$lt$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:173$3763: $auto$alumacc.cc:548:replace_alu$25157 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$lt$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:137$6822: $auto$alumacc.cc:548:replace_alu$25162 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$lt$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:136$6820: $auto$alumacc.cc:548:replace_alu$25167 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$lt$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:106$6793: $auto$alumacc.cc:548:replace_alu$25172 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$lt$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:105$6791: $auto$alumacc.cc:548:replace_alu$25177 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$lt$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:171$3760: $auto$alumacc.cc:548:replace_alu$25182 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$lt$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:172$3761: $auto$alumacc.cc:548:replace_alu$25187 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$lt$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:173$3763: $auto$alumacc.cc:548:replace_alu$25192 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$lt$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:137$6822: $auto$alumacc.cc:548:replace_alu$25197 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$lt$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:136$6820: $auto$alumacc.cc:548:replace_alu$25202 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$lt$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:106$6793: $auto$alumacc.cc:548:replace_alu$25207 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$lt$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:105$6791: $auto$alumacc.cc:548:replace_alu$25212 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$lt$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:171$3760: $auto$alumacc.cc:548:replace_alu$25217 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$lt$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:172$3761: $auto$alumacc.cc:548:replace_alu$25222 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$lt$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:173$3763: $auto$alumacc.cc:548:replace_alu$25227 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$lt$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:137$6822: $auto$alumacc.cc:548:replace_alu$25232 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$lt$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:136$6820: $auto$alumacc.cc:548:replace_alu$25237 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$lt$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:106$6793: $auto$alumacc.cc:548:replace_alu$25242 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$lt$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:105$6791: $auto$alumacc.cc:548:replace_alu$25247 + creating $alu cell for $flatten\u_dataflow_core.\u_act_fill.$gt$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:129$4171: $auto$alumacc.cc:548:replace_alu$25252 + creating $alu cell for $flatten\u_dataflow_core.\u_act_fill.$gt$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:129$4172: $auto$alumacc.cc:548:replace_alu$25263 + creating $alu cell for $flatten\u_dataflow_core.\u_act_fill.$gt$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:129$4173: $auto$alumacc.cc:548:replace_alu$25274 + creating $alu cell for $flatten\u_dataflow_core.\u_act_fill.$lt$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:204$4186: $auto$alumacc.cc:548:replace_alu$25285 + creating $alu cell for $flatten\u_dataflow_core.\u_act_fill.$gt$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:129$4170: $auto$alumacc.cc:548:replace_alu$25290 + creating $alu cell for $flatten\u_dataflow_core.\u_dep_mgr.$ge$hardware/v2/rtl/dependency_manager.v:152$5531: $auto$alumacc.cc:548:replace_alu$25301 + creating $alu cell for $flatten\u_dataflow_core.\u_dep_mgr.$ge$hardware/v2/rtl/dependency_manager.v:152$5605: $auto$alumacc.cc:548:replace_alu$25314 + creating $alu cell for $flatten\u_dataflow_core.\u_dep_mgr.$ge$hardware/v2/rtl/dependency_manager.v:152$5679: $auto$alumacc.cc:548:replace_alu$25327 + creating $alu cell for $flatten\u_dataflow_core.\u_dep_mgr.$ge$hardware/v2/rtl/dependency_manager.v:152$5753: $auto$alumacc.cc:548:replace_alu$25340 + creating $alu cell for $flatten\u_dataflow_core.\u_dep_mgr.$ge$hardware/v2/rtl/dependency_manager.v:152$5827: $auto$alumacc.cc:548:replace_alu$25353 + creating $alu cell for $flatten\u_dataflow_core.\u_dep_mgr.$ge$hardware/v2/rtl/dependency_manager.v:152$5901: $auto$alumacc.cc:548:replace_alu$25366 + creating $alu cell for $flatten\u_dataflow_core.\u_dep_mgr.$ge$hardware/v2/rtl/dependency_manager.v:152$5975: $auto$alumacc.cc:548:replace_alu$25379 + creating $alu cell for $flatten\u_dataflow_core.\u_dep_mgr.$ge$hardware/v2/rtl/dependency_manager.v:152$6049: $auto$alumacc.cc:548:replace_alu$25392 + creating $alu cell for $flatten\u_dataflow_core.\u_dep_mgr.$ge$hardware/v2/rtl/dependency_manager.v:152$6123: $auto$alumacc.cc:548:replace_alu$25405 + creating $alu cell for $flatten\u_dataflow_core.\u_dep_mgr.$ge$hardware/v2/rtl/dependency_manager.v:152$6197: $auto$alumacc.cc:548:replace_alu$25418 + creating $alu cell for $flatten\u_dataflow_core.\u_dep_mgr.$ge$hardware/v2/rtl/dependency_manager.v:152$6271: $auto$alumacc.cc:548:replace_alu$25431 + creating $alu cell for $flatten\u_dataflow_core.\u_dep_mgr.$ge$hardware/v2/rtl/dependency_manager.v:152$6345: $auto$alumacc.cc:548:replace_alu$25444 + creating $alu cell for $flatten\u_dataflow_core.\u_dep_mgr.$ge$hardware/v2/rtl/dependency_manager.v:152$6419: $auto$alumacc.cc:548:replace_alu$25457 + creating $alu cell for $flatten\u_dataflow_core.\u_dep_mgr.$ge$hardware/v2/rtl/dependency_manager.v:152$6493: $auto$alumacc.cc:548:replace_alu$25470 + creating $alu cell for $flatten\u_dataflow_core.\u_dep_mgr.$ge$hardware/v2/rtl/dependency_manager.v:152$6567: $auto$alumacc.cc:548:replace_alu$25483 + creating $alu cell for $flatten\u_dataflow_core.\u_dep_mgr.$ge$hardware/v2/rtl/dependency_manager.v:152$6641: $auto$alumacc.cc:548:replace_alu$25496 + creating $alu cell for $flatten\u_sdram_backend.$sub$hardware/v2/nms/rtl/sdram_unified_backend.v:292$7064: $auto$alumacc.cc:548:replace_alu$25509 + creating $alu cell for $flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:154$6644: $auto$alumacc.cc:548:replace_alu$25512 + creating $alu cell for $flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:154$6570: $auto$alumacc.cc:548:replace_alu$25515 + creating $alu cell for $flatten\u_arbiter.$add$hardware/v2/rtl/slot_mem_arbiter.v:157$7162: $auto$alumacc.cc:548:replace_alu$25518 + creating $alu cell for $flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:154$6496: $auto$alumacc.cc:548:replace_alu$25521 + creating $alu cell for $flatten\u_arbiter.$neg$hardware/v2/rtl/slot_mem_arbiter.v:164$7172: $auto$alumacc.cc:548:replace_alu$25524 + creating $alu cell for $flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:154$6422: $auto$alumacc.cc:548:replace_alu$25527 + creating $alu cell for $flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:154$6348: $auto$alumacc.cc:548:replace_alu$25530 + creating $alu cell for $flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:154$6274: $auto$alumacc.cc:548:replace_alu$25533 + creating $alu cell for $flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:154$6200: $auto$alumacc.cc:548:replace_alu$25536 + creating $alu cell for $flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:154$6126: $auto$alumacc.cc:548:replace_alu$25539 + creating $alu cell for $flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:154$6052: $auto$alumacc.cc:548:replace_alu$25542 + creating $alu cell for $flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:154$5978: $auto$alumacc.cc:548:replace_alu$25545 + creating $alu cell for $flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:154$5904: $auto$alumacc.cc:548:replace_alu$25548 + creating $alu cell for $flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:154$5830: $auto$alumacc.cc:548:replace_alu$25551 + creating $alu cell for $flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:154$5756: $auto$alumacc.cc:548:replace_alu$25554 + creating $alu cell for $flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:154$5682: $auto$alumacc.cc:548:replace_alu$25557 + creating $alu cell for $flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:154$5608: $auto$alumacc.cc:548:replace_alu$25560 + creating $alu cell for $flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:154$5534: $auto$alumacc.cc:548:replace_alu$25563 + creating $alu cell for $flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:136$5266: $auto$alumacc.cc:548:replace_alu$25566 + creating $alu cell for $flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:136$5264: $auto$alumacc.cc:548:replace_alu$25569 + creating $alu cell for $flatten\u_dataflow_core.\u_dep_mgr.$add$hardware/v2/rtl/dependency_manager.v:136$5262: $auto$alumacc.cc:548:replace_alu$25572 + creating $alu cell for $flatten\u_host_arb.$neg$hardware/v2/rtl/slot_mem_arbiter.v:164$7135: $auto$alumacc.cc:548:replace_alu$25575 + creating $alu cell for $flatten\u_dataflow_core.\u_director.$sub$hardware/v2/rtl/neural_director.v:231$4453: $auto$alumacc.cc:548:replace_alu$25578 + creating $alu cell for $flatten\u_dataflow_core.\u_director.$add$hardware/v2/rtl/neural_director.v:230$4452: $auto$alumacc.cc:548:replace_alu$25581 + creating $alu cell for $flatten\u_dataflow_core.\u_director.$add$hardware/v2/rtl/neural_director.v:213$4445: $auto$alumacc.cc:548:replace_alu$25584 + creating $alu cell for $flatten\u_dataflow_core.\u_director.$neg$hardware/v2/rtl/neural_director.v:212$4441: $auto$alumacc.cc:548:replace_alu$25587 + creating $alu cell for $flatten\u_dataflow_core.\u_director.$neg$hardware/v2/rtl/neural_director.v:211$4434: $auto$alumacc.cc:548:replace_alu$25590 + creating $alu cell for $flatten\u_dataflow_core.\u_director.$add$hardware/v2/rtl/neural_director.v:168$4359: $auto$alumacc.cc:548:replace_alu$25593 + creating $alu cell for $flatten\u_dataflow_core.\u_act_fill.\u_pf.$neg$hardware/v2/rtl/prefetch_engine.v:115$6850: $auto$alumacc.cc:548:replace_alu$25596 + creating $alu cell for $flatten\u_dataflow_core.\u_act_fill.\u_pf.$add$hardware/v2/rtl/prefetch_engine.v:119$6858: $auto$alumacc.cc:548:replace_alu$25599 + creating $alu cell for $flatten\u_host_arb.$add$hardware/v2/rtl/slot_mem_arbiter.v:157$7125: $auto$alumacc.cc:548:replace_alu$25602 + creating $alu cell for $flatten\u_dataflow_core.\u_act_fill.\u_pf.$add$hardware/v2/rtl/prefetch_engine.v:122$6860: $auto$alumacc.cc:548:replace_alu$25605 + creating $alu cell for $flatten\u_dataflow_core.\u_act_fill.$add$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:207$4192: $auto$alumacc.cc:548:replace_alu$25608 + creating $alu cell for $flatten\u_dataflow_core.\u_act_fill.$add$hardware/v2/nms/rtl/nms_activation_fill_ctrl_v3.v:181$4176: $auto$alumacc.cc:548:replace_alu$25611 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:133$6817: $auto$alumacc.cc:548:replace_alu$25614 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:134$6818: $auto$alumacc.cc:548:replace_alu$25617 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:139$6824: $auto$alumacc.cc:548:replace_alu$25620 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:139$6826: $auto$alumacc.cc:548:replace_alu$25623 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:150$6829: $auto$alumacc.cc:548:replace_alu$25626 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:143$6827: $auto$alumacc.cc:548:replace_alu$25629 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:151$6830: $auto$alumacc.cc:548:replace_alu$25632 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:150$6832: $auto$alumacc.cc:548:replace_alu$25635 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:103$6790: $auto$alumacc.cc:548:replace_alu$25638 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$add$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:264$3779: $auto$alumacc.cc:548:replace_alu$25641 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$sub$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:263$3777: $auto$alumacc.cc:548:replace_alu$25644 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$add$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:251$3776: $auto$alumacc.cc:548:replace_alu$25647 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.$add$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:247$3774: $auto$alumacc.cc:548:replace_alu$25650 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$add$hardware/v2/rtl/neural_processor.v:197$3733: $auto$alumacc.cc:548:replace_alu$25653 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$add$hardware/v2/rtl/neural_processor.v:197$3730: $auto$alumacc.cc:548:replace_alu$25656 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$add$hardware/v2/rtl/neural_processor.v:197$3728: $auto$alumacc.cc:548:replace_alu$25659 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3725: $auto$alumacc.cc:548:replace_alu$25662 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3723: $auto$alumacc.cc:548:replace_alu$25665 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3721: $auto$alumacc.cc:548:replace_alu$25668 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3719: $auto$alumacc.cc:548:replace_alu$25671 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[0].u_np.$add$hardware/v2/rtl/neural_processor.v:226$3688: $auto$alumacc.cc:548:replace_alu$25674 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:133$6817: $auto$alumacc.cc:548:replace_alu$25677 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:134$6818: $auto$alumacc.cc:548:replace_alu$25680 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:139$6824: $auto$alumacc.cc:548:replace_alu$25683 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:139$6826: $auto$alumacc.cc:548:replace_alu$25686 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:150$6829: $auto$alumacc.cc:548:replace_alu$25689 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:143$6827: $auto$alumacc.cc:548:replace_alu$25692 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:151$6830: $auto$alumacc.cc:548:replace_alu$25695 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:150$6832: $auto$alumacc.cc:548:replace_alu$25698 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:103$6790: $auto$alumacc.cc:548:replace_alu$25701 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$add$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:264$3779: $auto$alumacc.cc:548:replace_alu$25704 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$sub$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:263$3777: $auto$alumacc.cc:548:replace_alu$25707 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$add$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:251$3776: $auto$alumacc.cc:548:replace_alu$25710 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.$add$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:247$3774: $auto$alumacc.cc:548:replace_alu$25713 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$add$hardware/v2/rtl/neural_processor.v:197$3733: $auto$alumacc.cc:548:replace_alu$25716 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$add$hardware/v2/rtl/neural_processor.v:197$3730: $auto$alumacc.cc:548:replace_alu$25719 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$add$hardware/v2/rtl/neural_processor.v:197$3728: $auto$alumacc.cc:548:replace_alu$25722 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3725: $auto$alumacc.cc:548:replace_alu$25725 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3723: $auto$alumacc.cc:548:replace_alu$25728 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3721: $auto$alumacc.cc:548:replace_alu$25731 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3719: $auto$alumacc.cc:548:replace_alu$25734 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[1].u_np.$add$hardware/v2/rtl/neural_processor.v:226$3688: $auto$alumacc.cc:548:replace_alu$25737 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:133$6817: $auto$alumacc.cc:548:replace_alu$25740 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:134$6818: $auto$alumacc.cc:548:replace_alu$25743 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:139$6824: $auto$alumacc.cc:548:replace_alu$25746 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:139$6826: $auto$alumacc.cc:548:replace_alu$25749 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:150$6829: $auto$alumacc.cc:548:replace_alu$25752 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:143$6827: $auto$alumacc.cc:548:replace_alu$25755 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:151$6830: $auto$alumacc.cc:548:replace_alu$25758 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:150$6832: $auto$alumacc.cc:548:replace_alu$25761 + creating $alu cell for $flatten\u_arbiter_wide.$neg$hardware/v2/rtl/slot_mem_arbiter_wide.v:165$7103: $auto$alumacc.cc:548:replace_alu$25764 + creating $alu cell for $flatten\u_sdram_backend.$add$hardware/v2/nms/rtl/sdram_unified_backend.v:296$7065: $auto$alumacc.cc:548:replace_alu$25767 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:103$6790: $auto$alumacc.cc:548:replace_alu$25770 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$add$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:264$3779: $auto$alumacc.cc:548:replace_alu$25773 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$sub$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:263$3777: $auto$alumacc.cc:548:replace_alu$25776 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$add$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:251$3776: $auto$alumacc.cc:548:replace_alu$25779 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.$add$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:247$3774: $auto$alumacc.cc:548:replace_alu$25782 + creating $alu cell for $flatten\u_arbiter_wide.$add$hardware/v2/rtl/slot_mem_arbiter_wide.v:158$7089: $auto$alumacc.cc:548:replace_alu$25785 + creating $alu cell for $flatten\u_sdram_backend.\u_sdram_ctrl.$sub$hardware/v2/nms/rtl/sdram_controller.v:224$7423: $auto$alumacc.cc:548:replace_alu$25788 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$add$hardware/v2/rtl/neural_processor.v:197$3733: $auto$alumacc.cc:548:replace_alu$25791 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$add$hardware/v2/rtl/neural_processor.v:197$3730: $auto$alumacc.cc:548:replace_alu$25794 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$add$hardware/v2/rtl/neural_processor.v:197$3728: $auto$alumacc.cc:548:replace_alu$25797 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3725: $auto$alumacc.cc:548:replace_alu$25800 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3723: $auto$alumacc.cc:548:replace_alu$25803 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3721: $auto$alumacc.cc:548:replace_alu$25806 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3719: $auto$alumacc.cc:548:replace_alu$25809 + creating $alu cell for $flatten\u_sdram_backend.\u_sdram_ctrl.$sub$hardware/v2/nms/rtl/sdram_controller.v:256$7427: $auto$alumacc.cc:548:replace_alu$25812 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[2].u_np.$add$hardware/v2/rtl/neural_processor.v:226$3688: $auto$alumacc.cc:548:replace_alu$25815 + creating $alu cell for $flatten\u_sdram_backend.\u_sdram_ctrl.$add$hardware/v2/nms/rtl/sdram_controller.v:280$7433: $auto$alumacc.cc:548:replace_alu$25818 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:133$6817: $auto$alumacc.cc:548:replace_alu$25821 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:134$6818: $auto$alumacc.cc:548:replace_alu$25824 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:139$6824: $auto$alumacc.cc:548:replace_alu$25827 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:139$6826: $auto$alumacc.cc:548:replace_alu$25830 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:150$6829: $auto$alumacc.cc:548:replace_alu$25833 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:143$6827: $auto$alumacc.cc:548:replace_alu$25836 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:151$6830: $auto$alumacc.cc:548:replace_alu$25839 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:150$6832: $auto$alumacc.cc:548:replace_alu$25842 + creating $alu cell for $flatten\u_sdram_backend.\u_sdram_ctrl.$neg$hardware/v2/nms/rtl/sdram_controller.v:410$7449: $auto$alumacc.cc:548:replace_alu$25845 + creating $alu cell for $flatten\u_sdram_backend.\u_sdram_ctrl.$add$hardware/v2/nms/rtl/sdram_controller.v:397$7446: $auto$alumacc.cc:548:replace_alu$25848 + creating $alu cell for $flatten\u_sdram_backend.\u_sdram_ctrl.$add$hardware/v2/nms/rtl/sdram_controller.v:426$7460: $auto$alumacc.cc:548:replace_alu$25851 + creating $alu cell for $flatten\u_sdram_backend.$add$hardware/v2/nms/rtl/sdram_unified_backend.v:299$7067: $auto$alumacc.cc:548:replace_alu$25854 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:103$6790: $auto$alumacc.cc:548:replace_alu$25857 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$add$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:264$3779: $auto$alumacc.cc:548:replace_alu$25860 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$sub$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:263$3777: $auto$alumacc.cc:548:replace_alu$25863 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$add$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:251$3776: $auto$alumacc.cc:548:replace_alu$25866 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.$add$hardware/v2/nms/rtl/nms_memory_manager_stream_wide.v:247$3774: $auto$alumacc.cc:548:replace_alu$25869 + creating $alu cell for $auto$peepopt_pm.h:1040:block_9$24910: $auto$alumacc.cc:548:replace_alu$25872 + creating $alu cell for $auto$peepopt_pm.h:1040:block_9$24913: $auto$alumacc.cc:548:replace_alu$25875 + creating $alu cell for $auto$peepopt_pm.h:1040:block_9$24916: $auto$alumacc.cc:548:replace_alu$25878 + creating $alu cell for $auto$peepopt_pm.h:1040:block_9$24907: $auto$alumacc.cc:548:replace_alu$25881 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$add$hardware/v2/rtl/neural_processor.v:197$3733: $auto$alumacc.cc:548:replace_alu$25884 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$add$hardware/v2/rtl/neural_processor.v:197$3730: $auto$alumacc.cc:548:replace_alu$25887 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$add$hardware/v2/rtl/neural_processor.v:197$3728: $auto$alumacc.cc:548:replace_alu$25890 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3725: $auto$alumacc.cc:548:replace_alu$25893 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3723: $auto$alumacc.cc:548:replace_alu$25896 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3721: $auto$alumacc.cc:548:replace_alu$25899 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$add$hardware/v2/rtl/neural_processor.v:193$3719: $auto$alumacc.cc:548:replace_alu$25902 + creating $alu cell for $flatten\u_dataflow_core.\GEN_SLOT[3].u_np.$add$hardware/v2/rtl/neural_processor.v:226$3688: $auto$alumacc.cc:548:replace_alu$25905 + creating $alu cell for $flatten\u_spi_bridge.$add$hardware/v2/rtl/spi_host_bridge.v:208$7333: $auto$alumacc.cc:548:replace_alu$25908 + creating $alu cell for $flatten\u_spi_bridge.$sub$hardware/v2/rtl/spi_host_bridge.v:211$7336, $flatten\u_spi_bridge.$eq$hardware/v2/rtl/spi_host_bridge.v:203$7332: $auto$alumacc.cc:548:replace_alu$25911 + creating $alu cell for $flatten\u_spi_bridge.$add$hardware/v2/rtl/spi_host_bridge.v:333$7355: $auto$alumacc.cc:548:replace_alu$25916 + creating $alu cell for $flatten\u_spi_bridge.$add$hardware/v2/rtl/spi_host_bridge.v:391$7373: $auto$alumacc.cc:548:replace_alu$25919 + creating $alu cell for $flatten\u_spi_bridge.$sub$hardware/v2/rtl/spi_host_bridge.v:392$7374, $flatten\u_spi_bridge.$eq$hardware/v2/rtl/spi_host_bridge.v:394$7375: $auto$alumacc.cc:548:replace_alu$25922 + created 187 $alu and 0 $macc cells. + +19.25. Executing OPT pass (performing simple optimizations). + +19.25.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module fpga_neural_v2_top. + + +19.25.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\fpga_neural_v2_top'. +Computing hashes of 4278 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. +Computing hashes of 4275 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. + +Removed a total of 3 cells. + +19.25.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \fpga_neural_v2_top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +19.25.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \fpga_neural_v2_top. + New input vector for $reduce_and cell $auto$opt_dff.cc:337:make_patterns_logic$22669: { \u_spi_bridge.sclk_rise \u_spi_bridge.cs_active $auto$rtlil.cc:3267:Not$22648 $auto$alumacc.cc:564:replace_alu$25912 } + Optimizing cells in module \fpga_neural_v2_top. +Performed a total of 3 changes. + +19.25.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\fpga_neural_v2_top'. +Computing hashes of 4275 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. +Computing hashes of 4274 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. + +Removed a total of 1 cells. + +19.25.6. Executing OPT_DFF pass (perform DFF optimizations). +Adding SRST signal on $auto$ff.cc:337:slice$22720 ($sdff) from module fpga_neural_v2_top (D = $flatten\u_spi_bridge.$procmux$18570_Y [3:1], Q = \u_spi_bridge.byte_idx [3:1], rval = 3'000). + +19.25.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \fpga_neural_v2_top.. +Removed 5 unused cells and 327 unused wires. + + +19.25.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module fpga_neural_v2_top. + +19.25.9. Rerunning OPT passes. (Maybe there is more to do..) + +19.25.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \fpga_neural_v2_top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +19.25.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \fpga_neural_v2_top. +Performed a total of 0 changes. + +19.25.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\fpga_neural_v2_top'. +Computing hashes of 4271 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. +Computing hashes of 4270 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. + +Removed a total of 1 cells. + +19.25.13. Executing OPT_DFF pass (perform DFF optimizations). + +19.25.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \fpga_neural_v2_top.. +Removed 0 unused cells and 1 unused wires. + + +19.25.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module fpga_neural_v2_top. + +19.25.16. Rerunning OPT passes. (Maybe there is more to do..) + +19.25.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \fpga_neural_v2_top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +19.25.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \fpga_neural_v2_top. +Performed a total of 0 changes. + +19.25.19. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\fpga_neural_v2_top'. +Computing hashes of 4270 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. +Removed a total of 0 cells. + +19.25.20. Executing OPT_DFF pass (perform DFF optimizations). + +19.25.21. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \fpga_neural_v2_top.. + +19.25.22. Executing OPT_EXPR pass (perform const folding). +Optimizing module fpga_neural_v2_top. + +19.25.23. Finished fast OPT passes. (There is nothing left to do.) + +19.26. Executing MEMORY pass. + +19.26.1. Executing OPT_MEM pass (optimize memories). +Performed a total of 0 transformations. + +19.26.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). +Performed a total of 4212 transformations. + +19.26.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). + Analyzing fpga_neural_v2_top.u_sdram_backend.w_cache_valid write port 0. + Analyzing fpga_neural_v2_top.u_sdram_backend.w_cache_valid write port 1. + Analyzing fpga_neural_v2_top.u_sdram_backend.w_cache_valid write port 2. + Analyzing fpga_neural_v2_top.u_sdram_backend.w_cache_valid write port 3. + Analyzing fpga_neural_v2_top.u_sdram_backend.w_cache_valid write port 4. + Analyzing fpga_neural_v2_top.u_sdram_backend.w_cache_valid write port 5. + Analyzing fpga_neural_v2_top.u_sdram_backend.w_cache_addr write port 0. + Analyzing fpga_neural_v2_top.u_sdram_backend.w_cache_addr write port 1. + Analyzing fpga_neural_v2_top.u_sdram_backend.w_cache_data write port 0. + Analyzing fpga_neural_v2_top.u_sdram_backend.w_cache_data write port 1. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_result_addr write port 0. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_n_tiles write port 0. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_w_base write port 0. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_x_base write port 0. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_producer_ids write port 0. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_producer_ids write port 1. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_producer_ids write port 2. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_producer_ids write port 3. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 0. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 1. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 2. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 3. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 4. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 5. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 6. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 7. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 8. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 9. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 10. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 11. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 12. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 13. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 14. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 15. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 16. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 17. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 18. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 19. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 20. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 21. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 22. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 23. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 24. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 25. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 26. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 27. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 28. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 29. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 30. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 31. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 32. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 33. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 34. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 35. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 36. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 37. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 38. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 39. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 40. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 41. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 42. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 43. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 44. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 45. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 46. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 47. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 48. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 49. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 50. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 51. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 52. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 53. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 54. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 55. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 56. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 57. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 58. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 59. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 60. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 61. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 62. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 63. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 64. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 65. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 66. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 67. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 68. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 69. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 70. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 71. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 72. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 73. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 74. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 75. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 76. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 77. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 78. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 79. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved write port 80. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_required write port 0. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_required write port 1. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_required write port 2. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_required write port 3. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_required write port 4. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_required write port 5. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_required write port 6. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_required write port 7. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_required write port 8. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_required write port 9. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_required write port 10. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_required write port 11. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_required write port 12. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_required write port 13. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_required write port 14. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_required write port 15. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_required write port 16. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 0. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 1. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 2. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 3. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 4. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 5. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 6. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 7. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 8. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 9. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 10. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 11. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 12. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 13. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 14. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 15. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 16. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 17. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 18. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 19. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 20. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 21. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 22. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 23. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 24. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 25. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 26. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 27. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 28. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 29. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 30. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 31. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 32. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 33. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 34. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 35. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 36. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 37. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 38. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 39. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 40. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 41. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 42. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 43. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 44. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 45. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 46. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 47. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 48. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 49. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 50. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 51. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 52. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 53. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 54. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 55. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 56. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 57. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 58. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 59. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 60. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 61. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 62. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 63. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 64. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 65. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 66. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 67. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 68. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 69. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 70. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 71. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 72. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 73. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 74. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 75. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 76. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 77. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 78. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 79. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 80. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state write port 81. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_director.q_node_id write port 0. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_director.q_result_addr write port 0. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_director.q_n_tiles write port 0. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_director.q_w_base write port 0. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_director.q_x_base write port 0. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_act_mem.GEN_COPY[3].mem write port 0. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_act_mem.GEN_COPY[2].mem write port 0. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_act_mem.GEN_COPY[1].mem write port 0. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_act_mem.GEN_COPY[0].mem write port 0. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[3].GEN_LANE[7].mem write port 0. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[3].GEN_LANE[6].mem write port 0. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[3].GEN_LANE[5].mem write port 0. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[3].GEN_LANE[4].mem write port 0. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[3].GEN_LANE[3].mem write port 0. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[3].GEN_LANE[2].mem write port 0. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[3].GEN_LANE[1].mem write port 0. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[3].GEN_LANE[0].mem write port 0. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[2].GEN_LANE[7].mem write port 0. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[2].GEN_LANE[6].mem write port 0. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[2].GEN_LANE[5].mem write port 0. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[2].GEN_LANE[4].mem write port 0. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[2].GEN_LANE[3].mem write port 0. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[2].GEN_LANE[2].mem write port 0. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[2].GEN_LANE[1].mem write port 0. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[2].GEN_LANE[0].mem write port 0. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[1].GEN_LANE[7].mem write port 0. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[1].GEN_LANE[6].mem write port 0. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[1].GEN_LANE[5].mem write port 0. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[1].GEN_LANE[4].mem write port 0. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[1].GEN_LANE[3].mem write port 0. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[1].GEN_LANE[2].mem write port 0. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[1].GEN_LANE[1].mem write port 0. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[1].GEN_LANE[0].mem write port 0. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[0].GEN_LANE[7].mem write port 0. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[0].GEN_LANE[6].mem write port 0. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[0].GEN_LANE[5].mem write port 0. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[0].GEN_LANE[4].mem write port 0. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[0].GEN_LANE[3].mem write port 0. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[0].GEN_LANE[2].mem write port 0. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[0].GEN_LANE[1].mem write port 0. + Analyzing fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[0].GEN_LANE[0].mem write port 0. + +19.26.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). + +19.26.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). +Checking read port `\u_sdram_backend.w_cache_valid'[0] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_sdram_backend.w_cache_valid'[1] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_sdram_backend.w_cache_valid'[2] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_sdram_backend.w_cache_valid'[3] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_sdram_backend.w_cache_addr'[0] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_sdram_backend.w_cache_addr'[1] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_sdram_backend.w_cache_addr'[2] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_sdram_backend.w_cache_addr'[3] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_sdram_backend.w_cache_data'[0] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_result_addr'[0] in module `\fpga_neural_v2_top': merging output FF to cell. + Write port 0: non-transparent. +Checking read port `\u_dataflow_core.u_dep_mgr.node_n_tiles'[0] in module `\fpga_neural_v2_top': merging output FF to cell. + Write port 0: non-transparent. +Checking read port `\u_dataflow_core.u_dep_mgr.node_w_base'[0] in module `\fpga_neural_v2_top': merging output FF to cell. + Write port 0: non-transparent. +Checking read port `\u_dataflow_core.u_dep_mgr.node_x_base'[0] in module `\fpga_neural_v2_top': merging output FF to cell. + Write port 0: non-transparent. +Checking read port `\u_dataflow_core.u_dep_mgr.node_producer_ids'[0] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_producer_ids'[1] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_producer_ids'[2] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_producer_ids'[3] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_producer_ids'[4] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_producer_ids'[5] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_producer_ids'[6] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_producer_ids'[7] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_producer_ids'[8] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_producer_ids'[9] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_producer_ids'[10] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_producer_ids'[11] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_producer_ids'[12] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_producer_ids'[13] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_producer_ids'[14] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_producer_ids'[15] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_producer_ids'[16] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_producer_ids'[17] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_producer_ids'[18] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_producer_ids'[19] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_producer_ids'[20] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_producer_ids'[21] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_producer_ids'[22] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_producer_ids'[23] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_producer_ids'[24] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_producer_ids'[25] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_producer_ids'[26] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_producer_ids'[27] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_producer_ids'[28] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_producer_ids'[29] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_producer_ids'[30] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_producer_ids'[31] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_producer_ids'[32] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_producer_ids'[33] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_producer_ids'[34] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_producer_ids'[35] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_producer_ids'[36] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_producer_ids'[37] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_producer_ids'[38] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_producer_ids'[39] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_producer_ids'[40] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_producer_ids'[41] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_producer_ids'[42] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_producer_ids'[43] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_producer_ids'[44] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_producer_ids'[45] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_producer_ids'[46] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_producer_ids'[47] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_producer_ids'[48] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_producer_ids'[49] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_producer_ids'[50] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_producer_ids'[51] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_producer_ids'[52] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_producer_ids'[53] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_producer_ids'[54] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_producer_ids'[55] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_producer_ids'[56] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_producer_ids'[57] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_producer_ids'[58] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_producer_ids'[59] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_producer_ids'[60] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_producer_ids'[61] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_producer_ids'[62] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_producer_ids'[63] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_resolved'[0] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_resolved'[1] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_resolved'[2] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_resolved'[3] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_resolved'[4] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_resolved'[5] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_resolved'[6] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_resolved'[7] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_resolved'[8] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_resolved'[9] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_resolved'[10] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_resolved'[11] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_resolved'[12] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_resolved'[13] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_resolved'[14] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_resolved'[15] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_required'[0] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_required'[1] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_required'[2] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_required'[3] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_required'[4] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_required'[5] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_required'[6] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_required'[7] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_required'[8] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_required'[9] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_required'[10] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_required'[11] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_required'[12] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_required'[13] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_required'[14] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_required'[15] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_state'[0] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_state'[1] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_state'[2] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_state'[3] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_state'[4] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_state'[5] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_state'[6] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_state'[7] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_state'[8] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_state'[9] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_state'[10] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_state'[11] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_state'[12] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_state'[13] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_state'[14] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_state'[15] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_dep_mgr.node_state'[16] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_director.q_node_id'[0] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_director.q_result_addr'[0] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_director.q_n_tiles'[0] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_director.q_w_base'[0] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_director.q_x_base'[0] in module `\fpga_neural_v2_top': no output FF found. +Checking read port `\u_dataflow_core.u_act_mem.GEN_COPY[3].mem'[0] in module `\fpga_neural_v2_top': merging output FF to cell. + Write port 0: transparent. +Checking read port `\u_dataflow_core.u_act_mem.GEN_COPY[2].mem'[0] in module `\fpga_neural_v2_top': merging output FF to cell. + Write port 0: transparent. +Checking read port `\u_dataflow_core.u_act_mem.GEN_COPY[1].mem'[0] in module `\fpga_neural_v2_top': merging output FF to cell. + Write port 0: transparent. +Checking read port `\u_dataflow_core.u_act_mem.GEN_COPY[0].mem'[0] in module `\fpga_neural_v2_top': merging output FF to cell. + Write port 0: transparent. +Checking read port `\u_dataflow_core.u_wgt_mem.GEN_SLOT[3].GEN_LANE[7].mem'[0] in module `\fpga_neural_v2_top': merging output FF to cell. + Write port 0: transparent. +Checking read port `\u_dataflow_core.u_wgt_mem.GEN_SLOT[3].GEN_LANE[6].mem'[0] in module `\fpga_neural_v2_top': merging output FF to cell. + Write port 0: transparent. +Checking read port `\u_dataflow_core.u_wgt_mem.GEN_SLOT[3].GEN_LANE[5].mem'[0] in module `\fpga_neural_v2_top': merging output FF to cell. + Write port 0: transparent. +Checking read port `\u_dataflow_core.u_wgt_mem.GEN_SLOT[3].GEN_LANE[4].mem'[0] in module `\fpga_neural_v2_top': merging output FF to cell. + Write port 0: transparent. +Checking read port `\u_dataflow_core.u_wgt_mem.GEN_SLOT[3].GEN_LANE[3].mem'[0] in module `\fpga_neural_v2_top': merging output FF to cell. + Write port 0: transparent. +Checking read port `\u_dataflow_core.u_wgt_mem.GEN_SLOT[3].GEN_LANE[2].mem'[0] in module `\fpga_neural_v2_top': merging output FF to cell. + Write port 0: transparent. +Checking read port `\u_dataflow_core.u_wgt_mem.GEN_SLOT[3].GEN_LANE[1].mem'[0] in module `\fpga_neural_v2_top': merging output FF to cell. + Write port 0: transparent. +Checking read port `\u_dataflow_core.u_wgt_mem.GEN_SLOT[3].GEN_LANE[0].mem'[0] in module `\fpga_neural_v2_top': merging output FF to cell. + Write port 0: transparent. +Checking read port `\u_dataflow_core.u_wgt_mem.GEN_SLOT[2].GEN_LANE[7].mem'[0] in module `\fpga_neural_v2_top': merging output FF to cell. + Write port 0: transparent. +Checking read port `\u_dataflow_core.u_wgt_mem.GEN_SLOT[2].GEN_LANE[6].mem'[0] in module `\fpga_neural_v2_top': merging output FF to cell. + Write port 0: transparent. +Checking read port `\u_dataflow_core.u_wgt_mem.GEN_SLOT[2].GEN_LANE[5].mem'[0] in module `\fpga_neural_v2_top': merging output FF to cell. + Write port 0: transparent. +Checking read port `\u_dataflow_core.u_wgt_mem.GEN_SLOT[2].GEN_LANE[4].mem'[0] in module `\fpga_neural_v2_top': merging output FF to cell. + Write port 0: transparent. +Checking read port `\u_dataflow_core.u_wgt_mem.GEN_SLOT[2].GEN_LANE[3].mem'[0] in module `\fpga_neural_v2_top': merging output FF to cell. + Write port 0: transparent. +Checking read port `\u_dataflow_core.u_wgt_mem.GEN_SLOT[2].GEN_LANE[2].mem'[0] in module `\fpga_neural_v2_top': merging output FF to cell. + Write port 0: transparent. +Checking read port `\u_dataflow_core.u_wgt_mem.GEN_SLOT[2].GEN_LANE[1].mem'[0] in module `\fpga_neural_v2_top': merging output FF to cell. + Write port 0: transparent. +Checking read port `\u_dataflow_core.u_wgt_mem.GEN_SLOT[2].GEN_LANE[0].mem'[0] in module `\fpga_neural_v2_top': merging output FF to cell. + Write port 0: transparent. +Checking read port `\u_dataflow_core.u_wgt_mem.GEN_SLOT[1].GEN_LANE[7].mem'[0] in module `\fpga_neural_v2_top': merging output FF to cell. + Write port 0: transparent. +Checking read port `\u_dataflow_core.u_wgt_mem.GEN_SLOT[1].GEN_LANE[6].mem'[0] in module `\fpga_neural_v2_top': merging output FF to cell. + Write port 0: transparent. +Checking read port `\u_dataflow_core.u_wgt_mem.GEN_SLOT[1].GEN_LANE[5].mem'[0] in module `\fpga_neural_v2_top': merging output FF to cell. + Write port 0: transparent. +Checking read port `\u_dataflow_core.u_wgt_mem.GEN_SLOT[1].GEN_LANE[4].mem'[0] in module `\fpga_neural_v2_top': merging output FF to cell. + Write port 0: transparent. +Checking read port `\u_dataflow_core.u_wgt_mem.GEN_SLOT[1].GEN_LANE[3].mem'[0] in module `\fpga_neural_v2_top': merging output FF to cell. + Write port 0: transparent. +Checking read port `\u_dataflow_core.u_wgt_mem.GEN_SLOT[1].GEN_LANE[2].mem'[0] in module `\fpga_neural_v2_top': merging output FF to cell. + Write port 0: transparent. +Checking read port `\u_dataflow_core.u_wgt_mem.GEN_SLOT[1].GEN_LANE[1].mem'[0] in module `\fpga_neural_v2_top': merging output FF to cell. + Write port 0: transparent. +Checking read port `\u_dataflow_core.u_wgt_mem.GEN_SLOT[1].GEN_LANE[0].mem'[0] in module `\fpga_neural_v2_top': merging output FF to cell. + Write port 0: transparent. +Checking read port `\u_dataflow_core.u_wgt_mem.GEN_SLOT[0].GEN_LANE[7].mem'[0] in module `\fpga_neural_v2_top': merging output FF to cell. + Write port 0: transparent. +Checking read port `\u_dataflow_core.u_wgt_mem.GEN_SLOT[0].GEN_LANE[6].mem'[0] in module `\fpga_neural_v2_top': merging output FF to cell. + Write port 0: transparent. +Checking read port `\u_dataflow_core.u_wgt_mem.GEN_SLOT[0].GEN_LANE[5].mem'[0] in module `\fpga_neural_v2_top': merging output FF to cell. + Write port 0: transparent. +Checking read port `\u_dataflow_core.u_wgt_mem.GEN_SLOT[0].GEN_LANE[4].mem'[0] in module `\fpga_neural_v2_top': merging output FF to cell. + Write port 0: transparent. +Checking read port `\u_dataflow_core.u_wgt_mem.GEN_SLOT[0].GEN_LANE[3].mem'[0] in module `\fpga_neural_v2_top': merging output FF to cell. + Write port 0: transparent. +Checking read port `\u_dataflow_core.u_wgt_mem.GEN_SLOT[0].GEN_LANE[2].mem'[0] in module `\fpga_neural_v2_top': merging output FF to cell. + Write port 0: transparent. +Checking read port `\u_dataflow_core.u_wgt_mem.GEN_SLOT[0].GEN_LANE[1].mem'[0] in module `\fpga_neural_v2_top': merging output FF to cell. + Write port 0: transparent. +Checking read port `\u_dataflow_core.u_wgt_mem.GEN_SLOT[0].GEN_LANE[0].mem'[0] in module `\fpga_neural_v2_top': merging output FF to cell. + Write port 0: transparent. +Checking read port address `\u_sdram_backend.w_cache_valid'[0] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_sdram_backend.w_cache_valid'[1] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_sdram_backend.w_cache_valid'[2] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_sdram_backend.w_cache_valid'[3] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_sdram_backend.w_cache_addr'[0] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_sdram_backend.w_cache_addr'[1] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_sdram_backend.w_cache_addr'[2] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_sdram_backend.w_cache_addr'[3] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_sdram_backend.w_cache_data'[0] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_producer_ids'[0] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_producer_ids'[1] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_producer_ids'[2] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_producer_ids'[3] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_producer_ids'[4] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_producer_ids'[5] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_producer_ids'[6] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_producer_ids'[7] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_producer_ids'[8] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_producer_ids'[9] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_producer_ids'[10] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_producer_ids'[11] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_producer_ids'[12] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_producer_ids'[13] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_producer_ids'[14] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_producer_ids'[15] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_producer_ids'[16] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_producer_ids'[17] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_producer_ids'[18] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_producer_ids'[19] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_producer_ids'[20] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_producer_ids'[21] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_producer_ids'[22] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_producer_ids'[23] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_producer_ids'[24] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_producer_ids'[25] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_producer_ids'[26] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_producer_ids'[27] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_producer_ids'[28] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_producer_ids'[29] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_producer_ids'[30] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_producer_ids'[31] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_producer_ids'[32] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_producer_ids'[33] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_producer_ids'[34] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_producer_ids'[35] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_producer_ids'[36] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_producer_ids'[37] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_producer_ids'[38] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_producer_ids'[39] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_producer_ids'[40] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_producer_ids'[41] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_producer_ids'[42] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_producer_ids'[43] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_producer_ids'[44] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_producer_ids'[45] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_producer_ids'[46] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_producer_ids'[47] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_producer_ids'[48] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_producer_ids'[49] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_producer_ids'[50] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_producer_ids'[51] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_producer_ids'[52] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_producer_ids'[53] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_producer_ids'[54] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_producer_ids'[55] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_producer_ids'[56] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_producer_ids'[57] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_producer_ids'[58] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_producer_ids'[59] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_producer_ids'[60] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_producer_ids'[61] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_producer_ids'[62] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_producer_ids'[63] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_resolved'[0] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_resolved'[1] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_resolved'[2] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_resolved'[3] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_resolved'[4] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_resolved'[5] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_resolved'[6] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_resolved'[7] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_resolved'[8] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_resolved'[9] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_resolved'[10] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_resolved'[11] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_resolved'[12] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_resolved'[13] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_resolved'[14] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_resolved'[15] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_required'[0] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_required'[1] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_required'[2] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_required'[3] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_required'[4] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_required'[5] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_required'[6] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_required'[7] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_required'[8] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_required'[9] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_required'[10] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_required'[11] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_required'[12] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_required'[13] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_required'[14] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_required'[15] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_state'[0] in module `\fpga_neural_v2_top': merged address FF to cell. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_state'[1] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_state'[2] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_state'[3] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_state'[4] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_state'[5] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_state'[6] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_state'[7] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_state'[8] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_state'[9] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_state'[10] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_state'[11] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_state'[12] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_state'[13] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_state'[14] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_state'[15] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_dep_mgr.node_state'[16] in module `\fpga_neural_v2_top': no address FF found. +Checking read port address `\u_dataflow_core.u_director.q_node_id'[0] in module `\fpga_neural_v2_top': merged address FF to cell. +Checking read port address `\u_dataflow_core.u_director.q_result_addr'[0] in module `\fpga_neural_v2_top': merged address FF to cell. +Checking read port address `\u_dataflow_core.u_director.q_n_tiles'[0] in module `\fpga_neural_v2_top': merged address FF to cell. +Checking read port address `\u_dataflow_core.u_director.q_w_base'[0] in module `\fpga_neural_v2_top': merged address FF to cell. +Checking read port address `\u_dataflow_core.u_director.q_x_base'[0] in module `\fpga_neural_v2_top': merged address FF to cell. + +19.26.6. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \fpga_neural_v2_top.. +Removed 64 unused cells and 693 unused wires. + + +19.26.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). +Consolidating read ports of memory fpga_neural_v2_top.u_sdram_backend.w_cache_valid by address: + Merging ports 0, 1 (address 2'00). + Merging ports 0, 2 (address 2'00). +Consolidating read ports of memory fpga_neural_v2_top.u_sdram_backend.w_cache_valid by address: +Consolidating write ports of memory fpga_neural_v2_top.u_sdram_backend.w_cache_valid by address: + Merging ports 0, 1 (address 2'00). + Merging ports 0, 2 (address 2'00). +Consolidating write ports of memory fpga_neural_v2_top.u_sdram_backend.w_cache_valid by address: +Consolidating read ports of memory fpga_neural_v2_top.u_sdram_backend.w_cache_addr by address: + Merging ports 0, 1 (address 2'00). + Merging ports 0, 2 (address 2'00). +Consolidating read ports of memory fpga_neural_v2_top.u_sdram_backend.w_cache_addr by address: +Consolidating write ports of memory fpga_neural_v2_top.u_sdram_backend.w_cache_addr by address: + Merging ports 0, 1 (address \u_sdram_backend.w_alloc_ptr). +Consolidating write ports of memory fpga_neural_v2_top.u_sdram_backend.w_cache_data by address: + Merging ports 0, 1 (address \u_sdram_backend.w_alloc_ptr). +Consolidating read ports of memory fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_producer_ids by address: + Merging ports 0, 1 (address 6'000000). + Merging ports 0, 2 (address 6'000000). + Merging ports 0, 3 (address 6'000000). + Merging ports 0, 4 (address 6'000000). + Merging ports 0, 5 (address 6'000000). + Merging ports 0, 6 (address 6'000000). + Merging ports 0, 7 (address 6'000000). + Merging ports 0, 8 (address 6'000000). + Merging ports 0, 9 (address 6'000000). + Merging ports 0, 10 (address 6'000000). + Merging ports 0, 11 (address 6'000000). + Merging ports 0, 12 (address 6'000000). + Merging ports 0, 13 (address 6'000000). + Merging ports 0, 14 (address 6'000000). + Merging ports 0, 15 (address 6'000000). + Merging ports 0, 16 (address 6'000000). + Merging ports 0, 17 (address 6'000000). + Merging ports 0, 18 (address 6'000000). + Merging ports 0, 19 (address 6'000000). + Merging ports 0, 20 (address 6'000000). + Merging ports 0, 21 (address 6'000000). + Merging ports 0, 22 (address 6'000000). + Merging ports 0, 23 (address 6'000000). + Merging ports 0, 24 (address 6'000000). + Merging ports 0, 25 (address 6'000000). + Merging ports 0, 26 (address 6'000000). + Merging ports 0, 27 (address 6'000000). + Merging ports 0, 28 (address 6'000000). + Merging ports 0, 29 (address 6'000000). + Merging ports 0, 30 (address 6'000000). + Merging ports 0, 31 (address 6'000000). + Merging ports 0, 32 (address 6'000000). + Merging ports 34, 35 (address 6'100010). + Merging ports 36, 37 (address 6'100100). + Merging ports 36, 38 (address 6'100100). + Merging ports 36, 39 (address 6'100100). + Merging ports 40, 41 (address 6'101000). + Merging ports 40, 42 (address 6'101000). + Merging ports 40, 43 (address 6'101000). + Merging ports 40, 44 (address 6'101000). + Merging ports 40, 45 (address 6'101000). + Merging ports 40, 46 (address 6'101000). + Merging ports 40, 47 (address 6'101000). + Merging ports 48, 49 (address 6'110000). + Merging ports 48, 50 (address 6'110000). + Merging ports 48, 51 (address 6'110000). + Merging ports 48, 52 (address 6'110000). + Merging ports 48, 53 (address 6'110000). + Merging ports 48, 54 (address 6'110000). + Merging ports 48, 55 (address 6'110000). + Merging ports 48, 56 (address 6'110000). + Merging ports 48, 57 (address 6'110000). + Merging ports 48, 58 (address 6'110000). + Merging ports 48, 59 (address 6'110000). + Merging ports 48, 60 (address 6'110000). + Merging ports 48, 61 (address 6'110000). + Merging ports 48, 62 (address 6'110000). + Merging ports 48, 63 (address 6'110000). +Consolidating read ports of memory fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_producer_ids by address: + Merging ports 1, 2 (address 6'100001). + Merging ports 1, 3 (address 6'100000). + Merging ports 1, 4 (address 6'100000). + Merging ports 1, 5 (address 6'100000). +Consolidating read ports of memory fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_producer_ids by address: +Consolidating write ports of memory fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_producer_ids by address: +Consolidating read ports of memory fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved by address: + Merging ports 0, 1 (address 4'0000). + Merging ports 0, 2 (address 4'0000). + Merging ports 0, 3 (address 4'0000). + Merging ports 0, 4 (address 4'0000). + Merging ports 0, 5 (address 4'0000). + Merging ports 0, 6 (address 4'0000). + Merging ports 0, 7 (address 4'0000). + Merging ports 0, 8 (address 4'0000). + Merging ports 10, 11 (address 4'1010). + Merging ports 12, 13 (address 4'1100). + Merging ports 12, 14 (address 4'1100). + Merging ports 12, 15 (address 4'1100). +Consolidating read ports of memory fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved by address: + Merging ports 1, 2 (address 4'1001). + Merging ports 1, 3 (address 4'1000). +Consolidating read ports of memory fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved by address: +Consolidating write ports of memory fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved by address: + Merging ports 0, 1 (address 4'0000). + Merging ports 0, 2 (address 4'0000). + Merging ports 0, 3 (address 4'0000). + Merging ports 0, 4 (address 4'0000). + Merging ports 0, 5 (address 4'0000). + Merging ports 0, 6 (address 4'0000). + Merging ports 0, 7 (address 4'0000). + Merging ports 0, 8 (address 4'0000). + Merging ports 9, 49 (address 4'1001). + Merging ports 9, 50 (address 4'1000). + Merging ports 9, 51 (address 4'1000). + Merging ports 9, 52 (address 4'1000). + Merging ports 9, 53 (address 4'1000). + Merging ports 9, 54 (address 4'1000). + Merging ports 9, 55 (address 4'1000). + Merging ports 9, 56 (address 4'1000). + Merging ports 9, 57 (address 4'1000). + Merging ports 9, 58 (address 4'1000). + Merging ports 9, 59 (address 4'1000). + Merging ports 9, 60 (address 4'1000). + Merging ports 9, 61 (address 4'1000). + Merging ports 9, 62 (address 4'1000). + Merging ports 9, 63 (address 4'1000). + Merging ports 9, 64 (address 4'1000). + Merging ports 9, 65 (address 4'1000). + Merging ports 9, 66 (address 4'1000). + Merging ports 9, 67 (address 4'1000). + Merging ports 9, 68 (address 4'1000). + Merging ports 9, 69 (address 4'1000). + Merging ports 9, 70 (address 4'1000). + Merging ports 9, 71 (address 4'1000). + Merging ports 9, 72 (address 4'1000). + Merging ports 9, 73 (address 4'1000). + Merging ports 9, 74 (address 4'1000). + Merging ports 9, 75 (address 4'1000). + Merging ports 9, 76 (address 4'1000). + Merging ports 9, 77 (address 4'1000). + Merging ports 9, 78 (address 4'1000). + Merging ports 9, 79 (address 4'1000). + Merging ports 9, 80 (address 4'1000). + Merging ports 10, 11 (address 4'1010). + Merging ports 12, 13 (address 4'1100). + Merging ports 12, 14 (address 4'1100). + Merging ports 12, 15 (address 4'1100). + Merging ports 17, 18 (address 4'0000). + Merging ports 17, 19 (address 4'0000). + Merging ports 17, 20 (address 4'0000). + Merging ports 17, 21 (address 4'0000). + Merging ports 17, 22 (address 4'0000). + Merging ports 17, 23 (address 4'0000). + Merging ports 17, 24 (address 4'0000). + Merging ports 17, 25 (address 4'0000). + Merging ports 17, 26 (address 4'0000). + Merging ports 17, 27 (address 4'0000). + Merging ports 17, 28 (address 4'0000). + Merging ports 17, 29 (address 4'0000). + Merging ports 17, 30 (address 4'0000). + Merging ports 17, 31 (address 4'0000). + Merging ports 17, 32 (address 4'0000). + Merging ports 17, 33 (address 4'0000). + Merging ports 17, 34 (address 4'0000). + Merging ports 17, 35 (address 4'0000). + Merging ports 17, 36 (address 4'0000). + Merging ports 17, 37 (address 4'0000). + Merging ports 17, 38 (address 4'0000). + Merging ports 17, 39 (address 4'0000). + Merging ports 17, 40 (address 4'0000). + Merging ports 17, 41 (address 4'0000). + Merging ports 17, 42 (address 4'0000). + Merging ports 17, 43 (address 4'0000). + Merging ports 17, 44 (address 4'0000). + Merging ports 17, 45 (address 4'0000). + Merging ports 17, 46 (address 4'0000). + Merging ports 17, 47 (address 4'0000). + Merging ports 17, 48 (address 4'0000). +Consolidating write ports of memory fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved by address: + Merging ports 1, 2 (address 4'1000). + Merging ports 1, 3 (address 4'1000). + Merging ports 1, 5 (address 4'1000). +Consolidating write ports of memory fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved by address: +Consolidating read ports of memory fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_required by address: + Merging ports 0, 1 (address 4'0000). + Merging ports 0, 2 (address 4'0000). + Merging ports 0, 3 (address 4'0000). + Merging ports 0, 4 (address 4'0000). + Merging ports 0, 5 (address 4'0000). + Merging ports 0, 6 (address 4'0000). + Merging ports 0, 7 (address 4'0000). + Merging ports 0, 8 (address 4'0000). + Merging ports 10, 11 (address 4'1010). + Merging ports 12, 13 (address 4'1100). + Merging ports 12, 14 (address 4'1100). + Merging ports 12, 15 (address 4'1100). +Consolidating read ports of memory fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_required by address: + Merging ports 1, 2 (address 4'1001). + Merging ports 1, 3 (address 4'1000). +Consolidating read ports of memory fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_required by address: +Consolidating write ports of memory fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_required by address: + Merging ports 0, 1 (address 4'0000). + Merging ports 0, 2 (address 4'0000). + Merging ports 0, 3 (address 4'0000). + Merging ports 0, 4 (address 4'0000). + Merging ports 0, 5 (address 4'0000). + Merging ports 0, 6 (address 4'0000). + Merging ports 0, 7 (address 4'0000). + Merging ports 0, 8 (address 4'0000). + Merging ports 10, 11 (address 4'1010). + Merging ports 12, 13 (address 4'1100). + Merging ports 12, 14 (address 4'1100). + Merging ports 12, 15 (address 4'1100). +Consolidating write ports of memory fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_required by address: + Merging ports 1, 2 (address 4'1001). + Merging ports 1, 3 (address 4'1000). +Consolidating write ports of memory fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_required by address: +Consolidating read ports of memory fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state by address: + Merging ports 1, 2 (address 4'0000). + Merging ports 1, 3 (address 4'0000). + Merging ports 1, 4 (address 4'0000). + Merging ports 1, 5 (address 4'0000). + Merging ports 1, 6 (address 4'0000). + Merging ports 1, 7 (address 4'0000). + Merging ports 1, 8 (address 4'0000). + Merging ports 1, 9 (address 4'0000). + Merging ports 11, 12 (address 4'1010). + Merging ports 13, 14 (address 4'1100). + Merging ports 13, 15 (address 4'1100). + Merging ports 13, 16 (address 4'1100). +Consolidating read ports of memory fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state by address: + Merging ports 2, 3 (address 4'1001). + Merging ports 2, 4 (address 4'1000). +Consolidating read ports of memory fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state by address: +Consolidating write ports of memory fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state by address: + Merging ports 0, 1 (address 4'0000). + Merging ports 0, 2 (address 4'0000). + Merging ports 0, 3 (address 4'0000). + Merging ports 0, 4 (address 4'0000). + Merging ports 0, 5 (address 4'0000). + Merging ports 0, 6 (address 4'0000). + Merging ports 0, 7 (address 4'0000). + Merging ports 0, 8 (address 4'0000). + Merging ports 9, 49 (address 4'1001). + Merging ports 9, 50 (address 4'1000). + Merging ports 9, 51 (address 4'1000). + Merging ports 9, 52 (address 4'1000). + Merging ports 9, 53 (address 4'1000). + Merging ports 9, 54 (address 4'1000). + Merging ports 9, 55 (address 4'1000). + Merging ports 9, 56 (address 4'1000). + Merging ports 9, 57 (address 4'1000). + Merging ports 9, 58 (address 4'1000). + Merging ports 9, 59 (address 4'1000). + Merging ports 9, 60 (address 4'1000). + Merging ports 9, 61 (address 4'1000). + Merging ports 9, 62 (address 4'1000). + Merging ports 9, 63 (address 4'1000). + Merging ports 9, 64 (address 4'1000). + Merging ports 9, 65 (address 4'1000). + Merging ports 9, 66 (address 4'1000). + Merging ports 9, 67 (address 4'1000). + Merging ports 9, 68 (address 4'1000). + Merging ports 9, 69 (address 4'1000). + Merging ports 9, 70 (address 4'1000). + Merging ports 9, 71 (address 4'1000). + Merging ports 9, 72 (address 4'1000). + Merging ports 9, 73 (address 4'1000). + Merging ports 9, 74 (address 4'1000). + Merging ports 9, 75 (address 4'1000). + Merging ports 9, 76 (address 4'1000). + Merging ports 9, 77 (address 4'1000). + Merging ports 9, 78 (address 4'1000). + Merging ports 9, 79 (address 4'1000). + Merging ports 9, 80 (address 4'1000). + Merging ports 10, 11 (address 4'1010). + Merging ports 12, 13 (address 4'1100). + Merging ports 12, 14 (address 4'1100). + Merging ports 12, 15 (address 4'1100). + Merging ports 17, 18 (address 4'0000). + Merging ports 17, 19 (address 4'0000). + Merging ports 17, 20 (address 4'0000). + Merging ports 17, 21 (address 4'0000). + Merging ports 17, 22 (address 4'0000). + Merging ports 17, 23 (address 4'0000). + Merging ports 17, 24 (address 4'0000). + Merging ports 17, 25 (address 4'0000). + Merging ports 17, 26 (address 4'0000). + Merging ports 17, 27 (address 4'0000). + Merging ports 17, 28 (address 4'0000). + Merging ports 17, 29 (address 4'0000). + Merging ports 17, 30 (address 4'0000). + Merging ports 17, 31 (address 4'0000). + Merging ports 17, 32 (address 4'0000). + Merging ports 17, 33 (address 4'0000). + Merging ports 17, 34 (address 4'0000). + Merging ports 17, 35 (address 4'0000). + Merging ports 17, 36 (address 4'0000). + Merging ports 17, 37 (address 4'0000). + Merging ports 17, 38 (address 4'0000). + Merging ports 17, 39 (address 4'0000). + Merging ports 17, 40 (address 4'0000). + Merging ports 17, 41 (address 4'0000). + Merging ports 17, 42 (address 4'0000). + Merging ports 17, 43 (address 4'0000). + Merging ports 17, 44 (address 4'0000). + Merging ports 17, 45 (address 4'0000). + Merging ports 17, 46 (address 4'0000). + Merging ports 17, 47 (address 4'0000). + Merging ports 17, 48 (address 4'0000). +Consolidating write ports of memory fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state by address: + Merging ports 1, 2 (address 4'1000). + Merging ports 1, 3 (address 4'1000). + Merging ports 1, 5 (address 4'1000). +Consolidating write ports of memory fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state by address: +Consolidating write ports of memory fpga_neural_v2_top.u_sdram_backend.w_cache_valid using sat-based resource sharing: + Checking group clocked with posedge \u_arbiter.clk, width 1: ports 1, 2, 3. + Common input cone for all EN signals: 22 cells. + Size of unconstrained SAT problem: 528 variables, 1251 clauses + Merging port 2 into port 1. + Merging port 3 into port 1. +Consolidating write ports of memory fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_producer_ids using sat-based resource sharing: + Checking group clocked with posedge \u_arbiter.clk, width 4: ports 0, 1, 2, 3. + Common input cone for all EN signals: 6 cells. + Size of unconstrained SAT problem: 39 variables, 86 clauses + According to SAT solver sharing of port 0 with port 1 is not possible. + According to SAT solver sharing of port 0 with port 2 is not possible. + According to SAT solver sharing of port 0 with port 3 is not possible. + According to SAT solver sharing of port 1 with port 2 is not possible. + According to SAT solver sharing of port 1 with port 3 is not possible. + According to SAT solver sharing of port 2 with port 3 is not possible. +Consolidating write ports of memory fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved using sat-based resource sharing: + Checking group clocked with posedge \u_arbiter.clk, width 48: ports 0, 1. + Common input cone for all EN signals: 523 cells. + Size of unconstrained SAT problem: 4399 variables, 11182 clauses + According to SAT solver sharing of port 0 with port 1 is not possible. +Consolidating write ports of memory fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_required using sat-based resource sharing: +Consolidating write ports of memory fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state using sat-based resource sharing: + Checking group clocked with posedge \u_arbiter.clk, width 32: ports 0, 1. + Common input cone for all EN signals: 651 cells. + Size of unconstrained SAT problem: 6783 variables, 17518 clauses + According to SAT solver sharing of port 0 with port 1 is not possible. + Checking group clocked with posedge \u_arbiter.clk, width 2: ports 2, 3. + Common input cone for all EN signals: 790 cells. + Size of unconstrained SAT problem: 7490 variables, 19347 clauses + According to SAT solver sharing of port 2 with port 3 is not possible. + +19.26.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). +Performed a total of 0 transformations. + +19.26.9. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \fpga_neural_v2_top.. +Removed 8 unused cells and 179 unused wires. + + +19.26.10. Executing MEMORY_COLLECT pass (generating $mem cells). + +19.27. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \fpga_neural_v2_top.. + +19.28. Executing MEMORY_LIBMAP pass (mapping memories to cells). +mapping memory fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_result_addr via $__TRELLIS_DPR16X4_ +Extracted data FF from read port 0 of fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_result_addr: $\u_dataflow_core.u_dep_mgr.node_result_addr$rdreg[0] +mapping memory fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_n_tiles via $__TRELLIS_DPR16X4_ +Extracted data FF from read port 0 of fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_n_tiles: $\u_dataflow_core.u_dep_mgr.node_n_tiles$rdreg[0] +mapping memory fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_w_base via $__TRELLIS_DPR16X4_ +Extracted data FF from read port 0 of fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_w_base: $\u_dataflow_core.u_dep_mgr.node_w_base$rdreg[0] +mapping memory fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_x_base via $__TRELLIS_DPR16X4_ +Extracted data FF from read port 0 of fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_x_base: $\u_dataflow_core.u_dep_mgr.node_x_base$rdreg[0] +using FF mapping for memory fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_resolved +using FF mapping for memory fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_required +using FF mapping for memory fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_producer_ids +mapping memory fpga_neural_v2_top.u_sdram_backend.w_cache_data via $__TRELLIS_DPR16X4_ +mapping memory fpga_neural_v2_top.u_dataflow_core.u_director.q_node_id via $__TRELLIS_DPR16X4_ +Extracted addr FF from read port 0 of fpga_neural_v2_top.u_dataflow_core.u_director.q_node_id: $\u_dataflow_core.u_director.q_node_id$rdreg[0] +mapping memory fpga_neural_v2_top.u_dataflow_core.u_director.q_result_addr via $__TRELLIS_DPR16X4_ +Extracted addr FF from read port 0 of fpga_neural_v2_top.u_dataflow_core.u_director.q_result_addr: $\u_dataflow_core.u_director.q_result_addr$rdreg[0] +mapping memory fpga_neural_v2_top.u_dataflow_core.u_director.q_n_tiles via $__TRELLIS_DPR16X4_ +Extracted addr FF from read port 0 of fpga_neural_v2_top.u_dataflow_core.u_director.q_n_tiles: $\u_dataflow_core.u_director.q_n_tiles$rdreg[0] +mapping memory fpga_neural_v2_top.u_dataflow_core.u_director.q_w_base via $__TRELLIS_DPR16X4_ +Extracted addr FF from read port 0 of fpga_neural_v2_top.u_dataflow_core.u_director.q_w_base: $\u_dataflow_core.u_director.q_w_base$rdreg[0] +mapping memory fpga_neural_v2_top.u_dataflow_core.u_director.q_x_base via $__TRELLIS_DPR16X4_ +Extracted addr FF from read port 0 of fpga_neural_v2_top.u_dataflow_core.u_director.q_x_base: $\u_dataflow_core.u_director.q_x_base$rdreg[0] +mapping memory fpga_neural_v2_top.u_dataflow_core.u_act_mem.GEN_COPY[3].mem via $__TRELLIS_DPR16X4_ +Extracted data FF from read port 0 of fpga_neural_v2_top.u_dataflow_core.u_act_mem.GEN_COPY[3].mem: $\u_dataflow_core.u_act_mem.GEN_COPY[3].mem$rdreg[0] +mapping memory fpga_neural_v2_top.u_dataflow_core.u_act_mem.GEN_COPY[2].mem via $__TRELLIS_DPR16X4_ +Extracted data FF from read port 0 of fpga_neural_v2_top.u_dataflow_core.u_act_mem.GEN_COPY[2].mem: $\u_dataflow_core.u_act_mem.GEN_COPY[2].mem$rdreg[0] +mapping memory fpga_neural_v2_top.u_dataflow_core.u_act_mem.GEN_COPY[1].mem via $__TRELLIS_DPR16X4_ +Extracted data FF from read port 0 of fpga_neural_v2_top.u_dataflow_core.u_act_mem.GEN_COPY[1].mem: $\u_dataflow_core.u_act_mem.GEN_COPY[1].mem$rdreg[0] +mapping memory fpga_neural_v2_top.u_dataflow_core.u_act_mem.GEN_COPY[0].mem via $__TRELLIS_DPR16X4_ +Extracted data FF from read port 0 of fpga_neural_v2_top.u_dataflow_core.u_act_mem.GEN_COPY[0].mem: $\u_dataflow_core.u_act_mem.GEN_COPY[0].mem$rdreg[0] +mapping memory fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[3].GEN_LANE[7].mem via $__TRELLIS_DPR16X4_ +Extracted data FF from read port 0 of fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[3].GEN_LANE[7].mem: $\u_dataflow_core.u_wgt_mem.GEN_SLOT[3].GEN_LANE[7].mem$rdreg[0] +mapping memory fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[3].GEN_LANE[6].mem via $__TRELLIS_DPR16X4_ +Extracted data FF from read port 0 of fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[3].GEN_LANE[6].mem: $\u_dataflow_core.u_wgt_mem.GEN_SLOT[3].GEN_LANE[6].mem$rdreg[0] +mapping memory fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[3].GEN_LANE[5].mem via $__TRELLIS_DPR16X4_ +Extracted data FF from read port 0 of fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[3].GEN_LANE[5].mem: $\u_dataflow_core.u_wgt_mem.GEN_SLOT[3].GEN_LANE[5].mem$rdreg[0] +mapping memory fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[3].GEN_LANE[4].mem via $__TRELLIS_DPR16X4_ +Extracted data FF from read port 0 of fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[3].GEN_LANE[4].mem: $\u_dataflow_core.u_wgt_mem.GEN_SLOT[3].GEN_LANE[4].mem$rdreg[0] +mapping memory fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[3].GEN_LANE[3].mem via $__TRELLIS_DPR16X4_ +Extracted data FF from read port 0 of fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[3].GEN_LANE[3].mem: $\u_dataflow_core.u_wgt_mem.GEN_SLOT[3].GEN_LANE[3].mem$rdreg[0] +mapping memory fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[3].GEN_LANE[2].mem via $__TRELLIS_DPR16X4_ +Extracted data FF from read port 0 of fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[3].GEN_LANE[2].mem: $\u_dataflow_core.u_wgt_mem.GEN_SLOT[3].GEN_LANE[2].mem$rdreg[0] +mapping memory fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[3].GEN_LANE[1].mem via $__TRELLIS_DPR16X4_ +Extracted data FF from read port 0 of fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[3].GEN_LANE[1].mem: $\u_dataflow_core.u_wgt_mem.GEN_SLOT[3].GEN_LANE[1].mem$rdreg[0] +mapping memory fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[3].GEN_LANE[0].mem via $__TRELLIS_DPR16X4_ +Extracted data FF from read port 0 of fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[3].GEN_LANE[0].mem: $\u_dataflow_core.u_wgt_mem.GEN_SLOT[3].GEN_LANE[0].mem$rdreg[0] +mapping memory fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[2].GEN_LANE[7].mem via $__TRELLIS_DPR16X4_ +Extracted data FF from read port 0 of fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[2].GEN_LANE[7].mem: $\u_dataflow_core.u_wgt_mem.GEN_SLOT[2].GEN_LANE[7].mem$rdreg[0] +mapping memory fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[2].GEN_LANE[6].mem via $__TRELLIS_DPR16X4_ +Extracted data FF from read port 0 of fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[2].GEN_LANE[6].mem: $\u_dataflow_core.u_wgt_mem.GEN_SLOT[2].GEN_LANE[6].mem$rdreg[0] +mapping memory fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[2].GEN_LANE[5].mem via $__TRELLIS_DPR16X4_ +Extracted data FF from read port 0 of fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[2].GEN_LANE[5].mem: $\u_dataflow_core.u_wgt_mem.GEN_SLOT[2].GEN_LANE[5].mem$rdreg[0] +mapping memory fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[2].GEN_LANE[4].mem via $__TRELLIS_DPR16X4_ +Extracted data FF from read port 0 of fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[2].GEN_LANE[4].mem: $\u_dataflow_core.u_wgt_mem.GEN_SLOT[2].GEN_LANE[4].mem$rdreg[0] +mapping memory fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[2].GEN_LANE[3].mem via $__TRELLIS_DPR16X4_ +Extracted data FF from read port 0 of fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[2].GEN_LANE[3].mem: $\u_dataflow_core.u_wgt_mem.GEN_SLOT[2].GEN_LANE[3].mem$rdreg[0] +mapping memory fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[2].GEN_LANE[2].mem via $__TRELLIS_DPR16X4_ +Extracted data FF from read port 0 of fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[2].GEN_LANE[2].mem: $\u_dataflow_core.u_wgt_mem.GEN_SLOT[2].GEN_LANE[2].mem$rdreg[0] +mapping memory fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[2].GEN_LANE[1].mem via $__TRELLIS_DPR16X4_ +Extracted data FF from read port 0 of fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[2].GEN_LANE[1].mem: $\u_dataflow_core.u_wgt_mem.GEN_SLOT[2].GEN_LANE[1].mem$rdreg[0] +mapping memory fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[2].GEN_LANE[0].mem via $__TRELLIS_DPR16X4_ +Extracted data FF from read port 0 of fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[2].GEN_LANE[0].mem: $\u_dataflow_core.u_wgt_mem.GEN_SLOT[2].GEN_LANE[0].mem$rdreg[0] +mapping memory fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[1].GEN_LANE[7].mem via $__TRELLIS_DPR16X4_ +Extracted data FF from read port 0 of fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[1].GEN_LANE[7].mem: $\u_dataflow_core.u_wgt_mem.GEN_SLOT[1].GEN_LANE[7].mem$rdreg[0] +mapping memory fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[1].GEN_LANE[6].mem via $__TRELLIS_DPR16X4_ +Extracted data FF from read port 0 of fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[1].GEN_LANE[6].mem: $\u_dataflow_core.u_wgt_mem.GEN_SLOT[1].GEN_LANE[6].mem$rdreg[0] +mapping memory fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[1].GEN_LANE[5].mem via $__TRELLIS_DPR16X4_ +Extracted data FF from read port 0 of fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[1].GEN_LANE[5].mem: $\u_dataflow_core.u_wgt_mem.GEN_SLOT[1].GEN_LANE[5].mem$rdreg[0] +mapping memory fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[1].GEN_LANE[4].mem via $__TRELLIS_DPR16X4_ +Extracted data FF from read port 0 of fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[1].GEN_LANE[4].mem: $\u_dataflow_core.u_wgt_mem.GEN_SLOT[1].GEN_LANE[4].mem$rdreg[0] +mapping memory fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[1].GEN_LANE[3].mem via $__TRELLIS_DPR16X4_ +Extracted data FF from read port 0 of fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[1].GEN_LANE[3].mem: $\u_dataflow_core.u_wgt_mem.GEN_SLOT[1].GEN_LANE[3].mem$rdreg[0] +mapping memory fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[1].GEN_LANE[2].mem via $__TRELLIS_DPR16X4_ +Extracted data FF from read port 0 of fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[1].GEN_LANE[2].mem: $\u_dataflow_core.u_wgt_mem.GEN_SLOT[1].GEN_LANE[2].mem$rdreg[0] +mapping memory fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[1].GEN_LANE[1].mem via $__TRELLIS_DPR16X4_ +Extracted data FF from read port 0 of fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[1].GEN_LANE[1].mem: $\u_dataflow_core.u_wgt_mem.GEN_SLOT[1].GEN_LANE[1].mem$rdreg[0] +mapping memory fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[1].GEN_LANE[0].mem via $__TRELLIS_DPR16X4_ +Extracted data FF from read port 0 of fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[1].GEN_LANE[0].mem: $\u_dataflow_core.u_wgt_mem.GEN_SLOT[1].GEN_LANE[0].mem$rdreg[0] +mapping memory fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[0].GEN_LANE[7].mem via $__TRELLIS_DPR16X4_ +Extracted data FF from read port 0 of fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[0].GEN_LANE[7].mem: $\u_dataflow_core.u_wgt_mem.GEN_SLOT[0].GEN_LANE[7].mem$rdreg[0] +mapping memory fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[0].GEN_LANE[6].mem via $__TRELLIS_DPR16X4_ +Extracted data FF from read port 0 of fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[0].GEN_LANE[6].mem: $\u_dataflow_core.u_wgt_mem.GEN_SLOT[0].GEN_LANE[6].mem$rdreg[0] +mapping memory fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[0].GEN_LANE[5].mem via $__TRELLIS_DPR16X4_ +Extracted data FF from read port 0 of fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[0].GEN_LANE[5].mem: $\u_dataflow_core.u_wgt_mem.GEN_SLOT[0].GEN_LANE[5].mem$rdreg[0] +mapping memory fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[0].GEN_LANE[4].mem via $__TRELLIS_DPR16X4_ +Extracted data FF from read port 0 of fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[0].GEN_LANE[4].mem: $\u_dataflow_core.u_wgt_mem.GEN_SLOT[0].GEN_LANE[4].mem$rdreg[0] +mapping memory fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[0].GEN_LANE[3].mem via $__TRELLIS_DPR16X4_ +Extracted data FF from read port 0 of fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[0].GEN_LANE[3].mem: $\u_dataflow_core.u_wgt_mem.GEN_SLOT[0].GEN_LANE[3].mem$rdreg[0] +mapping memory fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[0].GEN_LANE[2].mem via $__TRELLIS_DPR16X4_ +Extracted data FF from read port 0 of fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[0].GEN_LANE[2].mem: $\u_dataflow_core.u_wgt_mem.GEN_SLOT[0].GEN_LANE[2].mem$rdreg[0] +mapping memory fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[0].GEN_LANE[1].mem via $__TRELLIS_DPR16X4_ +Extracted data FF from read port 0 of fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[0].GEN_LANE[1].mem: $\u_dataflow_core.u_wgt_mem.GEN_SLOT[0].GEN_LANE[1].mem$rdreg[0] +mapping memory fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[0].GEN_LANE[0].mem via $__TRELLIS_DPR16X4_ +Extracted data FF from read port 0 of fpga_neural_v2_top.u_dataflow_core.u_wgt_mem.GEN_SLOT[0].GEN_LANE[0].mem: $\u_dataflow_core.u_wgt_mem.GEN_SLOT[0].GEN_LANE[0].mem$rdreg[0] +using FF mapping for memory fpga_neural_v2_top.u_sdram_backend.w_cache_addr +using FF mapping for memory fpga_neural_v2_top.u_sdram_backend.w_cache_valid +using FF mapping for memory fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state + + +19.29. Executing TECHMAP pass (map to technology primitives). + +19.29.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v' to AST representation. +Generating RTLIL representation for module `$__TRELLIS_DPR16X4_'. +Successfully finished Verilog frontend. + +19.29.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v' to AST representation. +Generating RTLIL representation for module `$__DP16KD_'. +Generating RTLIL representation for module `$__PDPW16KD_'. +Successfully finished Verilog frontend. + +19.29.3. Continuing TECHMAP pass. +Using template $paramod$04778961cc1285a5efea28f98f28381eb2862208$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. +No more expansions possible. + + +19.30. Executing OPT pass (performing simple optimizations). + +19.30.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module fpga_neural_v2_top. + + +19.30.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\fpga_neural_v2_top'. +Computing hashes of 3976 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. +Computing hashes of 3873 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. +Computing hashes of 3841 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. +Computing hashes of 3837 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. + +Removed a total of 139 cells. + +19.30.3. Executing OPT_DFF pass (perform DFF optimizations). +Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$24403 ($sdffe) from module fpga_neural_v2_top. + +19.30.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \fpga_neural_v2_top.. +Removed 3 unused cells and 2195 unused wires. + + +19.30.5. Rerunning OPT passes. (Removed registers in this run.) + +19.30.6. Executing OPT_EXPR pass (perform const folding). +Optimizing module fpga_neural_v2_top. + + +19.30.7. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\fpga_neural_v2_top'. +Computing hashes of 3821 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. +Removed a total of 0 cells. + +19.30.8. Executing OPT_DFF pass (perform DFF optimizations). +Adding SRST signal on $\u_dataflow_core.u_director.q_node_id$rdreg[0] ($dff) from module fpga_neural_v2_top (D = $auto$rtlil.cc:3402:Mux$26827, Q = $\u_dataflow_core.u_director.q_n_tiles$rdreg[0]$q, rval = 3'000). +Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$24638 ($sdffe) from module fpga_neural_v2_top. + +19.30.9. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \fpga_neural_v2_top.. +Removed 1 unused cells and 12 unused wires. + + +19.30.10. Rerunning OPT passes. (Removed registers in this run.) + +19.30.11. Executing OPT_EXPR pass (perform const folding). +Optimizing module fpga_neural_v2_top. + +19.30.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\fpga_neural_v2_top'. +Computing hashes of 3819 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. +Removed a total of 0 cells. + +19.30.13. Executing OPT_DFF pass (perform DFF optimizations). + +19.30.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \fpga_neural_v2_top.. + +19.30.15. Finished fast OPT passes. + +19.31. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). +Mapping memory \u_dataflow_core.u_dep_mgr.node_resolved in module \fpga_neural_v2_top: + created 16 $dff cells and 0 static cells of width 3. + read interface: 0 $dff and 1 $mux cells. + write interface: 48 write mux blocks. +Mapping memory \u_dataflow_core.u_dep_mgr.node_required in module \fpga_neural_v2_top: + created 16 $dff cells and 0 static cells of width 3. + read interface: 0 $dff and 1 $mux cells. + write interface: 48 write mux blocks. +Mapping memory \u_dataflow_core.u_dep_mgr.node_producer_ids in module \fpga_neural_v2_top: + created 64 $dff cells and 0 static cells of width 4. + read interface: 0 $dff and 1 $mux cells. + write interface: 256 write mux blocks. +Mapping memory \u_sdram_backend.w_cache_addr in module \fpga_neural_v2_top: + created 4 $dff cells and 0 static cells of width 23. + read interface: 0 $dff and 3 $mux cells. + write interface: 4 write mux blocks. +Mapping memory \u_sdram_backend.w_cache_valid in module \fpga_neural_v2_top: + created 4 $dff cells and 0 static cells of width 1. + read interface: 0 $dff and 3 $mux cells. + write interface: 8 write mux blocks. +Mapping memory \u_dataflow_core.u_dep_mgr.node_state in module \fpga_neural_v2_top: + created 16 $dff cells and 0 static cells of width 2. +Extracted addr FF from read port 0 of fpga_neural_v2_top.u_dataflow_core.u_dep_mgr.node_state: $\u_dataflow_core.u_dep_mgr.node_state$rdreg[0] + read interface: 1 $dff and 16 $mux cells. + write interface: 64 write mux blocks. + +19.32. Executing OPT pass (performing simple optimizations). + +19.32.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module fpga_neural_v2_top. + + +19.32.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\fpga_neural_v2_top'. +Computing hashes of 4430 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. +Computing hashes of 4382 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. +Computing hashes of 4334 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. + +Removed a total of 96 cells. + +19.32.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \fpga_neural_v2_top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Replacing known input bits on port B of cell $auto$memory_share.cc:454:consolidate_wr_using_sat$28061: $auto$rtlil.cc:3271:ReduceOr$28055 -> 1'1 + Replacing known input bits on port B of cell $auto$memory_share.cc:454:consolidate_wr_using_sat$28053: $auto$rtlil.cc:3271:ReduceOr$28047 -> 1'1 + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +19.32.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \fpga_neural_v2_top. + Consolidated identical input bits for $mux cell $auto$memory_share.cc:274:consolidate_wr_by_addr$27558: + Old ports: A=2'00, B=2'10, Y=$auto$rtlil.cc:3402:Mux$27559 + New ports: A=1'0, B=1'1, Y=$auto$rtlil.cc:3402:Mux$27559 [1] + New connections: $auto$rtlil.cc:3402:Mux$27559 [0] = 1'0 + New ctrl vector for $pmux cell $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10078: $auto$opt_reduce.cc:137:opt_pmux$31508 + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$18131: + Old ports: A=4'0000, B=4'1111, Y=$flatten\u_dataflow_core.\u_dep_mgr.$1\first_ready_idx[3:0] + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_dep_mgr.$1\first_ready_idx[3:0] [0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$1\first_ready_idx[3:0] [3:1] = { $flatten\u_dataflow_core.\u_dep_mgr.$1\first_ready_idx[3:0] [0] $flatten\u_dataflow_core.\u_dep_mgr.$1\first_ready_idx[3:0] [0] $flatten\u_dataflow_core.\u_dep_mgr.$1\first_ready_idx[3:0] [0] } + Consolidated identical input bits for $mux cell $flatten\u_arbiter_wide.$procmux$8823: + Old ports: A=2'00, B=2'11, Y=$auto$wreduce.cc:514:run$24877 [1:0] + New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:514:run$24877 [0] + New connections: $auto$wreduce.cc:514:run$24877 [1] = $auto$wreduce.cc:514:run$24877 [0] + Consolidated identical input bits for $mux cell $flatten\u_arbiter.$procmux$8201: + Old ports: A=3'000, B=3'100, Y=$flatten\u_arbiter.$1\grant_idx[2:0] + New ports: A=1'0, B=1'1, Y=$flatten\u_arbiter.$1\grant_idx[2:0] [2] + New connections: $flatten\u_arbiter.$1\grant_idx[2:0] [1:0] = 2'00 + Consolidated identical input bits for $mux cell $auto$memory_share.cc:274:consolidate_wr_by_addr$26854: + Old ports: A={ $flatten\u_sdram_backend.$0$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:292$6938_DATA[22:0]$6979 [22:3] \u_sdram_backend.w_pending_addr [2:0] }, B={ $flatten\u_sdram_backend.$0$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:296$6940_DATA[22:0]$6985 [22:3] \u_sdram_backend.w_pending_addr [2:0] }, Y=$auto$rtlil.cc:3402:Mux$26855 + New ports: A=$flatten\u_sdram_backend.$0$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:292$6938_DATA[22:0]$6979 [22:3], B=$flatten\u_sdram_backend.$0$memwr$\w_cache_addr$hardware/v2/nms/rtl/sdram_unified_backend.v:296$6940_DATA[22:0]$6985 [22:3], Y=$auto$rtlil.cc:3402:Mux$26855 [22:3] + New connections: $auto$rtlil.cc:3402:Mux$26855 [2:0] = \u_sdram_backend.w_pending_addr [2:0] + Consolidated identical input bits for $mux cell $auto$memory_share.cc:274:consolidate_wr_by_addr$27970: + Old ports: A=2'10, B=2'00, Y=$auto$rtlil.cc:3402:Mux$27959 + New ports: A=1'1, B=1'0, Y=$auto$rtlil.cc:3402:Mux$27959 [1] + New connections: $auto$rtlil.cc:3402:Mux$27959 [0] = 1'0 + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_director.$procmux$19293: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_director.$1\free_slot_idx[1:0] + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_director.$1\free_slot_idx[1:0] [0] + New connections: $flatten\u_dataflow_core.\u_director.$1\free_slot_idx[1:0] [1] = $flatten\u_dataflow_core.\u_director.$1\free_slot_idx[1:0] [0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_director.$procmux$19281: + Old ports: A=2'00, B=2'11, Y=$flatten\u_dataflow_core.\u_director.$1\done_slot_idx[1:0] + New ports: A=1'0, B=1'1, Y=$flatten\u_dataflow_core.\u_director.$1\done_slot_idx[1:0] [0] + New connections: $flatten\u_dataflow_core.\u_director.$1\done_slot_idx[1:0] [1] = $flatten\u_dataflow_core.\u_director.$1\done_slot_idx[1:0] [0] + Consolidated identical input bits for $mux cell $flatten\u_sdram_backend.$procmux$9577: + Old ports: A={ \u_sdram_backend.ar_eff_addr [21:3] 3'000 }, B={ \u_sdram_backend.w_eff_addr [22:4] 3'000 }, Y=$flatten\u_sdram_backend.$procmux$9577_Y + New ports: A=\u_sdram_backend.ar_eff_addr [21:3], B=\u_sdram_backend.w_eff_addr [22:4], Y=$flatten\u_sdram_backend.$procmux$9577_Y [21:3] + New connections: $flatten\u_sdram_backend.$procmux$9577_Y [2:0] = 3'000 + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$procmux$10641: + Old ports: A={ $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:139$6826_Y [22:3] \u_dataflow_core.GEN_SLOT[0].u_mm.w_base_reg [2:0] }, B={ $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:150$6832_Y [22:3] \u_dataflow_core.GEN_SLOT[0].u_mm.w_base_reg [2:0] }, Y=$flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$procmux$10641_Y + New ports: A=$flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:139$6826_Y [22:3], B=$flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:150$6832_Y [22:3], Y=$flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$procmux$10641_Y [22:3] + New connections: $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$procmux$10641_Y [2:0] = \u_dataflow_core.GEN_SLOT[0].u_mm.w_base_reg [2:0] + New ctrl vector for $pmux cell $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10136: { \u_sdram_backend.u_sdram_ctrl.state [0] $auto$opt_reduce.cc:137:opt_pmux$31510 \u_sdram_backend.u_sdram_ctrl.state [2] \u_sdram_backend.u_sdram_ctrl.state [10:9] \u_sdram_backend.u_sdram_ctrl.state [5] } + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$procmux$10641: + Old ports: A={ $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:139$6826_Y [22:3] \u_dataflow_core.GEN_SLOT[1].u_mm.w_base_reg [2:0] }, B={ $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:150$6832_Y [22:3] \u_dataflow_core.GEN_SLOT[1].u_mm.w_base_reg [2:0] }, Y=$flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$procmux$10641_Y + New ports: A=$flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:139$6826_Y [22:3], B=$flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:150$6832_Y [22:3], Y=$flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$procmux$10641_Y [22:3] + New connections: $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$procmux$10641_Y [2:0] = \u_dataflow_core.GEN_SLOT[1].u_mm.w_base_reg [2:0] + New ctrl vector for $pmux cell $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10220: \u_sdram_backend.u_sdram_ctrl.state [10] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$procmux$10641: + Old ports: A={ $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:139$6826_Y [22:3] \u_dataflow_core.GEN_SLOT[2].u_mm.w_base_reg [2:0] }, B={ $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:150$6832_Y [22:3] \u_dataflow_core.GEN_SLOT[2].u_mm.w_base_reg [2:0] }, Y=$flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$procmux$10641_Y + New ports: A=$flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:139$6826_Y [22:3], B=$flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:150$6832_Y [22:3], Y=$flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$procmux$10641_Y [22:3] + New connections: $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$procmux$10641_Y [2:0] = \u_dataflow_core.GEN_SLOT[2].u_mm.w_base_reg [2:0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$procmux$10641: + Old ports: A={ $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:139$6826_Y [22:3] \u_dataflow_core.GEN_SLOT[3].u_mm.w_base_reg [2:0] }, B={ $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:150$6832_Y [22:3] \u_dataflow_core.GEN_SLOT[3].u_mm.w_base_reg [2:0] }, Y=$flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$procmux$10641_Y + New ports: A=$flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:139$6826_Y [22:3], B=$flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:150$6832_Y [22:3], Y=$flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$procmux$10641_Y [22:3] + New connections: $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$procmux$10641_Y [2:0] = \u_dataflow_core.GEN_SLOT[3].u_mm.w_base_reg [2:0] + Consolidated identical input bits for $mux cell $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10164: + Old ports: A=14'00000000000001, B=14'00000000000011, Y=$flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10164_Y + New ports: A=1'0, B=1'1, Y=$flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10164_Y [1] + New connections: { $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10164_Y [13:2] $flatten\u_sdram_backend.\u_sdram_ctrl.$procmux$10164_Y [0] } = 13'0000000000001 + Optimizing cells in module \fpga_neural_v2_top. + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$18125: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$1\first_ready_idx[3:0], B=4'1110, Y=$flatten\u_dataflow_core.\u_dep_mgr.$2\first_ready_idx[3:0] + New ports: A={ $flatten\u_dataflow_core.\u_dep_mgr.$1\first_ready_idx[3:0] [0] $flatten\u_dataflow_core.\u_dep_mgr.$1\first_ready_idx[3:0] [0] }, B=2'10, Y=$flatten\u_dataflow_core.\u_dep_mgr.$2\first_ready_idx[3:0] [1:0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$2\first_ready_idx[3:0] [3:2] = { $flatten\u_dataflow_core.\u_dep_mgr.$2\first_ready_idx[3:0] [1] $flatten\u_dataflow_core.\u_dep_mgr.$2\first_ready_idx[3:0] [1] } + Consolidated identical input bits for $mux cell $flatten\u_arbiter.$procmux$8195: + Old ports: A=$flatten\u_arbiter.$1\grant_idx[2:0], B=3'011, Y=$flatten\u_arbiter.$2\grant_idx[2:0] + New ports: A={ $flatten\u_arbiter.$1\grant_idx[2:0] [2] 1'0 }, B=2'01, Y={ $flatten\u_arbiter.$2\grant_idx[2:0] [2] $flatten\u_arbiter.$2\grant_idx[2:0] [0] } + New connections: $flatten\u_arbiter.$2\grant_idx[2:0] [1] = $flatten\u_arbiter.$2\grant_idx[2:0] [0] + Consolidated identical input bits for $mux cell $auto$memory_share.cc:274:consolidate_wr_by_addr$27570: + Old ports: A=$auto$rtlil.cc:3402:Mux$27559, B=2'10, Y=$auto$rtlil.cc:3402:Mux$27571 + New ports: A=$auto$rtlil.cc:3402:Mux$27559 [1], B=1'1, Y=$auto$rtlil.cc:3402:Mux$27571 [1] + New connections: $auto$rtlil.cc:3402:Mux$27571 [0] = 1'0 + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$procmux$10643: + Old ports: A={ $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:150$6829_Y [22:3] \u_dataflow_core.GEN_SLOT[0].u_mm.w_base_reg [2:0] }, B=$flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$procmux$10641_Y, Y=$flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$procmux$10643_Y + New ports: A=$flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:150$6829_Y [22:3], B=$flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$procmux$10641_Y [22:3], Y=$flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$procmux$10643_Y [22:3] + New connections: $flatten\u_dataflow_core.\GEN_SLOT[0].u_mm.\u_wpf.$procmux$10643_Y [2:0] = \u_dataflow_core.GEN_SLOT[0].u_mm.w_base_reg [2:0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$procmux$10643: + Old ports: A={ $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:150$6829_Y [22:3] \u_dataflow_core.GEN_SLOT[1].u_mm.w_base_reg [2:0] }, B=$flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$procmux$10641_Y, Y=$flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$procmux$10643_Y + New ports: A=$flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:150$6829_Y [22:3], B=$flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$procmux$10641_Y [22:3], Y=$flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$procmux$10643_Y [22:3] + New connections: $flatten\u_dataflow_core.\GEN_SLOT[1].u_mm.\u_wpf.$procmux$10643_Y [2:0] = \u_dataflow_core.GEN_SLOT[1].u_mm.w_base_reg [2:0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$procmux$10643: + Old ports: A={ $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:150$6829_Y [22:3] \u_dataflow_core.GEN_SLOT[2].u_mm.w_base_reg [2:0] }, B=$flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$procmux$10641_Y, Y=$flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$procmux$10643_Y + New ports: A=$flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:150$6829_Y [22:3], B=$flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$procmux$10641_Y [22:3], Y=$flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$procmux$10643_Y [22:3] + New connections: $flatten\u_dataflow_core.\GEN_SLOT[2].u_mm.\u_wpf.$procmux$10643_Y [2:0] = \u_dataflow_core.GEN_SLOT[2].u_mm.w_base_reg [2:0] + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$procmux$10643: + Old ports: A={ $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:150$6829_Y [22:3] \u_dataflow_core.GEN_SLOT[3].u_mm.w_base_reg [2:0] }, B=$flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$procmux$10641_Y, Y=$flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$procmux$10643_Y + New ports: A=$flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$add$hardware/v2/nms/rtl/weight_prefetch_engine_wide.v:150$6829_Y [22:3], B=$flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$procmux$10641_Y [22:3], Y=$flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$procmux$10643_Y [22:3] + New connections: $flatten\u_dataflow_core.\GEN_SLOT[3].u_mm.\u_wpf.$procmux$10643_Y [2:0] = \u_dataflow_core.GEN_SLOT[3].u_mm.w_base_reg [2:0] + Optimizing cells in module \fpga_neural_v2_top. + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$18119: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$2\first_ready_idx[3:0], B=4'1101, Y=$flatten\u_dataflow_core.\u_dep_mgr.$3\first_ready_idx[3:0] + New ports: A={ $flatten\u_dataflow_core.\u_dep_mgr.$2\first_ready_idx[3:0] [1] $flatten\u_dataflow_core.\u_dep_mgr.$2\first_ready_idx[3:0] [1:0] }, B=3'101, Y=$flatten\u_dataflow_core.\u_dep_mgr.$3\first_ready_idx[3:0] [2:0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$3\first_ready_idx[3:0] [3] = $flatten\u_dataflow_core.\u_dep_mgr.$3\first_ready_idx[3:0] [2] + Consolidated identical input bits for $mux cell $auto$memory_share.cc:274:consolidate_wr_by_addr$27582: + Old ports: A=$auto$rtlil.cc:3402:Mux$27571, B=2'10, Y=$auto$rtlil.cc:3402:Mux$27583 + New ports: A=$auto$rtlil.cc:3402:Mux$27571 [1], B=1'1, Y=$auto$rtlil.cc:3402:Mux$27583 [1] + New connections: $auto$rtlil.cc:3402:Mux$27583 [0] = 1'0 + Optimizing cells in module \fpga_neural_v2_top. + Consolidated identical input bits for $mux cell $flatten\u_dataflow_core.\u_dep_mgr.$procmux$18113: + Old ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$3\first_ready_idx[3:0], B=4'1100, Y=$flatten\u_dataflow_core.\u_dep_mgr.$4\first_ready_idx[3:0] + New ports: A=$flatten\u_dataflow_core.\u_dep_mgr.$3\first_ready_idx[3:0] [2:0], B=3'100, Y=$flatten\u_dataflow_core.\u_dep_mgr.$4\first_ready_idx[3:0] [2:0] + New connections: $flatten\u_dataflow_core.\u_dep_mgr.$4\first_ready_idx[3:0] [3] = $flatten\u_dataflow_core.\u_dep_mgr.$4\first_ready_idx[3:0] [2] + Consolidated identical input bits for $mux cell $auto$memory_share.cc:274:consolidate_wr_by_addr$27594: + Old ports: A=$auto$rtlil.cc:3402:Mux$27583, B=2'10, Y=$auto$rtlil.cc:3402:Mux$27595 + New ports: A=$auto$rtlil.cc:3402:Mux$27583 [1], B=1'1, Y=$auto$rtlil.cc:3402:Mux$27595 [1] + New connections: $auto$rtlil.cc:3402:Mux$27595 [0] = 1'0 + Optimizing cells in module \fpga_neural_v2_top. +Performed a total of 28 changes. + +19.32.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\fpga_neural_v2_top'. +Computing hashes of 4336 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. +Removed a total of 0 cells. + +19.32.6. Executing OPT_DFF pass (perform DFF optimizations). +Adding SRST signal on $auto$ff.cc:337:slice$24466 ($dffe) from module fpga_neural_v2_top (D = $flatten\u_sdram_backend.\u_sdram_ctrl.$add$hardware/v2/nms/rtl/sdram_controller.v:397$7446_Y, Q = \u_sdram_backend.u_sdram_ctrl.burst_idx, rval = 3'000). +Adding SRST signal on $\u_dataflow_core.u_dep_mgr.node_state$rdreg[0] ($dff) from module fpga_neural_v2_top (D = $auto$rtlil.cc:3402:Mux$26806, Q = $\u_dataflow_core.u_dep_mgr.node_state$rdreg[0]$q, rval = 4'0000). + +19.32.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \fpga_neural_v2_top.. +Removed 2 unused cells and 1074 unused wires. + + +19.32.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module fpga_neural_v2_top. + + +19.32.9. Rerunning OPT passes. (Maybe there is more to do..) + +19.32.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \fpga_neural_v2_top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +19.32.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \fpga_neural_v2_top. +Performed a total of 0 changes. + +19.32.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\fpga_neural_v2_top'. +Computing hashes of 4327 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. +Removed a total of 0 cells. + +19.32.13. Executing OPT_DFF pass (perform DFF optimizations). +Adding SRST signal on $memory\u_dataflow_core.u_dep_mgr.node_resolved[0]$28702 ($dff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_resolved$wrmux[0][1][0]$y$28746, Q = \u_dataflow_core.u_dep_mgr.node_resolved[0], rval = 3'000). +Adding EN signal on $auto$ff.cc:337:slice$31513 ($sdff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_resolved$wrmux[0][1][0]$y$28746, Q = \u_dataflow_core.u_dep_mgr.node_resolved[0]). +Adding SRST signal on $memory\u_dataflow_core.u_dep_mgr.node_resolved[1]$28704 ($dff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_resolved$wrmux[1][1][0]$y$28772, Q = \u_dataflow_core.u_dep_mgr.node_resolved[1], rval = 3'000). +Adding EN signal on $auto$ff.cc:337:slice$31517 ($sdff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_resolved$wrmux[1][1][0]$y$28772, Q = \u_dataflow_core.u_dep_mgr.node_resolved[1]). +Adding SRST signal on $memory\u_dataflow_core.u_dep_mgr.node_resolved[2]$28706 ($dff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_resolved$wrmux[2][1][0]$y$28790, Q = \u_dataflow_core.u_dep_mgr.node_resolved[2], rval = 3'000). +Adding EN signal on $auto$ff.cc:337:slice$31521 ($sdff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_resolved$wrmux[2][1][0]$y$28790, Q = \u_dataflow_core.u_dep_mgr.node_resolved[2]). +Adding SRST signal on $memory\u_dataflow_core.u_dep_mgr.node_resolved[3]$28708 ($dff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_resolved$wrmux[3][1][0]$y$28808, Q = \u_dataflow_core.u_dep_mgr.node_resolved[3], rval = 3'000). +Adding EN signal on $auto$ff.cc:337:slice$31525 ($sdff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_resolved$wrmux[3][1][0]$y$28808, Q = \u_dataflow_core.u_dep_mgr.node_resolved[3]). +Adding SRST signal on $memory\u_dataflow_core.u_dep_mgr.node_resolved[4]$28710 ($dff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_resolved$wrmux[4][1][0]$y$28824, Q = \u_dataflow_core.u_dep_mgr.node_resolved[4], rval = 3'000). +Adding EN signal on $auto$ff.cc:337:slice$31529 ($sdff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_resolved$wrmux[4][1][0]$y$28824, Q = \u_dataflow_core.u_dep_mgr.node_resolved[4]). +Adding SRST signal on $memory\u_dataflow_core.u_dep_mgr.node_resolved[5]$28712 ($dff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_resolved$wrmux[5][1][0]$y$28842, Q = \u_dataflow_core.u_dep_mgr.node_resolved[5], rval = 3'000). +Adding EN signal on $auto$ff.cc:337:slice$31533 ($sdff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_resolved$wrmux[5][1][0]$y$28842, Q = \u_dataflow_core.u_dep_mgr.node_resolved[5]). +Adding SRST signal on $memory\u_dataflow_core.u_dep_mgr.node_resolved[6]$28714 ($dff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_resolved$wrmux[6][1][0]$y$28856, Q = \u_dataflow_core.u_dep_mgr.node_resolved[6], rval = 3'000). +Adding EN signal on $auto$ff.cc:337:slice$31537 ($sdff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_resolved$wrmux[6][1][0]$y$28856, Q = \u_dataflow_core.u_dep_mgr.node_resolved[6]). +Adding SRST signal on $memory\u_dataflow_core.u_dep_mgr.node_resolved[7]$28716 ($dff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_resolved$wrmux[7][1][0]$y$28870, Q = \u_dataflow_core.u_dep_mgr.node_resolved[7], rval = 3'000). +Adding EN signal on $auto$ff.cc:337:slice$31541 ($sdff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_resolved$wrmux[7][1][0]$y$28870, Q = \u_dataflow_core.u_dep_mgr.node_resolved[7]). +Adding SRST signal on $memory\u_dataflow_core.u_dep_mgr.node_resolved[8]$28718 ($dff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_resolved$wrmux[8][1][0]$y$28884, Q = \u_dataflow_core.u_dep_mgr.node_resolved[8], rval = 3'000). +Adding EN signal on $auto$ff.cc:337:slice$31545 ($sdff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_resolved$wrmux[8][1][0]$y$28884, Q = \u_dataflow_core.u_dep_mgr.node_resolved[8]). +Adding SRST signal on $memory\u_dataflow_core.u_dep_mgr.node_resolved[9]$28720 ($dff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_resolved$wrmux[9][1][0]$y$28902, Q = \u_dataflow_core.u_dep_mgr.node_resolved[9], rval = 3'000). +Adding EN signal on $auto$ff.cc:337:slice$31549 ($sdff) from module fpga_neural_v2_top (D = $auto$rtlil.cc:3402:Mux$27027, Q = \u_dataflow_core.u_dep_mgr.node_resolved[9]). +Adding SRST signal on $memory\u_dataflow_core.u_dep_mgr.node_resolved[10]$28722 ($dff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_resolved$wrmux[10][1][0]$y$28916, Q = \u_dataflow_core.u_dep_mgr.node_resolved[10], rval = 3'000). +Adding EN signal on $auto$ff.cc:337:slice$31551 ($sdff) from module fpga_neural_v2_top (D = $auto$rtlil.cc:3402:Mux$27391, Q = \u_dataflow_core.u_dep_mgr.node_resolved[10]). +Adding SRST signal on $memory\u_dataflow_core.u_dep_mgr.node_resolved[11]$28724 ($dff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_resolved$wrmux[11][1][0]$y$28930, Q = \u_dataflow_core.u_dep_mgr.node_resolved[11], rval = 3'000). +Adding EN signal on $auto$ff.cc:337:slice$31553 ($sdff) from module fpga_neural_v2_top (D = $auto$rtlil.cc:3402:Mux$27395, Q = \u_dataflow_core.u_dep_mgr.node_resolved[11]). +Adding SRST signal on $memory\u_dataflow_core.u_dep_mgr.node_resolved[12]$28726 ($dff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_resolved$wrmux[12][1][0]$y$28944, Q = \u_dataflow_core.u_dep_mgr.node_resolved[12], rval = 3'000). +Adding EN signal on $auto$ff.cc:337:slice$31555 ($sdff) from module fpga_neural_v2_top (D = $auto$rtlil.cc:3402:Mux$27399, Q = \u_dataflow_core.u_dep_mgr.node_resolved[12]). +Adding SRST signal on $memory\u_dataflow_core.u_dep_mgr.node_resolved[13]$28728 ($dff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_resolved$wrmux[13][1][0]$y$28960, Q = \u_dataflow_core.u_dep_mgr.node_resolved[13], rval = 3'000). +Adding EN signal on $auto$ff.cc:337:slice$31557 ($sdff) from module fpga_neural_v2_top (D = $auto$rtlil.cc:3402:Mux$27403, Q = \u_dataflow_core.u_dep_mgr.node_resolved[13]). +Adding SRST signal on $memory\u_dataflow_core.u_dep_mgr.node_resolved[14]$28730 ($dff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_resolved$wrmux[14][1][0]$y$28974, Q = \u_dataflow_core.u_dep_mgr.node_resolved[14], rval = 3'000). +Adding EN signal on $auto$ff.cc:337:slice$31559 ($sdff) from module fpga_neural_v2_top (D = $auto$rtlil.cc:3402:Mux$27407, Q = \u_dataflow_core.u_dep_mgr.node_resolved[14]). +Adding SRST signal on $memory\u_dataflow_core.u_dep_mgr.node_resolved[15]$28732 ($dff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_resolved$wrmux[15][1][0]$y$28988, Q = \u_dataflow_core.u_dep_mgr.node_resolved[15], rval = 3'000). +Adding EN signal on $auto$ff.cc:337:slice$31561 ($sdff) from module fpga_neural_v2_top (D = $auto$rtlil.cc:3402:Mux$27411, Q = \u_dataflow_core.u_dep_mgr.node_resolved[15]). +Adding SRST signal on $memory\u_dataflow_core.u_dep_mgr.node_state[11]$31129 ($dff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_state$wrmux[11][2][0]$y$31426, Q = \u_dataflow_core.u_dep_mgr.node_state[11], rval = 2'11). +Adding EN signal on $auto$ff.cc:337:slice$31563 ($sdff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_state$wrmux[11][2][0]$y$31426, Q = \u_dataflow_core.u_dep_mgr.node_state[11]). +Adding SRST signal on $memory\u_dataflow_core.u_dep_mgr.node_state[12]$31131 ($dff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_state$wrmux[12][2][0]$y$31444, Q = \u_dataflow_core.u_dep_mgr.node_state[12], rval = 2'11). +Adding EN signal on $auto$ff.cc:337:slice$31567 ($sdff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_state$wrmux[12][2][0]$y$31444, Q = \u_dataflow_core.u_dep_mgr.node_state[12]). +Adding SRST signal on $memory\u_dataflow_core.u_dep_mgr.node_state[13]$31133 ($dff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_state$wrmux[13][2][0]$y$31464, Q = \u_dataflow_core.u_dep_mgr.node_state[13], rval = 2'11). +Adding EN signal on $auto$ff.cc:337:slice$31571 ($sdff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_state$wrmux[13][2][0]$y$31464, Q = \u_dataflow_core.u_dep_mgr.node_state[13]). +Adding SRST signal on $memory\u_dataflow_core.u_dep_mgr.node_state[14]$31135 ($dff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_state$wrmux[14][2][0]$y$31482, Q = \u_dataflow_core.u_dep_mgr.node_state[14], rval = 2'11). +Adding EN signal on $auto$ff.cc:337:slice$31575 ($sdff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_state$wrmux[14][2][0]$y$31482, Q = \u_dataflow_core.u_dep_mgr.node_state[14]). +Adding SRST signal on $memory\u_dataflow_core.u_dep_mgr.node_state[2]$31111 ($dff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_state$wrmux[2][2][0]$y$31250, Q = \u_dataflow_core.u_dep_mgr.node_state[2], rval = 2'11). +Adding EN signal on $auto$ff.cc:337:slice$31579 ($sdff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_state$wrmux[2][2][0]$y$31250, Q = \u_dataflow_core.u_dep_mgr.node_state[2]). +Adding SRST signal on $memory\u_dataflow_core.u_dep_mgr.node_state[9]$31125 ($dff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_state$wrmux[9][2][0]$y$31390, Q = \u_dataflow_core.u_dep_mgr.node_state[9], rval = 2'11). +Adding EN signal on $auto$ff.cc:337:slice$31583 ($sdff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_state$wrmux[9][2][0]$y$31390, Q = \u_dataflow_core.u_dep_mgr.node_state[9]). +Adding SRST signal on $memory\u_dataflow_core.u_dep_mgr.node_state[15]$31137 ($dff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_state$wrmux[15][2][0]$y$31500, Q = \u_dataflow_core.u_dep_mgr.node_state[15], rval = 2'11). +Adding EN signal on $auto$ff.cc:337:slice$31587 ($sdff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_state$wrmux[15][2][0]$y$31500, Q = \u_dataflow_core.u_dep_mgr.node_state[15]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_required[0]$28995 ($dff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_required$wrmux[0][2][0]$y$29043, Q = \u_dataflow_core.u_dep_mgr.node_required[0]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_required[1]$28997 ($dff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_required$wrmux[1][2][0]$y$29055, Q = \u_dataflow_core.u_dep_mgr.node_required[1]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_required[2]$28999 ($dff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_required$wrmux[2][2][0]$y$29067, Q = \u_dataflow_core.u_dep_mgr.node_required[2]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_required[3]$29001 ($dff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_required$wrmux[3][2][0]$y$29079, Q = \u_dataflow_core.u_dep_mgr.node_required[3]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_required[4]$29003 ($dff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_required$wrmux[4][2][0]$y$29091, Q = \u_dataflow_core.u_dep_mgr.node_required[4]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_required[5]$29005 ($dff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_required$wrmux[5][2][0]$y$29103, Q = \u_dataflow_core.u_dep_mgr.node_required[5]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_required[6]$29007 ($dff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_required$wrmux[6][2][0]$y$29115, Q = \u_dataflow_core.u_dep_mgr.node_required[6]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_required[7]$29009 ($dff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_required$wrmux[7][2][0]$y$29127, Q = \u_dataflow_core.u_dep_mgr.node_required[7]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_required[8]$29011 ($dff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_required$wrmux[8][2][0]$y$29141, Q = \u_dataflow_core.u_dep_mgr.node_required[8]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_required[9]$29013 ($dff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_required$wrmux[9][2][0]$y$29153, Q = \u_dataflow_core.u_dep_mgr.node_required[9]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_required[10]$29015 ($dff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_required$wrmux[10][2][0]$y$29165, Q = \u_dataflow_core.u_dep_mgr.node_required[10]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_required[11]$29017 ($dff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_required$wrmux[11][2][0]$y$29177, Q = \u_dataflow_core.u_dep_mgr.node_required[11]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_required[12]$29019 ($dff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_required$wrmux[12][2][0]$y$29189, Q = \u_dataflow_core.u_dep_mgr.node_required[12]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_required[13]$29021 ($dff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_required$wrmux[13][2][0]$y$29201, Q = \u_dataflow_core.u_dep_mgr.node_required[13]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_required[14]$29023 ($dff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_required$wrmux[14][2][0]$y$29213, Q = \u_dataflow_core.u_dep_mgr.node_required[14]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_required[15]$29025 ($dff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_required$wrmux[15][2][0]$y$29225, Q = \u_dataflow_core.u_dep_mgr.node_required[15]). +Adding SRST signal on $memory\u_dataflow_core.u_dep_mgr.node_state[6]$31119 ($dff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_state$wrmux[6][2][0]$y$31332, Q = \u_dataflow_core.u_dep_mgr.node_state[6], rval = 2'11). +Adding EN signal on $auto$ff.cc:337:slice$31639 ($sdff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_state$wrmux[6][2][0]$y$31332, Q = \u_dataflow_core.u_dep_mgr.node_state[6]). +Adding SRST signal on $memory\u_dataflow_core.u_dep_mgr.node_state[10]$31127 ($dff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_state$wrmux[10][2][0]$y$31408, Q = \u_dataflow_core.u_dep_mgr.node_state[10], rval = 2'11). +Adding EN signal on $auto$ff.cc:337:slice$31643 ($sdff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_state$wrmux[10][2][0]$y$31408, Q = \u_dataflow_core.u_dep_mgr.node_state[10]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_producer_ids[0]$29226 ($dff) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_producer_ids [3:0], Q = \u_dataflow_core.u_dep_mgr.node_producer_ids[0]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_producer_ids[1]$29228 ($dff) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_producer_ids [7:4], Q = \u_dataflow_core.u_dep_mgr.node_producer_ids[1]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_producer_ids[2]$29230 ($dff) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_producer_ids [11:8], Q = \u_dataflow_core.u_dep_mgr.node_producer_ids[2]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_producer_ids[3]$29232 ($dff) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_producer_ids [15:12], Q = \u_dataflow_core.u_dep_mgr.node_producer_ids[3]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_producer_ids[4]$29234 ($dff) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_producer_ids [3:0], Q = \u_dataflow_core.u_dep_mgr.node_producer_ids[4]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_producer_ids[5]$29236 ($dff) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_producer_ids [7:4], Q = \u_dataflow_core.u_dep_mgr.node_producer_ids[5]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_producer_ids[6]$29238 ($dff) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_producer_ids [11:8], Q = \u_dataflow_core.u_dep_mgr.node_producer_ids[6]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_producer_ids[7]$29240 ($dff) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_producer_ids [15:12], Q = \u_dataflow_core.u_dep_mgr.node_producer_ids[7]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_producer_ids[8]$29242 ($dff) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_producer_ids [3:0], Q = \u_dataflow_core.u_dep_mgr.node_producer_ids[8]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_producer_ids[9]$29244 ($dff) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_producer_ids [7:4], Q = \u_dataflow_core.u_dep_mgr.node_producer_ids[9]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_producer_ids[10]$29246 ($dff) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_producer_ids [11:8], Q = \u_dataflow_core.u_dep_mgr.node_producer_ids[10]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_producer_ids[11]$29248 ($dff) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_producer_ids [15:12], Q = \u_dataflow_core.u_dep_mgr.node_producer_ids[11]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_producer_ids[12]$29250 ($dff) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_producer_ids [3:0], Q = \u_dataflow_core.u_dep_mgr.node_producer_ids[12]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_producer_ids[13]$29252 ($dff) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_producer_ids [7:4], Q = \u_dataflow_core.u_dep_mgr.node_producer_ids[13]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_producer_ids[14]$29254 ($dff) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_producer_ids [11:8], Q = \u_dataflow_core.u_dep_mgr.node_producer_ids[14]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_producer_ids[15]$29256 ($dff) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_producer_ids [15:12], Q = \u_dataflow_core.u_dep_mgr.node_producer_ids[15]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_producer_ids[16]$29258 ($dff) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_producer_ids [3:0], Q = \u_dataflow_core.u_dep_mgr.node_producer_ids[16]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_producer_ids[17]$29260 ($dff) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_producer_ids [7:4], Q = \u_dataflow_core.u_dep_mgr.node_producer_ids[17]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_producer_ids[18]$29262 ($dff) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_producer_ids [11:8], Q = \u_dataflow_core.u_dep_mgr.node_producer_ids[18]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_producer_ids[19]$29264 ($dff) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_producer_ids [15:12], Q = \u_dataflow_core.u_dep_mgr.node_producer_ids[19]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_producer_ids[20]$29266 ($dff) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_producer_ids [3:0], Q = \u_dataflow_core.u_dep_mgr.node_producer_ids[20]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_producer_ids[21]$29268 ($dff) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_producer_ids [7:4], Q = \u_dataflow_core.u_dep_mgr.node_producer_ids[21]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_producer_ids[22]$29270 ($dff) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_producer_ids [11:8], Q = \u_dataflow_core.u_dep_mgr.node_producer_ids[22]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_producer_ids[23]$29272 ($dff) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_producer_ids [15:12], Q = \u_dataflow_core.u_dep_mgr.node_producer_ids[23]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_producer_ids[24]$29274 ($dff) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_producer_ids [3:0], Q = \u_dataflow_core.u_dep_mgr.node_producer_ids[24]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_producer_ids[25]$29276 ($dff) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_producer_ids [7:4], Q = \u_dataflow_core.u_dep_mgr.node_producer_ids[25]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_producer_ids[26]$29278 ($dff) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_producer_ids [11:8], Q = \u_dataflow_core.u_dep_mgr.node_producer_ids[26]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_producer_ids[27]$29280 ($dff) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_producer_ids [15:12], Q = \u_dataflow_core.u_dep_mgr.node_producer_ids[27]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_producer_ids[28]$29282 ($dff) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_producer_ids [3:0], Q = \u_dataflow_core.u_dep_mgr.node_producer_ids[28]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_producer_ids[29]$29284 ($dff) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_producer_ids [7:4], Q = \u_dataflow_core.u_dep_mgr.node_producer_ids[29]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_producer_ids[30]$29286 ($dff) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_producer_ids [11:8], Q = \u_dataflow_core.u_dep_mgr.node_producer_ids[30]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_producer_ids[31]$29288 ($dff) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_producer_ids [15:12], Q = \u_dataflow_core.u_dep_mgr.node_producer_ids[31]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_producer_ids[32]$29290 ($dff) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_producer_ids [3:0], Q = \u_dataflow_core.u_dep_mgr.node_producer_ids[32]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_producer_ids[33]$29292 ($dff) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_producer_ids [7:4], Q = \u_dataflow_core.u_dep_mgr.node_producer_ids[33]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_producer_ids[34]$29294 ($dff) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_producer_ids [11:8], Q = \u_dataflow_core.u_dep_mgr.node_producer_ids[34]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_producer_ids[35]$29296 ($dff) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_producer_ids [15:12], Q = \u_dataflow_core.u_dep_mgr.node_producer_ids[35]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_producer_ids[36]$29298 ($dff) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_producer_ids [3:0], Q = \u_dataflow_core.u_dep_mgr.node_producer_ids[36]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_producer_ids[37]$29300 ($dff) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_producer_ids [7:4], Q = \u_dataflow_core.u_dep_mgr.node_producer_ids[37]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_producer_ids[38]$29302 ($dff) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_producer_ids [11:8], Q = \u_dataflow_core.u_dep_mgr.node_producer_ids[38]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_producer_ids[39]$29304 ($dff) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_producer_ids [15:12], Q = \u_dataflow_core.u_dep_mgr.node_producer_ids[39]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_producer_ids[40]$29306 ($dff) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_producer_ids [3:0], Q = \u_dataflow_core.u_dep_mgr.node_producer_ids[40]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_producer_ids[41]$29308 ($dff) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_producer_ids [7:4], Q = \u_dataflow_core.u_dep_mgr.node_producer_ids[41]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_producer_ids[42]$29310 ($dff) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_producer_ids [11:8], Q = \u_dataflow_core.u_dep_mgr.node_producer_ids[42]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_producer_ids[43]$29312 ($dff) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_producer_ids [15:12], Q = \u_dataflow_core.u_dep_mgr.node_producer_ids[43]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_producer_ids[44]$29314 ($dff) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_producer_ids [3:0], Q = \u_dataflow_core.u_dep_mgr.node_producer_ids[44]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_producer_ids[45]$29316 ($dff) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_producer_ids [7:4], Q = \u_dataflow_core.u_dep_mgr.node_producer_ids[45]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_producer_ids[46]$29318 ($dff) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_producer_ids [11:8], Q = \u_dataflow_core.u_dep_mgr.node_producer_ids[46]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_producer_ids[47]$29320 ($dff) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_producer_ids [15:12], Q = \u_dataflow_core.u_dep_mgr.node_producer_ids[47]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_producer_ids[48]$29322 ($dff) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_producer_ids [3:0], Q = \u_dataflow_core.u_dep_mgr.node_producer_ids[48]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_producer_ids[49]$29324 ($dff) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_producer_ids [7:4], Q = \u_dataflow_core.u_dep_mgr.node_producer_ids[49]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_producer_ids[50]$29326 ($dff) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_producer_ids [11:8], Q = \u_dataflow_core.u_dep_mgr.node_producer_ids[50]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_producer_ids[51]$29328 ($dff) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_producer_ids [15:12], Q = \u_dataflow_core.u_dep_mgr.node_producer_ids[51]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_producer_ids[52]$29330 ($dff) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_producer_ids [3:0], Q = \u_dataflow_core.u_dep_mgr.node_producer_ids[52]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_producer_ids[53]$29332 ($dff) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_producer_ids [7:4], Q = \u_dataflow_core.u_dep_mgr.node_producer_ids[53]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_producer_ids[54]$29334 ($dff) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_producer_ids [11:8], Q = \u_dataflow_core.u_dep_mgr.node_producer_ids[54]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_producer_ids[55]$29336 ($dff) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_producer_ids [15:12], Q = \u_dataflow_core.u_dep_mgr.node_producer_ids[55]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_producer_ids[56]$29338 ($dff) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_producer_ids [3:0], Q = \u_dataflow_core.u_dep_mgr.node_producer_ids[56]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_producer_ids[57]$29340 ($dff) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_producer_ids [7:4], Q = \u_dataflow_core.u_dep_mgr.node_producer_ids[57]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_producer_ids[58]$29342 ($dff) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_producer_ids [11:8], Q = \u_dataflow_core.u_dep_mgr.node_producer_ids[58]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_producer_ids[59]$29344 ($dff) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_producer_ids [15:12], Q = \u_dataflow_core.u_dep_mgr.node_producer_ids[59]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_producer_ids[60]$29346 ($dff) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_producer_ids [3:0], Q = \u_dataflow_core.u_dep_mgr.node_producer_ids[60]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_producer_ids[61]$29348 ($dff) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_producer_ids [7:4], Q = \u_dataflow_core.u_dep_mgr.node_producer_ids[61]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_producer_ids[62]$29350 ($dff) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_producer_ids [11:8], Q = \u_dataflow_core.u_dep_mgr.node_producer_ids[62]). +Adding EN signal on $memory\u_dataflow_core.u_dep_mgr.node_producer_ids[63]$29352 ($dff) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_producer_ids [15:12], Q = \u_dataflow_core.u_dep_mgr.node_producer_ids[63]). +Adding SRST signal on $memory\u_dataflow_core.u_dep_mgr.node_state[4]$31115 ($dff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_state$wrmux[4][2][0]$y$31292, Q = \u_dataflow_core.u_dep_mgr.node_state[4], rval = 2'11). +Adding EN signal on $auto$ff.cc:337:slice$31711 ($sdff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_state$wrmux[4][2][0]$y$31292, Q = \u_dataflow_core.u_dep_mgr.node_state[4]). +Adding SRST signal on $memory\u_dataflow_core.u_dep_mgr.node_state[5]$31117 ($dff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_state$wrmux[5][2][0]$y$31314, Q = \u_dataflow_core.u_dep_mgr.node_state[5], rval = 2'11). +Adding EN signal on $auto$ff.cc:337:slice$31715 ($sdff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_state$wrmux[5][2][0]$y$31314, Q = \u_dataflow_core.u_dep_mgr.node_state[5]). +Adding SRST signal on $memory\u_dataflow_core.u_dep_mgr.node_state[3]$31113 ($dff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_state$wrmux[3][2][0]$y$31272, Q = \u_dataflow_core.u_dep_mgr.node_state[3], rval = 2'11). +Adding EN signal on $auto$ff.cc:337:slice$31719 ($sdff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_state$wrmux[3][2][0]$y$31272, Q = \u_dataflow_core.u_dep_mgr.node_state[3]). +Adding EN signal on $memory\u_sdram_backend.w_cache_addr[0]$30993 ($dff) from module fpga_neural_v2_top (D = { $auto$rtlil.cc:3402:Mux$26855 [22:3] \u_sdram_backend.w_pending_addr [2:0] }, Q = \u_sdram_backend.w_cache_addr[0]). +Adding EN signal on $memory\u_sdram_backend.w_cache_addr[1]$30995 ($dff) from module fpga_neural_v2_top (D = { $auto$rtlil.cc:3402:Mux$26855 [22:3] \u_sdram_backend.w_pending_addr [2:0] }, Q = \u_sdram_backend.w_cache_addr[1]). +Adding EN signal on $memory\u_sdram_backend.w_cache_addr[2]$30997 ($dff) from module fpga_neural_v2_top (D = { $auto$rtlil.cc:3402:Mux$26855 [22:3] \u_sdram_backend.w_pending_addr [2:0] }, Q = \u_sdram_backend.w_cache_addr[2]). +Adding EN signal on $memory\u_sdram_backend.w_cache_addr[3]$30999 ($dff) from module fpga_neural_v2_top (D = { $auto$rtlil.cc:3402:Mux$26855 [22:3] \u_sdram_backend.w_pending_addr [2:0] }, Q = \u_sdram_backend.w_cache_addr[3]). +Adding SRST signal on $memory\u_dataflow_core.u_dep_mgr.node_state[0]$31107 ($dff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_state$wrmux[0][2][0]$y$31198, Q = \u_dataflow_core.u_dep_mgr.node_state[0], rval = 2'11). +Adding EN signal on $auto$ff.cc:337:slice$31727 ($sdff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_state$wrmux[0][2][0]$y$31198, Q = \u_dataflow_core.u_dep_mgr.node_state[0]). +Adding SRST signal on $memory\u_dataflow_core.u_dep_mgr.node_state[1]$31109 ($dff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_state$wrmux[1][2][0]$y$31228, Q = \u_dataflow_core.u_dep_mgr.node_state[1], rval = 2'11). +Adding EN signal on $auto$ff.cc:337:slice$31731 ($sdff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_state$wrmux[1][2][0]$y$31228, Q = \u_dataflow_core.u_dep_mgr.node_state[1]). +Adding SRST signal on $memory\u_dataflow_core.u_dep_mgr.node_state[7]$31121 ($dff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_state$wrmux[7][2][0]$y$31350, Q = \u_dataflow_core.u_dep_mgr.node_state[7], rval = 2'11). +Adding EN signal on $auto$ff.cc:337:slice$31735 ($sdff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_state$wrmux[7][2][0]$y$31350, Q = \u_dataflow_core.u_dep_mgr.node_state[7]). +Adding SRST signal on $memory\u_dataflow_core.u_dep_mgr.node_state[8]$31123 ($dff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_state$wrmux[8][2][0]$y$31368, Q = \u_dataflow_core.u_dep_mgr.node_state[8], rval = 2'11). +Adding EN signal on $auto$ff.cc:337:slice$31739 ($sdff) from module fpga_neural_v2_top (D = $memory\u_dataflow_core.u_dep_mgr.node_state$wrmux[8][2][0]$y$31368, Q = \u_dataflow_core.u_dep_mgr.node_state[8]). +Adding EN signal on $memory\u_sdram_backend.w_cache_valid[0]$31042 ($dff) from module fpga_neural_v2_top (D = $memory\u_sdram_backend.w_cache_valid$wrmux[0][1][0]$y$31072, Q = \u_sdram_backend.w_cache_valid[0]). +Adding EN signal on $memory\u_sdram_backend.w_cache_valid[1]$31044 ($dff) from module fpga_neural_v2_top (D = $memory\u_sdram_backend.w_cache_valid$wrmux[1][1][0]$y$31084, Q = \u_sdram_backend.w_cache_valid[1]). +Adding EN signal on $memory\u_sdram_backend.w_cache_valid[2]$31046 ($dff) from module fpga_neural_v2_top (D = $memory\u_sdram_backend.w_cache_valid$wrmux[2][1][0]$y$31096, Q = \u_sdram_backend.w_cache_valid[2]). +Adding EN signal on $memory\u_sdram_backend.w_cache_valid[3]$31048 ($dff) from module fpga_neural_v2_top (D = $auto$rtlil.cc:3271:ReduceOr$28055, Q = \u_sdram_backend.w_cache_valid[3]). +Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$24249 ($sdffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 1 on $auto$ff.cc:337:slice$24249 ($sdffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 2 on $auto$ff.cc:337:slice$24249 ($sdffe) from module fpga_neural_v2_top. + +19.32.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \fpga_neural_v2_top.. +Removed 108 unused cells and 115 unused wires. + + +19.32.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module fpga_neural_v2_top. + + +19.32.16. Rerunning OPT passes. (Maybe there is more to do..) + +19.32.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \fpga_neural_v2_top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +19.32.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \fpga_neural_v2_top. + Consolidated identical input bits for $mux cell $memory\u_dataflow_core.u_dep_mgr.node_state$wrmux[4][1][0]$31287: + Old ports: A=2'00, B=2'10, Y=$memory\u_dataflow_core.u_dep_mgr.node_state$wrmux[4][1][0]$y$31288 + New ports: A=1'0, B=1'1, Y=$memory\u_dataflow_core.u_dep_mgr.node_state$wrmux[4][1][0]$y$31288 [1] + New connections: $memory\u_dataflow_core.u_dep_mgr.node_state$wrmux[4][1][0]$y$31288 [0] = 1'0 + Consolidated identical input bits for $mux cell $memory\u_dataflow_core.u_dep_mgr.node_state$wrmux[2][1][0]$31245: + Old ports: A=2'00, B=2'10, Y=$memory\u_dataflow_core.u_dep_mgr.node_state$wrmux[2][1][0]$y$31246 + New ports: A=1'0, B=1'1, Y=$memory\u_dataflow_core.u_dep_mgr.node_state$wrmux[2][1][0]$y$31246 [1] + New connections: $memory\u_dataflow_core.u_dep_mgr.node_state$wrmux[2][1][0]$y$31246 [0] = 1'0 + Consolidated identical input bits for $mux cell $memory\u_dataflow_core.u_dep_mgr.node_state$wrmux[6][1][0]$31327: + Old ports: A=2'00, B=2'10, Y=$memory\u_dataflow_core.u_dep_mgr.node_state$wrmux[6][1][0]$y$31328 + New ports: A=1'0, B=1'1, Y=$memory\u_dataflow_core.u_dep_mgr.node_state$wrmux[6][1][0]$y$31328 [1] + New connections: $memory\u_dataflow_core.u_dep_mgr.node_state$wrmux[6][1][0]$y$31328 [0] = 1'0 + Consolidated identical input bits for $mux cell $memory\u_dataflow_core.u_dep_mgr.node_state$wrmux[7][1][0]$31345: + Old ports: A=2'00, B=2'10, Y=$memory\u_dataflow_core.u_dep_mgr.node_state$wrmux[7][1][0]$y$31346 + New ports: A=1'0, B=1'1, Y=$memory\u_dataflow_core.u_dep_mgr.node_state$wrmux[7][1][0]$y$31346 [1] + New connections: $memory\u_dataflow_core.u_dep_mgr.node_state$wrmux[7][1][0]$y$31346 [0] = 1'0 + Consolidated identical input bits for $mux cell $memory\u_dataflow_core.u_dep_mgr.node_state$wrmux[8][1][0]$31363: + Old ports: A=2'00, B=2'10, Y=$memory\u_dataflow_core.u_dep_mgr.node_state$wrmux[8][1][0]$y$31364 + New ports: A=1'0, B=1'1, Y=$memory\u_dataflow_core.u_dep_mgr.node_state$wrmux[8][1][0]$y$31364 [1] + New connections: $memory\u_dataflow_core.u_dep_mgr.node_state$wrmux[8][1][0]$y$31364 [0] = 1'0 + Consolidated identical input bits for $mux cell $memory\u_dataflow_core.u_dep_mgr.node_state$wrmux[1][1][0]$31223: + Old ports: A=2'00, B=2'10, Y=$memory\u_dataflow_core.u_dep_mgr.node_state$wrmux[1][1][0]$y$31224 + New ports: A=1'0, B=1'1, Y=$memory\u_dataflow_core.u_dep_mgr.node_state$wrmux[1][1][0]$y$31224 [1] + New connections: $memory\u_dataflow_core.u_dep_mgr.node_state$wrmux[1][1][0]$y$31224 [0] = 1'0 + Consolidated identical input bits for $mux cell $memory\u_dataflow_core.u_dep_mgr.node_state$wrmux[0][1][0]$31193: + Old ports: A=2'00, B=2'10, Y=$memory\u_dataflow_core.u_dep_mgr.node_state$wrmux[0][1][0]$y$31194 + New ports: A=1'0, B=1'1, Y=$memory\u_dataflow_core.u_dep_mgr.node_state$wrmux[0][1][0]$y$31194 [1] + New connections: $memory\u_dataflow_core.u_dep_mgr.node_state$wrmux[0][1][0]$y$31194 [0] = 1'0 + Consolidated identical input bits for $mux cell $memory\u_dataflow_core.u_dep_mgr.node_state$wrmux[5][1][0]$31309: + Old ports: A=2'00, B=2'10, Y=$memory\u_dataflow_core.u_dep_mgr.node_state$wrmux[5][1][0]$y$31310 + New ports: A=1'0, B=1'1, Y=$memory\u_dataflow_core.u_dep_mgr.node_state$wrmux[5][1][0]$y$31310 [1] + New connections: $memory\u_dataflow_core.u_dep_mgr.node_state$wrmux[5][1][0]$y$31310 [0] = 1'0 + Consolidated identical input bits for $mux cell $memory\u_dataflow_core.u_dep_mgr.node_state$wrmux[3][1][0]$31267: + Old ports: A=2'00, B=2'10, Y=$memory\u_dataflow_core.u_dep_mgr.node_state$wrmux[3][1][0]$y$31268 + New ports: A=1'0, B=1'1, Y=$memory\u_dataflow_core.u_dep_mgr.node_state$wrmux[3][1][0]$y$31268 [1] + New connections: $memory\u_dataflow_core.u_dep_mgr.node_state$wrmux[3][1][0]$y$31268 [0] = 1'0 + Optimizing cells in module \fpga_neural_v2_top. +Performed a total of 9 changes. + +19.32.19. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\fpga_neural_v2_top'. +Computing hashes of 4219 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. +Removed a total of 0 cells. + +19.32.20. Executing OPT_DFF pass (perform DFF optimizations). +Adding SRST signal on $auto$ff.cc:337:slice$31743 ($dffe) from module fpga_neural_v2_top (D = $auto$rtlil.cc:3271:ReduceOr$28055, Q = \u_sdram_backend.w_cache_valid[0], rval = 1'0). +Adding SRST signal on $auto$ff.cc:337:slice$31749 ($dffe) from module fpga_neural_v2_top (D = $auto$rtlil.cc:3271:ReduceOr$28055, Q = \u_sdram_backend.w_cache_valid[2], rval = 1'0). +Adding SRST signal on $auto$ff.cc:337:slice$31591 ($dffe) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_required, Q = \u_dataflow_core.u_dep_mgr.node_required[0], rval = 3'000). +Adding SRST signal on $auto$ff.cc:337:slice$31594 ($dffe) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_required, Q = \u_dataflow_core.u_dep_mgr.node_required[1], rval = 3'000). +Adding SRST signal on $auto$ff.cc:337:slice$31597 ($dffe) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_required, Q = \u_dataflow_core.u_dep_mgr.node_required[2], rval = 3'000). +Adding SRST signal on $auto$ff.cc:337:slice$31600 ($dffe) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_required, Q = \u_dataflow_core.u_dep_mgr.node_required[3], rval = 3'000). +Adding SRST signal on $auto$ff.cc:337:slice$31603 ($dffe) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_required, Q = \u_dataflow_core.u_dep_mgr.node_required[4], rval = 3'000). +Adding SRST signal on $auto$ff.cc:337:slice$31606 ($dffe) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_required, Q = \u_dataflow_core.u_dep_mgr.node_required[5], rval = 3'000). +Adding SRST signal on $auto$ff.cc:337:slice$31609 ($dffe) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_required, Q = \u_dataflow_core.u_dep_mgr.node_required[6], rval = 3'000). +Adding SRST signal on $auto$ff.cc:337:slice$31612 ($dffe) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_required, Q = \u_dataflow_core.u_dep_mgr.node_required[7], rval = 3'000). +Adding SRST signal on $auto$ff.cc:337:slice$31615 ($dffe) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_required, Q = \u_dataflow_core.u_dep_mgr.node_required[8], rval = 3'000). +Adding SRST signal on $auto$ff.cc:337:slice$31618 ($dffe) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_required, Q = \u_dataflow_core.u_dep_mgr.node_required[9], rval = 3'000). +Adding SRST signal on $auto$ff.cc:337:slice$31621 ($dffe) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_required, Q = \u_dataflow_core.u_dep_mgr.node_required[10], rval = 3'000). +Adding SRST signal on $auto$ff.cc:337:slice$31624 ($dffe) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_required, Q = \u_dataflow_core.u_dep_mgr.node_required[11], rval = 3'000). +Adding SRST signal on $auto$ff.cc:337:slice$31627 ($dffe) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_required, Q = \u_dataflow_core.u_dep_mgr.node_required[12], rval = 3'000). +Adding SRST signal on $auto$ff.cc:337:slice$31630 ($dffe) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_required, Q = \u_dataflow_core.u_dep_mgr.node_required[13], rval = 3'000). +Adding SRST signal on $auto$ff.cc:337:slice$31633 ($dffe) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_required, Q = \u_dataflow_core.u_dep_mgr.node_required[14], rval = 3'000). +Adding SRST signal on $auto$ff.cc:337:slice$31636 ($dffe) from module fpga_neural_v2_top (D = \u_spi_bridge.reg_required, Q = \u_dataflow_core.u_dep_mgr.node_required[15], rval = 3'000). +Adding SRST signal on $auto$ff.cc:337:slice$31746 ($dffe) from module fpga_neural_v2_top (D = $auto$rtlil.cc:3271:ReduceOr$28055, Q = \u_sdram_backend.w_cache_valid[1], rval = 1'0). +Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$24454 ($dffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 1 on $auto$ff.cc:337:slice$24454 ($dffe) from module fpga_neural_v2_top. +Setting constant 0-bit at position 2 on $auto$ff.cc:337:slice$24454 ($dffe) from module fpga_neural_v2_top. + +19.32.21. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \fpga_neural_v2_top.. +Removed 19 unused cells and 63 unused wires. + + +19.32.22. Executing OPT_EXPR pass (perform const folding). +Optimizing module fpga_neural_v2_top. + + +19.32.23. Rerunning OPT passes. (Maybe there is more to do..) + +19.32.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \fpga_neural_v2_top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +19.32.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \fpga_neural_v2_top. +Performed a total of 0 changes. + +19.32.26. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\fpga_neural_v2_top'. +Computing hashes of 4191 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. +Removed a total of 0 cells. + +19.32.27. Executing OPT_DFF pass (perform DFF optimizations). + +19.32.28. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \fpga_neural_v2_top.. +Removed 0 unused cells and 9 unused wires. + + +19.32.29. Executing OPT_EXPR pass (perform const folding). +Optimizing module fpga_neural_v2_top. + +19.32.30. Rerunning OPT passes. (Maybe there is more to do..) + +19.32.31. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \fpga_neural_v2_top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +19.32.32. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \fpga_neural_v2_top. +Performed a total of 0 changes. + +19.32.33. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\fpga_neural_v2_top'. +Computing hashes of 4191 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. +Removed a total of 0 cells. + +19.32.34. Executing OPT_DFF pass (perform DFF optimizations). + +19.32.35. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \fpga_neural_v2_top.. + +19.32.36. Executing OPT_EXPR pass (perform const folding). +Optimizing module fpga_neural_v2_top. + +19.32.37. Finished fast OPT passes. (There is nothing left to do.) + +19.33. Executing TECHMAP pass (map to technology primitives). + +19.33.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `$__div_mod_u'. +Generating RTLIL representation for module `$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Generating RTLIL representation for module `$connect'. +Generating RTLIL representation for module `$input_port'. +Successfully finished Verilog frontend. + +19.33.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v' to AST representation. +Generating RTLIL representation for module `\_80_ccu2c_alu'. +Successfully finished Verilog frontend. + +19.33.3. Continuing TECHMAP pass. +Using extmapper simplemap for cells of type $dffe. +Using extmapper simplemap for cells of type $sdffce. +Using extmapper simplemap for cells of type $sdffe. +Using extmapper simplemap for cells of type $reduce_bool. +Using extmapper simplemap for cells of type $sdff. +Using extmapper simplemap for cells of type $reduce_or. +Using extmapper simplemap for cells of type $and. +Using extmapper simplemap for cells of type $not. +Using extmapper simplemap for cells of type $mux. +Using extmapper simplemap for cells of type $eq. +Using extmapper simplemap for cells of type $or. +Using extmapper simplemap for cells of type $logic_not. +Using extmapper simplemap for cells of type $reduce_and. +Using template $paramod$a1665ef28c749ebcdbe9aecd466e644647b56463\_80_ccu2c_alu for cells of type $alu. +Using template $paramod$36fdbc18fab0758c8553dda57bd33e3f8f3e8765\_80_ccu2c_alu for cells of type $alu. +Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_90_alu for cells of type $alu. +Using template $paramod$3ef7d3dd227da7627a99c5e5a6a4deb817573e39\_90_alu for cells of type $alu. +Using template $paramod$2653f68ddb8eab7b1907b4a20767b72a824a7a36\_80_ccu2c_alu for cells of type $alu. +Using template $paramod$2470b7ea32c975a55c3ab8b283381b72d09e16d3\_80_ccu2c_alu for cells of type $alu. +Using template $paramod$5e21cfa2ff6d644e10a0fc1dcdb22e5eb183bcd3\_80_ccu2c_alu for cells of type $alu. +Using template $paramod$c9d98d2d0793a6d8797b9c088dbedb26a7be7121\_80_ccu2c_alu for cells of type $alu. +Using template $paramod$5e23d2e0f07f5403e3d2c5b606bab0c16e4174c1\_80_ccu2c_alu for cells of type $alu. +Using template $paramod$672a140277c71df8314410f22acc08d55222c3c7\_80_ccu2c_alu for cells of type $alu. +Using template $paramod$b3c20b05d9b1fc2c940ef2f6c917486aead042e8\_90_alu for cells of type $alu. +Using template $paramod$175e67c02b86e96b1288b9dc100122520d7240d8\_90_alu for cells of type $alu. +Using template $paramod$bfceb922395790c0ce92e9f9b5b428d4fc72cc30\_90_alu for cells of type $alu. +Using template $paramod$3e2546d640bb80c4407ce51aec1dbdbdc5bff143\_80_ccu2c_alu for cells of type $alu. +Using template $paramod$1d1e68f77481583066c6d429218f48ea9d5739b3\_90_alu for cells of type $alu. +Using template $paramod$420fbc8134b4c458452de534da94701c18f4eecd\_80_ccu2c_alu for cells of type $alu. +Using template $paramod$6fc37af1c109ae54e8aed83fcd995c12d378ce93\_80_ccu2c_alu for cells of type $alu. +Using template $paramod$fc972a7a46956c1788f3cb5257b53c8f1df2d0cc\_90_alu for cells of type $alu. +Using template $paramod$1ed7ec530b1ba361931392f2f8504f82ccdfecaa\_80_ccu2c_alu for cells of type $alu. +Using template $paramod$ce0ec84be7047712840b0952f343ee9e63ef75d1\_80_ccu2c_alu for cells of type $alu. +Using template $paramod$b2a133671413f5163ef51e71d3ce65b4258273f1\_90_alu for cells of type $alu. +Using template $paramod$80fcdb50ca3efbe6404f287ea6e9e408f0b4aab5\_80_ccu2c_alu for cells of type $alu. +Using template $paramod$3ef274a4ad1e446c08416d1cf6cb5ab03146d407\_80_ccu2c_alu for cells of type $alu. +Using template $paramod$ef8fb1849064cca7dc908988762d3374786d9fdb\_90_alu for cells of type $alu. +Using template $paramod$8742280fdebca84e1c87f2a86ed84f62d558f4cc\_90_alu for cells of type $alu. +Using template $paramod$a34b5acad484c4a8af9dd5e006e7ce9f7539a991\_90_alu for cells of type $alu. +Using template $paramod$025d767fc934a3e7d59a671de523743ebaa07759\_90_alu for cells of type $alu. +Using template $paramod$d8458b3c47920e79a4e96c2be935e3ae586a4c76\_80_ccu2c_alu for cells of type $alu. +Using template $paramod$78e969f2586efcf3a5b0b0440bcca0db83d5cca2\_90_alu for cells of type $alu. +Using template $paramod$5168aae49e4c2f5be022b435d3f3df25f30776ec\_80_ccu2c_alu for cells of type $alu. +Using template $paramod$6df0329addda9228fcc2546de2aaf14ad26c98e1\_80_ccu2c_alu for cells of type $alu. +Using template $paramod$e04283ca12514baf3d204c6994bec8f178dd89f8\_80_ccu2c_alu for cells of type $alu. +Using template $paramod$b18e16801adf491a64caa0542270798e5d4ac6b6\_80_ccu2c_alu for cells of type $alu. +Using extmapper simplemap for cells of type $bmux. +Using extmapper simplemap for cells of type $ne. +Using extmapper simplemap for cells of type $dff. +Using extmapper simplemap for cells of type $adff. +Using extmapper simplemap for cells of type $pmux. +Using extmapper simplemap for cells of type $logic_and. +Using template $paramod$constmap:8876c1e1fa289f4793438d4e34d232728e6a9746$paramod$92adee9538f2381d8e5006822c900eb986d754e8\_90_shift_shiftx for cells of type $shiftx. +Using extmapper simplemap for cells of type $logic_or. +Using template $paramod$constmap:5a4bd879cde68fe23882c6a271f9c4bb8714bccb$paramod$08bf5f0725d292174acacf8edfe87d18d48f6e70\_90_shift_shiftx for cells of type $shift. +Analyzing pattern of constant bits for this cell: + Constant input on bit 0 of port A: 1'1 + Constant input on bit 1 of port A: 1'1 + Constant input on bit 2 of port A: 1'1 + Constant input on bit 3 of port A: 1'1 + Constant input on bit 4 of port A: 1'1 + Constant input on bit 5 of port A: 1'1 + Constant input on bit 6 of port A: 1'1 + Constant input on bit 7 of port A: 1'1 + Constant input on bit 8 of port A: 1'1 + Constant input on bit 9 of port A: 1'1 + Constant input on bit 10 of port A: 1'1 + Constant input on bit 11 of port A: 1'1 + Constant input on bit 12 of port A: 1'1 + Constant input on bit 13 of port A: 1'1 + Constant input on bit 14 of port A: 1'1 + Constant input on bit 15 of port A: 1'1 +Creating constmapped module `$paramod$constmap:decda5b4632abbcf04bf9650a2dac76960d9cb80$paramod$08bf5f0725d292174acacf8edfe87d18d48f6e70\_90_shift_shiftx'. + +19.33.93. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module $paramod$constmap:decda5b4632abbcf04bf9650a2dac76960d9cb80$paramod$08bf5f0725d292174acacf8edfe87d18d48f6e70\_90_shift_shiftx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. + dead port 2/2 on $mux $procmux$50318. + dead port 2/2 on $mux $procmux$50324. + dead port 2/2 on $mux $procmux$50330. + dead port 2/2 on $mux $procmux$50336. + dead port 2/2 on $mux $procmux$50342. + dead port 2/2 on $mux $procmux$50348. + dead port 2/2 on $mux $procmux$50354. +Removed 7 multiplexer ports. + + +19.33.94. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod$constmap:decda5b4632abbcf04bf9650a2dac76960d9cb80$paramod$08bf5f0725d292174acacf8edfe87d18d48f6e70\_90_shift_shiftx. + +Removed 0 unused cells and 12 unused wires. +Using template $paramod$constmap:decda5b4632abbcf04bf9650a2dac76960d9cb80$paramod$08bf5f0725d292174acacf8edfe87d18d48f6e70\_90_shift_shiftx for cells of type $shift. +Using template $paramod$constmap:f30e016643cdb78b03bc6146a268597b7789262d$paramod$4e33147aa56d8c514f5e3e64af4e016a996d124e\_90_shift_shiftx for cells of type $shift. +Analyzing pattern of constant bits for this cell: + Constant input on bit 0 of port A: 1'1 + Constant input on bit 1 of port A: 1'1 + Constant input on bit 2 of port A: 1'1 + Constant input on bit 3 of port A: 1'1 + Constant input on bit 4 of port A: 1'1 + Constant input on bit 5 of port A: 1'1 + Constant input on bit 6 of port A: 1'1 + Constant input on bit 7 of port A: 1'1 + Constant input on bit 8 of port A: 1'1 + Constant input on bit 9 of port A: 1'1 + Constant input on bit 10 of port A: 1'1 + Constant input on bit 11 of port A: 1'1 + Constant input on bit 12 of port A: 1'1 + Constant input on bit 13 of port A: 1'1 + Constant input on bit 14 of port A: 1'1 + Constant input on bit 15 of port A: 1'1 + Constant input on bit 16 of port A: 1'1 + Constant input on bit 17 of port A: 1'1 + Constant input on bit 18 of port A: 1'1 + Constant input on bit 19 of port A: 1'1 + Constant input on bit 20 of port A: 1'1 + Constant input on bit 21 of port A: 1'1 + Constant input on bit 22 of port A: 1'1 +Creating constmapped module `$paramod$constmap:fdf1d1b176de14bfd33690c77b41951c8a2dab34$paramod$4e33147aa56d8c514f5e3e64af4e016a996d124e\_90_shift_shiftx'. + +19.33.100. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module $paramod$constmap:fdf1d1b176de14bfd33690c77b41951c8a2dab34$paramod$4e33147aa56d8c514f5e3e64af4e016a996d124e\_90_shift_shiftx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. + dead port 2/2 on $mux $procmux$50722. + dead port 2/2 on $mux $procmux$50728. + dead port 2/2 on $mux $procmux$50734. + dead port 2/2 on $mux $procmux$50740. + dead port 2/2 on $mux $procmux$50746. + dead port 2/2 on $mux $procmux$50752. + dead port 2/2 on $mux $procmux$50758. +Removed 7 multiplexer ports. + + +19.33.101. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod$constmap:fdf1d1b176de14bfd33690c77b41951c8a2dab34$paramod$4e33147aa56d8c514f5e3e64af4e016a996d124e\_90_shift_shiftx. + +Removed 0 unused cells and 12 unused wires. +Using template $paramod$constmap:fdf1d1b176de14bfd33690c77b41951c8a2dab34$paramod$4e33147aa56d8c514f5e3e64af4e016a996d124e\_90_shift_shiftx for cells of type $shift. +Using template $paramod$constmap:d6fff7a1d5912e7277ff55b9a478b5115760128b$paramod$64b19f47ed5f126636dbd98d727ec46a7ec08d71\_90_shift_shiftx for cells of type $shift. +Using extmapper simplemap for cells of type $lut. +Using template $paramod$constmap:226703dc17679b399fdd3f77971b14118ab809e2$paramod$35d35d14a64c888f466d35398fe1889a42aa3977\_90_shift_shiftx for cells of type $shift. +Analyzing pattern of constant bits for this cell: + Constant input on bit 0 of port A: 1'1 +Creating constmapped module `$paramod$constmap:c8c303563bad1341fd703b0bd89fda2e98b10e35$paramod$35d35d14a64c888f466d35398fe1889a42aa3977\_90_shift_shiftx'. + +19.33.112. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module $paramod$constmap:c8c303563bad1341fd703b0bd89fda2e98b10e35$paramod$35d35d14a64c888f466d35398fe1889a42aa3977\_90_shift_shiftx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. + dead port 2/2 on $mux $procmux$54591. + dead port 2/2 on $mux $procmux$54597. + dead port 2/2 on $mux $procmux$54603. +Removed 3 multiplexer ports. + + +19.33.113. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod$constmap:c8c303563bad1341fd703b0bd89fda2e98b10e35$paramod$35d35d14a64c888f466d35398fe1889a42aa3977\_90_shift_shiftx. + +Removed 0 unused cells and 9 unused wires. +Using template $paramod$constmap:c8c303563bad1341fd703b0bd89fda2e98b10e35$paramod$35d35d14a64c888f466d35398fe1889a42aa3977\_90_shift_shiftx for cells of type $shift. +Using template $paramod$constmap:83693fb37e535fe2f4f04375ac74587ec91f67c5$paramod$89e7daf67ba8538cc0ad7edbb2ef4702cb735e6c\_90_shift_shiftx for cells of type $shiftx. +Analyzing pattern of constant bits for this cell: + Constant input on bit 4 of port A: 1'0 +Creating constmapped module `$paramod$constmap:e64b80da36eb16eecdc602c5deeb8a8d72952640$paramod$89e7daf67ba8538cc0ad7edbb2ef4702cb735e6c\_90_shift_shiftx'. + +19.33.119. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module $paramod$constmap:e64b80da36eb16eecdc602c5deeb8a8d72952640$paramod$89e7daf67ba8538cc0ad7edbb2ef4702cb735e6c\_90_shift_shiftx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. + dead port 2/2 on $mux $procmux$54628. + dead port 2/2 on $mux $procmux$54634. + dead port 2/2 on $mux $procmux$54640. +Removed 3 multiplexer ports. + + +19.33.120. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod$constmap:e64b80da36eb16eecdc602c5deeb8a8d72952640$paramod$89e7daf67ba8538cc0ad7edbb2ef4702cb735e6c\_90_shift_shiftx. + +Removed 0 unused cells and 10 unused wires. +Using template $paramod$constmap:e64b80da36eb16eecdc602c5deeb8a8d72952640$paramod$89e7daf67ba8538cc0ad7edbb2ef4702cb735e6c\_90_shift_shiftx for cells of type $shiftx. +Using template $paramod$constmap:920599cb2184ab0d3a3df17ec9fa744f1eabccc8$paramod$cedf4aa7cd4baad38a7d2755402136fd292204b2\_90_shift_shiftx for cells of type $shift. +Analyzing pattern of constant bits for this cell: + Constant input on bit 0 of port A: 1'1 +Creating constmapped module `$paramod$constmap:643f2e79e48a529ebf28e2380f10fdf31723c2db$paramod$cedf4aa7cd4baad38a7d2755402136fd292204b2\_90_shift_shiftx'. + +19.33.126. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module $paramod$constmap:643f2e79e48a529ebf28e2380f10fdf31723c2db$paramod$cedf4aa7cd4baad38a7d2755402136fd292204b2\_90_shift_shiftx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. + dead port 2/2 on $mux $procmux$54692. + dead port 2/2 on $mux $procmux$54698. +Removed 2 multiplexer ports. + + +19.33.127. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod$constmap:643f2e79e48a529ebf28e2380f10fdf31723c2db$paramod$cedf4aa7cd4baad38a7d2755402136fd292204b2\_90_shift_shiftx. + +Removed 0 unused cells and 8 unused wires. +Using template $paramod$constmap:643f2e79e48a529ebf28e2380f10fdf31723c2db$paramod$cedf4aa7cd4baad38a7d2755402136fd292204b2\_90_shift_shiftx for cells of type $shift. +Using template $paramod$constmap:de554f9cc18e049d5b7dc95f0bcf8e03e57019ff$paramod$1e265d9719406ee45a570be27d6567e3eeff81e5\_90_shift_shiftx for cells of type $shiftx. +Using template $paramod$constmap:f1b556d266d48a0bf052a196aa1980be109ce7d8$paramod$9d6bbabc3d2506981f229d240236b41321b3f0fd\_90_shift_shiftx for cells of type $shift. +Analyzing pattern of constant bits for this cell: + Constant input on bit 0 of port A: 1'1 +Creating constmapped module `$paramod$constmap:23ea9e4c6486f763f8573a3e8bba281bf9102098$paramod$9d6bbabc3d2506981f229d240236b41321b3f0fd\_90_shift_shiftx'. + +19.33.138. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module $paramod$constmap:23ea9e4c6486f763f8573a3e8bba281bf9102098$paramod$9d6bbabc3d2506981f229d240236b41321b3f0fd\_90_shift_shiftx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. + dead port 2/2 on $mux $procmux$54813. + dead port 2/2 on $mux $procmux$54819. + dead port 2/2 on $mux $procmux$54825. +Removed 3 multiplexer ports. + + +19.33.139. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod$constmap:23ea9e4c6486f763f8573a3e8bba281bf9102098$paramod$9d6bbabc3d2506981f229d240236b41321b3f0fd\_90_shift_shiftx. + +Removed 0 unused cells and 9 unused wires. +Using template $paramod$constmap:23ea9e4c6486f763f8573a3e8bba281bf9102098$paramod$9d6bbabc3d2506981f229d240236b41321b3f0fd\_90_shift_shiftx for cells of type $shift. +Using extmapper simplemap for cells of type $tribuf. +Using template $paramod$constmap:db7e03035a5c333cdeb3ea0c36f6b6e41ea02c8d$paramod$35d43f283fa197ecd06c429c67def546fd6dc204\_90_shift_shiftx for cells of type $shift. +Analyzing pattern of constant bits for this cell: +Creating constmapped module `$paramod$constmap:08457d22cad9d2ac4717a875d109a7d5370a2c5e$paramod$35d43f283fa197ecd06c429c67def546fd6dc204\_90_shift_shiftx'. + +19.33.145. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module $paramod$constmap:08457d22cad9d2ac4717a875d109a7d5370a2c5e$paramod$35d43f283fa197ecd06c429c67def546fd6dc204\_90_shift_shiftx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. + dead port 2/2 on $mux $procmux$54966. + dead port 2/2 on $mux $procmux$54972. + dead port 2/2 on $mux $procmux$54978. + dead port 2/2 on $mux $procmux$54984. + dead port 2/2 on $mux $procmux$54990. + dead port 2/2 on $mux $procmux$54996. + dead port 2/2 on $mux $procmux$55002. + dead port 2/2 on $mux $procmux$55008. +Removed 8 multiplexer ports. + + +19.33.146. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod$constmap:08457d22cad9d2ac4717a875d109a7d5370a2c5e$paramod$35d43f283fa197ecd06c429c67def546fd6dc204\_90_shift_shiftx. + +Removed 0 unused cells and 13 unused wires. +Using template $paramod$constmap:08457d22cad9d2ac4717a875d109a7d5370a2c5e$paramod$35d43f283fa197ecd06c429c67def546fd6dc204\_90_shift_shiftx for cells of type $shift. +Using template $paramod$constmap:3d1ff99555816656cd6991f5ed8df0c604e3693f$paramod$c55b0d19d395c4530d8988846abca2168db15663\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl. +Analyzing pattern of constant bits for this cell: + Constant input on bit 0 of port B: 1'0 + Constant input on bit 0 of port A: 1'1 + Constant input on bit 1 of port A: 1'1 +Creating constmapped module `$paramod$constmap:dd2e94c249d72472b1434e2e80c1eb2d90aba94c$paramod$c55b0d19d395c4530d8988846abca2168db15663\_90_shift_ops_shr_shl_sshl_sshr'. + +19.33.152. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module $paramod$constmap:dd2e94c249d72472b1434e2e80c1eb2d90aba94c$paramod$c55b0d19d395c4530d8988846abca2168db15663\_90_shift_ops_shr_shl_sshl_sshr.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + + +19.33.153. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod$constmap:dd2e94c249d72472b1434e2e80c1eb2d90aba94c$paramod$c55b0d19d395c4530d8988846abca2168db15663\_90_shift_ops_shr_shl_sshl_sshr. + +Removed 0 unused cells and 10 unused wires. +Using template $paramod$constmap:dd2e94c249d72472b1434e2e80c1eb2d90aba94c$paramod$c55b0d19d395c4530d8988846abca2168db15663\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl. +Using extmapper simplemap for cells of type $xor. +Using extmapper simplemap for cells of type $pos. +Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000100 for cells of type $fa. +Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000100 for cells of type $lcu. +Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000011 for cells of type $fa. +Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000011 for cells of type $lcu. +Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000010 for cells of type $fa. +Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000010 for cells of type $lcu. +Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000001 for cells of type $fa. +Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000001 for cells of type $lcu. +No more expansions possible. + + +19.34. Executing OPT pass (performing simple optimizations). + +19.34.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module fpga_neural_v2_top. + + +19.34.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\fpga_neural_v2_top'. +Computing hashes of 31829 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. +Computing hashes of 29702 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. +Computing hashes of 28752 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. +Computing hashes of 28379 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. +Computing hashes of 28252 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. +Computing hashes of 28187 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. +Computing hashes of 28177 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. +Computing hashes of 28168 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. +Computing hashes of 28164 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. +Computing hashes of 28160 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. +Computing hashes of 28156 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. +Computing hashes of 28152 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. +Computing hashes of 28148 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. +Computing hashes of 28144 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. +Computing hashes of 28140 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. +Computing hashes of 28136 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. +Computing hashes of 28132 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. +Computing hashes of 28128 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. +Computing hashes of 28124 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. +Computing hashes of 28120 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. +Computing hashes of 28116 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. +Computing hashes of 28112 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. +Computing hashes of 28108 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. +Computing hashes of 28104 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. +Computing hashes of 28100 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. +Computing hashes of 28097 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. + +Removed a total of 3732 cells. + +19.34.3. Executing OPT_DFF pass (perform DFF optimizations). +Adding SRST signal on $auto$ff.cc:337:slice$37926 ($_SDFF_PP0_) from module fpga_neural_v2_top (D = $auto$simplemap.cc:189:logic_reduce$56347, Q = \u_sdram_backend.w_ready, rval = 1'0). +Adding SRST signal on $auto$ff.cc:337:slice$37349 ($_SDFF_PP0_) from module fpga_neural_v2_top (D = $auto$simplemap.cc:189:logic_reduce$50208, Q = \u_dataflow_core.u_act_fill.u_pf.mem_req, rval = 1'0). +Adding SRST signal on $auto$ff.cc:337:slice$37228 ($_SDFF_PP0_) from module fpga_neural_v2_top (D = $auto$simplemap.cc:189:logic_reduce$55615, Q = \u_sdram_backend.u_sdram_ctrl.dq_out_en, rval = 1'0). +Adding SRST signal on $auto$ff.cc:337:slice$36931 ($_SDFF_PP0_) from module fpga_neural_v2_top (D = $auto$simplemap.cc:189:logic_reduce$55606, Q = \u_sdram_backend.u_sdram_ctrl.ready, rval = 1'0). +Adding SRST signal on $auto$ff.cc:337:slice$36794 ($_SDFF_PP0_) from module fpga_neural_v2_top (D = $auto$simplemap.cc:189:logic_reduce$55634, Q = \u_sdram_backend.u_sdram_ctrl.sdram_dqm [1], rval = 1'0). +Adding SRST signal on $auto$ff.cc:337:slice$36719 ($_SDFF_PP1_) from module fpga_neural_v2_top (D = $auto$simplemap.cc:189:logic_reduce$55654, Q = \u_sdram_backend.u_sdram_ctrl.sdram_we_n, rval = 1'1). +Adding SRST signal on $auto$ff.cc:337:slice$36718 ($_SDFF_PP1_) from module fpga_neural_v2_top (D = $auto$simplemap.cc:189:logic_reduce$55674, Q = \u_sdram_backend.u_sdram_ctrl.sdram_cas_n, rval = 1'1). +Adding SRST signal on $auto$ff.cc:337:slice$36717 ($_SDFF_PP1_) from module fpga_neural_v2_top (D = $auto$simplemap.cc:189:logic_reduce$55696, Q = \u_sdram_backend.u_sdram_ctrl.sdram_ras_n, rval = 1'1). +Adding SRST signal on $auto$ff.cc:337:slice$36793 ($_SDFF_PP0_) from module fpga_neural_v2_top (D = $auto$simplemap.cc:189:logic_reduce$55627, Q = \u_sdram_backend.u_sdram_ctrl.sdram_dqm [0], rval = 1'0). + +19.34.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \fpga_neural_v2_top.. +Removed 5661 unused cells and 11770 unused wires. + + +19.34.5. Rerunning OPT passes. (Removed registers in this run.) + +19.34.6. Executing OPT_EXPR pass (perform const folding). +Optimizing module fpga_neural_v2_top. + + +19.34.7. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\fpga_neural_v2_top'. +Computing hashes of 22393 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. +Computing hashes of 22391 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. +Computing hashes of 22389 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. + +Removed a total of 4 cells. + +19.34.8. Executing OPT_DFF pass (perform DFF optimizations). + +19.34.9. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \fpga_neural_v2_top.. +Removed 0 unused cells and 7 unused wires. + + +19.34.10. Finished fast OPT passes. + +19.35. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \fpga_neural_v2_top.. + +19.36. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). + +19.37. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\fpga_neural_v2_top'. +Computing hashes of 22858 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. +Computing hashes of 22513 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. +Computing hashes of 22451 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. + +Removed a total of 407 cells. + +19.38. Executing TECHMAP pass (map to technology primitives). + +19.38.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation. +Generating RTLIL representation for module `$_DFF_N_'. +Generating RTLIL representation for module `$_DFF_P_'. +Generating RTLIL representation for module `$_DFFE_NN_'. +Generating RTLIL representation for module `$_DFFE_PN_'. +Generating RTLIL representation for module `$_DFFE_NP_'. +Generating RTLIL representation for module `$_DFFE_PP_'. +Generating RTLIL representation for module `$_DFF_NP0_'. +Generating RTLIL representation for module `$_DFF_NP1_'. +Generating RTLIL representation for module `$_DFF_PP0_'. +Generating RTLIL representation for module `$_DFF_PP1_'. +Generating RTLIL representation for module `$_SDFF_NP0_'. +Generating RTLIL representation for module `$_SDFF_NP1_'. +Generating RTLIL representation for module `$_SDFF_PP0_'. +Generating RTLIL representation for module `$_SDFF_PP1_'. +Generating RTLIL representation for module `$_DFFE_NP0P_'. +Generating RTLIL representation for module `$_DFFE_NP1P_'. +Generating RTLIL representation for module `$_DFFE_PP0P_'. +Generating RTLIL representation for module `$_DFFE_PP1P_'. +Generating RTLIL representation for module `$_DFFE_NP0N_'. +Generating RTLIL representation for module `$_DFFE_NP1N_'. +Generating RTLIL representation for module `$_DFFE_PP0N_'. +Generating RTLIL representation for module `$_DFFE_PP1N_'. +Generating RTLIL representation for module `$_SDFFE_NP0P_'. +Generating RTLIL representation for module `$_SDFFE_NP1P_'. +Generating RTLIL representation for module `$_SDFFE_PP0P_'. +Generating RTLIL representation for module `$_SDFFE_PP1P_'. +Generating RTLIL representation for module `$_SDFFE_NP0N_'. +Generating RTLIL representation for module `$_SDFFE_NP1N_'. +Generating RTLIL representation for module `$_SDFFE_PP0N_'. +Generating RTLIL representation for module `$_SDFFE_PP1N_'. +Generating RTLIL representation for module `$_ALDFF_NP_'. +Generating RTLIL representation for module `$_ALDFF_PP_'. +Generating RTLIL representation for module `$_ALDFFE_NPN_'. +Generating RTLIL representation for module `$_ALDFFE_NPP_'. +Generating RTLIL representation for module `$_ALDFFE_PPN_'. +Generating RTLIL representation for module `$_ALDFFE_PPP_'. +Generating RTLIL representation for module `\FD1P3AX'. +Generating RTLIL representation for module `\FD1P3AY'. +Generating RTLIL representation for module `\FD1P3BX'. +Generating RTLIL representation for module `\FD1P3DX'. +Generating RTLIL representation for module `\FD1P3IX'. +Generating RTLIL representation for module `\FD1P3JX'. +Generating RTLIL representation for module `\FD1S3AX'. +Generating RTLIL representation for module `\FD1S3AY'. +Generating RTLIL representation for module `\FD1S3BX'. +Generating RTLIL representation for module `\FD1S3DX'. +Generating RTLIL representation for module `\FD1S3IX'. +Generating RTLIL representation for module `\FD1S3JX'. +Generating RTLIL representation for module `\IFS1P3BX'. +Generating RTLIL representation for module `\IFS1P3DX'. +Generating RTLIL representation for module `\IFS1P3IX'. +Generating RTLIL representation for module `\IFS1P3JX'. +Generating RTLIL representation for module `\OFS1P3BX'. +Generating RTLIL representation for module `\OFS1P3DX'. +Generating RTLIL representation for module `\OFS1P3IX'. +Generating RTLIL representation for module `\OFS1P3JX'. +Generating RTLIL representation for module `\IB'. +Generating RTLIL representation for module `\IBPU'. +Generating RTLIL representation for module `\IBPD'. +Generating RTLIL representation for module `\OB'. +Generating RTLIL representation for module `\OBZ'. +Generating RTLIL representation for module `\OBZPU'. +Generating RTLIL representation for module `\OBZPD'. +Generating RTLIL representation for module `\OBCO'. +Generating RTLIL representation for module `\BB'. +Generating RTLIL representation for module `\BBPU'. +Generating RTLIL representation for module `\BBPD'. +Generating RTLIL representation for module `\ILVDS'. +Generating RTLIL representation for module `\OLVDS'. +Successfully finished Verilog frontend. + +19.38.2. Continuing TECHMAP pass. +Using template $_SDFF_PP0_ for cells of type $_SDFF_PP0_. +Using template $_SDFF_PP1_ for cells of type $_SDFF_PP1_. +Using template $paramod$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PP_. +Using template $paramod$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_. +Using template $_DFF_PP0_ for cells of type $_DFF_PP0_. +Using template $_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_. +Using template $paramod$_DFFE_PN_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PN_. +Using template $_SDFFE_PP0N_ for cells of type $_SDFFE_PP0N_. +Using template $_SDFFE_PP1P_ for cells of type $_SDFFE_PP1P_. +No more expansions possible. + + +19.39. Executing OPT_EXPR pass (perform const folding). +Optimizing module fpga_neural_v2_top. + + +19.40. Executing SIMPLEMAP pass (map simple cells to gate primitives). + +19.41. Executing LATTICE_GSR pass (implement FF init values). +Handling GSR in fpga_neural_v2_top. + +19.42. Executing ATTRMVCP pass (move or copy attributes). + +19.43. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \fpga_neural_v2_top.. +Removed 1 unused cells and 33468 unused wires. + + +19.44. Executing CHECK pass (checking for obvious problems). +Checking module fpga_neural_v2_top... +Found and reported 0 problems. + +19.45. Executing TECHMAP pass (map to technology primitives). + +19.45.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/latches_map.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/latches_map.v' to AST representation. +Generating RTLIL representation for module `$_DLATCH_N_'. +Generating RTLIL representation for module `$_DLATCH_P_'. +Successfully finished Verilog frontend. + +19.45.2. Continuing TECHMAP pass. +No more expansions possible. + + +19.46. Executing ABC9 pass. + +19.46.1. Executing ABC9_OPS pass (helper functions for ABC9). + +19.46.2. Executing ABC9_OPS pass (helper functions for ABC9). + +19.46.3. Executing PROC pass (convert processes to netlists). + +19.46.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +19.46.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Marked 1 switch rules as full_case in process $proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:282$104119 in module $paramod$68581f66a8fa831820fa7633bd24ba569ae9d7e3\TRELLIS_FF. +Removed a total of 0 dead cases. + +19.46.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 0 redundant assignments. +Promoted 1 assignment to connection. + +19.46.3.4. Executing PROC_INIT pass (extract init attributes). +Found init rule in `$paramod$68581f66a8fa831820fa7633bd24ba569ae9d7e3\TRELLIS_FF.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:278$104120'. + Set init value: \Q = 1'0 + +19.46.3.5. Executing PROC_ARST pass (detect async resets in processes). +Found async reset \muxlsr in `$paramod$68581f66a8fa831820fa7633bd24ba569ae9d7e3\TRELLIS_FF.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:282$104119'. + +19.46.3.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + + +19.46.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). +Creating decoders for process `$paramod$68581f66a8fa831820fa7633bd24ba569ae9d7e3\TRELLIS_FF.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:278$104120'. +Creating decoders for process `$paramod$68581f66a8fa831820fa7633bd24ba569ae9d7e3\TRELLIS_FF.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:282$104119'. + 1/1: $0\Q[0:0] + +19.46.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). + +19.46.3.9. Executing PROC_DFF pass (convert process syncs to FFs). +Creating register for signal `$paramod$68581f66a8fa831820fa7633bd24ba569ae9d7e3\TRELLIS_FF.\Q' using process `$paramod$68581f66a8fa831820fa7633bd24ba569ae9d7e3\TRELLIS_FF.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:282$104119'. + created $adff cell `$procdff$104125' with positive edge clock and positive level reset. + +19.46.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +19.46.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Removing empty process `$paramod$68581f66a8fa831820fa7633bd24ba569ae9d7e3\TRELLIS_FF.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:278$104120'. +Found and cleaned up 1 empty switch in `$paramod$68581f66a8fa831820fa7633bd24ba569ae9d7e3\TRELLIS_FF.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:282$104119'. +Removing empty process `$paramod$68581f66a8fa831820fa7633bd24ba569ae9d7e3\TRELLIS_FF.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:282$104119'. +Cleaned up 1 empty switch. + +19.46.4. Executing PROC pass (convert processes to netlists). + +19.46.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:151$104182'. +Cleaned up 1 empty switch. + +19.46.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Marked 1 switch rules as full_case in process $proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$104183 in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. +Removed a total of 0 dead cases. + +19.46.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 0 redundant assignments. +Promoted 22 assignments to connections. + +19.46.4.4. Executing PROC_INIT pass (extract init attributes). + +19.46.4.5. Executing PROC_ARST pass (detect async resets in processes). + +19.46.4.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + + +19.46.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). +Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$104207'. +Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$104183'. + 1/3: $1$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$104181_EN[3:0]$104189 + 2/3: $1$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$104181_DATA[3:0]$104188 + 3/3: $1$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$104181_ADDR[3:0]$104187 +Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:151$104182'. + +19.46.4.8. Executing PROC_DLATCH pass (convert process syncs to latches). +No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\i' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$104207'. +No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$104165_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$104207'. +No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$104166_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$104207'. +No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$104167_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$104207'. +No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$104168_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$104207'. +No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$104169_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$104207'. +No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$104170_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$104207'. +No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$104171_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$104207'. +No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$104172_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$104207'. +No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$104173_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$104207'. +No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$104174_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$104207'. +No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$104175_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$104207'. +No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$104176_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$104207'. +No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$104177_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$104207'. +No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$104178_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$104207'. +No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$104179_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$104207'. +No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$104180_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$104207'. +No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\muxwre' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:151$104182'. + +19.46.4.9. Executing PROC_DFF pass (convert process syncs to FFs). +Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$104181_ADDR' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$104183'. + created $dff cell `$procdff$104233' with positive edge clock. +Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$104181_DATA' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$104183'. + created $dff cell `$procdff$104234' with positive edge clock. +Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$104181_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$104183'. + created $dff cell `$procdff$104235' with positive edge clock. + +19.46.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +19.46.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$104207'. +Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$104183'. +Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$104183'. +Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:151$104182'. +Cleaned up 1 empty switch. + +19.46.5. Executing SCC pass (detecting logic loops). +Found an SCC: $auto$simplemap.cc:298:simplemap_mux$56143 $auto$simplemap.cc:46:simplemap_not$32510 $auto$simplemap.cc:298:simplemap_mux$32578 $auto$simplemap.cc:298:simplemap_mux$32581 $auto$simplemap.cc:106:simplemap_bitop$32509 $auto$simplemap.cc:106:simplemap_bitop$58174 $auto$simplemap.cc:106:simplemap_bitop$32507 $auto$simplemap.cc:46:simplemap_not$32511 $auto$simplemap.cc:106:simplemap_bitop$32508 $auto$simplemap.cc:298:simplemap_mux$32577 $auto$simplemap.cc:298:simplemap_mux$32580 $auto$simplemap.cc:298:simplemap_mux$56142 $auto$simplemap.cc:298:simplemap_mux$56139 $auto$simplemap.cc:256:simplemap_logbin$56742 $auto$ff.cc:337:slice$31860 $auto$dfflegalize.cc:998:flip_pol$97552 $auto$ff.cc:573:convert_ce_over_srst$97550 $auto$simplemap.cc:157:simplemap_reduce$31934 $auto$simplemap.cc:106:simplemap_bitop$58173 $auto$simplemap.cc:298:simplemap_mux$56137 $auto$simplemap.cc:256:simplemap_logbin$56799 $auto$ff.cc:337:slice$31910 $auto$dfflegalize.cc:998:flip_pol$97626 $auto$ff.cc:573:convert_ce_over_srst$97624 $auto$simplemap.cc:157:simplemap_reduce$31936 $auto$simplemap.cc:106:simplemap_bitop$58172 $auto$simplemap.cc:298:simplemap_mux$32576 $auto$simplemap.cc:298:simplemap_mux$32579 $auto$simplemap.cc:298:simplemap_mux$56335 $auto$simplemap.cc:298:simplemap_mux$56353 $auto$simplemap.cc:256:simplemap_logbin$56627 $auto$simplemap.cc:298:simplemap_mux$56141 $auto$simplemap.cc:298:simplemap_mux$56138 $auto$simplemap.cc:256:simplemap_logbin$56685 $auto$ff.cc:337:slice$31909 $auto$dfflegalize.cc:998:flip_pol$97622 $auto$ff.cc:573:convert_ce_over_srst$97620 $auto$simplemap.cc:157:simplemap_reduce$31932 +Found an SCC: $auto$simplemap.cc:46:simplemap_not$59790 $auto$ff.cc:337:slice$32471 $auto$simplemap.cc:46:simplemap_not$59789 $auto$ff.cc:337:slice$32470 $auto$simplemap.cc:157:simplemap_reduce$37041 $auto$simplemap.cc:157:simplemap_reduce$37242 $auto$simplemap.cc:372:simplemap_lut$55501 $auto$simplemap.cc:372:simplemap_lut$55499 $auto$simplemap.cc:157:simplemap_reduce$37044 $auto$simplemap.cc:157:simplemap_reduce$37040 $auto$simplemap.cc:157:simplemap_reduce$37060 $auto$simplemap.cc:157:simplemap_reduce$55489 $auto$simplemap.cc:157:simplemap_reduce$55487 $auto$opt_expr.cc:607:replace_const_cells$94651 $auto$ff.cc:337:slice$32469 $auto$dfflegalize.cc:998:flip_pol$97410 $auto$ff.cc:573:convert_ce_over_srst$97630 $auto$simplemap.cc:157:simplemap_reduce$37046 +Found an SCC: $auto$simplemap.cc:256:simplemap_logbin$47855 $auto$ff.cc:337:slice$41061 $auto$simplemap.cc:157:simplemap_reduce$41063 $auto$simplemap.cc:256:simplemap_logbin$47854 +Found an SCC: $auto$simplemap.cc:256:simplemap_logbin$53727 $auto$ff.cc:337:slice$35793 $auto$simplemap.cc:157:simplemap_reduce$35795 +Found 4 SCCs in module fpga_neural_v2_top. +Found 4 SCCs. + +19.46.6. Executing ABC9_OPS pass (helper functions for ABC9). + +19.46.7. Executing TECHMAP pass (map to technology primitives). + +19.46.7.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `$__div_mod_u'. +Generating RTLIL representation for module `$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Generating RTLIL representation for module `$connect'. +Generating RTLIL representation for module `$input_port'. +Successfully finished Verilog frontend. + +19.46.7.2. Continuing TECHMAP pass. +No more expansions possible. + + +19.46.8. Executing OPT pass (performing simple optimizations). + +19.46.8.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod$68581f66a8fa831820fa7633bd24ba569ae9d7e3\TRELLIS_FF. +Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. + +19.46.8.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `$paramod$68581f66a8fa831820fa7633bd24ba569ae9d7e3\TRELLIS_FF'. +Computing hashes of 2 cells of `$paramod$68581f66a8fa831820fa7633bd24ba569ae9d7e3\TRELLIS_FF'. +Finding duplicate cells in `$paramod$68581f66a8fa831820fa7633bd24ba569ae9d7e3\TRELLIS_FF'. +Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'. +Computing hashes of 2 cells of `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'. +Finding duplicate cells in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'. +Removed a total of 0 cells. + +19.46.8.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module $paramod$68581f66a8fa831820fa7633bd24ba569ae9d7e3\TRELLIS_FF.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +19.46.8.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module $paramod$68581f66a8fa831820fa7633bd24ba569ae9d7e3\TRELLIS_FF. + Optimizing cells in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. +Performed a total of 0 changes. + +19.46.8.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `$paramod$68581f66a8fa831820fa7633bd24ba569ae9d7e3\TRELLIS_FF'. +Computing hashes of 2 cells of `$paramod$68581f66a8fa831820fa7633bd24ba569ae9d7e3\TRELLIS_FF'. +Finding duplicate cells in `$paramod$68581f66a8fa831820fa7633bd24ba569ae9d7e3\TRELLIS_FF'. +Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'. +Computing hashes of 2 cells of `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'. +Finding duplicate cells in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'. +Removed a total of 0 cells. + +19.46.8.6. Executing OPT_DFF pass (perform DFF optimizations). + +19.46.8.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module $paramod$68581f66a8fa831820fa7633bd24ba569ae9d7e3\TRELLIS_FF.. +Finding unused cells or wires in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.. + +19.46.8.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod$68581f66a8fa831820fa7633bd24ba569ae9d7e3\TRELLIS_FF. +Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. + +19.46.8.9. Finished fast OPT passes. (There is nothing left to do.) + +19.46.9. Executing TECHMAP pass (map to technology primitives). + +19.46.9.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_map.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_map.v' to AST representation. +Successfully finished Verilog frontend. + +19.46.9.2. Continuing TECHMAP pass. +Using template $paramod$68581f66a8fa831820fa7633bd24ba569ae9d7e3\TRELLIS_FF for cells of type $paramod$68581f66a8fa831820fa7633bd24ba569ae9d7e3\TRELLIS_FF. +Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. +No more expansions possible. + + +19.46.10. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_model.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_model.v' to AST representation. +Generating RTLIL representation for module `$__ABC9_DELAY'. +Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. +Generating RTLIL representation for module `$__DFF_N__$abc9_flop'. +Generating RTLIL representation for module `$__DFF_P__$abc9_flop'. +Successfully finished Verilog frontend. + +19.46.11. Executing ABC9_OPS pass (helper functions for ABC9). + + +19.46.12. Executing ABC9_OPS pass (helper functions for ABC9). + +19.46.13. Executing ABC9_OPS pass (helper functions for ABC9). + + +19.46.14. Executing TECHMAP pass (map to technology primitives). + +19.46.14.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `$__div_mod_u'. +Generating RTLIL representation for module `$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Generating RTLIL representation for module `$connect'. +Generating RTLIL representation for module `$input_port'. +Successfully finished Verilog frontend. + +19.46.14.2. Continuing TECHMAP pass. +Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C. +Using extmapper simplemap for cells of type $or. +Using extmapper simplemap for cells of type $and. +Using extmapper simplemap for cells of type $not. +Using extmapper simplemap for cells of type $xor. +Using template $paramod\LUT2\INIT=4'1010 for cells of type LUT2. +Using template $paramod\LUT4\INIT=16'1001011010101010 for cells of type LUT4. +Using extmapper simplemap for cells of type $mux. +No more expansions possible. + + +19.46.15. Executing OPT pass (performing simple optimizations). + +19.46.15.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module fpga_neural_v2_top. + + +19.46.15.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\fpga_neural_v2_top'. +Computing hashes of 59 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. +Computing hashes of 57 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. + +Removed a total of 2 cells. + +19.46.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \fpga_neural_v2_top.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +19.46.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \fpga_neural_v2_top. +Performed a total of 0 changes. + +19.46.15.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\fpga_neural_v2_top'. +Computing hashes of 57 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. +Removed a total of 0 cells. + +19.46.15.6. Executing OPT_DFF pass (perform DFF optimizations). + +19.46.15.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \fpga_neural_v2_top.. +Removed 0 unused cells and 55 unused wires. + + +19.46.15.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module fpga_neural_v2_top. + +19.46.15.9. Rerunning OPT passes. (Maybe there is more to do..) + +19.46.15.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \fpga_neural_v2_top.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +19.46.15.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \fpga_neural_v2_top. +Performed a total of 0 changes. + +19.46.15.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\fpga_neural_v2_top'. +Computing hashes of 57 cells of `\fpga_neural_v2_top'. +Finding duplicate cells in `\fpga_neural_v2_top'. +Removed a total of 0 cells. + +19.46.15.13. Executing OPT_DFF pass (perform DFF optimizations). + +19.46.15.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \fpga_neural_v2_top.. + +19.46.15.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module fpga_neural_v2_top. + +19.46.15.16. Finished fast OPT passes. (There is nothing left to do.) + +19.46.16. Executing AIGMAP pass (map logic to AIG). +Module fpga_neural_v2_top: replaced 18 cells with 120 new cells, skipped 39 cells. + replaced 3 cell types: + 14 $_MUX_ + 2 $_OR_ + 2 $_XOR_ + not replaced 3 cell types: + 4 $_AND_ + 4 $_NOT_ + 31 $specify2 + +19.46.17. Executing AIGMAP pass (map logic to AIG). +Module fpga_neural_v2_top: replaced 11586 cells with 72092 new cells, skipped 10945 cells. + replaced 5 cell types: + 8 $_ANDNOT_ + 7821 $_MUX_ + 24 $_ORNOT_ + 2958 $_OR_ + 775 $_XOR_ + not replaced 13 cell types: + 1951 $_AND_ + 1341 $_NOT_ + 16 $_TBUF_ + 1 $__ABC9_SCC_BREAKER + 27 $scopeinfo + 6320 TRELLIS_FF + 1 EHXPLLL + 32 MULT18X18D + 2 $paramod$68581f66a8fa831820fa7633bd24ba569ae9d7e3\TRELLIS_FF + 868 $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C + 192 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 + 2 $paramod$68581f66a8fa831820fa7633bd24ba569ae9d7e3\TRELLIS_FF_$abc9_byp + 192 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp + +19.46.17.1. Executing ABC9_OPS pass (helper functions for ABC9). + +19.46.17.2. Executing ABC9_OPS pass (helper functions for ABC9). + +19.46.17.3. Executing XAIGER backend. + +Extracted 30729 AND gates and 90915 wires from module `fpga_neural_v2_top' to a netlist network with 7629 inputs and 7086 outputs. + +19.46.17.4. Executing ABC9_EXE pass (technology mapping using ABC9). + +19.46.17.5. Executing ABC9. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ======== ABC command line "source /abc.script" +ABC: + read_lut /input.lut +ABC: + read_box /input.box +ABC: + &read /input.xaig +ABC: + &ps +ABC: /input : i/o = 7629/ 7086 and = 22542 lev = 58 (2.10) mem = 0.68 MB box = 1062 bb = 194 +ABC: + &scorr +ABC: Warning: The network is combinational. +ABC: + &sweep +ABC: + &dc2 +ABC: + &dch -f -r +ABC: + &ps +ABC: /input : i/o = 7629/ 7086 and = 20600 lev = 27 (1.04) mem = 0.63 MB ch = 2544 box = 932 bb = 191 +ABC: cst = 0 cls = 2385 lit = 2544 unused = 26281 proof = 0 +ABC: + &if -W 300 -v +ABC: K = 7. Memory (bytes): Truth = 0. Cut = 76. Obj = 156. Set = 780. CutMin = no +ABC: Node = 20600. Ch = 2385. Total mem = 7.62 MB. Peak cut mem = 0.28 MB. +ABC: P: Del = 5454.00. Ar = 15016.0. Edge = 19693. Cut = 189085. T = 0.02 sec +ABC: P: Del = 5454.00. Ar = 15361.0. Edge = 20062. Cut = 186763. T = 0.02 sec +ABC: P: Del = 5454.00. Ar = 5467.0. Edge = 15169. Cut = 376734. T = 0.04 sec +ABC: F: Del = 5454.00. Ar = 4679.0. Edge = 14028. Cut = 355559. T = 0.04 sec +ABC: A: Del = 5453.00. Ar = 4512.0. Edge = 13095. Cut = 336417. T = 0.05 sec +ABC: A: Del = 5453.00. Ar = 4498.0. Edge = 13073. Cut = 334897. T = 0.05 sec +ABC: Total time = 0.21 sec +ABC: + &write -n /output.aig +ABC: + &mfs +ABC: + &ps -l +ABC: /input : i/o = 7629/ 7086 and = 11807 lev = 22 (1.02) mem = 0.53 MB box = 904 bb = 191 +ABC: Mapping (K=7) : lut = 3665 edge = 12163 lev = 11 (0.56) levB = 27 mem = 0.22 MB +ABC: LUT = 3665 : 2=538 14.7 % 3=1771 48.3 % 4=1011 27.6 % 5=341 9.3 % 6=3 0.1 % 7=1 0.0 % Ave = 3.32 +ABC: + &write -n /output.aig +ABC: + &verify +ABC: Networks are equivalent. Time = 0.26 sec +ABC: + time +ABC: elapse: 1.53 seconds, total: 1.53 seconds + +19.46.17.6. Executing AIGER frontend. + +Removed 18740 unused cells and 40347 unused wires. + +19.46.17.7. Executing ABC_OPS_REINTEGRATE pass (reintegrate ABC mapped design into module). +ABC RESULTS: $lut cells: 3717 +ABC RESULTS: $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C cells: 713 +ABC RESULTS: $paramod$68581f66a8fa831820fa7633bd24ba569ae9d7e3\TRELLIS_FF_$abc9_byp cells: 2 +ABC RESULTS: $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp cells: 189 +ABC RESULTS: input signals: 605 +ABC RESULTS: output signals: 990 + +Removing temp directory. + +19.46.18. Executing TECHMAP pass (map to technology primitives). + +19.46.18.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_unmap.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_unmap.v' to AST representation. +Generating RTLIL representation for module `$__DFF_x__$abc9_flop'. +Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. +Successfully finished Verilog frontend. + +19.46.18.2. Continuing TECHMAP pass. +Using template $paramod$__ABC9_SCC_BREAKER\WIDTH=32'00000000000000000000000000000100 for cells of type $__ABC9_SCC_BREAKER. +Using template $paramod$68581f66a8fa831820fa7633bd24ba569ae9d7e3\TRELLIS_FF for cells of type $paramod$68581f66a8fa831820fa7633bd24ba569ae9d7e3\TRELLIS_FF. +Using template $paramod$68581f66a8fa831820fa7633bd24ba569ae9d7e3\TRELLIS_FF_$abc9_byp for cells of type $paramod$68581f66a8fa831820fa7633bd24ba569ae9d7e3\TRELLIS_FF_$abc9_byp. +Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. +Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C. +Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp. +No more expansions possible. + +Removed 636 unused cells and 105552 unused wires. + +19.47. Executing TECHMAP pass (map to technology primitives). + +19.47.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation. +Generating RTLIL representation for module `$_DFF_N_'. +Generating RTLIL representation for module `$_DFF_P_'. +Generating RTLIL representation for module `$_DFFE_NN_'. +Generating RTLIL representation for module `$_DFFE_PN_'. +Generating RTLIL representation for module `$_DFFE_NP_'. +Generating RTLIL representation for module `$_DFFE_PP_'. +Generating RTLIL representation for module `$_DFF_NP0_'. +Generating RTLIL representation for module `$_DFF_NP1_'. +Generating RTLIL representation for module `$_DFF_PP0_'. +Generating RTLIL representation for module `$_DFF_PP1_'. +Generating RTLIL representation for module `$_SDFF_NP0_'. +Generating RTLIL representation for module `$_SDFF_NP1_'. +Generating RTLIL representation for module `$_SDFF_PP0_'. +Generating RTLIL representation for module `$_SDFF_PP1_'. +Generating RTLIL representation for module `$_DFFE_NP0P_'. +Generating RTLIL representation for module `$_DFFE_NP1P_'. +Generating RTLIL representation for module `$_DFFE_PP0P_'. +Generating RTLIL representation for module `$_DFFE_PP1P_'. +Generating RTLIL representation for module `$_DFFE_NP0N_'. +Generating RTLIL representation for module `$_DFFE_NP1N_'. +Generating RTLIL representation for module `$_DFFE_PP0N_'. +Generating RTLIL representation for module `$_DFFE_PP1N_'. +Generating RTLIL representation for module `$_SDFFE_NP0P_'. +Generating RTLIL representation for module `$_SDFFE_NP1P_'. +Generating RTLIL representation for module `$_SDFFE_PP0P_'. +Generating RTLIL representation for module `$_SDFFE_PP1P_'. +Generating RTLIL representation for module `$_SDFFE_NP0N_'. +Generating RTLIL representation for module `$_SDFFE_NP1N_'. +Generating RTLIL representation for module `$_SDFFE_PP0N_'. +Generating RTLIL representation for module `$_SDFFE_PP1N_'. +Generating RTLIL representation for module `$_ALDFF_NP_'. +Generating RTLIL representation for module `$_ALDFF_PP_'. +Generating RTLIL representation for module `$_ALDFFE_NPN_'. +Generating RTLIL representation for module `$_ALDFFE_NPP_'. +Generating RTLIL representation for module `$_ALDFFE_PPN_'. +Generating RTLIL representation for module `$_ALDFFE_PPP_'. +Generating RTLIL representation for module `\FD1P3AX'. +Generating RTLIL representation for module `\FD1P3AY'. +Generating RTLIL representation for module `\FD1P3BX'. +Generating RTLIL representation for module `\FD1P3DX'. +Generating RTLIL representation for module `\FD1P3IX'. +Generating RTLIL representation for module `\FD1P3JX'. +Generating RTLIL representation for module `\FD1S3AX'. +Generating RTLIL representation for module `\FD1S3AY'. +Generating RTLIL representation for module `\FD1S3BX'. +Generating RTLIL representation for module `\FD1S3DX'. +Generating RTLIL representation for module `\FD1S3IX'. +Generating RTLIL representation for module `\FD1S3JX'. +Generating RTLIL representation for module `\IFS1P3BX'. +Generating RTLIL representation for module `\IFS1P3DX'. +Generating RTLIL representation for module `\IFS1P3IX'. +Generating RTLIL representation for module `\IFS1P3JX'. +Generating RTLIL representation for module `\OFS1P3BX'. +Generating RTLIL representation for module `\OFS1P3DX'. +Generating RTLIL representation for module `\OFS1P3IX'. +Generating RTLIL representation for module `\OFS1P3JX'. +Generating RTLIL representation for module `\IB'. +Generating RTLIL representation for module `\IBPU'. +Generating RTLIL representation for module `\IBPD'. +Generating RTLIL representation for module `\OB'. +Generating RTLIL representation for module `\OBZ'. +Generating RTLIL representation for module `\OBZPU'. +Generating RTLIL representation for module `\OBZPD'. +Generating RTLIL representation for module `\OBCO'. +Generating RTLIL representation for module `\BB'. +Generating RTLIL representation for module `\BBPU'. +Generating RTLIL representation for module `\BBPD'. +Generating RTLIL representation for module `\ILVDS'. +Generating RTLIL representation for module `\OLVDS'. +Generating RTLIL representation for module `$lut'. +Successfully finished Verilog frontend. + +19.47.2. Continuing TECHMAP pass. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0111 for cells of type $lut. +Using template $paramod$43779580bfffd5d5a9f321249a174febf1dac288$lut for cells of type $lut. +Using template $paramod$65d5d5c1e01bf41ee659754efba932f3d99198e5$lut for cells of type $lut. +Using template $paramod$d52cb446bc89fafcaa49f2b908e540f513a4d760$lut for cells of type $lut. +Using template $paramod$992bdc10cff2c6edd722994f0e1044bc863f79f7$lut for cells of type $lut. +Using template $paramod$b86b68a00733dbecb31d58a14a13683475a2002a$lut for cells of type $lut. +Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut. +Using template $paramod$c6a1f9ea79b7bb1672d5d3c63312684d0f3defb6$lut for cells of type $lut. +Using template $paramod$2d07c1a6c53c7b878509360922c4fa5ebedc3011$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110000 for cells of type $lut. +Using template $paramod$df196ed0a1da5c4a58c5e08a1dac304fd3fccaab$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010000 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11010000 for cells of type $lut. +Using template $paramod$e6049326c8634f79a905c381bb150ca718b543fa$lut for cells of type $lut. +Using template $paramod$f056b3cf42701dfc7f540d463578d46c622fe830$lut for cells of type $lut. +Using template $paramod$97866f90cbab54c1961aec5f8b1cf3bc32901aaf$lut for cells of type $lut. +Using template $paramod$2382b0dd4cb27fd4312681c40a6dd179c2a7a26a$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut. +Using template $paramod$eced46750b43aa9efabd63e9db30cd976a863157$lut for cells of type $lut. +Using template $paramod$b4f85a6321a00b090afc4e21d68e7b99eb94d149$lut for cells of type $lut. +Using template $paramod$ce23c8cef76b1a8b8b143bfa07ff3a4e4564b99e$lut for cells of type $lut. +Using template $paramod$18fa685a8cdb30eb6c664aa12d728a07c3fe94f1$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110100 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut. +Using template $paramod$0c822c65361ce832091b6c90f1a02f1ee0b109d4$lut for cells of type $lut. +Using template $paramod$da8506f47f742e881b922814186ffb6479b7a435$lut for cells of type $lut. +Using template $paramod$8d7a8d6e3356de09670738ba85f2c6b874f6b06d$lut for cells of type $lut. +Using template $paramod$c71ed138d834112b80a85f4478e2e21f72e5c48b$lut for cells of type $lut. +Using template $paramod$7f1c32e84a484762a42537f3470f578565adc487$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11000100 for cells of type $lut. +Using template $paramod$c0b24172d263163a8e6b59024cdb9dfb57b52d61$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000111 for cells of type $lut. +Using template $paramod$d63a590219c0ec3420247908946355403fa96fc0$lut for cells of type $lut. +Using template $paramod$c28a8b7ce0535d090c4cfb52e9c74affd52b110c$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010101 for cells of type $lut. +Using template $paramod$797d866167df3a8c4e1aa8edd8722133c7535936$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101000 for cells of type $lut. +Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010111 for cells of type $lut. +Using template $paramod$19451f719aa4a75f15cb977ed4212a1c1a1550e9$lut for cells of type $lut. +Using template $paramod$2e74fb09cb948401fecf1c7c22f99c9187989088$lut for cells of type $lut. +Using template $paramod$fca001e3e0b52158a872e76e56c01ec10dfbb1de$lut for cells of type $lut. +Using template $paramod$95647f061a452a57330090c74bbb5ab75f7ee34a$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10100010 for cells of type $lut. +Using template $paramod$5c7d886f3b88971ac55fed4bca034a87bf180f7d$lut for cells of type $lut. +Using template $paramod$c388bdf5bc34e848632d723db494e9a79bee28dd$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut. +Using template $paramod$74a12c4d30e035eeda2d34c53b77373f2b2df37a$lut for cells of type $lut. +Using template $paramod$82b4a585d1edcb5c6e755dc9bd3392228a1c1304$lut for cells of type $lut. +Using template $paramod$179512a187da069f3b79ef6612a41e494e7d54b6$lut for cells of type $lut. +Using template $paramod$d6ca727e39f31d51d29072e0f33aa09c65e37336$lut for cells of type $lut. +Using template $paramod$67a75dc9271b5d9a17b9baae1fe5ef0486ab8e34$lut for cells of type $lut. +Using template $paramod$40882341c54dcd36f630f00dd7e46a35652abd36$lut for cells of type $lut. +Using template $paramod$25445fb9dd8fc77490980c6bd2e9dbc53c6e84a5$lut for cells of type $lut. +Using template $paramod$8e44661def013b6bf9fe6f8b049ef2c838d749f9$lut for cells of type $lut. +Using template $paramod$a5516fc31d1e552de2435200bb732b4d4ad63a9c$lut for cells of type $lut. +Using template $paramod$3c1d8d3aefaa123989da142f0d4f6c0bc5c20fff$lut for cells of type $lut. +Using template $paramod$0b164be298220d32b1283d259e9078af3bc3e0cd$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00011011 for cells of type $lut. +Using template $paramod$2ed945693823e972236d8ef3dfa1036e6ba89bd3$lut for cells of type $lut. +Using template $paramod$859bbf20189511d5622298a363e8f136876f0d6c$lut for cells of type $lut. +Using template $paramod$c9b834dc9c2f376b2a44311c706cb34f7f0a4014$lut for cells of type $lut. +Using template $paramod$133ad27679cc12d115c56a20436ffefcefb608a9$lut for cells of type $lut. +Using template $paramod$04b674496422df8889c01c3744b94097628ccfbc$lut for cells of type $lut. +Using template $paramod$de9f5f73d1a4b7cf393fccc6f7957f70685c2fa7$lut for cells of type $lut. +Using template $paramod$e6a488add0b5a2d742e2ae29f62ce7616e04271d$lut for cells of type $lut. +Using template $paramod$018d71a0fe325d6362687fe53ac13dd6340e400d$lut for cells of type $lut. +Using template $paramod$6cafb465f31c34f6bb6b9412b7e75000e2a2081c$lut for cells of type $lut. +Using template $paramod$7d35f3eb4056e6484203c99fe42cfcf1dfaba704$lut for cells of type $lut. +Using template $paramod$234fd643079033ba0cbc98ff572df9b7b7a0dc86$lut for cells of type $lut. +Using template $paramod$ab8bb87959c5d7cfa27886cee1355b38e054a61a$lut for cells of type $lut. +Using template $paramod$a6597eda4608f36e684c1dd07ed552fcbec112b2$lut for cells of type $lut. +Using template $paramod$608f40069c27841a5b3bdf03643a34bdc8974072$lut for cells of type $lut. +Using template $paramod$ec6c71d259df49ae0842190ffaff1179e43a8db4$lut for cells of type $lut. +Using template $paramod$11ec7271d8e6e5aeaace08c13e4c601f10e31038$lut for cells of type $lut. +Using template $paramod$aa87f4b44361d4073f55a64babebb83974861eee$lut for cells of type $lut. +Using template $paramod$2e721a1d17b3565829744fa2151e996e88c8a4ad$lut for cells of type $lut. +Using template $paramod$6e238df02989b317f10820a22773676e71120644$lut for cells of type $lut. +Using template $paramod$ae3a43343511e19fb300feaa5c0de22b62b0fa1b$lut for cells of type $lut. +Using template $paramod$f9d1c438f06419c3f069fb8ccb89c9102658adee$lut for cells of type $lut. +Using template $paramod$bf80ab5b82bc1c590371914612ed4ab80a2743a3$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010101 for cells of type $lut. +Using template $paramod$1241d759e3df4cac11dc7c99c36b0d1b07f7a673$lut for cells of type $lut. +Using template $paramod$38ddb5cd59e13482af3017fd3f8559df8cf1d4b7$lut for cells of type $lut. +Using template $paramod$e8f04aa93deb6aa077b1364bd7ddec17553d6e97$lut for cells of type $lut. +Using template $paramod$101238f3d8d49ab12a9b49a2f01cd503b26e9c61$lut for cells of type $lut. +Using template $paramod$782961deb8dc512aef835b73aa3765da3ab3c15c$lut for cells of type $lut. +Using template $paramod$45e1ac2b5fd4b86909f4a625ffe4b86335039347$lut for cells of type $lut. +Using template $paramod$f8f63b209b7230e81958663ff24fef1613156af7$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut. +Using template $paramod$f9813472aa48e533b3838c6f2316dc2e78c66111$lut for cells of type $lut. +Using template $paramod$7adc57507d26297b53947c4ff437bb539e2f0373$lut for cells of type $lut. +Using template $paramod$8614da24b3846fe751594d00fba789cfcb7b874c$lut for cells of type $lut. +Using template $paramod$62fb31b1a783eac472264027492b859f55ad08ed$lut for cells of type $lut. +Using template $paramod$f85f1073c412d406200a6a72283f918c8b751314$lut for cells of type $lut. +Using template $paramod$30305e55a780880b9c824fe3509a4d981acb0f2b$lut for cells of type $lut. +Using template $paramod$db85cac9b36977710f9657a368f30c4079b2320d$lut for cells of type $lut. +Using template $paramod$76387b60a3c62f4b59b6ea97413c9a4015bf6d34$lut for cells of type $lut. +Using template $paramod$e5761adfcc530461835be17350166b9d43dfadee$lut for cells of type $lut. +Using template $paramod$eb5fbd1b65e62545447a20e380b5162190426002$lut for cells of type $lut. +Using template $paramod$e51a8a571bee774247b38f52d6e85fd62ae52cea$lut for cells of type $lut. +Using template $paramod$0943324992873f68d548adee292d09c6d57581d1$lut for cells of type $lut. +Using template $paramod$20798777255c214e32de3304ce8faa1fdfa2f474$lut for cells of type $lut. +Using template $paramod$ae791f726a3e4646e7a6f56a901a56ed7ce9fcc8$lut for cells of type $lut. +Using template $paramod$a4640096cbef09c4ef8613155a589c40164ac034$lut for cells of type $lut. +Using template $paramod$c7b42a606c163d81f7b9611e21316ed18e513411$lut for cells of type $lut. +Using template $paramod$1441752f75f40414168532910704745ad88e7c69$lut for cells of type $lut. +Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8$lut for cells of type $lut. +Using template $paramod$c6875dac01295afda46f6ee5efd18642dbf4346d$lut for cells of type $lut. +Using template $paramod$f377b83bfd4274750d2cc48e6e3fa52263d09667$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001010 for cells of type $lut. +Using template $paramod$223d1ec0b6718782528b6753a31b303111f0a5a3$lut for cells of type $lut. +Using template $paramod$52953750219effadf43093a566baf492fdd6b6c8$lut for cells of type $lut. +Using template $paramod$9ae0f136c9ed34a2deb323e9b2a3a520eea61514$lut for cells of type $lut. +Using template $paramod$4e09fb85ad5980549134c5674f63e37de31e60bc$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000010 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1101 for cells of type $lut. +Using template $paramod$eba7de026ff587370e320127e266317dae097a89$lut for cells of type $lut. +Using template $paramod$ea5280fce2698f0f291737e66fca69a1d9d058e1$lut for cells of type $lut. +Using template $paramod$35059585e93e18989247e13034fd6a1ce4de9957$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001100 for cells of type $lut. +Using template $paramod$6ef2f0cf9ee7045cbb81aa2f4be3a6d3a9eb99ec$lut for cells of type $lut. +Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8$lut for cells of type $lut. +Using template $paramod$18e50808df562b188523e13714b96fedec6427c1$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001110 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100000 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001100 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut. +Using template $paramod$a36e8dae1e0b2cdcb9b3245705273d04c20fcd11$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001000 for cells of type $lut. +Using template $paramod$2ea69c779d6c1b79ac5a87b0d1523c67d5628dba$lut for cells of type $lut. +Using template $paramod$fdcae86fcfd036c1880a04306ae771a9d7579c31$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010011 for cells of type $lut. +Using template $paramod$250e9ed6c15020113b6b30a5ef7c8f11f208ca8e$lut for cells of type $lut. +Using template $paramod$32abbd1d449a67fb913b4733374e345d4c17175b$lut for cells of type $lut. +Using template $paramod$7ffcd6f97926b26c1ce973d3db39a23c2201eed8$lut for cells of type $lut. +Using template $paramod$0fcb06ed76df01e8d45bc2b9e6c8a9b43fa42cb4$lut for cells of type $lut. +Using template $paramod$c1a19a87ccbbb03d43a72335db63f692ddf82cc1$lut for cells of type $lut. +Using template $paramod$20235ca863361fbc253329cfc7eeea38c77404dc$lut for cells of type $lut. +Using template $paramod$2955ab75367a3dc9d6f50d3655eebcd4f615031f$lut for cells of type $lut. +Using template $paramod$5d2a75dcd2d4c90fca15a1510e937941a10741dd$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111110 for cells of type $lut. +Using template $paramod$364c9ffbffac467d60dfec81bba4e18476c15602$lut for cells of type $lut. +Using template $paramod$47a8214374025465e226fa66bee690ff33268a25$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001111 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000100 for cells of type $lut. +Using template $paramod$5e9374f44a27c3f8a1c38af244ec43ceb4fb8d4f$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut. +Using template $paramod$88f765f8c631a451551f4db4bcef4c92b710663d$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100010 for cells of type $lut. +Using template $paramod$56abb120b7f083882b1440587b6d9f3a229c9ef5$lut for cells of type $lut. +Using template $paramod$ba7b4568c306470a7f204c239212739869e234a1$lut for cells of type $lut. +Using template $paramod$7ed31fc00b1e5ea4e6f7d572afcd9937b67f68a0$lut for cells of type $lut. +Using template $paramod$8494168726d27c2200605afcf1fb7470bf987857$lut for cells of type $lut. +Using template $paramod$8512f4fb47fa9596f76cdbe5b407a5b54df368e7$lut for cells of type $lut. +Using template $paramod$7f1c52278eddb3d70b5a9ca9e97f0a9d36d85ce5$lut for cells of type $lut. +Using template $paramod$fa8852d442134efa381df9456239cde7cc3e31ff$lut for cells of type $lut. +Using template $paramod$f45429e380905f064bb0bad3a8bdb941708e63a7$lut for cells of type $lut. +Using template $paramod$359fe4e746656bf9c72aecaff84fc7bdea9f55a5$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111101 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111000 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010100 for cells of type $lut. +Using template $paramod$34d8179c3f4e5c9b014184678126740a73fec819$lut for cells of type $lut. +Using template $paramod$504c9f1ca6facbed70a8a05210386b24177f23fe$lut for cells of type $lut. +Using template $paramod$b4410865e8124402796f9dfbf73ef8d279fdbd08$lut for cells of type $lut. +Using template $paramod$19f568890ed784cb1efc3ce1b67eed20a6c54d9a$lut for cells of type $lut. +Using template $paramod$334e9e8cd93e28a94b0fed9006e0006d02d14ef9$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101011 for cells of type $lut. +Using template $paramod$dbbe0ea5aadf61e5da6ebbf1f47442d5facdca4e$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101010 for cells of type $lut. +Using template $paramod$0e7ce19e5da99c6675c7a5220f7cc55270b24ac0$lut for cells of type $lut. +Using template $paramod$170ecd93704f4aa989379b6e48410c95fb3a4af5$lut for cells of type $lut. +Using template $paramod$b0f6b2e191ce6d56c3504697d8cad28a26d6ef39$lut for cells of type $lut. +Using template $paramod$7678d9b19a5d0d97b38072e3ff7e0cc3a11c961b$lut for cells of type $lut. +Using template $paramod$e3448403426c0001b025f0525857c7be64a55828$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100000 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000100 for cells of type $lut. +Using template $paramod$6c22e4c9acd607e1249c5e3017b6703f378da140$lut for cells of type $lut. +Using template $paramod$9e354de8d358bf081aa0c089488ea3bc5b7c2fd9$lut for cells of type $lut. +Using template $paramod$e2a18bf756b6896f39d0e8969d3847f6f93b4ece$lut for cells of type $lut. +Using template $paramod$4d9437f28ee827cf4006287c53ecaa1266100fca$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110001 for cells of type $lut. +Using template $paramod$52fa1b2073b9054923f466bbb768e0ea7c69c9e3$lut for cells of type $lut. +Using template $paramod$37cbd66b1bb96fdf033ea86280ae98f0988c69d1$lut for cells of type $lut. +Using template $paramod$a4404e742e43b8bf8bde71df8b64cbe0c6ba02bd$lut for cells of type $lut. +Using template $paramod$bffd3a72f0a752ec6432b783a2614ddb6d255b5e$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00111010 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111010 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101110 for cells of type $lut. +Using template $paramod$ea0daa5c0efb0f7b64dadf4ba473c3906b6cb63f$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001101 for cells of type $lut. +Using template $paramod$b2192df6f90569fea4015d0a6658bdc192199f95$lut for cells of type $lut. +Using template $paramod$703a13a751e631ef123f38f7d2125aeabec0f94c$lut for cells of type $lut. +Using template $paramod$58685d136f916910674b7cdb559b8c116c3484e1$lut for cells of type $lut. +Using template $paramod$7ffc04c088a4897014506d1e561a14b627924059$lut for cells of type $lut. +Using template $paramod$a49560c57293d842b4cf7a38a8a09c32c1002e11$lut for cells of type $lut. +Using template $paramod$0ae7705354ab4bfd071e2551e0df024a40a698f7$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011000 for cells of type $lut. +Using template $paramod$44236511622e197854fa4814b088d63bb24df320$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111000 for cells of type $lut. +Using template $paramod$5dc745bb48e2cf535179547ba13f0fe5364d6d54$lut for cells of type $lut. +Using template $paramod$b61592988ab1e135761653be3cf83c6aa216aa9a$lut for cells of type $lut. +Using template $paramod$8b24407096beec47292ddeb1567a058197a320b9$lut for cells of type $lut. +Using template $paramod$8fd8efe0a495790cc9ddc97266933ea8a8cd7b45$lut for cells of type $lut. +Using template $paramod$e8e168ec2634b22e1171e63d365ebf8587eff03a$lut for cells of type $lut. +Using template $paramod$f3b603d1450c2c61ce732232fcb5fe1f2884aa83$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001110 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101111 for cells of type $lut. +Using template $paramod$8c24dc0cdd336b7fb88bbf7eed45cec5cbae862b$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001110 for cells of type $lut. +Using template $paramod$f9b715fbf1040e81e900b2461c2390d17ed5e988$lut for cells of type $lut. +Using template $paramod$6be53ab59e0a69757fc32adb071ddcb64e8c87b6$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110100 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110010 for cells of type $lut. +Using template $paramod$aac6d59f355a7d23229185f164512777990d6c1e$lut for cells of type $lut. +Using template $paramod$c032795a569e6541865ceaf4a542b65f5d837918$lut for cells of type $lut. +Using template $paramod$1bf3509a544426de1daa8b6919ee1df60c7165ec$lut for cells of type $lut. +Using template $paramod$120c20f632ce45d8913b24863643696ec017df28$lut for cells of type $lut. +Using template $paramod$876c24896b01cb56f94396467313f37de43f07cc$lut for cells of type $lut. +Using template $paramod$b89c522b7f70adaee1a35d80e932f38159b6a445$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101100 for cells of type $lut. +Using template $paramod$54d8b64ed755e82e7e992673de152e8730c42cbd$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100100 for cells of type $lut. +Using template $paramod$89ddbc2adee46e16a995ee97de1cb5a2b3106788$lut for cells of type $lut. +Using template $paramod$1113564b57022624ca058af09cacbcc529e2ba49$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001101 for cells of type $lut. +Using template $paramod$19c1a1b75dca0b9ba7cfe2be811099b4da088cfb$lut for cells of type $lut. +Using template $paramod$78019d9330dbe9ad13a0e0d1d22a6248c95029a9$lut for cells of type $lut. +Using template $paramod$e5759512db67494ff77fbdfc66dff4006376568f$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101010 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100011 for cells of type $lut. +Using template $paramod$3c3fed19c6fd1d349196eeef2e653fb0a32b5a50$lut for cells of type $lut. +Using template $paramod$cc08dba3aac8677e797984bdf18a09dd37547dd3$lut for cells of type $lut. +Using template $paramod$1b53a9695a0f80de7517b50863b438fd2b7f56da$lut for cells of type $lut. +Using template $paramod$0babebe51def8f4db6daaf70fa957a9414a7eb6e$lut for cells of type $lut. +Using template $paramod$4834046533425f54583d6bd31e49deb63455e1a5$lut for cells of type $lut. +Using template $paramod$3b383aa74b05b60cb9cabc0ba0eca4dea92c2b33$lut for cells of type $lut. +Using template $paramod$b80b9886d11b28e1ad6b253f8cc7222b59f03349$lut for cells of type $lut. +Using template $paramod$86d1a43c2f1d620ff2cef866448dd1258c868fad$lut for cells of type $lut. +Using template $paramod$00ac4aed4342e779b085d633e930287e40c108df$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01100011 for cells of type $lut. +Using template $paramod$b12c06dcea4e94212d81ae51560e40391ac83400$lut for cells of type $lut. +Using template $paramod$619b7c9a4d44585e10b42f7fb79b16304cca97c5$lut for cells of type $lut. +Using template $paramod$17c27ffdda03355f95b2ba5edc73ca082237c935$lut for cells of type $lut. +Using template $paramod$bf3c695b03cbb3727b63eb2bf69127329bf3a602$lut for cells of type $lut. +Using template $paramod$001d9634602f00137f774620efde4c651c7a59ca$lut for cells of type $lut. +Using template $paramod$c39c4706281147502fb727e3061e39485b38781d$lut for cells of type $lut. +Using template $paramod$a5788e8bd3559e65ba7c6a1d93529c6fb76569b9$lut for cells of type $lut. +Using template $paramod$b4d0f4738a5ce50c7f36c2aa2ecc09cfb874f2b6$lut for cells of type $lut. +Using template $paramod$17fd36fab32bce162e5828682c2ba9fa7f9e273b$lut for cells of type $lut. +Using template $paramod$53ce561f80f32d4298a3beadc88b6c5c78293221$lut for cells of type $lut. +Using template $paramod$7bb6a37e65823eeb4b38c370fec30ab082759a14$lut for cells of type $lut. +Using template $paramod$cdc5bba2585477f1744fd1f869bebc8beb23d707$lut for cells of type $lut. +Using template $paramod$9891217114ca63a6e9d48073351d843bb1d46faf$lut for cells of type $lut. +Using template $paramod$c79843a7a21eda73c585e76a35dd51b0a4d6fd36$lut for cells of type $lut. +Using template $paramod$a8b2b0f3a3fd7b01c99e8d61bb72f602bd41af54$lut for cells of type $lut. +Using template $paramod$d5c7dda3e544463bf43ed73dadb51262f5dcf2fe$lut for cells of type $lut. +Using template $paramod$9dd298ae76fb41ac94779a83c068607fbc09ce4f$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101000 for cells of type $lut. +Using template $paramod$5552b23a89809fed2b1588e8f91bb3893be2e6ce$lut for cells of type $lut. +Using template $paramod$23ba03b3f106a8b0f20f18bfebd862b419996ddc$lut for cells of type $lut. +Using template $paramod$d6a246575d0ba3dcbbccd768ad41b602f82ff057$lut for cells of type $lut. +Using template $paramod$412464b189b15787e0205fff1bb0d2bb7909d0b3$lut for cells of type $lut. +Using template $paramod$baa939b0bd5b3e0c8760492528669bd58f640542$lut for cells of type $lut. +Using template $paramod$7f8dcbbcc0931c3398304053d9bb53ce1acb1b1f$lut for cells of type $lut. +Using template $paramod$4c41f1623393f37dcc4e2d184a7f0d948ea506e4$lut for cells of type $lut. +Using template $paramod$cbf0a50c953b6a4c7e5a4cf3ec7fcd294af3c37d$lut for cells of type $lut. +Using template $paramod$1cabbe2f17ea824b0f9f091fd1dc13fff0b3a362$lut for cells of type $lut. +Using template $paramod$94446be4303ee2efa6f5d021831138c8c905d289$lut for cells of type $lut. +Using template $paramod$68fe50ee5a60a0bed36b1b1843c805d7bc807f41$lut for cells of type $lut. +Using template $paramod$6b7c9c56fc2a32a479d463d5f3b0d3f4673b67f1$lut for cells of type $lut. +Using template $paramod$9e394303e290a474880b56f98766417009256d93$lut for cells of type $lut. +Using template $paramod$509061f88e1db7dfaf19873d4cc611e2870d15d9$lut for cells of type $lut. +Using template $paramod$7b809938766c3068dc017c276033f224fcfb7189$lut for cells of type $lut. +Using template $paramod$bdd0743498c1b082701359850a99d6fbd624c0dd$lut for cells of type $lut. +Using template $paramod$af01034afe1bdbc87587d263805971d96e724ed7$lut for cells of type $lut. +Using template $paramod$66658cbed86a8310f9b7ba1190d35eff90ee749b$lut for cells of type $lut. +Using template $paramod$97472f517efe00e2e4bbd270b2ef0f8e6d9a1199$lut for cells of type $lut. +Using template $paramod$873c285bdccf0ac2b60d2304ea5cd14bf211d2a6$lut for cells of type $lut. +Using template $paramod$b2e8d279775d333b39e310bd45fd5952acdde290$lut for cells of type $lut. +Using template $paramod$ddace04fba544e6adc4cdda6a50048ddd7c111af$lut for cells of type $lut. +Using template $paramod$b587e1dcd8f8a9800d395e4aeecac52c55d6f585$lut for cells of type $lut. +Using template $paramod$114cec172d8a99287ecce5b94f20863d32d39458$lut for cells of type $lut. +Using template $paramod$fccccf8bb2add7667329c686feec7546eb9a3ae3$lut for cells of type $lut. +Using template $paramod$db08fd84fb3c4d6a41eaec6adfffe445fb7eb17f$lut for cells of type $lut. +Using template $paramod$7aa8140c7d6de3160b21e7ff84e0f93f69f7fcc6$lut for cells of type $lut. +Using template $paramod$b9d8b7e91a2c68da033af948ea0bd8bdebbaf6b2$lut for cells of type $lut. +Using template $paramod$2978a73989be3e1278af72b9db666c30fa0ff85b$lut for cells of type $lut. +Using template $paramod$cd6c4b4da6d8737b72fd2dc8f5d83d8967445809$lut for cells of type $lut. +Using template $paramod$fb2de0338fd9cb56279bec3d2d5d229fcea1942b$lut for cells of type $lut. +Using template $paramod$3a75385b1beb239786b9fcdc898b53110e63595f$lut for cells of type $lut. +Using template $paramod$9085b12d8ba976889f5f19665d793e2ee93c26a6$lut for cells of type $lut. +Using template $paramod$8f8f3ed0dfbd822273417c0b66ef033f29ee6b95$lut for cells of type $lut. +Using template $paramod$8cd5a5f75f43fffe243164dff2e5d4f1454af19a$lut for cells of type $lut. +Using template $paramod$e9c77024ca501b890c641f9c0b10e27242db8730$lut for cells of type $lut. +Using template $paramod$364d53446b8be453ea4311ff48988217fbc0109a$lut for cells of type $lut. +Using template $paramod$b43cdd6ca89f8faa7ea02c4f2b202cefaf655ede$lut for cells of type $lut. +Using template $paramod$5321e04f7ce32c091123c3570ab562efb1c81402$lut for cells of type $lut. +Using template $paramod$4e9e23686d07a1fd91232ab07371e48a0e62a680$lut for cells of type $lut. +Using template $paramod$03b3a4faa837145629f036b6abb5dd15cd761ea0$lut for cells of type $lut. +Using template $paramod$7c085cdbf0919cd3ad402d9495d97f0d71e4db93$lut for cells of type $lut. +Using template $paramod$4ee9301f068c856aba9d3809c1f967373138c2fb$lut for cells of type $lut. +Using template $paramod$fbd873e1000c0820c47d5f909c10980edcf0c495$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110001 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110010 for cells of type $lut. +Using template $paramod$3d7168c8134c4765b84a7b86d5ef7e1e65bbf4a0$lut for cells of type $lut. +Using template $paramod$3fd3cd243a8b2f71b0ffe04bdaebf6ad83bcc78e$lut for cells of type $lut. +Using template $paramod$973818279bc95792902f3c09371fd2407d04a2a5$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010001 for cells of type $lut. +Using template $paramod$9c6e6a10ea00e5b0682f6243b802d7839a398197$lut for cells of type $lut. +Using template $paramod$4b2297966ddb718657b80566604f97685ffc0120$lut for cells of type $lut. +Using template $paramod$51e48538280474c9f69a3d6951615d32243ae75c$lut for cells of type $lut. +Using template $paramod$251994398653c4cf8de320f1e306e535d5d2d624$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10100011 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101110 for cells of type $lut. +Using template $paramod$bdd2828c357e2988c59ecf555c59dc2c3d2828f9$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000110 for cells of type $lut. +Using template $paramod$be1aa0fb8e9f3e33e95bf6d002bf0e4c2e1bcc2d$lut for cells of type $lut. +Using template $paramod$f87bcf1791971b4eaa30f3f28437044fef878a04$lut for cells of type $lut. +Using template $paramod$e00d03686849cf5e50e9f0c13f0f78958ff5e7ae$lut for cells of type $lut. +Using template $paramod$c5b694ec89d7629b942ccf6a9be1d39e24f8edec$lut for cells of type $lut. +Using template $paramod$e6494397b405f26532371dd0857aece2fef514a9$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01100000 for cells of type $lut. +Using template $paramod$72043e0aa7fa64cb454e3c2ca3dbe1636171896a$lut for cells of type $lut. +Using template $paramod$cf652acbfbf67d2248e3045cd0f09c58ca55886c$lut for cells of type $lut. +Using template $paramod$10b7b810a6a6f18bc62789393bbe16e6a166c87b$lut for cells of type $lut. +Using template $paramod$766f851776a2d25e13728c9147ddfe7ff70917a3$lut for cells of type $lut. +Using template $paramod$2e37a29808ea9d028852cbc67bbcbc7bc127b77a$lut for cells of type $lut. +Using template $paramod$8384e66d408d22ab39dfb451efb7879731befeb8$lut for cells of type $lut. +Using template $paramod$2597d4bb6cf001a4497f4fe00c6e27e205da7639$lut for cells of type $lut. +Using template $paramod$148c80d43c5f325be6f9e4d60b0cf503f7dcc483$lut for cells of type $lut. +Using template $paramod$1b8a7be169f96aab855f9736a0d25a533c1b7a6e$lut for cells of type $lut. +Using template $paramod$d909494d67d7075f17a422f7cb5526f6d6564ea6$lut for cells of type $lut. +Using template $paramod$8d3ce9be81cff69f90f3cfd65305257300b4cb85$lut for cells of type $lut. +Using template $paramod$a50bbaf70b48eb6d78317eddf4f7e11e8988acec$lut for cells of type $lut. +Using template $paramod$e3e4230bb990723642112b292aa705ee0cbad0d4$lut for cells of type $lut. +Using template $paramod$7c0c958e927437390cb58f1395b98e0852db607c$lut for cells of type $lut. +Using template $paramod$c68110307ed3a83d1f1d050a34218c458bce2221$lut for cells of type $lut. +Using template $paramod$bba54c1ef87367812b4c15f4aed5ac70773df775$lut for cells of type $lut. +Using template $paramod$6023c671e114c4eb0467aa8a0b08e183f33ec2fd$lut for cells of type $lut. +Using template $paramod$cad45b6c9da81941161a13849773fe2ed4bc1c6f$lut for cells of type $lut. +Using template $paramod$6f3f060a82077d7722793a80a7f81ffcda8e7f4d$lut for cells of type $lut. +Using template $paramod$d47075a53ff1dff553bbe454ba83286b2e9de7dd$lut for cells of type $lut. +Using template $paramod$ea79e410ad0f4fc3326666c891e1f3992816d636$lut for cells of type $lut. +Using template $paramod$7c7b4989092be945ede883fe9e8e3c40a69802d1$lut for cells of type $lut. +Using template $paramod$bed46d4bec2425331313fb232ee344931dd93d96$lut for cells of type $lut. +Using template $paramod$df5999ec14d68f76a12ccd5d94c718f688537d4e$lut for cells of type $lut. +Using template $paramod$78b7f61776f7b3e82414706b5df5da710258defb$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000101 for cells of type $lut. +Using template $paramod$756861dd4dfe0a5b9de37af2241117b1958e2ffe$lut for cells of type $lut. +Using template $paramod$b431bfd938e35871dd0b7668e1503c7e8b9d491c$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010110 for cells of type $lut. +Using template $paramod$59b5899ed100f80c8878cb0ee0bc66b8f67d7b7b$lut for cells of type $lut. +Using template $paramod$09deb89cf77b6e37f6ed7fef8d797dc05c0b2eee$lut for cells of type $lut. +Using template $paramod$a9ba23df824f693c44e722629fd8c1fae157385c$lut for cells of type $lut. +Using template $paramod$81d8a60fd95b1a9f9ef71c12a774ae6988cb9fd5$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110000 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11000110 for cells of type $lut. +Using template $paramod$07b1b12ce0305f55108770e958fd02caedfebdf8$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut. +No more expansions possible. + + +19.48. Executing OPT_LUT_INS pass (discard unused LUT inputs). +Optimizing LUTs in fpga_neural_v2_top. + Optimizing lut $abc$249067$lut$aiger249066$11767.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$249067$lut$aiger249066$11763.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$249067$lut$aiger249066$11759.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$249067$lut$aiger249066$11755.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$249067$lut$aiger249066$14324.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$249067$lut$aiger249066$14324.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249374.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249389.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249390.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249392.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249397.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249418.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249423.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249429.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249465.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249475.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249499.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249577.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$249067$lut$aiger249066$11339.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$249067$lut$aiger249066$10735.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) + Optimizing lut $abc$249067$lut$aiger249066$10735.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) + Optimizing lut $abc$249067$lut$aiger249066$10735.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) + Optimizing lut $abc$249067$lut$aiger249066$10735.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) + Optimizing lut $abc$249067$lut$aiger249066$10735.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) + Optimizing lut $abc$249067$lut$aiger249066$10853.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$249067$lut$aiger249066$10853.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) + Optimizing lut $abc$249067$lut$aiger249066$11455.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$249067$lut$aiger249066$11463.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$249067$lut$aiger249066$11468.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$249067$lut$aiger$o11161.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$249067$lut$aiger249066$14457.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$249067$lut$aiger249066$13117.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$249067$lut$aiger249066$11130.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$249067$lut$aiger249066$11256.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$249067$lut$aiger$o8447.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$249067$lut$aiger249066$14311.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$249067$lut$aiger249066$11119.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$249067$lut$aiger249066$11287.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$249067$lut$aiger249066$11299.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$249067$lut$aiger$o8405.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$249067$lut$aiger249066$11149.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$249067$lut$aiger249066$11334.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$249067$lut$aiger249066$11339.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$249067$lut$aiger249066$11350.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249489.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$249067$lut$aiger249066$15403.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$249067$lut$aiger249066$11408.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$249067$lut$aiger$o10300.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$249067$lut$aiger$o10300.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$249067$lut$aiger249066$11429.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$249067$lut$aiger$o11161.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$249067$lut$aiger249066$11450.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$249067$lut$aiger249066$11455.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$249067$lut$aiger$o9746.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$249067$lut$aiger$o9746.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$249067$lut$aiger249066$11450.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$249067$lut$aiger249066$11463.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$249067$lut$aiger249066$11468.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$249067$lut$aiger$o9745.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$249067$lut$aiger$o9745.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$249067$lut$aiger249066$11074.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$249067$lut$aiger249066$14637.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$249067$lut$aiger249066$11527.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$249067$lut$aiger249066$13430.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$249067$lut$aiger249066$11553.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$249067$lut$aiger249066$13005.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$249067$lut$aiger249066$13389.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$249067$lut$aiger249066$11560.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$249067$lut$aiger$o10117.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$249067$lut$aiger$o8379.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$249067$lut$aiger249066$11601.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$249067$lut$aiger$o9555.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$249067$lut$aiger$o9557.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$249067$lut$aiger$o9557.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$249067$lut$aiger249066$11635.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$249067$lut$aiger249066$14726.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$249067$lut$aiger249066$15504.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$249067$lut$aiger$o8681.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$249067$lut$aiger249066$11695.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$249067$lut$aiger249066$11339.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$249067$lut$aiger249066$11701.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$249067$lut$aiger249066$13523.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$249067$lut$aiger$o9570.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$249067$lut$aiger$o9570.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$249067$lut$aiger249066$13538.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$249067$lut$aiger249066$11771.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$249067$lut$aiger$o8540.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$249067$lut$aiger249066$11781.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$249067$lut$aiger249066$13553.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$249067$lut$aiger249066$11809.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$249067$lut$aiger249066$17031.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$249067$lut$aiger249066$13582.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$249067$lut$aiger$o9308.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$249067$lut$aiger249066$11886.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$249067$lut$aiger$o8914.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$249067$lut$aiger$o8914.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249391.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$249067$lut$aiger$o8915.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$249067$lut$aiger$o8915.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$249067$lut$aiger$o8212.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$249067$lut$aiger249066$13666.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$249067$lut$aiger249066$11969.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$249067$lut$aiger249066$12005.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249687.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$249067$lut$aiger249066$12059.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$249067$lut$aiger249066$14939.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$249067$lut$aiger249066$12086.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$249067$lut$aiger249066$12118.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249495.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$249067$lut$aiger249066$16502.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$249067$lut$aiger$o8800.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$249067$lut$aiger249066$13838.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$249067$lut$aiger$o10886.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$249067$lut$aiger$o10886.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$249067$lut$aiger249066$12181.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$249067$lut$aiger249066$13854.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$249067$lut$aiger249066$14985.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$249067$lut$aiger249066$13863.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$249067$lut$aiger249066$12203.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$249067$lut$aiger249066$12218.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$249067$lut$aiger$o8297.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$249067$lut$aiger$o8297.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$249067$lut$aiger249066$12235.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$249067$lut$aiger249066$13892.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$249067$lut$aiger249066$13897.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249468.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$249067$lut$aiger249066$16529.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$249067$lut$aiger249066$12310.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$249067$lut$aiger$o10874.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$249067$lut$aiger$o10874.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$249067$lut$aiger249066$13958.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$249067$lut$aiger$o10873.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$249067$lut$aiger$o10873.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$249067$lut$aiger249066$12347.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$249067$lut$aiger249066$13974.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$249067$lut$aiger249066$12373.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$249067$lut$aiger249066$13992.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$249067$lut$aiger249066$15067.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$249067$lut$aiger$o11007.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$249067$lut$aiger$o11007.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$249067$lut$aiger249066$12403.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$249067$lut$aiger249066$14025.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$249067$lut$aiger249066$15090.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$249067$lut$aiger249066$12434.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$249067$lut$aiger249066$14032.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249325.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249325.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$249067$lut$aiger$o8014.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249332.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249332.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$249067$lut$aiger$o8022.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$249067$lut$aiger$o8022.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249340.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$249067$lut$aiger249066$12545.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249340.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$249067$lut$aiger$o9397.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$249067$lut$aiger249066$15138.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$249067$lut$aiger249066$12579.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249348.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249348.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$249067$lut$aiger249066$14113.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249355.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249355.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249361.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249361.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249369.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$249067$lut$aiger249066$17258.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249369.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$249067$lut$aiger249066$14104.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249374.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$249067$lut$aiger249066$14324.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249377.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$249067$lut$aiger249066$12664.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$249067$lut$aiger249066$14155.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$249067$lut$aiger249066$14166.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249456.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249388.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249388.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249389.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249391.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249392.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$249067$lut$aiger249066$14186.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249396.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249396.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249397.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$249067$lut$aiger249066$17438.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$249067$lut$aiger$o8739.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249417.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249417.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249418.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$249067$lut$aiger249066$14216.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249422.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249423.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$249067$lut$aiger249066$14227.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249428.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249428.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249429.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$249067$lut$aiger249066$15848.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249436.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249436.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$249067$lut$aiger249066$14253.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$249067$lut$aiger249066$12816.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249452.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249452.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$249067$lut$aiger$o10296.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$249067$lut$aiger$o10296.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$249067$lut$aiger$o10117.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249456.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249458.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249458.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$249067$lut$aiger249066$14287.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249462.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249463.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$249067$lut$aiger249066$12874.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249465.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249467.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249468.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249471.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$249067$lut$aiger$o10477.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$249067$lut$aiger$o10477.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249475.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$249067$lut$aiger$o10476.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$249067$lut$aiger$o10476.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249491.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249491.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$249067$lut$aiger249066$12952.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249499.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$249067$lut$aiger249066$15905.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$249067$lut$aiger249066$10853.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$249067$lut$aiger249066$10925.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$249067$lut$aiger249066$10864.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$249067$lut$aiger249066$10822.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249520.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249529.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249534.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$249067$lut$aiger249066$10761.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$249067$lut$aiger249066$10950.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$249067$lut$aiger249066$10681.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$249067$lut$aiger249066$10649.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$249067$lut$aiger249066$14795.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249577.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$249067$lut$aiger249066$10539.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249651.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249653.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$249067$lut$aiger249066$11006.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$249067$lut$aiger249066$11002.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$249067$lut$aiger249066$10977.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$249067$lut$aiger249066$10961.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249508.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$249067$lut$aiger249066$10914.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$249067$lut$aiger249066$10905.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$249067$lut$aiger249066$10884.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$249508.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) +Removed 0 unused cells and 8118 unused wires. + +19.49. Executing AUTONAME pass. +Renamed 15660 objects in module fpga_neural_v2_top. + + +19.50. Executing HIERARCHY pass (managing design hierarchy). +Attribute `top' found on module `fpga_neural_v2_top'. Setting top module to fpga_neural_v2_top. + +19.50.1. Analyzing design hierarchy.. +Top module: \fpga_neural_v2_top + +19.50.2. Analyzing design hierarchy.. +Top module: \fpga_neural_v2_top +Removed 0 unused modules. + +19.51. Printing statistics. + +=== fpga_neural_v2_top === + + +----------Local Count, excluding submodules. + | + 5416 wires + 31651 wire bits + 5416 public wires + 31651 public wire bits + 16 ports + 44 port bits + 76 cells + 16 $_TBUF_ + 27 $scopeinfo + 1 EHXPLLL + 32 MULT18X18D + 11655 submodules + 713 CCU2C + 6 L6MUX21 + 4074 LUT4 + 351 PFUMX + 189 TRELLIS_DPR16X4 + 6322 TRELLIS_FF + +=== design hierarchy === + + +----------Count including submodules. + | + 76 fpga_neural_v2_top + + +----------Count including submodules. + | + 5416 wires + 31651 wire bits + 5416 public wires + 31651 public wire bits + 16 ports + 44 port bits + - memories + - memory bits + - processes + 76 cells + 16 $_TBUF_ + 27 $scopeinfo + 1 EHXPLLL + 32 MULT18X18D + 11655 submodules + 713 CCU2C + 6 L6MUX21 + 4074 LUT4 + 351 PFUMX + 189 TRELLIS_DPR16X4 + 6322 TRELLIS_FF + +19.52. Executing CHECK pass (checking for obvious problems). +Checking module fpga_neural_v2_top... +Found and reported 0 problems. + +19.53. Executing JSON backend. + +Warnings: 38 unique messages, 43 total +End of script. Logfile hash: c230660eff, time: 7.19s, user: 6.42s, system: 0.15s, MEM: 362.62 MB peak +Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101) +Time spent: 18% 1x abc9_exe (1 sec), 11% 37x opt_clean (0 sec), ... diff --git a/hardware/v2/reports/step_final_timing.csv b/hardware/v2/reports/step_final_timing.csv new file mode 100644 index 0000000..c02bb49 --- /dev/null +++ b/hardware/v2/reports/step_final_timing.csv @@ -0,0 +1,9 @@ +seed,fmax_mhz,pass_at_64mhz,slack_ns_at_64mhz +1,73.17,PASS,1.958 +2,68.90,PASS,1.111 +3,72.10,PASS,1.755 +4,68.51,PASS,1.029 +5,69.29,PASS,1.193 +6,73.03,PASS,1.931 +7,74.17,PASS,2.143 +8,70.10,PASS,1.360