feat(v2): M2 Neural Processor Array, N_PROCESSORS resource sweep
Implements M2 of the V2 roadmap: neural_processor_array.v instantiates
N_PROCESSORS independent neural_processor (M1) units, each with its
own dedicated point-to-point job/operand/result interface -- no shared
bus or mux at this level (arbitration is explicitly the Neural
Director's job, M5).
Verified with Verilator (tb_neural_processor_array.v, N_PROCESSORS=4):
7/7 tests pass, including a same-cycle 4-way concurrent launch with
different tile counts and a staggered-start test where a
later-launched, shorter job completes before an earlier-launched,
longer one -- confirming genuine independent concurrent execution
(§18/§34: a blocked/busy processor must not block the others).
Real resource/timing sweep for N_PROCESSORS in {1,2,4,8} (Yosys +
nextpnr-ecp5, real place&route): Fmax stays above the 80MHz target
throughout (159.11 -> 134.70 MHz), but MULT18X18D usage scales
linearly and reaches 88% of the LFE5U-45F's 72 DSPs at N=8 while
LUT/FF stay under 6% -- DSP, not LUT/FF/routing, is the first hard
ceiling on N_PROCESSORS at P_IN=8 (decisions.log DEC-0005). Measured
via a dedicated synthesis-only timing harness after the array's wide
per-processor buses were found to exhaust the device's TRELLIS_IO pin
budget as a bare top-level module beyond N=1 (errors.log ERR-0005) --
not a logic limit, an artifact of testing the array in isolation
before the Memory Manager/Director (M4/M5) exist to consume those
ports on-chip.
Full log trail (development/experiments/errors/decisions/simulation/
synthesis/timing/benchmark.log) in hardware/v2/logs/ per the project's
logging mandate.
Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
This commit is contained in:
Claude Sonnet 5
@@ -18,3 +18,25 @@ stall %, effective MAC/s: not yet meaningful at this milestone (single
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isolated processor, no streaming benchmark harness yet -- deferred to
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M2 once neural_processor_array.v exists and a real workload can be
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timed end-to-end).
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[2026-09-05] M2 Neural Processor Array, N_PROCESSORS sweep (P_IN=8,
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ACC_WIDTH=32 each; synthesized via the timing harness, see errors.log
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ERR-0005 for why)
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| N_PROCESSORS | Fmax (POST-P&R) | LUT | FF | DSP (MULT18X18D) | DSP % of 72 |
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|--------------|------------------|-----|------|-------------------|-------------|
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| 1 | 159.11 MHz | 59 | 409 | 8 | 11% |
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| 2 | 149.59 MHz | 106 | 786 | 16 | 22% |
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| 4 | 151.01 MHz | 207 | 1540 | 32 | 44% |
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| 8 | 134.70 MHz | 374 | 3048 | 64 | 88% |
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All figures POST-P&R (real nextpnr-ecp5), all PASS at the 80MHz
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target. LUT4 utilization stays under 6% of the device even at N=8;
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DSP is the binding resource (see decisions.log DEC-0005), reaching 88%
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at N=8 -- N_PROCESSORS=9 would already exceed the LFE5U-45F's 72
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MULT18X18D budget at P_IN=8. Theoretical MAC/cycle (THEORETICAL, not
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yet measured end-to-end -- no real workload/benchmark harness exists
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until M9): N_PROCESSORS * P_IN MACs/cycle when all processors are
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simultaneously streaming tiles (8, 16, 32, 64 for N=1/2/4/8 -- verified
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achievable in principle by EXP-0003's concurrent/staggered simulation,
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not yet measured as a sustained throughput number).
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@@ -201,3 +201,50 @@ resolved by picking whichever answer looks more convenient.
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STATUS:
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ACCEPTED
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---
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DEC-0005
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DATE: 2026-09-05
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DECISION:
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Treat DSP (MULT18X18D) budget, not LUT/FF/routing, as the primary
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constraint when exploring the N_PROCESSORS x P_IN trade-off space
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(§16) going forward.
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WHY:
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Real place&route measurement (EXP-0003) shows MULT18X18D usage
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scaling linearly and reaching 88% of the LFE5U-45F-8BG381's 72 total
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DSPs at N_PROCESSORS=8, P_IN=8 -- while LUT4/FF usage stays under 6%
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at the SAME configuration and Fmax is still comfortably above the
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80MHz target (134.70 MHz). This means the naive "just add more
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processors" scaling (§8/§16) hits a hard DSP ceiling around
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N_PROCESSORS=9 at P_IN=8, long before LUT/FF/routing/timing become
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relevant -- the opposite of what LUT/FF utilization alone would
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suggest if read in isolation.
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EVIDENCE:
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experiments.log EXP-0003 -- MULT18X18D 8/16/32/64 (11%/22%/44%/88% of
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72) at N_PROCESSORS 1/2/4/8, LUT4 under 6% throughout, Fmax PASS at
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80MHz throughout (159.11/149.59/151.01/134.70 MHz).
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ALTERNATIVES:
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Assume LUT/FF/routing congestion would be the limiting factor (the
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naive expectation for "more parallel copies of a datapath"). Rejected
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by direct measurement, not assumed -- §16 explicitly requires
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choosing the final configuration "sulla base del throughput effettivo
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... non dell'utilizzo massimo delle risorse", and knowing WHICH
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resource binds first is a prerequisite for that.
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RESULT:
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Future N_PROCESSORS x P_IN sweeps (§16, deferred to a dedicated
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scripts/sweep/ run per §31) should budget MULT18X18D count explicitly
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(N_PROCESSORS * P_IN <= ~72, minus whatever the rest of the real
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system needs once M4/PSRAM integration lands) rather than only
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tracking LUT/FF. A smaller P_IN with more N_PROCESSORS (or vice versa)
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is a live trade-off worth exploring precisely because of this ceiling,
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not merely a stylistic choice.
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STATUS:
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ACCEPTED
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@@ -59,3 +59,32 @@ errors: vedi errors.log ERR-0001, ERR-0002, ERR-0003, ERR-0004.
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decision: vedi decisions.log DEC-0002, DEC-0003, DEC-0004.
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next_action: M2 -- neural_processor_array.v, sweep N_PROCESSORS
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(1,2,4,8), misura timing/risorse/throughput/utilization reali.
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[2026-09-05T14:30:00Z] commit=dc0b331 session=v2-M2-processor-array
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module: hardware/v2/rtl/neural_processor_array.v + hardware/v2/sim/
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tb_neural_processor_array.v + hardware/v2/synthesis/
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harness_neural_processor_array.v
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action: implementato M2 -- Neural Processor Array, N_PROCESSORS
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parametrico, ogni processore con interfaccia job/operand/result
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dedicata (nessun bus condiviso/mux a questo livello, §7). Testato
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N_PROCESSORS=4 con esecuzione concorrente reale (lancio simultaneo
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di 4 job diversi, più un test a partenza sfalsata) e con lo sweep
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reale N_PROCESSORS={1,2,4,8} per sintesi/place&route.
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reason: roadmap M2.
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result: 7/7 test PASS (Verilator), confermata esecuzione concorrente e
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indipendente (un job più corto lanciato dopo completa prima di uno
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più lungo lanciato prima -- non c'e' serializzazione nascosta).
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Sintesi/P&R reali per N=1/2/4/8: 0 problemi CHECK, scaling lineare
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delle risorse, Fmax sempre PASS a 80MHz (159.11/149.59/151.01/134.70
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MHz). Scoperta reale non assunta: il DSP (MULT18X18D) e' la prima
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risorsa a saturare (88% a N=8), non LUT/FF (sotto il 6% anche a
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N=8) -- vedi decisions.log DEC-0005.
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errors: ERR-0005 (artefatto di sintesi da pin-count, non un bug RTL --
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workaround con un harness dedicato, vedi errors.log). Un primo
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tentativo di harness alimentava dati identici a ogni processore/lane
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MAC, e Yosys deduplicava silenziosamente tutto a 1x indipendentemente
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da N -- scoperto verificando che lo scaling fosse davvero lineare
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prima di fidarsi dei numeri.
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decision: vedi decisions.log DEC-0005.
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next_action: M3 -- activation_buffer.v / weight_buffer.v /
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result_buffer.v (profondita' parametrica, valutare BRAM mapping).
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@@ -98,3 +98,29 @@ NOTE: this session's V1 certification campaign (docs/validation/,
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this V2-kickoff session (V1 is frozen, not to be touched) and was
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not performed. See decisions.log DEC-0004.
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STATUS: OPEN CAVEAT, not actioned in this session by design.
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ERR-0005 (synthesis measurement artifact, WORKED AROUND, not an RTL bug)
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DATE: 2026-09-05
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MODULE: hardware/v2/rtl/neural_processor_array.v
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SYMPTOM: synthesizing neural_processor_array as a bare top-level
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module (every per-processor job/operand/result field exposed as a
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real TRELLIS_IO pin) works at N_PROCESSORS=1 but fails place&route
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at N_PROCESSORS=2 with "Unable to place cell ...$tr_io, no BELs
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remaining to implement cell type 'TRELLIS_IO'".
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ROOT CAUSE: not a logic/timing limit -- the LFE5U-45F-8BG381 package
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has 245 TRELLIS_IO pins total; the array's wide per-processor buses
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(input_data/weight_data alone are DATA_WIDTH*P_IN*N_PROCESSORS bits)
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exceed that budget once N_PROCESSORS>=2, purely because these ports
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have no on-chip consumer yet (the Memory Manager/M4 and Neural
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Director/M5 that will drive them in the real system don't exist
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yet).
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WORKAROUND: hardware/v2/synthesis/harness_neural_processor_array.v --
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a synthesis-only wrapper (NOT part of rtl/, not a functional
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deliverable) that drives all wide buses from an internal free-
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running LFSR and reduces outputs to a small checksum, keeping only
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clk/rst/seed/checksum as real top-level pins. See its own header
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comment and experiments.log EXP-0003 for the resulting real
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resource/Fmax numbers.
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STATUS: WORKED AROUND. Will become moot once M4/M5 exist and the array
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is synthesized as part of a larger design with on-chip ports instead
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of a bare top-level module.
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@@ -98,3 +98,64 @@ decision: ACC_WIDTH=32 remains the M1 default (matches V1 exactly for
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comparison run).
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next_action: revisit ACC_WIDTH choice during M10 (Optimization) with a
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real seed sweep, not before.
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EXP-0003
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timestamp: 2026-09-05T14:30:00Z
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git_commit: dc0b331 (+ uncommitted M2 work)
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session: v2-M2-processor-array
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module: hardware/v2/rtl/neural_processor_array.v
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configuration: N_PROCESSORS in {1,2,4,8}, P_IN=8, ACC_WIDTH=32 each
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action: M2 -- functional array + real N_PROCESSORS resource/timing sweep
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command (sim, Verilator): verilator --binary --timing -j 0 -Wno-fatal
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--top-module tb -o /tmp/vtb_array hardware/v2/rtl/neural_processor.v
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hardware/v2/rtl/neural_processor_array.v
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hardware/v2/sim/tb_neural_processor_array.v && /tmp/vtb_array
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command (synth/timing): see hardware/v2/synthesis/harness_n{1,2,4,8}/
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(yosys.log, nextpnr.log) -- synthesized via
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hardware/v2/synthesis/harness_neural_processor_array.v, a
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synthesis-only timing harness (see its own header comment and
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errors.log ERR-0005 for why the array cannot be synthesized as a
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bare top-level module beyond N_PROCESSORS=1 without it).
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result:
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SIMULATED (N_PROCESSORS=4, tb_neural_processor_array.v): 7/7 tests
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PASS -- single-processor sanity, 4 processors launched the SAME
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cycle with different tile counts (finish at different times,
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proving true concurrency), and a staggered-start test (processor 1
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launched mid-way through processor 0's 6-tile job, both complete
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correctly and independently, confirming §18/§34's "un processor
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bloccato non deve bloccare gli altri").
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SYNTHESIZED (resource scaling, harness): perfectly linear in
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N_PROCESSORS, confirming no unintended resource sharing:
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N=1: LUT=59 FF=409 MULT18X18D=8 CCU2C=96
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N=2: LUT=106 FF=786 MULT18X18D=16 CCU2C=192
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N=4: LUT=207 FF=1540 MULT18X18D=32 CCU2C=384
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N=8: LUT=374 FF=3048 MULT18X18D=64 CCU2C=768
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0 CHECK problems in every configuration.
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POST-P&R (real nextpnr-ecp5, --45k --package CABGA381 --speed 8
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--freq 80): Fmax PASS at 80MHz in every configuration:
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N=1: 159.11 MHz N=2: 149.59 MHz
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N=4: 151.01 MHz N=8: 134.70 MHz
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Fmax decreases gently with N (routing congestion), never close to
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failing the 80MHz target up to N=8.
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REAL RESOURCE CEILING FOUND (not assumed, measured via nextpnr's own
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device utilisation report): MULT18X18D usage is 22%/44%/88% of the
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LFE5U-45F's 72 total DSPs at N=2/4/8 respectively, while LUT4/FF
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usage stays under 6% even at N=8. **DSP (not LUT/FF/routing) is
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the first hard ceiling as N_PROCESSORS grows at P_IN=8** --
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N_PROCESSORS=9 would already exceed the device's 72 MULT18X18D
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budget at P_IN=8, before accounting for any multipliers the rest
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of a real system (Memory Manager, PSRAM path, etc.) might need.
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See decisions.log DEC-0005 and benchmark.log.
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errors: ERR-0005 (toplevel-pin-count synthesis artifact, worked around
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with the timing harness -- see errors.log); a first harness attempt
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fed every processor and every MAC lane identical LFSR-derived data,
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which Yosys correctly (from pure logic-equivalence) collapsed via
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CSE down to 1 processor's worth of multipliers regardless of N --
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fixed by giving each processor AND each of its P_IN MAC lanes a
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distinct bit-rotated data source, confirmed by the corrected,
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properly-linear MULT18X18D counts above.
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decision: see decisions.log DEC-0005 (DSP is the binding constraint,
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not LUT/FF -- informs how the N_PROCESSORS x P_IN trade-off should
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be explored going forward).
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next_action: M3 -- activation_buffer.v / weight_buffer.v /
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result_buffer.v.
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@@ -15,3 +15,16 @@ PASS/FAIL: 7/7 PASS (ACC_WIDTH=32); 7/7 PASS (ACC_WIDTH=24, EXP-0002)
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bit-exact result: V1.y === V2.result_data for every case, both widths
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stall cycles / memory wait / utilization: N/A (no Memory Manager yet,
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M1 operands fed directly by testbench per the roadmap)
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[2026-09-05] EXP-0003 -- hardware/v2/sim/tb_neural_processor_array.v
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(N_PROCESSORS=4)
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test: 7 cases (single-processor sanity; 4-way same-cycle concurrent
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launch with different tile counts; staggered-start 2-processor test)
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simulator: Verilator 5.050 (--binary --timing)
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PASS/FAIL: 7/7 PASS
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bit-exact result: N/A at this milestone (hand-computed expected
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values, arithmetic itself already bit-exact-certified vs V1 at M1)
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concurrency: confirmed genuine -- in the staggered test, the
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later-launched, shorter job (processor 1) completes BEFORE the
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earlier-launched, longer job (processor 0), proving independent
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progress rather than serialization.
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@@ -14,3 +14,16 @@ CHECK: 0 problems. 36 warnings, all "multiple conflicting drivers for
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LUT: 49 FF: 509 DSP(MULT18X18D): 8 BRAM: 0 CCU2C: 88
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CHECK: 0 problems, same 36 benign warnings as EXP-0001.
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Log: hardware/v2/synthesis/neural_processor_p8_acc24/yosys.log
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[2026-09-05] EXP-0003 -- neural_processor_array via
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harness_neural_processor_array.v (synthesis-only wrapper, see
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errors.log ERR-0005), N_PROCESSORS in {1,2,4,8}, P_IN=8
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N=1: LUT=59 FF=409 MULT18X18D=8 CCU2C=96
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N=2: LUT=106 FF=786 MULT18X18D=16 CCU2C=192
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N=4: LUT=207 FF=1540 MULT18X18D=32 CCU2C=384
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N=8: LUT=374 FF=3048 MULT18X18D=64 CCU2C=768
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CHECK: 0 problems in all 4 configurations. Perfectly linear scaling in
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N confirms no unintended cross-processor resource sharing (a first,
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flawed harness attempt fed identical data to every processor/lane
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and Yosys silently deduplicated down to 1x regardless of N -- caught
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by checking for exactly this linearity before trusting the numbers).
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@@ -20,3 +20,14 @@ Delta vs ACC_WIDTH=32: -6.91 MHz (-3.8%) despite FEWER resources --
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(no seed sweep run to confirm either way -- see experiments.log
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EXP-0002 and benchmark.log). Log: hardware/v2/synthesis/
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neural_processor_p8_acc24/nextpnr.log
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[2026-09-05] EXP-0003 -- N_PROCESSORS sweep (P_IN=8), real nextpnr-ecp5
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--45k --package CABGA381 --speed 8 --freq 80 --lpf-allow-unconstrained
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N=1: Fmax=159.11 MHz PASS MULT18X18D 8/72 (11%)
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N=2: Fmax=149.59 MHz PASS MULT18X18D 16/72 (22%)
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N=4: Fmax=151.01 MHz PASS MULT18X18D 32/72 (44%)
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N=8: Fmax=134.70 MHz PASS MULT18X18D 64/72 (88%)
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TRELLIS_IO stays at 18/245 (7%) throughout (harness has only
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clk/rst/seed/checksum as real pins, by design -- see ERR-0005).
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See decisions.log DEC-0005: DSP, not Fmax or LUT/FF, is the resource
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that will first prevent scaling N_PROCESSORS further at P_IN=8.
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