michele

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• Joined on 2026-09-15

Repositories

7

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michele pushed to v3-artix7 at michele/FPGA-Neural 2026-09-20 20:54:55 +00:00

932aec2490 feat: real first step of 4x4 hybrid systolic architecture (EXP-0089)

michele pushed to v3-artix7 at michele/FPGA-Neural 2026-09-20 17:27:02 +00:00

7f9ece12dc docs: real P&R signoff for the result-writeback engine (EXP-0088)

michele pushed to v3-artix7 at michele/FPGA-Neural 2026-09-20 17:19:03 +00:00

ccaf3ee059 feat: real result-writeback engine, removes the last hard N-scaling pin blocker (EXP-0088)

michele pushed to v3-artix7 at michele/FPGA-Neural 2026-09-20 16:37:47 +00:00

344e798ad5 feat: real DDRManager re-measurement at 32-bit channel + BOM/pinout docs (EXP-0087)

michele pushed to v3-artix7 at michele/FPGA-Neural 2026-09-20 16:05:35 +00:00

678caa9bce docs: real timing closure for 32-bit DDR3 channel (EXP-0086)

michele pushed to v3-artix7 at michele/FPGA-Neural 2026-09-20 14:33:48 +00:00

bdc821222f feat: real active-low data_ready_n sticky IRQ pin (EXP-0085)

michele pushed to v3-artix7 at michele/FPGA-Neural 2026-09-20 14:28:50 +00:00

9dead54ebf feat: real 32-bit DDR3 channel widening - functionally complete, timing NOT yet closed (EXP-0084)

michele pushed to v3-artix7 at michele/FPGA-Neural 2026-09-20 11:22:19 +00:00

376ccb6ee2 docs: capture two more exploratory scaling directions (BRAM cache, ESP32-side scheduling)

michele pushed to v3-artix7 at michele/FPGA-Neural 2026-09-20 11:18:50 +00:00

32d32f4c0e docs: capture exploratory 4x4 hybrid systolic scaling direction (not built)

michele pushed to v3-artix7 at michele/FPGA-Neural 2026-09-20 08:59:48 +00:00

fa327b75ca feat: DDRManager phase 1 - single-slot look-ahead activation prefetch (EXP-0083)

michele pushed to v3-artix7 at michele/FPGA-Neural 2026-09-20 08:07:19 +00:00

cbd16dd727 docs: sync physical/architecture docs with EXP-0081/0082 reality, add 32-bit vs dual-channel analysis

michele pushed to v3-artix7 at michele/FPGA-Neural 2026-09-20 08:02:02 +00:00

e6768623d6 docs: confirm denser activation packing is real-timing-safe, margin improved (EXP-0082)

michele pushed to v3-artix7 at michele/FPGA-Neural 2026-09-20 07:55:19 +00:00

8ad04987de feat: denser activation packing, real bandwidth ceiling doubled (EXP-0081)

michele pushed to v3-artix7 at michele/FPGA-Neural 2026-09-20 07:44:11 +00:00

27cf5f36da docs: complete architecture analysis - DDR3 bandwidth is the real ceiling, not DSP count (EXP-0080)

michele pushed to v3-artix7 at michele/FPGA-Neural 2026-09-20 06:13:18 +00:00

43a12379a5 feat: MILESTONE - real activation-fetch engine, full N=2 system verified on real DDR3 (EXP-0079)

michele pushed to v3-artix7 at michele/FPGA-Neural 2026-09-20 05:24:36 +00:00

78577dde59 docs: log real Vivado stale-source bug + final flash-bridge P&R signoff (EXP-0078)

michele pushed to v3-artix7 at michele/FPGA-Neural 2026-09-19 19:45:19 +00:00

a4c080da83 feat: config-flash passthrough bridge via STARTUPE2, real board-exclusive flash access (EXP-0077)

michele pushed to v3-artix7 at michele/FPGA-Neural 2026-09-19 17:22:35 +00:00

fd6cc7a2fa docs: log final re-verified real P&R signoff after SPI fix + reg file (EXP-0076)

michele pushed to v3-artix7 at michele/FPGA-Neural 2026-09-19 16:31:55 +00:00

ca17765fe3 fix: real SPI MISO bit-corruption bug found+fixed; add register file + pin plan (EXP-0075)

michele pushed to v3-artix7 at michele/FPGA-Neural 2026-09-19 15:47:43 +00:00

835ae881dc feat: MILESTONE - first real in-context P&R, timing closes at 310MHz DDR3 (EXP-0074)