michele
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  • Joined on 2026-09-15
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michele pushed to n16-timing-closure at michele/FPGA-Neural 2026-09-21 22:17:25 +00:00
f9b366d747 feat: N=16 real timing CLOSED via extra MAC pipeline stage (EXP-0097, branch n16-timing-closure)
michele created branch n16-timing-closure in michele/FPGA-Neural 2026-09-21 22:17:24 +00:00
michele pushed to cursor/pcb-hf-analisi-675d at michele/periscope 2026-09-21 18:49:26 +00:00
20733f0ec6 Add remaining PCB analysis checks to run_pcb_checks (2.62.1).
michele pushed to cursor/pcb-hf-analisi-675d at michele/periscope 2026-09-21 18:43:07 +00:00
69d5dd9313 Add HF line and bus analysis to run_pcb_checks (2.62.0).
michele created branch cursor/pcb-hf-analisi-675d in michele/periscope 2026-09-21 18:43:07 +00:00
michele pushed to cursor/readme-rewrite-f758 at michele/periscope 2026-09-21 15:56:40 +00:00
309644e654 Rewrite README as Periscope PCB-analysis product copy.
michele created branch cursor/readme-rewrite-f758 in michele/periscope 2026-09-21 15:56:40 +00:00
michele pushed to cursor/interface-class-certifiers-72b2 at michele/periscope 2026-09-21 15:31:47 +00:00
michele created branch cursor/interface-class-certifiers-72b2 in michele/periscope 2026-09-21 15:31:46 +00:00
michele pushed to v3-artix7 at michele/FPGA-Neural 2026-09-21 06:57:17 +00:00
4c59b7e7c8 docs: add preliminary datasheet for FPGA-Neural N8 (semiconductor-style)
michele pushed to v3-artix7 at michele/FPGA-Neural 2026-09-21 06:54:28 +00:00
fc0130e2e2 docs: LaTeX chapters for hardware, chip architecture, and tests/timing
michele pushed to v3-artix7 at michele/FPGA-Neural 2026-09-21 06:29:06 +00:00
264950923b feat: N=8 hybrid systolic promoted to the real, definitive deployment target (EXP-0096)
michele pushed to v3-artix7 at michele/FPGA-Neural 2026-09-21 05:56:23 +00:00
6d06404428 feat: real N=4/N=8 timing curve -- N=8 REALLY CLOSES (0 failing endpoints, EXP-0095)
michele pushed to v3-artix7 at michele/FPGA-Neural 2026-09-21 00:39:48 +00:00
67ccb420d6 docs: real P&R directive tuning closes most of remaining N=16 timing gap (EXP-0094 cont.)
michele pushed to v3-artix7 at michele/FPGA-Neural 2026-09-21 00:25:47 +00:00
9e1f16db47 feat: real hierarchical 2-level arbiter, real N=16 timing WNS -0.913ns -> -0.646ns (EXP-0094)
michele pushed to v3-artix7 at michele/FPGA-Neural 2026-09-20 22:41:21 +00:00
50c940a41d docs: real, full P&R for N=16 hybrid systolic system -- timing NOT met (EXP-0093)
michele pushed to v3-artix7 at michele/FPGA-Neural 2026-09-20 22:31:08 +00:00
996dda3415 feat: real functional xsim verification of N=16 hybrid systolic system (EXP-0092)
michele pushed to v3-artix7 at michele/FPGA-Neural 2026-09-20 22:12:14 +00:00
4acc669d43 feat: real N=16 hybrid systolic top-level, synthesis-only pass (EXP-0091)
michele pushed to v3-artix7 at michele/FPGA-Neural 2026-09-20 22:05:19 +00:00
bd1fb5dc14 feat: real Director extension for group dispatch + systolic_group.v P&R sanity check (EXP-0090)
michele pushed to v3-artix7 at michele/FPGA-Neural 2026-09-20 20:54:55 +00:00
932aec2490 feat: real first step of 4x4 hybrid systolic architecture (EXP-0089)