michele
4df04df5d4
Add /api/library datasheet import and component GET/PUT with no exam. Reorganize pytest into datasheet, library, schematic, PCB, and AF+AI. Document Rust criteria (none chosen; no rustup) and coding conformity.
399 lines
15 KiB
Python
399 lines
15 KiB
Python
"""Phase A: HF pair integrity + CPU/FPGA/DDR class — only if present.
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Via ≠ pad ≠ track ≠ zone. No invented Z/I/mm. Skip when evidence is missing.
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"""
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from __future__ import annotations
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from backend.periscopex.finding_engine import complete_finding, lookup_rule
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from backend.periscopex.hf_bus_class import check_memory_fpga_classes
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from backend.periscopex.hf_line_check import check_hf_lines
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from backend.periscopex.models import (
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Component,
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ComponentConstraints,
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ComponentType,
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DesignGraph,
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LayoutDielectric,
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LayoutFootprint,
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LayoutGraph,
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LayoutPad,
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LayoutSegment,
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LayoutStackup,
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LayoutVia,
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LayoutZone,
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Net,
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NetType,
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Pin,
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PinConnection,
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ResistorSpecs,
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)
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from backend.periscopex.pcb_checks import run_pcb_checks
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from backend.periscopex.si_check import bus_class, check_si, skip_si_net
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def _ic(ref: str, pins: dict[str, str], *, mpn: str = "PHY", subtype: str | None = None) -> Component:
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return Component(
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reference=ref, value=mpn, footprint="",
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component_type=ComponentType.IC, mpn=mpn,
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component_subtype=subtype, pins=pins,
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)
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def _net(name: str, *pairs: tuple[str, str], ntype: NetType = NetType.SIGNAL) -> Net:
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return Net(
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name=name, net_type=ntype,
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pins=[PinConnection(component_ref=r, pin_number=p) for r, p in pairs],
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)
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def _usb_graph() -> DesignGraph:
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return DesignGraph(
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components={
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"U1": _ic("U1", {"1": "USB_D+", "2": "USB_D-"}),
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"J2": Component(
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reference="J2", value="USB_C", footprint="",
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component_type=ComponentType.CONNECTOR, pins={"A6": "USB_D+", "A7": "USB_D-"},
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),
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},
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nets={
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"USB_D+": _net("USB_D+", ("U1", "1"), ("J2", "A6")),
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"USB_D-": _net("USB_D-", ("U1", "2"), ("J2", "A7")),
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},
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)
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def _fp_with_pads(ref: str, pads: list[LayoutPad], x: float = 0.0, y: float = 0.0) -> LayoutFootprint:
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return LayoutFootprint(reference=ref, footprint="P", x=x, y=y, pads=pads)
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def test_bus_class_mipi_hf_clk_not_xtal():
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assert bus_class("MIPI_D0_P") == "mipi"
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assert bus_class("CSI_CLK_N") == "mipi"
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assert bus_class("DSI_D1_P") == "mipi"
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assert bus_class("GTX_CLK") == "hf_clk"
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assert bus_class("PCIE_REFCLK") == "pcie"
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assert bus_class("CLK_P") == "hf_clk"
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assert bus_class("XTAL_IN") is None
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assert bus_class("OSCIN") is None
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assert bus_class("HFXIN") is None
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assert skip_si_net("USB_CC1")
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assert bus_class("USB_D+") == "usb2"
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def test_no_layout_skips_hf_geometry():
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assert check_hf_lines(_usb_graph(), {}, None) == []
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assert check_hf_lines(_usb_graph(), {}, LayoutGraph()) == []
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def test_pad_to_pad_usb_has_no_stub():
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layout = LayoutGraph(
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footprints={
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"U1": _fp_with_pads("U1", [
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LayoutPad(number="1", x=0.0, y=0.0, net="USB_D+"),
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LayoutPad(number="2", x=0.0, y=0.4, net="USB_D-"),
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]),
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"J2": _fp_with_pads("J2", [
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LayoutPad(number="A6", x=10.0, y=0.0, net="USB_D+"),
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LayoutPad(number="A7", x=10.0, y=0.4, net="USB_D-"),
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], x=10.0),
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},
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segments=[
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LayoutSegment(start=(0, 0), end=(10, 0), width=0.2, layer="F.Cu", net="USB_D+"),
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LayoutSegment(start=(0, 0.4), end=(10, 0.4), width=0.2, layer="F.Cu", net="USB_D-"),
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],
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)
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findings = check_hf_lines(_usb_graph(), {}, layout)
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assert [f for f in findings if f.rule_id == "PE-SI-007"] == []
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def test_via_is_not_a_stub():
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layout = LayoutGraph(
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footprints={
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"U1": _fp_with_pads("U1", [LayoutPad(number="1", x=0.0, y=0.0, net="USB_D+")]),
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"J2": _fp_with_pads("J2", [LayoutPad(number="A6", x=10.0, y=0.0, net="USB_D+")], x=10.0),
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},
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segments=[
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LayoutSegment(start=(0, 0), end=(5, 0), width=0.2, layer="F.Cu", net="USB_D+"),
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LayoutSegment(start=(5, 0), end=(10, 0), width=0.2, layer="B.Cu", net="USB_D+"),
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],
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vias=[LayoutVia(x=5.0, y=0.0, net="USB_D+", drill=0.3)],
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)
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findings = check_hf_lines(_usb_graph(), {}, layout)
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assert [f for f in findings if f.rule_id == "PE-SI-007"] == []
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assert all(not isinstance(v, LayoutPad) for v in layout.vias)
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def test_zone_is_not_a_track_stub():
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layout = LayoutGraph(
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footprints={
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"U1": _fp_with_pads("U1", [LayoutPad(number="1", x=0.0, y=0.0, net="USB_D+")]),
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},
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segments=[
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LayoutSegment(start=(0, 0), end=(4, 0), width=0.2, layer="F.Cu", net="USB_D+"),
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],
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zones=[LayoutZone(
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net="USB_D+", layer="F.Cu",
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outlines=[[(3.5, -1.0), (8.0, -1.0), (8.0, 1.0), (3.5, 1.0)]],
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)],
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)
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findings = check_hf_lines(_usb_graph(), {}, layout)
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assert [f for f in findings if f.rule_id == "PE-SI-007"] == []
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def test_dangling_track_stub_vs_datasheet_mm_is_fail():
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layout = LayoutGraph(
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footprints={
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"U1": _fp_with_pads("U1", [LayoutPad(number="1", x=0.0, y=0.0, net="USB_D+")]),
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"J2": _fp_with_pads("J2", [LayoutPad(number="A6", x=10.0, y=0.0, net="USB_D+")], x=10.0),
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},
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segments=[
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LayoutSegment(start=(0, 0), end=(10, 0), width=0.2, layer="F.Cu", net="USB_D+"),
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LayoutSegment(start=(10, 0), end=(10, 3), width=0.2, layer="F.Cu", net="USB_D+"),
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],
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)
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cons = ComponentConstraints(
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mpn="PHY", pintable=[Pin(number="1", name="D+")],
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absolute_maximum_ratings=[], rules=[],
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layout_rules=[{
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"kind": "stub", "net_class": "usb2", "max_distance_mm": 1.0,
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"note": "USB stub < 1 mm", "source_page": 12,
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}],
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)
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findings = check_hf_lines(_usb_graph(), {"PHY": cons}, layout)
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stubs = [f for f in findings if f.rule_id == "PE-SI-007"]
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assert len(stubs) == 1
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assert stubs[0].finding.startswith("FAIL:")
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assert stubs[0].facts.startswith("stub_mm=")
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assert "1" in stubs[0].requirement
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complete_finding(stubs[0])
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assert stubs[0].status == "WARNING"
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assert stubs[0].finding_class != "RULE" or stubs[0].provenance != "MANDATORY"
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assert stubs[0].evidence_status == "SUFFICIENT"
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def test_measured_stub_without_datasheet_mm_is_insufficient():
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layout = LayoutGraph(
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footprints={
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"U1": _fp_with_pads("U1", [LayoutPad(number="1", x=0.0, y=0.0, net="USB_D+")]),
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"J2": _fp_with_pads("J2", [LayoutPad(number="A6", x=10.0, y=0.0, net="USB_D+")], x=10.0),
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},
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segments=[
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LayoutSegment(start=(0, 0), end=(10, 0), width=0.2, layer="F.Cu", net="USB_D+"),
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LayoutSegment(start=(5, 0), end=(5, 4), width=0.2, layer="F.Cu", net="USB_D+"),
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],
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)
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findings = check_hf_lines(_usb_graph(), {}, layout)
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stubs = [f for f in findings if f.rule_id == "PE-SI-007"]
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assert len(stubs) == 1
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assert stubs[0].status == "INFO"
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assert stubs[0].evidence_status == "INSUFFICIENT"
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assert "90" not in (stubs[0].requirement or "")
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assert "FAIL" not in stubs[0].finding
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def test_split_under_pair_needs_stackup_and_zone():
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segs = [
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LayoutSegment(start=(0, 0), end=(20, 0), width=0.2, layer="F.Cu", net="USB_D+"),
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]
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bare = LayoutGraph(segments=segs)
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assert [f for f in check_hf_lines(_usb_graph(), {}, bare) if f.rule_id == "PE-SI-011"] == []
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stack = LayoutStackup(
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copper_layers=["F.Cu", "B.Cu"],
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dielectrics=[LayoutDielectric(name="dielectric_1", er=4.5, height_mm=0.2)],
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copper_thickness_mm=0.035,
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)
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no_zone = LayoutGraph(segments=segs, stackup=stack)
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assert [f for f in check_hf_lines(_usb_graph(), {}, no_zone) if f.rule_id == "PE-SI-011"] == []
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covered = LayoutGraph(
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segments=segs, stackup=stack,
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zones=[LayoutZone(
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net="GND", layer="B.Cu",
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outlines=[[(-1, -2), (21, -2), (21, 2), (-1, 2)]],
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)],
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)
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assert [f for f in check_hf_lines(_usb_graph(), {}, covered) if f.rule_id == "PE-SI-011"] == []
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split = LayoutGraph(
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segments=segs, stackup=stack,
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zones=[LayoutZone(
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net="GND", layer="B.Cu",
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outlines=[[(0, -2), (5, -2), (5, 2), (0, 2)]],
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)],
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)
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hits = [f for f in check_hf_lines(_usb_graph(), {}, split) if f.rule_id == "PE-SI-011"]
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assert len(hits) == 1
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assert hits[0].status == "WARNING"
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assert hits[0].finding_class == "REVIEW"
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assert hits[0].facts
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assert hits[0].requirement
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assert hits[0].inference
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complete_finding(hits[0])
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assert hits[0].status != "ERROR"
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def test_bom_termination_is_fact_missing_is_skip():
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layout = LayoutGraph(
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segments=[
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LayoutSegment(start=(0, 0), end=(10, 0), width=0.2, layer="F.Cu", net="USB_D+"),
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],
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)
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g = _usb_graph()
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assert [f for f in check_hf_lines(g, {}, layout) if f.rule_id == "PE-SI-012"] == []
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g.components["R22"] = Component(
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reference="R22", value="22R", footprint="",
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component_type=ComponentType.RESISTOR,
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pins={"1": "USB_D+", "2": "USB_D+_PHY"},
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specs=ResistorSpecs(value_ohms=22.0, value_formatted="22"),
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)
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g.nets["USB_D+_PHY"] = _net("USB_D+_PHY", ("R22", "2"))
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g.nets["USB_D+"].pins.append(PinConnection(component_ref="R22", pin_number="1"))
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found = [f for f in check_hf_lines(g, {}, layout) if f.rule_id == "PE-SI-012"]
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assert len(found) == 1
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assert found[0].status == "INFO"
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assert found[0].evidence_status == "SUFFICIENT"
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assert "R22" in found[0].facts
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assert "22" in found[0].facts
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assert "50 Ω" not in found[0].requirement
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def test_no_ddr_cpu_fpga_on_usb_only_graph():
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findings = check_memory_fpga_classes(_usb_graph())
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assert findings == []
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ids = {f.rule_id for f in run_pcb_checks(_usb_graph(), {}, None)}
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assert not any(str(i).startswith(("PE-DDR", "PE-CPU", "PE-FPGA")) for i in ids)
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def test_ddr_present_class_and_nets_skip_invented_vtt():
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pins = {str(i + 1): f"DDR3_DQ{i}" for i in range(8)}
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pins["20"] = "DDR3_DQS0_P"
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pins["21"] = "DDR3_DQS0_N"
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pins["22"] = "DDR3_CK_P"
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pins["23"] = "DDR3_CK_N"
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pins["24"] = "DDR3_A0"
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comps = {"U10": _ic("U10", pins, mpn="MT41K256M16TW", subtype="ic.memory.ddr")}
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nets = {n: _net(n, ("U10", p)) for p, n in pins.items()}
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g = DesignGraph(components=comps, nets=nets)
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findings = check_memory_fpga_classes(g)
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for f in findings:
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complete_finding(f)
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assert [f.rule_id for f in findings if f.rule_id == "PE-DDR-001"]
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assert [f for f in findings if f.rule_id == "PE-DDR-001"][0].status == "INFO"
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assert [f for f in findings if f.rule_id == "PE-DDR-002"][0].status == "INFO"
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assert not any(f.rule_id == "PE-DDR-003" for f in findings)
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assert not any((f.rule_id or "").startswith("PE-CPU") for f in findings)
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assert not any((f.rule_id or "").startswith("PE-FPGA") for f in findings)
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g.nets["DDR_VTT"] = _net("DDR_VTT", ("U10", "30"), ntype=NetType.POWER)
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g.components["U10"].pins["30"] = "DDR_VTT"
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with_vtt = check_memory_fpga_classes(g)
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assert [f for f in with_vtt if f.rule_id == "PE-DDR-003"][0].status == "INFO"
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def test_cpu_parallel_bus_only_when_data_addr_control_exist():
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mcu_pins = {str(i + 1): f"MCU_D{i}" for i in range(8)}
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for i in range(8):
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mcu_pins[str(20 + i)] = f"MCU_A{i}"
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mcu_pins["40"] = "MCU_NWE"
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mcu_pins["41"] = "MCU_NOE"
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mcu_pins["42"] = "MCU_NCS"
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sram_pins = dict(mcu_pins)
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comps = {
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"U1": _ic("U1", mcu_pins, mpn="STM32F407", subtype="ic.mcu"),
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"U2": _ic("U2", sram_pins, mpn="IS61WV51216", subtype="ic.memory.sram"),
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}
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nets = {}
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for p, n in mcu_pins.items():
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nets[n] = _net(n, ("U1", p), ("U2", p))
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g = DesignGraph(components=comps, nets=nets)
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findings = check_memory_fpga_classes(g)
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ids = {f.rule_id for f in findings}
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assert "PE-CPU-001" in ids
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assert "PE-CPU-002" in ids
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assert "PE-CPU-003" in ids
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assert "PE-CPU-004" in ids
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assert not any(str(i).startswith("PE-DDR") for i in ids)
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assert not any(str(i).startswith("PE-FPGA") for i in ids)
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gpio = DesignGraph(
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components={"U1": _ic("U1", {"1": "GPIO0", "2": "GPIO1"}, mpn="MSPM0", subtype="ic.mcu")},
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nets={
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"GPIO0": _net("GPIO0", ("U1", "1")),
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"GPIO1": _net("GPIO1", ("U1", "2")),
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},
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)
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assert check_memory_fpga_classes(gpio) == []
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def test_fpga_only_when_present_config_flash_optional():
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fpga_pins = {"1": "IO_L1P", "2": "IO_L1N", "3": "VCCINT", "4": "VCCIO"}
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g = DesignGraph(
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components={"U5": _ic("U5", fpga_pins, mpn="XC7A35T", subtype="ic.fpga")},
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nets={
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"IO_L1P": _net("IO_L1P", ("U5", "1")),
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"IO_L1N": _net("IO_L1N", ("U5", "2")),
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"VCCINT": _net("VCCINT", ("U5", "3"), ntype=NetType.POWER),
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"VCCIO": _net("VCCIO", ("U5", "4"), ntype=NetType.POWER),
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},
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)
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findings = check_memory_fpga_classes(g)
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ids = {f.rule_id for f in findings}
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assert "PE-FPGA-001" in ids
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assert "PE-FPGA-003" in ids
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assert "PE-FPGA-002" not in ids
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assert not any(str(i).startswith("PE-DDR") for i in ids)
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assert not any(str(i).startswith("PE-CPU") for i in ids)
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g.components["U6"] = _ic("U6", {"1": "FPGA_CS", "2": "FPGA_MOSI"}, mpn="W25Q64", subtype="ic.memory.flash")
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g.nets["FPGA_CS"] = _net("FPGA_CS", ("U6", "1"), ("U5", "10"))
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g.components["U5"].pins["10"] = "FPGA_CS"
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with_flash = check_memory_fpga_classes(g)
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assert any(f.rule_id == "PE-FPGA-002" for f in with_flash)
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def test_rule_catalog_hf_ids():
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for rid, domain in (
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("PE-SI-007", "pcb"),
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("PE-SI-011", "pcb"),
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("PE-SI-012", "pcb"),
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("PE-DDR-001", "shared"),
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("PE-DDR-002", "shared"),
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("PE-DDR-003", "shared"),
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("PE-CPU-001", "shared"),
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("PE-CPU-002", "shared"),
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("PE-CPU-003", "shared"),
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("PE-CPU-004", "shared"),
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("PE-FPGA-001", "shared"),
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("PE-FPGA-002", "shared"),
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("PE-FPGA-003", "shared"),
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):
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rec = lookup_rule(rid)
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assert rec is not None, rid
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assert rec.domain == domain
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def test_existing_si_usb_not_polluted_by_hf_geometry():
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layout = LayoutGraph(
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segments=[
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LayoutSegment(start=(0, 0), end=(10, 0), width=0.2, layer="F.Cu", net="USB_D+"),
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LayoutSegment(start=(0, 0.4), end=(12.5, 0.4), width=0.2, layer="F.Cu", net="USB_D-"),
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],
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vias=[LayoutVia(x=1, y=0.2, net="GND", drill=0.3)],
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)
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findings = check_si(_usb_graph(), {}, layout, [
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{
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"net_name": "USB_D+", "partner_net_name": "USB_D-",
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"z0_avg_ohms": 88.0, "z0_min_ohms": 46.0, "z0_max_ohms": 92.0,
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"length_mm": 10.0, "topologies": ["MICROSTRIP"],
|
|
},
|
|
{
|
|
"net_name": "USB_D-", "partner_net_name": "USB_D+",
|
|
"z0_avg_ohms": 88.0, "z0_min_ohms": 46.0, "z0_max_ohms": 92.0,
|
|
"length_mm": 12.5, "topologies": ["MICROSTRIP"],
|
|
},
|
|
])
|
|
assert any(f.rule_id == "PE-SI-010" for f in findings)
|
|
assert all(f.rule_id != "PE-SI-002" for f in findings)
|