KiCad stitching/thermal vias inside a footprint are (via) or copper-only
thru_hole (pad) objects. parse_kicad_pcb was appending every (pad) to
LayoutFootprint.pads, so PE-BOM-011 compared datasheet pin_count to via
numbers. Nested vias join LayoutGraph.vias; soldered THT pads stay pads.
Live review_ic_async comes from review_session; PinScope validate.py and
validation_tools.py stay in dependency as _inherited_review_ic_async fallback.
Keep validate.py and the finding engine as-is. AGPL LICENSE stays at the repo root.
Docker overlays dependency then src. Do not delete the inherited tree.
PE-SI-009 no longer treats ESP32 CHIP_PU/EN RC as a USB series R.
USB without a library Z number stays PE-SI-010 measurement-only.
Pintable skill 1.13.0 requires net_class on SI kinds (usb2/usb3/MDI/RGMII/DDR3).
Package/pinout/ratings mismatches, SPOF as REVIEW, EMI only with a
datasheet quote, and Tj from copper+vias+θJA when every parameter exists.
Re-extract SI layout_rules from 1.12.0; ImpedenceFinder license stays UNKNOWN.
Each layout_rules SI requirement (diff/SE Z, skew, max length, spacing,
ref plane, vias, layer, return, series R) is one PASS/FAIL/MARGIN finding
with FACT and REQUIREMENT. USB/HDMI/PCIe/ETH/LVDS/DDR only; I2C GPIO CC
and analog REGN are skipped. No invented 90 Ω.
The status watcher synthesized pcb_error with pcb_status=complete (terminal)
when the worker finished before pcb_complete arrived. Map that hatch to
pcb_complete, publish the event before flipping status, and send /pcb to
the layout report tree.
PE-ESD-001 only on J* connector–IC nets (skip NC, unconnected, VSYS/GND/3V3).
PE-PI-001 treats any capacitor on the rail, including KiCad slash prefixes, as
decoupling. Sort findings ERROR then WARNING then INFO, then RULE/RISK/REVIEW/INFO.
Report sidebar is a collapsed expand-on-click tree instead of an all-open list.
GET /report and complete_findings fail-soft and sort the same way.
ERROR stays only for RULE+MANDATORY. Hierarchy walks component→pin→net→block.
Derating is PASS/MARGIN/RISK from Vop/Vrated. Timing and PI skip without numbers.
ESD and HS return path are REVIEW, not RULE ERROR.
Layout and AI findings always get action (fallback recommendation). The card
renders that sentence in the body. PCB review context now includes vias under
the footprint, copper thickness, nearby widths, courtyard, and keepout polygons.
Fill action on every finding and show it in the report. Stitch/return only
on large HS/power nets. Parse stackup thickness, arcs, and vias from the
board. IC courtyard pad copper is not PE-PLC-004 RULE. Recommended RC/cap
stay REVIEW.
FACT, REQUIREMENT, and INFERENCE are separate fields; datasheet provenance
lives in the rule DB so Recommended cannot stay ERROR; LLM output is REVIEW.
Designer decisions persist across rescans. Schematic and PCB share one library
and the same finding object in the report UI.
PCB AI skips a second PDF exam (pintable cache, pdf_path=None) and the report
gains a PCB exam section plus power-trace, thermal, via, Kelvin, and GND-stitch
checks grounded in board geometry and extracted specs.
Pad-net compare strips leading slash and nested sheet path so /ESP32_EN
matches ESP32_EN. If every mismatch is only that prefix, emit PE-LAY-003
once instead of per-pad reconnect errors.
A container rebuild left Emmaforo status=running with no process, so
PCB start kept 409. Heal on GET now matches placement/PCB: complete if
report.json exists, otherwise error.
update_project used meta.user_id for the path, so JWT projects that still
have user_id=local never persisted pcb_status=queued and the PCB worker
exited as draft. Point writes at the prefix used to read the project.
Refuse update-periscope.sh unless dirname resolves to the canonical
checkout, set compose project name periscope, and document that the
GitHub clone URL may still be manvalan/pinscope.
Documents a parallel MODE=pcb exam job (inventory + datasheet-gated
checks) that reuses placement_check, si_check, and the placement job
pattern. Parks F2 packing/export.
/login 404ed from marketing CTAs; redirect to /sign-in and accept pinscope-local tokens plus dual-host CORS so login works on both hostnames.
Co-authored-by: Cursor <cursoragent@cursor.com>
Rename the core package to periscopex, update UI/docs/Docker/deploy defaults to periscope.michelebigi.it, and keep legacy version/storage key aliases so existing projects keep working.
Co-authored-by: Cursor <cursoragent@cursor.com>
Progetta now returns a parametric radiator geometry (segments + preview + .kicad_mod) so the layout can be replicated without inventing EM results.
Co-authored-by: Cursor <cursoragent@cursor.com>
EN/BOOT/REGN/PMID bypass and flying bootstrap caps get real roles; other is omitted from assemble_order.
Co-authored-by: Cursor <cursoragent@cursor.com>
Stop LDO 3V3 groups from inheriting VSYS caps/filters, drop connector/switch noise, and align Power rails with domain membership.
Co-authored-by: Cursor <cursoragent@cursor.com>
Treat PCB/application layout guidance as a first-class extract, keep those pages in PDF trim, and re-run IC extraction once when rules are still empty under older model_version.
Co-authored-by: Cursor <cursoragent@cursor.com>
Propose positions only from PCB footprints plus numeric decoupling max_distance_mm; otherwise skip with an explicit reason.
Co-authored-by: Cursor <cursoragent@cursor.com>
Sidebar tabs show routing-first topology from placement_plan/functional_groups, with IC groups and satellite roles highlighted per domain and per supply rail.
Co-authored-by: Cursor <cursoragent@cursor.com>
If the event log already ends with pipeline_complete, flip meta to complete on project/status fetch so Progress no longer spins on a dead worker.
Co-authored-by: Cursor <cursoragent@cursor.com>
Gate /progress SSE and auto-redirect on a live queued/running status so historical pipeline_complete events no longer flash Processing then open the report.
Co-authored-by: Cursor <cursoragent@cursor.com>
Open finished projects on the hub instead of /report, and hard-navigate when leaving nested report/progress/placement routes for Dashboard, Library, and hub tabs.
Co-authored-by: Cursor <cursoragent@cursor.com>
Ship a free, analysis-independent job that writes placement_plan.json (domains/satellites, no mm) with API, SSE progress, and a minimal project UI.
Co-authored-by: Cursor <cursoragent@cursor.com>
Write routing-first domain/satellite topology after graph_build, and
flag crystal CL mismatches and NC pins on active nets without inventing
millimetres.
Co-authored-by: Cursor <cursoragent@cursor.com>
AUTH_JWT_SECRET was never written because upsert ran before git pull;
sidebar used Button asChild which Base UI does not support.
Co-authored-by: Cursor <cursoragent@cursor.com>
michele
