micheleandClaude Sonnet 5
d6376e8f2a
Real synthesis and place-and-route of the actual final board-level
top (fpga_neural_v2_top.v -- SPI bridge, real EHXPLLL, reset_sync,
compute+memory core), against a real, fully ball-assigned LPF. Also
ports the V2 datasheet to LaTeX using V1's own preamble/macros/
typography, and records a real (non-ESP32, honestly labeled) software
reference comparison.
Synthesis (Yosys, real run): 0 CHECK-pass problems, 38 unique warnings
(43 total), all matching this project's own previously-reviewed benign
set (neural_processor.v's known genvar multi-driver artifact, small-
array-to-register unrolling, the real SDRAM DQ tristate bus) -- no new
warnings from the SPI bridge, PLL, or reset synchronizer.
TRELLIS_FF=6322, TRELLIS_COMB=7084, MULT18X18D=32, EHXPLLL=1 (real PLL
confirmed present), DP16KD=0 (all small SRAMs -> distributed RAM).
Place-and-route (nextpnr-ecp5, real runs, 8 seeds, new
v2_board_top.lpf with all 44 top-level signals ball-assigned from the
official Lattice pinout CSV -- no placeholders): 8/8 PASS at 64MHz.
Worst 68.51MHz (seed 4), best 74.17MHz (seed 7), mean 71.16MHz. Zero
unrouted nets, zero placement/routing errors, TRELLIS_IO=44/245 (17%).
Critical path alternates between dependency_manager's own priority
encoder and sdram_unified_backend's own weight-cache hit-index logic,
matching this project's own prior documented timing investigations --
not a new defect.
New: hardware/v2/constraints/v2_board_top.lpf (final LPF, supersedes
v2_unified.lpf for the board-level top), hardware/v2/reports/
step_final_{synthesis,pnr_worst_seed4,timing}.* (raw evidence),
hardware/v2/docs/DatasheetLatex/ (V2 datasheet, real LaTeX build,
16 pages, visually inspected, ported from hardware/v1/docs/
DatasheetLatex/'s own preamble and macros).
Real, honestly-labeled software baseline: the D-Stress arithmetic
(256 neurons x 128 INT8 MACs) compiled and run on THIS development
machine (Apple M4, arm64, NOT an embedded target, NOT ESP32) --
1.28us/inference, included in the datasheet with an explicit
disclosure that no physical ESP32 hardware was available for a real
embedded-target comparison.
Remaining, disclosed, NOT-yet-closed items (this commit does NOT
claim silicon readiness): real KiCad schematic + ERC, PCB layout,
sourced BOM, real power current-budget estimate, SDRAM-datasheet-
parameter cross-check, configuration-flash selection, and (necessarily)
physical fabrication/bring-up. See hardware/v2/docs/DatasheetLatex/
chapters/08-status-roadmap.tex for the complete, itemized checklist.
Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
31 lines
2.4 KiB
TeX
31 lines
2.4 KiB
TeX
\babel@toc {english}{}\relax
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\contentsline {chapter}{\numberline {1}Overview}{1}{chapter.1}%
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\contentsline {section}{\numberline {1.1}Document scope and status labels}{1}{section.1.1}%
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\contentsline {section}{\numberline {1.2}Frozen reference configuration}{1}{section.1.2}%
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\contentsline {chapter}{\numberline {2}Architecture}{2}{chapter.2}%
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\contentsline {section}{\numberline {2.1}Compute: Neural Multiprocessor}{2}{section.2.1}%
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\contentsline {section}{\numberline {2.2}Unified single-SDRAM memory}{2}{section.2.2}%
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\contentsline {section}{\numberline {2.3}Read-timing discipline (ERR-0025)}{3}{section.2.3}%
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\contentsline {chapter}{\numberline {3}Clock and reset architecture}{4}{chapter.3}%
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\contentsline {section}{\numberline {3.1}Clock generation}{4}{section.3.1}%
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\contentsline {section}{\numberline {3.2}Reset architecture}{4}{section.3.2}%
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\contentsline {chapter}{\numberline {4}Host interface (SPI)}{5}{chapter.4}%
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\contentsline {section}{\numberline {4.1}Opcodes}{5}{section.4.1}%
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\contentsline {section}{\numberline {4.2}Verification}{5}{section.4.2}%
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\contentsline {chapter}{\numberline {5}Pinout, place-and-route, and timing}{6}{chapter.5}%
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\contentsline {section}{\numberline {5.1}Final pinout}{6}{section.5.1}%
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\contentsline {section}{\numberline {5.2}Synthesis (real, this revision)}{6}{section.5.2}%
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\contentsline {section}{\numberline {5.3}Place and route: 8-seed timing table}{6}{section.5.3}%
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\contentsline {chapter}{\numberline {6}Power, SDRAM electrical, and configuration}{8}{chapter.6}%
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\contentsline {section}{\numberline {6.1}Power architecture -- status: OPEN}{8}{section.6.1}%
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\contentsline {section}{\numberline {6.2}SDRAM electrical / timing sign-off -- status: PARTIAL}{8}{section.6.2}%
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\contentsline {section}{\numberline {6.3}Configuration -- status: OPEN}{8}{section.6.3}%
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\contentsline {chapter}{\numberline {7}Benchmarks}{9}{chapter.7}%
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\contentsline {section}{\numberline {7.1}Internal benchmark: D-Stress workload}{9}{section.7.1}%
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\contentsline {section}{\numberline {7.2}Host-interface pacing benchmark}{9}{section.7.2}%
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\contentsline {section}{\numberline {7.3}Software reference comparison}{9}{section.7.3}%
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\contentsline {chapter}{\numberline {8}Chip readiness and roadmap}{11}{chapter.8}%
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\contentsline {section}{\numberline {8.1}Precise readiness checklist}{11}{section.8.1}%
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\contentsline {section}{\numberline {8.2}Final answer}{11}{section.8.2}%
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\contentsline {section}{\numberline {8.3}Roadmap}{11}{section.8.3}%
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