micheleandClaude Sonnet 5 e6768623d6 docs: confirm denser activation packing is real-timing-safe, margin improved (EXP-0082) ...

Real P&R: WNS +0.068ns (up from +0.030ns), 0 failing endpoints, 5437
LUTs, 16 DSP48E1. Confirms EXP-0081's "register the select bit at
request time" design genuinely kept the fix off the critical path.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC

2026-09-20 10:01:58 +02:00

benchmark_results

feat: add FPGA-Neural benchmark tooling + same-tier ECP5 P2/P4/P8 results

2026-09-02 19:48:03 +02:00

docs

docs: complete architecture analysis - DDR3 bandwidth is the real ceiling, not DSP count (EXP-0080)

2026-09-20 09:44:10 +02:00

hardware

docs: confirm denser activation packing is real-timing-safe, margin improved (EXP-0082)

2026-09-20 10:01:58 +02:00

sim

chore: remove root-level V1 duplicates, superseded by hardware/v1/ freeze

2026-09-07 05:30:17 +02:00

synth/ecp5

chore: remove root-level V1 duplicates, superseded by hardware/v1/ freeze

2026-09-07 05:30:17 +02:00

tools/neural_sim

chore: remove root-level V1 duplicates, superseded by hardware/v1/ freeze

2026-09-07 05:30:17 +02:00

.gitignore

feat: add FPGA-Neural benchmark tooling + same-tier ECP5 P2/P4/P8 results

2026-09-02 19:48:03 +02:00

.gitmodules

docs: extract V2 datasheet into submodule

2026-09-16 23:03:43 +02:00

CLAUDE.md

docs: complete architecture analysis - DDR3 bandwidth is the real ceiling, not DSP count (EXP-0080)

2026-09-20 09:44:10 +02:00

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