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FPGA-Neural/hardware
micheleandClaude Sonnet 5 e6768623d6 docs: confirm denser activation packing is real-timing-safe, margin improved (EXP-0082)
Real P&R: WNS +0.068ns (up from +0.030ns), 0 failing endpoints, 5437
LUTs, 16 DSP48E1. Confirms EXP-0081's "register the select bit at
request time" design genuinely kept the fix off the critical path.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
2026-09-20 10:01:58 +02:00
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