FPGA-Neural

T

micheleandClaude Sonnet 5 e3fe007469 docs: reframe primary docs -- N=16 is now the real fabrication target

Physical board fabrication moved to N=16 (with the EXP-0097 MAC-
pipeline fix); v3-artix7 fast-forward merged with n16-timing-closure.
No physical board change needed -- DDR3/SPI/flash/config pins are
identical across all N_GROUPS values. N=2/N=8 kept documented as real,
valid fallback signoffs.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC

2026-09-22 08:36:37 +02:00

benchmark_results

feat: add FPGA-Neural benchmark tooling + same-tier ECP5 P2/P4/P8 results

2026-09-02 19:48:03 +02:00

docs

docs: reframe primary docs -- N=16 is now the real fabrication target

2026-09-22 08:36:37 +02:00

hardware

docs: consolidate N=16 to N=8's own level of rigor (EXP-0098) -- whole family real and closed

2026-09-22 01:15:15 +02:00

sim

chore: remove root-level V1 duplicates, superseded by hardware/v1/ freeze