FPGA-Neural

T

micheleandClaude Sonnet 5 94b63705be exp: N=8 packed-core array real P&R, isolates placement density from interconnect (EXP-0060)

New hardware/v3/rtl/np_packed_array.v: flat array of 8 unmodified
neural_processor_packed.v instances, fully independent I/O, zero
shared arbiter/Director logic -- isolates exactly one variable
(DSP/placement density) from EXP-0059's single-core baseline.

Real Vivado post-route: 64/240 DSP48E1 (26.67%), WNS -2.592ns @
200MHz -> Fmax ~131.7MHz, only -2.4% vs the single-core 134.9MHz.
Placement density alone is NOT the main driver of the ECP5-era gap
between isolated-core and full-system Fmax -- narrows the question
for the still-unbuilt real Director/arbiter/memory integration.

Full writeup in hardware/v2/logs/experiments.log EXP-0060.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC

2026-09-16 23:29:54 +02:00

benchmark_results

feat: add FPGA-Neural benchmark tooling + same-tier ECP5 P2/P4/P8 results

2026-09-02 19:48:03 +02:00

docs

chore: remove root-level V1 duplicates, superseded by hardware/v1/ freeze

2026-09-07 05:30:17 +02:00

hardware

exp: N=8 packed-core array real P&R, isolates placement density from interconnect (EXP-0060)

2026-09-16 23:29:54 +02:00

sim

chore: remove root-level V1 duplicates, superseded by hardware/v1/ freeze