FPGA-Neural

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micheleandClaude Sonnet 5 835ae881dc feat: MILESTONE - first real in-context P&R, timing closes at 310MHz DDR3 (EXP-0074)

n2_system_ddr3_top.v: the first synthesizable top wiring the real
mig_7series_0 DDR3 controller (public wrapper, real calibration) +
mig_native_adapter.v + sdram_arbiter_n.v (3-way: 2 packed_slot + host
raw-access) + neural_director_packed.v + spi_host_bridge_v3.v.

Real Vivado in-context synth+impl against the actual MIG-generated
XDC (pin locations, DDR3 timing exceptions) on xc7a100tcsg324-2:
route_design 100%, all timing constraints met (WNS +0.040ns, WHS
+0.048ns, 0 failing endpoints), 310.078MHz DDR3 PHY clock / 155.039MHz
compute domain, 5140 LUTs / 5952 regs / 16 DSP48E1 / 0 BRAM.

Fixed three real issues found getting here: a SystemVerilog literal
synth_design can't parse, MIG stub port mismatch (calib_tap_* isn't
exposed in this IP config), and a genuine design mistake -- exposing
packed_slot.v's activation-fetch stand-in ports as literal top-level
pins demanded ~360 I/O against the package's 324 total. Made that
interface internal (stub-driven) instead.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC

2026-09-19 17:47:40 +02:00

host_mem_bridge.v

feat: host_mem_bridge.v, word<->burst translator for host DDR3 access (EXP-0071)

2026-09-17 08:53:23 +02:00

mac2_dsp_packed.v

v3: real Artix-7 compute core -- DSP48 packing verified, 2 real bugs found and fixed

2026-09-16 19:48:46 +02:00

mig_native_adapter.v

feat: real DDR3 memory path verified against MIG's own ddr3_model.sv (EXP-0068)

2026-09-17 08:43:22 +02:00

n2_system_ddr3_top.v

feat: MILESTONE - first real in-context P&R, timing closes at 310MHz DDR3 (EXP-0074)